Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7002969	1			T1	19		T2	30		T3	364
all_levels[1]	2390118	1			T1	1		T2	12125		T3	80
all_levels[2]	434591	1			T1	2		T2	2200		T3	47
all_levels[3]	272831	1			T1	4		T3	26		T6	1179
all_levels[4]	278186	1			T1	5		T3	14		T6	1184
all_levels[5]	288365	1			T1	45		T3	18		T4	3
all_levels[6]	204163	1			T1	12		T3	15		T6	1184
all_levels[7]	217841	1			T1	123		T3	19		T6	1161
all_levels[8]	485973	1			T1	1		T3	10		T6	5219
all_levels[9]	180803	1			T1	2		T3	19		T6	1515
all_levels[10]	182497	1			T1	1		T3	17		T6	1177
all_levels[11]	213888	1			T3	5		T6	1176		T11	2
all_levels[12]	313269	1			T1	7		T3	40		T6	1176
all_levels[13]	182770	1			T3	12		T6	1173		T11	25
all_levels[14]	317567	1			T3	6		T6	1181		T17	95
all_levels[15]	235983	1			T4	2		T6	1182		T17	48
all_levels[16]	427671	1			T6	1163		T17	101		T12	2
all_levels[17]	580681	1			T1	1		T3	1		T4	3
all_levels[18]	194906	1			T3	3		T6	1182		T8	3
all_levels[19]	247479	1			T3	25		T6	1180		T11	5
all_levels[20]	176434	1			T3	11		T6	1183		T11	3
all_levels[21]	432014	1			T6	1182		T17	70		T34	3
all_levels[22]	206883	1			T1	3		T5	12		T6	1183
all_levels[23]	246613	1			T6	1181		T17	157		T12	1
all_levels[24]	196156	1			T5	3		T6	1183		T17	168
all_levels[25]	147439	1			T1	1		T4	1		T5	4
all_levels[26]	187830	1			T6	1872		T39	4		T17	172
all_levels[27]	627174	1			T1	1		T5	1		T17	168
all_levels[28]	307628	1			T1	5		T5	1		T17	171
all_levels[29]	199195	1			T1	2		T5	1		T11	1
all_levels[30]	283011	1			T1	1		T5	1		T39	1
all_levels[31]	556312	1			T4	2		T17	171		T12	473
all_levels[32]	10576896	1			T1	30		T11	7		T81	7

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28791652

1

T1

266

T2

14319

T3

731

auto[1]

4484

1

T2

36

T3

1

T4

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7000389	1			T1	19		T2	3		T3	364
all_levels[0]	auto[1]	2580	1			T2	27		T5	3		T8	6
all_levels[1]	auto[0]	2389760	1			T1	1		T2	12116		T3	80
all_levels[1]	auto[1]	358	1			T2	9		T8	1		T39	3
all_levels[2]	auto[0]	434562	1			T1	2		T2	2200		T3	47
all_levels[2]	auto[1]	29	1			T40	1		T199	1		T296	1
all_levels[3]	auto[0]	272711	1			T1	4		T3	26		T6	1179
all_levels[3]	auto[1]	120	1			T284	1		T136	1		T47	1
all_levels[4]	auto[0]	278162	1			T1	5		T3	14		T6	1184
all_levels[4]	auto[1]	24	1			T284	2		T318	1		T159	1
all_levels[5]	auto[0]	288339	1			T1	45		T3	18		T4	3
all_levels[5]	auto[1]	26	1			T266	4		T345	1		T346	1
all_levels[6]	auto[0]	204122	1			T1	12		T3	15		T6	1184
all_levels[6]	auto[1]	41	1			T8	1		T41	4		T181	1
all_levels[7]	auto[0]	217692	1			T1	123		T3	19		T6	1161
all_levels[7]	auto[1]	149	1			T130	2		T205	3		T32	5
all_levels[8]	auto[0]	485958	1			T1	1		T3	10		T6	5219
all_levels[8]	auto[1]	15	1			T53	1		T347	1		T189	1
all_levels[9]	auto[0]	180764	1			T1	2		T3	19		T6	1514
all_levels[9]	auto[1]	39	1			T6	1		T135	1		T192	2
all_levels[10]	auto[0]	182463	1			T1	1		T3	17		T6	1177
all_levels[10]	auto[1]	34	1			T277	1		T348	1		T349	1
all_levels[11]	auto[0]	213858	1			T3	5		T6	1176		T11	2
all_levels[11]	auto[1]	30	1			T43	2		T217	1		T336	1
all_levels[12]	auto[0]	313231	1			T1	7		T3	39		T6	1176
all_levels[12]	auto[1]	38	1			T3	1		T135	1		T48	3
all_levels[13]	auto[0]	182745	1			T3	12		T6	1173		T11	24
all_levels[13]	auto[1]	25	1			T11	1		T41	2		T136	1
all_levels[14]	auto[0]	317533	1			T3	6		T6	1181		T17	95
all_levels[14]	auto[1]	34	1			T47	1		T310	1		T350	1
all_levels[15]	auto[0]	235854	1			T4	2		T6	1182		T17	48
all_levels[15]	auto[1]	129	1			T181	1		T124	21		T273	1
all_levels[16]	auto[0]	427648	1			T6	1163		T17	101		T12	2
all_levels[16]	auto[1]	23	1			T136	1		T112	4		T351	1
all_levels[17]	auto[0]	580661	1			T1	1		T3	1		T4	2
all_levels[17]	auto[1]	20	1			T4	1		T179	1		T345	1
all_levels[18]	auto[0]	194877	1			T3	3		T6	1182		T8	2
all_levels[18]	auto[1]	29	1			T8	1		T43	1		T133	1
all_levels[19]	auto[0]	247462	1			T3	25		T6	1180		T11	5
all_levels[19]	auto[1]	17	1			T144	1		T159	2		T160	4
all_levels[20]	auto[0]	176415	1			T3	11		T6	1183		T11	3
all_levels[20]	auto[1]	19	1			T320	1		T352	1		T353	1
all_levels[21]	auto[0]	431997	1			T6	1182		T17	70		T34	3
all_levels[21]	auto[1]	17	1			T37	1		T43	1		T284	2
all_levels[22]	auto[0]	206864	1			T1	3		T5	11		T6	1183
all_levels[22]	auto[1]	19	1			T5	1		T284	1		T277	1
all_levels[23]	auto[0]	246603	1			T6	1181		T17	157		T12	1
all_levels[23]	auto[1]	10	1			T111	1		T246	1		T354	1
all_levels[24]	auto[0]	196141	1			T5	2		T6	1183		T17	168
all_levels[24]	auto[1]	15	1			T5	1		T152	2		T355	2
all_levels[25]	auto[0]	147414	1			T1	1		T4	1		T5	2
all_levels[25]	auto[1]	25	1			T5	2		T81	1		T47	1
all_levels[26]	auto[0]	187818	1			T6	1872		T39	2		T17	172
all_levels[26]	auto[1]	12	1			T39	2		T348	1		T356	1
all_levels[27]	auto[0]	627162	1			T1	1		T5	1		T17	168
all_levels[27]	auto[1]	12	1			T40	3		T277	1		T283	1
all_levels[28]	auto[0]	307611	1			T1	5		T5	1		T17	171
all_levels[28]	auto[1]	17	1			T145	1		T357	1		T358	1
all_levels[29]	auto[0]	199184	1			T1	2		T5	1		T11	1
all_levels[29]	auto[1]	11	1			T191	1		T359	1		T227	2
all_levels[30]	auto[0]	282992	1			T1	1		T5	1		T39	1
all_levels[30]	auto[1]	19	1			T33	1		T205	1		T109	3
all_levels[31]	auto[0]	556291	1			T4	2		T17	171		T12	473
all_levels[31]	auto[1]	21	1			T336	1		T360	1		T226	1
all_levels[32]	auto[0]	10576369	1			T1	30		T11	7		T81	2
all_levels[32]	auto[1]	527	1			T81	5		T12	1		T34	1