Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	773	1			T12	7		T20	18		T18	7
all_values[1]	773	1			T12	7		T20	18		T18	7
all_values[2]	773	1			T12	7		T20	18		T18	7
all_values[3]	773	1			T12	7		T20	18		T18	7
all_values[4]	773	1			T12	7		T20	18		T18	7
all_values[5]	773	1			T12	7		T20	18		T18	7
all_values[6]	773	1			T12	7		T20	18		T18	7
all_values[7]	773	1			T12	7		T20	18		T18	7
all_values[8]	773	1			T12	7		T20	18		T18	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3749

1

T12

29

T20

87

T18

37

auto[1]

3208

1

T12

34

T20

75

T18

26

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2281

1

T12

20

T20

53

T18

13

auto[1]

4676

1

T12

43

T20

109

T18

50

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4033

1

T12

37

T20

93

T18

33

auto[1]

2924

1

T12

26

T20

69

T18

30

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	223	1			T20	5		T28	1		T29	1
all_values[0]	auto[0]	auto[1]	auto[1]	211	1			T12	3		T20	3		T18	2
all_values[0]	auto[1]	auto[0]	auto[1]	194	1			T12	1		T20	6		T18	3
all_values[0]	auto[1]	auto[1]	auto[1]	145	1			T12	3		T20	4		T18	2
all_values[1]	auto[0]	auto[0]	auto[0]	261	1			T20	6		T18	2		T28	2
all_values[1]	auto[0]	auto[1]	auto[0]	187	1			T12	4		T20	4		T18	2
all_values[1]	auto[1]	auto[0]	auto[1]	176	1			T20	3		T18	2		T28	3
all_values[1]	auto[1]	auto[1]	auto[1]	149	1			T12	3		T20	5		T18	1
all_values[2]	auto[0]	auto[0]	auto[0]	160	1			T12	2		T20	7		T18	1
all_values[2]	auto[0]	auto[0]	auto[1]	69	1			T12	1		T20	1		T18	1
all_values[2]	auto[0]	auto[1]	auto[0]	151	1			T12	1		T20	2		T18	2
all_values[2]	auto[0]	auto[1]	auto[1]	65	1			T12	1		T20	1		T28	1
all_values[2]	auto[1]	auto[0]	auto[1]	169	1			T20	4		T18	2		T28	3
all_values[2]	auto[1]	auto[1]	auto[1]	159	1			T12	2		T20	3		T18	1
all_values[3]	auto[0]	auto[0]	auto[0]	159	1			T12	1		T20	1		T18	1
all_values[3]	auto[0]	auto[0]	auto[1]	77	1			T12	2		T20	6		T18	2
all_values[3]	auto[0]	auto[1]	auto[0]	134	1			T20	2		T28	1		T29	1
all_values[3]	auto[0]	auto[1]	auto[1]	68	1			T20	2		T18	1		T28	1
all_values[3]	auto[1]	auto[0]	auto[1]	177	1			T20	2		T18	3		T28	1
all_values[3]	auto[1]	auto[1]	auto[1]	158	1			T12	4		T20	5		T28	5
all_values[4]	auto[0]	auto[0]	auto[0]	148	1			T20	7		T18	1		T28	1
all_values[4]	auto[0]	auto[0]	auto[1]	89	1			T12	1		T20	2		T18	3
all_values[4]	auto[0]	auto[1]	auto[0]	113	1			T12	1		T28	2		T29	1
all_values[4]	auto[0]	auto[1]	auto[1]	93	1			T12	1		T20	1		T28	4
all_values[4]	auto[1]	auto[0]	auto[1]	197	1			T12	4		T20	5		T18	2
all_values[4]	auto[1]	auto[1]	auto[1]	133	1			T20	3		T18	1		T28	3
all_values[5]	auto[0]	auto[0]	auto[0]	173	1			T12	3		T20	3		T28	1
all_values[5]	auto[0]	auto[0]	auto[1]	73	1			T20	2		T28	4		T29	1
all_values[5]	auto[0]	auto[1]	auto[0]	145	1			T12	3		T20	5		T18	2
all_values[5]	auto[0]	auto[1]	auto[1]	72	1			T20	2		T18	2		T29	1
all_values[5]	auto[1]	auto[0]	auto[1]	163	1			T20	4		T18	1		T28	2
all_values[5]	auto[1]	auto[1]	auto[1]	147	1			T12	1		T20	2		T18	2
all_values[6]	auto[0]	auto[0]	auto[0]	170	1			T12	1		T20	4		T18	1
all_values[6]	auto[0]	auto[0]	auto[1]	65	1			T20	2		T28	1		T32	1
all_values[6]	auto[0]	auto[1]	auto[0]	150	1			T12	1		T20	5		T28	2
all_values[6]	auto[0]	auto[1]	auto[1]	84	1			T12	2		T18	3		T28	2
all_values[6]	auto[1]	auto[0]	auto[1]	166	1			T12	1		T20	4		T18	1
all_values[6]	auto[1]	auto[1]	auto[1]	138	1			T12	2		T20	3		T18	2
all_values[7]	auto[0]	auto[0]	auto[0]	170	1			T12	2		T20	3		T30	2
all_values[7]	auto[0]	auto[0]	auto[1]	74	1			T12	2		T20	1		T18	2
all_values[7]	auto[0]	auto[1]	auto[0]	160	1			T12	1		T20	4		T18	1
all_values[7]	auto[0]	auto[1]	auto[1]	54	1			T20	2		T28	1		T29	1
all_values[7]	auto[1]	auto[0]	auto[1]	190	1			T12	2		T20	3		T18	3
all_values[7]	auto[1]	auto[1]	auto[1]	125	1			T20	5		T18	1		T29	1
all_values[8]	auto[0]	auto[0]	auto[1]	230	1			T12	4		T20	2		T18	3
all_values[8]	auto[0]	auto[1]	auto[1]	205	1			T20	8		T18	1		T28	2
all_values[8]	auto[1]	auto[0]	auto[1]	176	1			T12	2		T20	4		T18	3
all_values[8]	auto[1]	auto[1]	auto[1]	162	1			T12	1		T20	4		T28	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal