Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.59


Total test records in report: 1315
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T129 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1842096750 Aug 10 05:58:21 PM PDT 24 Aug 10 05:58:22 PM PDT 24 385832332 ps
T1256 /workspace/coverage/cover_reg_top/9.uart_tl_errors.1086353508 Aug 10 05:58:11 PM PDT 24 Aug 10 05:58:13 PM PDT 24 35693636 ps
T1257 /workspace/coverage/cover_reg_top/21.uart_intr_test.2644385953 Aug 10 05:58:36 PM PDT 24 Aug 10 05:58:36 PM PDT 24 46034876 ps
T1258 /workspace/coverage/cover_reg_top/29.uart_intr_test.806485248 Aug 10 05:58:34 PM PDT 24 Aug 10 05:58:35 PM PDT 24 17737957 ps
T1259 /workspace/coverage/cover_reg_top/2.uart_tl_errors.867719229 Aug 10 05:58:04 PM PDT 24 Aug 10 05:58:06 PM PDT 24 500479033 ps
T1260 /workspace/coverage/cover_reg_top/20.uart_intr_test.1863045249 Aug 10 05:58:52 PM PDT 24 Aug 10 05:58:53 PM PDT 24 11431085 ps
T66 /workspace/coverage/cover_reg_top/11.uart_csr_rw.2587331232 Aug 10 05:58:19 PM PDT 24 Aug 10 05:58:20 PM PDT 24 22229855 ps
T1261 /workspace/coverage/cover_reg_top/19.uart_tl_errors.2290642360 Aug 10 05:58:49 PM PDT 24 Aug 10 05:58:51 PM PDT 24 27498083 ps
T1262 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2090211217 Aug 10 05:58:03 PM PDT 24 Aug 10 05:58:04 PM PDT 24 41852623 ps
T1263 /workspace/coverage/cover_reg_top/41.uart_intr_test.1973289796 Aug 10 05:58:41 PM PDT 24 Aug 10 05:58:42 PM PDT 24 41445929 ps
T1264 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2535357602 Aug 10 05:58:02 PM PDT 24 Aug 10 05:58:04 PM PDT 24 148558248 ps
T1265 /workspace/coverage/cover_reg_top/46.uart_intr_test.408495142 Aug 10 05:58:27 PM PDT 24 Aug 10 05:58:28 PM PDT 24 55303811 ps
T1266 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.281724640 Aug 10 05:58:26 PM PDT 24 Aug 10 05:58:27 PM PDT 24 240196619 ps
T1267 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.4188231708 Aug 10 05:58:09 PM PDT 24 Aug 10 05:58:10 PM PDT 24 38470688 ps
T1268 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3757223711 Aug 10 05:58:22 PM PDT 24 Aug 10 05:58:23 PM PDT 24 156148964 ps
T1269 /workspace/coverage/cover_reg_top/2.uart_intr_test.3494115566 Aug 10 05:58:07 PM PDT 24 Aug 10 05:58:07 PM PDT 24 15023283 ps
T1270 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2070687203 Aug 10 05:58:24 PM PDT 24 Aug 10 05:58:25 PM PDT 24 18231206 ps
T1271 /workspace/coverage/cover_reg_top/3.uart_tl_errors.1766498396 Aug 10 05:58:07 PM PDT 24 Aug 10 05:58:09 PM PDT 24 70806304 ps
T1272 /workspace/coverage/cover_reg_top/18.uart_tl_errors.178166143 Aug 10 05:58:18 PM PDT 24 Aug 10 05:58:20 PM PDT 24 86613657 ps
T71 /workspace/coverage/cover_reg_top/18.uart_csr_rw.1396678124 Aug 10 05:58:25 PM PDT 24 Aug 10 05:58:26 PM PDT 24 19806928 ps
T1273 /workspace/coverage/cover_reg_top/28.uart_intr_test.1302496458 Aug 10 05:58:48 PM PDT 24 Aug 10 05:58:49 PM PDT 24 15834882 ps
T1274 /workspace/coverage/cover_reg_top/40.uart_intr_test.3140196253 Aug 10 05:58:46 PM PDT 24 Aug 10 05:58:47 PM PDT 24 12375584 ps
T1275 /workspace/coverage/cover_reg_top/43.uart_intr_test.4271207316 Aug 10 05:58:29 PM PDT 24 Aug 10 05:58:30 PM PDT 24 25217496 ps
T1276 /workspace/coverage/cover_reg_top/17.uart_intr_test.277572634 Aug 10 05:58:20 PM PDT 24 Aug 10 05:58:21 PM PDT 24 16263889 ps
T1277 /workspace/coverage/cover_reg_top/2.uart_csr_rw.4104608307 Aug 10 05:58:04 PM PDT 24 Aug 10 05:58:05 PM PDT 24 12639685 ps
T1278 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1048911698 Aug 10 05:58:27 PM PDT 24 Aug 10 05:58:28 PM PDT 24 105925390 ps
T1279 /workspace/coverage/cover_reg_top/48.uart_intr_test.429277628 Aug 10 05:58:28 PM PDT 24 Aug 10 05:58:29 PM PDT 24 14154099 ps
T1280 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2176055487 Aug 10 05:58:25 PM PDT 24 Aug 10 05:58:26 PM PDT 24 18671832 ps
T1281 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2307104446 Aug 10 05:58:23 PM PDT 24 Aug 10 05:58:24 PM PDT 24 418795716 ps
T1282 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1538462711 Aug 10 05:58:17 PM PDT 24 Aug 10 05:58:18 PM PDT 24 17047866 ps
T1283 /workspace/coverage/cover_reg_top/4.uart_tl_errors.1393156071 Aug 10 05:58:07 PM PDT 24 Aug 10 05:58:09 PM PDT 24 287158868 ps
T1284 /workspace/coverage/cover_reg_top/26.uart_intr_test.1597777983 Aug 10 05:58:32 PM PDT 24 Aug 10 05:58:33 PM PDT 24 35336757 ps
T1285 /workspace/coverage/cover_reg_top/1.uart_csr_rw.3794314955 Aug 10 05:58:05 PM PDT 24 Aug 10 05:58:06 PM PDT 24 139509038 ps
T1286 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2476295239 Aug 10 05:58:02 PM PDT 24 Aug 10 05:58:04 PM PDT 24 547875292 ps
T1287 /workspace/coverage/cover_reg_top/7.uart_intr_test.2017435419 Aug 10 05:58:12 PM PDT 24 Aug 10 05:58:13 PM PDT 24 27345796 ps
T1288 /workspace/coverage/cover_reg_top/8.uart_intr_test.1262114496 Aug 10 05:58:25 PM PDT 24 Aug 10 05:58:26 PM PDT 24 28542737 ps
T1289 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3245022805 Aug 10 05:58:03 PM PDT 24 Aug 10 05:58:04 PM PDT 24 15035436 ps
T1290 /workspace/coverage/cover_reg_top/15.uart_intr_test.1311990066 Aug 10 05:58:18 PM PDT 24 Aug 10 05:58:19 PM PDT 24 15907261 ps
T1291 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3685072841 Aug 10 05:58:09 PM PDT 24 Aug 10 05:58:10 PM PDT 24 92449452 ps
T1292 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3637054690 Aug 10 05:58:03 PM PDT 24 Aug 10 05:58:04 PM PDT 24 21474998 ps
T1293 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2578515327 Aug 10 05:58:14 PM PDT 24 Aug 10 05:58:15 PM PDT 24 21175340 ps
T1294 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3604845031 Aug 10 05:58:26 PM PDT 24 Aug 10 05:58:28 PM PDT 24 117125267 ps
T1295 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1176970333 Aug 10 05:58:25 PM PDT 24 Aug 10 05:58:26 PM PDT 24 72518478 ps
T1296 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.150740145 Aug 10 05:58:23 PM PDT 24 Aug 10 05:58:24 PM PDT 24 93350023 ps
T1297 /workspace/coverage/cover_reg_top/19.uart_intr_test.3902940085 Aug 10 05:58:51 PM PDT 24 Aug 10 05:58:51 PM PDT 24 21020488 ps
T1298 /workspace/coverage/cover_reg_top/34.uart_intr_test.1911450364 Aug 10 05:58:40 PM PDT 24 Aug 10 05:58:41 PM PDT 24 20639664 ps
T1299 /workspace/coverage/cover_reg_top/36.uart_intr_test.1622500955 Aug 10 05:58:29 PM PDT 24 Aug 10 05:58:29 PM PDT 24 47505671 ps
T1300 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1593780313 Aug 10 05:58:02 PM PDT 24 Aug 10 05:58:03 PM PDT 24 135539630 ps
T1301 /workspace/coverage/cover_reg_top/15.uart_csr_rw.2586327476 Aug 10 05:58:25 PM PDT 24 Aug 10 05:58:26 PM PDT 24 33615694 ps
T1302 /workspace/coverage/cover_reg_top/3.uart_intr_test.2424960196 Aug 10 05:58:05 PM PDT 24 Aug 10 05:58:06 PM PDT 24 31468372 ps
T1303 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.4150284689 Aug 10 05:58:20 PM PDT 24 Aug 10 05:58:21 PM PDT 24 183935678 ps
T67 /workspace/coverage/cover_reg_top/3.uart_csr_rw.2673952841 Aug 10 05:58:14 PM PDT 24 Aug 10 05:58:15 PM PDT 24 24463932 ps
T1304 /workspace/coverage/cover_reg_top/12.uart_csr_rw.3528605619 Aug 10 05:58:27 PM PDT 24 Aug 10 05:58:28 PM PDT 24 169457631 ps
T1305 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.207213991 Aug 10 05:58:02 PM PDT 24 Aug 10 05:58:03 PM PDT 24 34586583 ps
T68 /workspace/coverage/cover_reg_top/13.uart_csr_rw.1586524953 Aug 10 05:58:25 PM PDT 24 Aug 10 05:58:26 PM PDT 24 19762591 ps
T1306 /workspace/coverage/cover_reg_top/14.uart_intr_test.1506897854 Aug 10 05:58:27 PM PDT 24 Aug 10 05:58:27 PM PDT 24 46710654 ps
T1307 /workspace/coverage/cover_reg_top/47.uart_intr_test.1244486377 Aug 10 05:58:47 PM PDT 24 Aug 10 05:58:48 PM PDT 24 16568157 ps
T1308 /workspace/coverage/cover_reg_top/1.uart_intr_test.4118157836 Aug 10 05:58:07 PM PDT 24 Aug 10 05:58:07 PM PDT 24 13417291 ps
T1309 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1532556499 Aug 10 05:58:12 PM PDT 24 Aug 10 05:58:13 PM PDT 24 32950499 ps
T1310 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.4133498578 Aug 10 05:58:04 PM PDT 24 Aug 10 05:58:05 PM PDT 24 57855498 ps
T1311 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.16802291 Aug 10 05:58:17 PM PDT 24 Aug 10 05:58:18 PM PDT 24 20287850 ps
T1312 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.282616490 Aug 10 05:58:24 PM PDT 24 Aug 10 05:58:25 PM PDT 24 26280240 ps
T1313 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.4154680602 Aug 10 05:58:24 PM PDT 24 Aug 10 05:58:25 PM PDT 24 16246314 ps
T1314 /workspace/coverage/cover_reg_top/4.uart_intr_test.2472884923 Aug 10 05:58:10 PM PDT 24 Aug 10 05:58:10 PM PDT 24 43276439 ps
T1315 /workspace/coverage/cover_reg_top/17.uart_tl_errors.871053014 Aug 10 05:58:26 PM PDT 24 Aug 10 05:58:27 PM PDT 24 53517397 ps

Test location /workspace/coverage/default/1.uart_intr.4252004645
Short name T10
Test name
Test status
Simulation time 27842472730 ps
CPU time 54.24 seconds
Started Aug 10 06:08:36 PM PDT 24
Finished Aug 10 06:09:30 PM PDT 24
Peak memory 199912 kb
Host smart-64913d47-9c79-42b0-b2f4-354aed2ad7a6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252004645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.4252004645
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1337946532
Short name T32
Test name
Test status
Simulation time 272448293845 ps
CPU time 698.08 seconds
Started Aug 10 06:13:37 PM PDT 24
Finished Aug 10 06:25:16 PM PDT 24
Peak memory 216312 kb
Host smart-d6840e31-e88f-4100-902d-50290e5d0afb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337946532 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1337946532
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_stress_all.3124054198
Short name T14
Test name
Test status
Simulation time 324692720299 ps
CPU time 1001.48 seconds
Started Aug 10 06:13:08 PM PDT 24
Finished Aug 10 06:29:50 PM PDT 24
Peak memory 200020 kb
Host smart-c6793da1-1c54-4501-95c5-eda4ceb2d9d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124054198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.3124054198
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.4229186648
Short name T20
Test name
Test status
Simulation time 111149255239 ps
CPU time 1485.02 seconds
Started Aug 10 06:14:35 PM PDT 24
Finished Aug 10 06:39:21 PM PDT 24
Peak memory 232200 kb
Host smart-3298ed68-b8a8-467d-98ab-90fb3b789537
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229186648 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.4229186648
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_noise_filter.673665006
Short name T3
Test name
Test status
Simulation time 144465857843 ps
CPU time 111.5 seconds
Started Aug 10 06:11:49 PM PDT 24
Finished Aug 10 06:13:41 PM PDT 24
Peak memory 199092 kb
Host smart-106e429b-407d-491d-ac48-253e7a40fa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673665006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.673665006
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1082786462
Short name T29
Test name
Test status
Simulation time 111998352185 ps
CPU time 860.86 seconds
Started Aug 10 06:14:42 PM PDT 24
Finished Aug 10 06:29:03 PM PDT 24
Peak memory 216556 kb
Host smart-08ebebe1-d3ac-417c-baec-0da18c2d1e67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082786462 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1082786462
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.3523350518
Short name T53
Test name
Test status
Simulation time 79846509063 ps
CPU time 687.39 seconds
Started Aug 10 06:14:08 PM PDT 24
Finished Aug 10 06:25:36 PM PDT 24
Peak memory 216600 kb
Host smart-e360a453-76cf-4f4a-a6c8-dec0ed2aa0f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523350518 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.3523350518
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_stress_all.2999879794
Short name T43
Test name
Test status
Simulation time 328265263537 ps
CPU time 258.63 seconds
Started Aug 10 06:09:18 PM PDT 24
Finished Aug 10 06:13:37 PM PDT 24
Peak memory 208188 kb
Host smart-cad2258c-bd22-42dd-adef-5dec7d3334e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999879794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2999879794
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.799770449
Short name T142
Test name
Test status
Simulation time 275713032880 ps
CPU time 2218.77 seconds
Started Aug 10 06:12:08 PM PDT 24
Finished Aug 10 06:49:07 PM PDT 24
Peak memory 232944 kb
Host smart-d5c02504-4ce5-4347-8829-0f4fcb650116
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799770449 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.799770449
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1702453292
Short name T85
Test name
Test status
Simulation time 124309992 ps
CPU time 1.19 seconds
Started Aug 10 05:58:11 PM PDT 24
Finished Aug 10 05:58:13 PM PDT 24
Peak memory 199616 kb
Host smart-b4279a77-d159-4332-a6c6-9e60459dbc3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702453292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1702453292
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/default/11.uart_alert_test.3370534544
Short name T372
Test name
Test status
Simulation time 13413627 ps
CPU time 0.55 seconds
Started Aug 10 06:10:30 PM PDT 24
Finished Aug 10 06:10:31 PM PDT 24
Peak memory 195644 kb
Host smart-74955a78-40c0-40c9-9c1b-06bdad82374e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370534544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3370534544
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2496558273
Short name T119
Test name
Test status
Simulation time 226005743213 ps
CPU time 722.35 seconds
Started Aug 10 06:11:48 PM PDT 24
Finished Aug 10 06:23:51 PM PDT 24
Peak memory 214724 kb
Host smart-431742a0-c82f-498b-a849-7fb956286d36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496558273 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2496558273
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1881729378
Short name T145
Test name
Test status
Simulation time 1964541857795 ps
CPU time 1736.13 seconds
Started Aug 10 06:14:49 PM PDT 24
Finished Aug 10 06:43:45 PM PDT 24
Peak memory 232928 kb
Host smart-c356445d-467f-43c1-b7fc-ed1bf986a006
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881729378 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1881729378
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.337677784
Short name T288
Test name
Test status
Simulation time 125349350929 ps
CPU time 190.5 seconds
Started Aug 10 06:10:12 PM PDT 24
Finished Aug 10 06:13:23 PM PDT 24
Peak memory 199904 kb
Host smart-d4f4915b-a681-4112-8e85-4475f5a282a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=337677784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.337677784
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_stress_all.2667752473
Short name T151
Test name
Test status
Simulation time 439688122427 ps
CPU time 248.07 seconds
Started Aug 10 06:11:29 PM PDT 24
Finished Aug 10 06:15:38 PM PDT 24
Peak memory 208224 kb
Host smart-8716c51a-fdfe-45c2-aab7-d1170aee23cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667752473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2667752473
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.4231054640
Short name T236
Test name
Test status
Simulation time 117054924117 ps
CPU time 137.46 seconds
Started Aug 10 06:15:24 PM PDT 24
Finished Aug 10 06:17:42 PM PDT 24
Peak memory 199936 kb
Host smart-5a34ed1b-d7cc-43eb-a0ff-37cdee0e4b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231054640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.4231054640
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1659471688
Short name T26
Test name
Test status
Simulation time 283208062 ps
CPU time 0.77 seconds
Started Aug 10 06:08:28 PM PDT 24
Finished Aug 10 06:08:29 PM PDT 24
Peak memory 218332 kb
Host smart-a59faf6c-e646-40ec-8f83-53c4efc2372c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659471688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1659471688
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.880088527
Short name T279
Test name
Test status
Simulation time 124098432141 ps
CPU time 1575.27 seconds
Started Aug 10 06:11:38 PM PDT 24
Finished Aug 10 06:37:53 PM PDT 24
Peak memory 216556 kb
Host smart-2acaff64-899a-408b-b32a-8f355ad792c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880088527 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.880088527
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3115025292
Short name T50
Test name
Test status
Simulation time 294065593213 ps
CPU time 179.75 seconds
Started Aug 10 06:10:19 PM PDT 24
Finished Aug 10 06:13:18 PM PDT 24
Peak memory 199840 kb
Host smart-49b4eb03-5f58-4811-b386-6225775c0a2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3115025292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3115025292
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_stress_all.2004533104
Short name T48
Test name
Test status
Simulation time 275752036389 ps
CPU time 338.76 seconds
Started Aug 10 06:12:11 PM PDT 24
Finished Aug 10 06:17:50 PM PDT 24
Peak memory 199500 kb
Host smart-aeb6c6c3-b3d9-46ff-9058-d94353491389
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004533104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2004533104
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.2815167287
Short name T8
Test name
Test status
Simulation time 25345516163 ps
CPU time 32.58 seconds
Started Aug 10 06:15:10 PM PDT 24
Finished Aug 10 06:15:43 PM PDT 24
Peak memory 199968 kb
Host smart-2968f503-d237-449a-a7db-d697642f8f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815167287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2815167287
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3153017917
Short name T63
Test name
Test status
Simulation time 23846524 ps
CPU time 0.6 seconds
Started Aug 10 05:58:23 PM PDT 24
Finished Aug 10 05:58:24 PM PDT 24
Peak memory 195784 kb
Host smart-1b21c97d-eddd-4880-9157-24306577b58e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153017917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3153017917
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/default/17.uart_stress_all.563846222
Short name T454
Test name
Test status
Simulation time 157146082866 ps
CPU time 540.62 seconds
Started Aug 10 06:11:09 PM PDT 24
Finished Aug 10 06:20:10 PM PDT 24
Peak memory 208284 kb
Host smart-3963a6d4-dfc7-4dac-b745-76dcd11dfb6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563846222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.563846222
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3894925916
Short name T39
Test name
Test status
Simulation time 146072766780 ps
CPU time 56.3 seconds
Started Aug 10 06:16:08 PM PDT 24
Finished Aug 10 06:17:04 PM PDT 24
Peak memory 199976 kb
Host smart-0db78a06-a031-4b06-be3a-bd46b7292b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894925916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3894925916
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.4274867845
Short name T268
Test name
Test status
Simulation time 144341085228 ps
CPU time 203.5 seconds
Started Aug 10 06:10:59 PM PDT 24
Finished Aug 10 06:14:23 PM PDT 24
Peak memory 199940 kb
Host smart-9da2114c-ba6c-4917-9dc9-88164838e7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274867845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.4274867845
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1054710519
Short name T41
Test name
Test status
Simulation time 70477209144 ps
CPU time 41.46 seconds
Started Aug 10 06:14:35 PM PDT 24
Finished Aug 10 06:15:16 PM PDT 24
Peak memory 199840 kb
Host smart-fea18fd8-e2cc-41fc-b651-e6bd6d93e190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054710519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1054710519
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.236474352
Short name T270
Test name
Test status
Simulation time 243470842335 ps
CPU time 372.99 seconds
Started Aug 10 06:09:02 PM PDT 24
Finished Aug 10 06:15:15 PM PDT 24
Peak memory 199956 kb
Host smart-016c2904-0b1f-4f0a-9667-6dc859fc0976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236474352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.236474352
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1948855706
Short name T194
Test name
Test status
Simulation time 153685400430 ps
CPU time 370.22 seconds
Started Aug 10 06:15:11 PM PDT 24
Finished Aug 10 06:21:21 PM PDT 24
Peak memory 199876 kb
Host smart-1c23ea05-66a9-4279-9ca0-34f75f81c786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948855706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1948855706
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1125241641
Short name T28
Test name
Test status
Simulation time 88219433997 ps
CPU time 841.81 seconds
Started Aug 10 06:09:38 PM PDT 24
Finished Aug 10 06:23:40 PM PDT 24
Peak memory 216508 kb
Host smart-efe8d2aa-cd24-4d3b-83ac-fc59d97f0958
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125241641 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1125241641
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3811676603
Short name T281
Test name
Test status
Simulation time 139156374559 ps
CPU time 104.99 seconds
Started Aug 10 06:11:36 PM PDT 24
Finished Aug 10 06:13:21 PM PDT 24
Peak memory 200108 kb
Host smart-b5217e2f-d2bf-48f2-9462-5a519de103e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811676603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3811676603
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3616310986
Short name T144
Test name
Test status
Simulation time 35961863347 ps
CPU time 33.81 seconds
Started Aug 10 06:09:40 PM PDT 24
Finished Aug 10 06:10:14 PM PDT 24
Peak memory 199892 kb
Host smart-a3312c2b-7d97-4fc8-9cf8-c20dc32b4194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616310986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3616310986
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.3198757506
Short name T62
Test name
Test status
Simulation time 79557575552 ps
CPU time 254.36 seconds
Started Aug 10 06:14:35 PM PDT 24
Finished Aug 10 06:18:49 PM PDT 24
Peak memory 216644 kb
Host smart-003bddd1-e193-4a81-b85f-610c655b2acc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198757506 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3198757506
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2840795488
Short name T88
Test name
Test status
Simulation time 196706549 ps
CPU time 1.35 seconds
Started Aug 10 05:58:21 PM PDT 24
Finished Aug 10 05:58:22 PM PDT 24
Peak memory 199524 kb
Host smart-7cbea702-8c05-4971-9e12-7789a91cb55a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840795488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2840795488
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2711481415
Short name T283
Test name
Test status
Simulation time 37293240747 ps
CPU time 67.75 seconds
Started Aug 10 06:15:49 PM PDT 24
Finished Aug 10 06:16:56 PM PDT 24
Peak memory 199860 kb
Host smart-9cc1ead8-1ee7-4631-9d4c-65661c0500a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711481415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2711481415
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all.131331682
Short name T246
Test name
Test status
Simulation time 314504214484 ps
CPU time 445.96 seconds
Started Aug 10 06:08:37 PM PDT 24
Finished Aug 10 06:16:03 PM PDT 24
Peak memory 200220 kb
Host smart-beee47be-e518-4314-bf25-2a200a98c653
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131331682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.131331682
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.149753965
Short name T345
Test name
Test status
Simulation time 40151841217 ps
CPU time 8.72 seconds
Started Aug 10 06:15:35 PM PDT 24
Finished Aug 10 06:15:43 PM PDT 24
Peak memory 199908 kb
Host smart-3061cf7f-e465-4a27-8c69-defe054df957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149753965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.149753965
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.225850653
Short name T168
Test name
Test status
Simulation time 54573456938 ps
CPU time 252.74 seconds
Started Aug 10 06:15:44 PM PDT 24
Finished Aug 10 06:19:57 PM PDT 24
Peak memory 199968 kb
Host smart-602a7194-b1df-4dbb-a254-210f5081700a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225850653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.225850653
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.3783508013
Short name T340
Test name
Test status
Simulation time 243423060060 ps
CPU time 1117.63 seconds
Started Aug 10 06:14:58 PM PDT 24
Finished Aug 10 06:33:36 PM PDT 24
Peak memory 231252 kb
Host smart-3829ac6b-ded5-4b33-82bf-7105eaefec19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783508013 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.3783508013
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.4250684975
Short name T298
Test name
Test status
Simulation time 29106994889 ps
CPU time 16.12 seconds
Started Aug 10 06:08:25 PM PDT 24
Finished Aug 10 06:08:41 PM PDT 24
Peak memory 199904 kb
Host smart-ebd61a2f-85cb-4599-9e02-af1ef03fcce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250684975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.4250684975
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.1888517373
Short name T243
Test name
Test status
Simulation time 193259200656 ps
CPU time 79.65 seconds
Started Aug 10 06:15:05 PM PDT 24
Finished Aug 10 06:16:25 PM PDT 24
Peak memory 200004 kb
Host smart-89de468c-b413-4fec-b85d-8541f39e243f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888517373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1888517373
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.1831968302
Short name T234
Test name
Test status
Simulation time 37537558296 ps
CPU time 15.6 seconds
Started Aug 10 06:15:34 PM PDT 24
Finished Aug 10 06:15:50 PM PDT 24
Peak memory 199912 kb
Host smart-4b5a7323-f57e-4b40-b65f-ee1f6c0f43a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831968302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1831968302
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_stress_all.2368570761
Short name T207
Test name
Test status
Simulation time 160302882273 ps
CPU time 379.54 seconds
Started Aug 10 06:14:11 PM PDT 24
Finished Aug 10 06:20:30 PM PDT 24
Peak memory 208312 kb
Host smart-8b5a49e8-7840-4fe4-8b5a-8d650f48f30a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368570761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2368570761
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.1967774926
Short name T239
Test name
Test status
Simulation time 116593355746 ps
CPU time 188.52 seconds
Started Aug 10 06:14:56 PM PDT 24
Finished Aug 10 06:18:05 PM PDT 24
Peak memory 199904 kb
Host smart-6a9429b8-6626-45fd-8303-2831552f9f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967774926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1967774926
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.3569464928
Short name T56
Test name
Test status
Simulation time 852235207240 ps
CPU time 1313.37 seconds
Started Aug 10 06:10:26 PM PDT 24
Finished Aug 10 06:32:19 PM PDT 24
Peak memory 225900 kb
Host smart-3f3a43c9-93d7-49df-955e-4c745ccb3b2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569464928 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.3569464928
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2706949329
Short name T227
Test name
Test status
Simulation time 87995466985 ps
CPU time 31.77 seconds
Started Aug 10 06:16:13 PM PDT 24
Finished Aug 10 06:16:45 PM PDT 24
Peak memory 199680 kb
Host smart-0a8df2c9-264d-4718-bd9e-0592495190e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706949329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2706949329
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.4282877994
Short name T764
Test name
Test status
Simulation time 98184660895 ps
CPU time 36.98 seconds
Started Aug 10 06:14:01 PM PDT 24
Finished Aug 10 06:14:38 PM PDT 24
Peak memory 199908 kb
Host smart-f2e46acd-12ee-49e9-a207-b2e881d0a17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282877994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.4282877994
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3305476987
Short name T143
Test name
Test status
Simulation time 150945641517 ps
CPU time 234.21 seconds
Started Aug 10 06:15:04 PM PDT 24
Finished Aug 10 06:18:58 PM PDT 24
Peak memory 199900 kb
Host smart-ffe27d48-b0cb-4394-820a-51ffb493f40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305476987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3305476987
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2767084455
Short name T170
Test name
Test status
Simulation time 31707132161 ps
CPU time 30.39 seconds
Started Aug 10 06:10:30 PM PDT 24
Finished Aug 10 06:11:01 PM PDT 24
Peak memory 199976 kb
Host smart-7e8d3127-baaa-41e8-ab69-aab10cc45653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767084455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2767084455
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.1026800439
Short name T205
Test name
Test status
Simulation time 22707520826 ps
CPU time 76.46 seconds
Started Aug 10 06:15:17 PM PDT 24
Finished Aug 10 06:16:33 PM PDT 24
Peak memory 199916 kb
Host smart-87f4944a-1b6c-4a68-a9ea-bc6e8d84e294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026800439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1026800439
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all.3708352771
Short name T219
Test name
Test status
Simulation time 306656003826 ps
CPU time 712.53 seconds
Started Aug 10 06:10:50 PM PDT 24
Finished Aug 10 06:22:43 PM PDT 24
Peak memory 200144 kb
Host smart-da861b13-5df6-43d1-8367-677a362ccd86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708352771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3708352771
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3298031300
Short name T196
Test name
Test status
Simulation time 16967734798 ps
CPU time 26.08 seconds
Started Aug 10 06:15:25 PM PDT 24
Finished Aug 10 06:15:52 PM PDT 24
Peak memory 199856 kb
Host smart-fb9da7a6-059d-4782-8ae1-ed64e261c638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298031300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3298031300
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.524217817
Short name T286
Test name
Test status
Simulation time 24334320989 ps
CPU time 39.51 seconds
Started Aug 10 06:15:37 PM PDT 24
Finished Aug 10 06:16:16 PM PDT 24
Peak memory 199908 kb
Host smart-c8bd06c2-b326-40c2-b660-53f1915462ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524217817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.524217817
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_stress_all.3078804535
Short name T171
Test name
Test status
Simulation time 628411000777 ps
CPU time 601.91 seconds
Started Aug 10 06:11:18 PM PDT 24
Finished Aug 10 06:21:20 PM PDT 24
Peak memory 199928 kb
Host smart-95faaf66-338d-4af7-8d6a-d4d494c4bc03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078804535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3078804535
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.937017436
Short name T174
Test name
Test status
Simulation time 48504301009 ps
CPU time 21.55 seconds
Started Aug 10 06:15:50 PM PDT 24
Finished Aug 10 06:16:12 PM PDT 24
Peak memory 199896 kb
Host smart-969acffa-74f9-4d91-b989-2690ad7d5fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937017436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.937017436
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2444408558
Short name T213
Test name
Test status
Simulation time 286759604574 ps
CPU time 46.95 seconds
Started Aug 10 06:16:15 PM PDT 24
Finished Aug 10 06:17:02 PM PDT 24
Peak memory 199968 kb
Host smart-5094773f-88cb-4e1d-be4d-fbf48a3e8dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444408558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2444408558
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1053242027
Short name T192
Test name
Test status
Simulation time 42012621082 ps
CPU time 64.59 seconds
Started Aug 10 06:16:26 PM PDT 24
Finished Aug 10 06:17:31 PM PDT 24
Peak memory 199916 kb
Host smart-cd1b8465-30d4-4afd-ba9b-85bd55dbc20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053242027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1053242027
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_noise_filter.3816057152
Short name T350
Test name
Test status
Simulation time 144660640827 ps
CPU time 113.74 seconds
Started Aug 10 06:14:11 PM PDT 24
Finished Aug 10 06:16:05 PM PDT 24
Peak memory 200064 kb
Host smart-8555d286-59c7-4e90-ad13-274a1a87f5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816057152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.3816057152
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.698670216
Short name T1151
Test name
Test status
Simulation time 26362851380 ps
CPU time 40.79 seconds
Started Aug 10 06:10:12 PM PDT 24
Finished Aug 10 06:10:52 PM PDT 24
Peak memory 199756 kb
Host smart-c5977072-20bd-4dbb-8862-a04b1ccc984a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698670216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.698670216
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3086130993
Short name T982
Test name
Test status
Simulation time 76244103851 ps
CPU time 115.21 seconds
Started Aug 10 06:15:03 PM PDT 24
Finished Aug 10 06:16:58 PM PDT 24
Peak memory 199916 kb
Host smart-a06ed06c-e191-44f2-8e54-8da786975162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086130993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3086130993
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1987403739
Short name T250
Test name
Test status
Simulation time 22643886988 ps
CPU time 29.85 seconds
Started Aug 10 06:15:11 PM PDT 24
Finished Aug 10 06:15:41 PM PDT 24
Peak memory 199988 kb
Host smart-6ca31b38-b69f-4791-b9fa-578bc5c17268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987403739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1987403739
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.3463199918
Short name T231
Test name
Test status
Simulation time 15546027189 ps
CPU time 27.62 seconds
Started Aug 10 06:15:12 PM PDT 24
Finished Aug 10 06:15:39 PM PDT 24
Peak memory 199864 kb
Host smart-340513f7-aad6-4924-b5b1-82830661c4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463199918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3463199918
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1135113064
Short name T247
Test name
Test status
Simulation time 106605088328 ps
CPU time 53.53 seconds
Started Aug 10 06:15:22 PM PDT 24
Finished Aug 10 06:16:16 PM PDT 24
Peak memory 199980 kb
Host smart-5751d76c-d80c-4289-86b7-8bba576b50f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135113064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1135113064
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2338213263
Short name T232
Test name
Test status
Simulation time 79143033836 ps
CPU time 131.36 seconds
Started Aug 10 06:15:35 PM PDT 24
Finished Aug 10 06:17:46 PM PDT 24
Peak memory 199912 kb
Host smart-14672e6c-efa9-4acd-913c-3de8897b976d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338213263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2338213263
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.366223308
Short name T164
Test name
Test status
Simulation time 81056851482 ps
CPU time 36.85 seconds
Started Aug 10 06:11:02 PM PDT 24
Finished Aug 10 06:11:39 PM PDT 24
Peak memory 199956 kb
Host smart-c45a9cd6-61b8-40ef-896c-7704f3a7cec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366223308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.366223308
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.2593824077
Short name T1068
Test name
Test status
Simulation time 42739513806 ps
CPU time 131.54 seconds
Started Aug 10 06:15:41 PM PDT 24
Finished Aug 10 06:17:53 PM PDT 24
Peak memory 199912 kb
Host smart-7bf37c3d-348b-4366-bfac-69334a40ea8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593824077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2593824077
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.805947394
Short name T185
Test name
Test status
Simulation time 52403678292 ps
CPU time 81.74 seconds
Started Aug 10 06:15:41 PM PDT 24
Finished Aug 10 06:17:03 PM PDT 24
Peak memory 199904 kb
Host smart-7281d43d-e295-40ad-9d8a-838173b85ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805947394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.805947394
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.2708764000
Short name T136
Test name
Test status
Simulation time 200500787226 ps
CPU time 148.06 seconds
Started Aug 10 06:16:16 PM PDT 24
Finished Aug 10 06:18:44 PM PDT 24
Peak memory 199916 kb
Host smart-a3a47531-3b9b-4705-b40e-a392378c6b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708764000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2708764000
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.4093027242
Short name T244
Test name
Test status
Simulation time 25082094819 ps
CPU time 44.28 seconds
Started Aug 10 06:16:23 PM PDT 24
Finished Aug 10 06:17:08 PM PDT 24
Peak memory 199896 kb
Host smart-48a79228-0c4c-4fd6-ba2a-b6aaba2132f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093027242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.4093027242
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1295820486
Short name T251
Test name
Test status
Simulation time 23114315171 ps
CPU time 40.59 seconds
Started Aug 10 06:12:40 PM PDT 24
Finished Aug 10 06:13:21 PM PDT 24
Peak memory 199728 kb
Host smart-baeafb46-0dfb-4c1a-a9f2-e5211a0165c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295820486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1295820486
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3763594372
Short name T238
Test name
Test status
Simulation time 62727577729 ps
CPU time 25.28 seconds
Started Aug 10 06:13:00 PM PDT 24
Finished Aug 10 06:13:25 PM PDT 24
Peak memory 199968 kb
Host smart-9f34cec9-ad71-458f-b415-13d776605c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763594372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3763594372
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3683194727
Short name T242
Test name
Test status
Simulation time 48258905301 ps
CPU time 20.17 seconds
Started Aug 10 06:14:16 PM PDT 24
Finished Aug 10 06:14:36 PM PDT 24
Peak memory 199920 kb
Host smart-ef0f009c-d518-4286-8c13-a020e031f4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683194727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3683194727
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3081431131
Short name T245
Test name
Test status
Simulation time 49483655182 ps
CPU time 41.26 seconds
Started Aug 10 06:14:30 PM PDT 24
Finished Aug 10 06:15:12 PM PDT 24
Peak memory 199856 kb
Host smart-1020f9bb-c820-436d-830f-af377e94c2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081431131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3081431131
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.195362090
Short name T253
Test name
Test status
Simulation time 21752258551 ps
CPU time 10.04 seconds
Started Aug 10 06:14:41 PM PDT 24
Finished Aug 10 06:14:52 PM PDT 24
Peak memory 199688 kb
Host smart-8f33733e-bf6d-4fc7-bb78-154dd73f761b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195362090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.195362090
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.150740145
Short name T1296
Test name
Test status
Simulation time 93350023 ps
CPU time 0.77 seconds
Started Aug 10 05:58:23 PM PDT 24
Finished Aug 10 05:58:24 PM PDT 24
Peak memory 196840 kb
Host smart-ae7a6591-554a-4ae0-ade6-c1068d014b05
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150740145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.150740145
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.371956516
Short name T1213
Test name
Test status
Simulation time 922887545 ps
CPU time 2.4 seconds
Started Aug 10 05:58:06 PM PDT 24
Finished Aug 10 05:58:08 PM PDT 24
Peak memory 198396 kb
Host smart-526a4a10-41b7-4779-9494-d197f837e4bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371956516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.371956516
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1879003397
Short name T1220
Test name
Test status
Simulation time 20208505 ps
CPU time 0.58 seconds
Started Aug 10 05:58:03 PM PDT 24
Finished Aug 10 05:58:04 PM PDT 24
Peak memory 195832 kb
Host smart-502ebcbf-09d5-4c49-b04a-213e2b89d73c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879003397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1879003397
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3637054690
Short name T1292
Test name
Test status
Simulation time 21474998 ps
CPU time 0.72 seconds
Started Aug 10 05:58:03 PM PDT 24
Finished Aug 10 05:58:04 PM PDT 24
Peak memory 198712 kb
Host smart-dcd3e31d-ffca-4168-9cd2-f9be9d773d2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637054690 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3637054690
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.4277183438
Short name T72
Test name
Test status
Simulation time 27264748 ps
CPU time 0.55 seconds
Started Aug 10 05:58:04 PM PDT 24
Finished Aug 10 05:58:05 PM PDT 24
Peak memory 195932 kb
Host smart-ff7f51a4-8207-48d3-9388-6c358d26afa2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277183438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.4277183438
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.654452166
Short name T1247
Test name
Test status
Simulation time 14661242 ps
CPU time 0.6 seconds
Started Aug 10 05:58:06 PM PDT 24
Finished Aug 10 05:58:07 PM PDT 24
Peak memory 194860 kb
Host smart-087bf5dc-746b-451b-b18b-d458184ba822
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654452166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.654452166
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.17258869
Short name T1231
Test name
Test status
Simulation time 18583008 ps
CPU time 0.64 seconds
Started Aug 10 05:58:02 PM PDT 24
Finished Aug 10 05:58:03 PM PDT 24
Peak memory 195876 kb
Host smart-0eb2e27f-6a94-42d2-adfa-596940964085
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17258869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_o
utstanding.17258869
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3223125035
Short name T1192
Test name
Test status
Simulation time 636192189 ps
CPU time 2.2 seconds
Started Aug 10 05:58:04 PM PDT 24
Finished Aug 10 05:58:07 PM PDT 24
Peak memory 200500 kb
Host smart-11167e38-407a-4875-a4b9-48bfafedf5cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223125035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3223125035
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2476295239
Short name T1286
Test name
Test status
Simulation time 547875292 ps
CPU time 1.3 seconds
Started Aug 10 05:58:02 PM PDT 24
Finished Aug 10 05:58:04 PM PDT 24
Peak memory 199728 kb
Host smart-4a8390ef-5006-4ea4-bdfc-1250668afec0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476295239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2476295239
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2090211217
Short name T1262
Test name
Test status
Simulation time 41852623 ps
CPU time 0.7 seconds
Started Aug 10 05:58:03 PM PDT 24
Finished Aug 10 05:58:04 PM PDT 24
Peak memory 195288 kb
Host smart-98e3405d-29f1-4499-91dd-0e5f84536d61
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090211217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2090211217
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3059737338
Short name T1187
Test name
Test status
Simulation time 56847135 ps
CPU time 2.15 seconds
Started Aug 10 05:58:03 PM PDT 24
Finished Aug 10 05:58:05 PM PDT 24
Peak memory 198312 kb
Host smart-9b582213-9016-4575-a297-be092937d1a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059737338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3059737338
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.268698998
Short name T1203
Test name
Test status
Simulation time 45647978 ps
CPU time 0.61 seconds
Started Aug 10 05:58:04 PM PDT 24
Finished Aug 10 05:58:05 PM PDT 24
Peak memory 195824 kb
Host smart-2168e2b6-875f-46d0-8aab-096b674dd79d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268698998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.268698998
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.4133498578
Short name T1310
Test name
Test status
Simulation time 57855498 ps
CPU time 0.84 seconds
Started Aug 10 05:58:04 PM PDT 24
Finished Aug 10 05:58:05 PM PDT 24
Peak memory 200232 kb
Host smart-93e8496e-49a2-42f8-99f2-3c610fbabd31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133498578 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.4133498578
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3794314955
Short name T1285
Test name
Test status
Simulation time 139509038 ps
CPU time 0.58 seconds
Started Aug 10 05:58:05 PM PDT 24
Finished Aug 10 05:58:06 PM PDT 24
Peak memory 195808 kb
Host smart-abb2a319-6c72-440b-b73a-a17f4fce7e6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794314955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3794314955
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.4118157836
Short name T1308
Test name
Test status
Simulation time 13417291 ps
CPU time 0.57 seconds
Started Aug 10 05:58:07 PM PDT 24
Finished Aug 10 05:58:07 PM PDT 24
Peak memory 194812 kb
Host smart-f4ed6814-7c15-488e-a07c-8ffe83072470
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118157836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.4118157836
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.102041376
Short name T1245
Test name
Test status
Simulation time 19851622 ps
CPU time 0.63 seconds
Started Aug 10 05:58:06 PM PDT 24
Finished Aug 10 05:58:07 PM PDT 24
Peak memory 195012 kb
Host smart-06783806-1e8a-42b5-9f3a-502e0b189421
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102041376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_
outstanding.102041376
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1465828043
Short name T1209
Test name
Test status
Simulation time 79291214 ps
CPU time 1.14 seconds
Started Aug 10 05:58:11 PM PDT 24
Finished Aug 10 05:58:13 PM PDT 24
Peak memory 200416 kb
Host smart-b933587c-ab13-4c6b-921f-e607018495cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465828043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1465828043
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1816882525
Short name T1219
Test name
Test status
Simulation time 23013486 ps
CPU time 0.8 seconds
Started Aug 10 05:58:30 PM PDT 24
Finished Aug 10 05:58:31 PM PDT 24
Peak memory 199392 kb
Host smart-d4555bc7-2cde-4883-a18b-550d6279ffbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816882525 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1816882525
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.83132947
Short name T78
Test name
Test status
Simulation time 94894863 ps
CPU time 0.6 seconds
Started Aug 10 05:58:25 PM PDT 24
Finished Aug 10 05:58:26 PM PDT 24
Peak memory 195924 kb
Host smart-8db0ea0e-b894-4ee1-9aaf-dabfe82c06b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83132947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.83132947
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.966128020
Short name T1210
Test name
Test status
Simulation time 14945744 ps
CPU time 0.57 seconds
Started Aug 10 05:58:18 PM PDT 24
Finished Aug 10 05:58:19 PM PDT 24
Peak memory 194816 kb
Host smart-2176a7b3-e8bb-4f1d-9179-16fd503a2590
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966128020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.966128020
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2747632269
Short name T1216
Test name
Test status
Simulation time 50914439 ps
CPU time 0.78 seconds
Started Aug 10 05:58:23 PM PDT 24
Finished Aug 10 05:58:24 PM PDT 24
Peak memory 198160 kb
Host smart-21b18ce9-7b5a-47f0-9b2e-5f916c010b43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747632269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2747632269
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3845771177
Short name T1222
Test name
Test status
Simulation time 949314364 ps
CPU time 2.05 seconds
Started Aug 10 05:58:19 PM PDT 24
Finished Aug 10 05:58:21 PM PDT 24
Peak memory 200448 kb
Host smart-a2e7199c-ef2e-46ca-b57c-9f709bcc2df0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845771177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3845771177
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1717419886
Short name T90
Test name
Test status
Simulation time 261998557 ps
CPU time 1.27 seconds
Started Aug 10 05:58:27 PM PDT 24
Finished Aug 10 05:58:28 PM PDT 24
Peak memory 199820 kb
Host smart-30eb22f9-3ab5-4ab5-97d4-66bb8cc01f9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717419886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1717419886
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1982910139
Short name T1184
Test name
Test status
Simulation time 92185430 ps
CPU time 0.86 seconds
Started Aug 10 05:58:32 PM PDT 24
Finished Aug 10 05:58:33 PM PDT 24
Peak memory 200168 kb
Host smart-dbd01149-3555-4ed9-bee3-e90a117ef479
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982910139 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1982910139
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2587331232
Short name T66
Test name
Test status
Simulation time 22229855 ps
CPU time 0.58 seconds
Started Aug 10 05:58:19 PM PDT 24
Finished Aug 10 05:58:20 PM PDT 24
Peak memory 195780 kb
Host smart-5b4d7984-be8e-4188-b285-dbc79e949eb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587331232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2587331232
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1666043596
Short name T1188
Test name
Test status
Simulation time 15342851 ps
CPU time 0.55 seconds
Started Aug 10 05:58:24 PM PDT 24
Finished Aug 10 05:58:25 PM PDT 24
Peak memory 194808 kb
Host smart-f5c74a11-d6fb-4770-bc4c-65f34c213bbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666043596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1666043596
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2915432119
Short name T76
Test name
Test status
Simulation time 20534998 ps
CPU time 0.64 seconds
Started Aug 10 05:58:27 PM PDT 24
Finished Aug 10 05:58:28 PM PDT 24
Peak memory 195916 kb
Host smart-979a53d7-2933-4605-ba37-d1675f6381c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915432119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.2915432119
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.2219188833
Short name T1206
Test name
Test status
Simulation time 63969393 ps
CPU time 1.43 seconds
Started Aug 10 05:58:25 PM PDT 24
Finished Aug 10 05:58:27 PM PDT 24
Peak memory 200400 kb
Host smart-63a88a32-40a6-42de-afd2-dc88d254703d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219188833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2219188833
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2307104446
Short name T1281
Test name
Test status
Simulation time 418795716 ps
CPU time 0.91 seconds
Started Aug 10 05:58:23 PM PDT 24
Finished Aug 10 05:58:24 PM PDT 24
Peak memory 199412 kb
Host smart-750b9d41-5781-4ddb-878f-c2b9331e34cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307104446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2307104446
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3604845031
Short name T1294
Test name
Test status
Simulation time 117125267 ps
CPU time 1.33 seconds
Started Aug 10 05:58:26 PM PDT 24
Finished Aug 10 05:58:28 PM PDT 24
Peak memory 200508 kb
Host smart-09705e1e-ce05-4112-8078-37392bca8e45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604845031 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3604845031
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.3528605619
Short name T1304
Test name
Test status
Simulation time 169457631 ps
CPU time 0.6 seconds
Started Aug 10 05:58:27 PM PDT 24
Finished Aug 10 05:58:28 PM PDT 24
Peak memory 196040 kb
Host smart-1031ddac-efdb-48a9-a043-6b54c7700b31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528605619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3528605619
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3826612736
Short name T1236
Test name
Test status
Simulation time 38974629 ps
CPU time 0.58 seconds
Started Aug 10 05:58:20 PM PDT 24
Finished Aug 10 05:58:21 PM PDT 24
Peak memory 194704 kb
Host smart-cf74e81e-8a66-4c66-a4ae-1d0784864a4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826612736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3826612736
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2176055487
Short name T1280
Test name
Test status
Simulation time 18671832 ps
CPU time 0.71 seconds
Started Aug 10 05:58:25 PM PDT 24
Finished Aug 10 05:58:26 PM PDT 24
Peak memory 196880 kb
Host smart-59b206dd-3497-4a78-8de2-707f0e98273c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176055487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2176055487
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1629074527
Short name T1218
Test name
Test status
Simulation time 40892489 ps
CPU time 1.13 seconds
Started Aug 10 05:58:28 PM PDT 24
Finished Aug 10 05:58:29 PM PDT 24
Peak memory 200300 kb
Host smart-ef3bd74e-95f6-4035-a658-17256ca25e82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629074527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1629074527
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2508705802
Short name T1248
Test name
Test status
Simulation time 90429167 ps
CPU time 1.28 seconds
Started Aug 10 05:58:24 PM PDT 24
Finished Aug 10 05:58:26 PM PDT 24
Peak memory 199792 kb
Host smart-abdcd7a4-1150-44a5-acfc-c85576595aa4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508705802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2508705802
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2070687203
Short name T1270
Test name
Test status
Simulation time 18231206 ps
CPU time 0.68 seconds
Started Aug 10 05:58:24 PM PDT 24
Finished Aug 10 05:58:25 PM PDT 24
Peak memory 197972 kb
Host smart-d21a9578-5543-4a8e-aff9-394cd5093b4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070687203 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2070687203
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1586524953
Short name T68
Test name
Test status
Simulation time 19762591 ps
CPU time 0.58 seconds
Started Aug 10 05:58:25 PM PDT 24
Finished Aug 10 05:58:26 PM PDT 24
Peak memory 195840 kb
Host smart-b53bc528-2ded-4b9c-a1be-aa79af8eaffc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586524953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1586524953
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.544282947
Short name T1255
Test name
Test status
Simulation time 126183670 ps
CPU time 0.57 seconds
Started Aug 10 05:58:20 PM PDT 24
Finished Aug 10 05:58:20 PM PDT 24
Peak memory 194768 kb
Host smart-57eac8fc-4f00-4aae-856e-9932341681ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544282947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.544282947
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.282616490
Short name T1312
Test name
Test status
Simulation time 26280240 ps
CPU time 0.66 seconds
Started Aug 10 05:58:24 PM PDT 24
Finished Aug 10 05:58:25 PM PDT 24
Peak memory 195876 kb
Host smart-c4e3d5e7-454f-4522-a8ea-8c244d65b93a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282616490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.282616490
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.2373673754
Short name T1182
Test name
Test status
Simulation time 143911855 ps
CPU time 2.36 seconds
Started Aug 10 05:58:35 PM PDT 24
Finished Aug 10 05:58:38 PM PDT 24
Peak memory 200452 kb
Host smart-25535807-c8bc-4145-9fcc-851bba84a2b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373673754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.2373673754
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1176970333
Short name T1295
Test name
Test status
Simulation time 72518478 ps
CPU time 1.21 seconds
Started Aug 10 05:58:25 PM PDT 24
Finished Aug 10 05:58:26 PM PDT 24
Peak memory 199804 kb
Host smart-44c6d8e1-9b60-406f-ac68-093053992417
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176970333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1176970333
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2641216427
Short name T1233
Test name
Test status
Simulation time 27623557 ps
CPU time 0.82 seconds
Started Aug 10 05:58:20 PM PDT 24
Finished Aug 10 05:58:21 PM PDT 24
Peak memory 200228 kb
Host smart-77a7bc90-99dc-4132-9101-8e1ddc8e7b20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641216427 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2641216427
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.1506897854
Short name T1306
Test name
Test status
Simulation time 46710654 ps
CPU time 0.58 seconds
Started Aug 10 05:58:27 PM PDT 24
Finished Aug 10 05:58:27 PM PDT 24
Peak memory 194788 kb
Host smart-8ee0123d-a20a-467c-8773-f9b3d0127c06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506897854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1506897854
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.461000039
Short name T1252
Test name
Test status
Simulation time 18352071 ps
CPU time 0.76 seconds
Started Aug 10 05:58:20 PM PDT 24
Finished Aug 10 05:58:21 PM PDT 24
Peak memory 197704 kb
Host smart-a6e9ec79-be74-4986-9b00-e4edb5fbf72f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461000039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr
_outstanding.461000039
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.4282830831
Short name T1201
Test name
Test status
Simulation time 327302010 ps
CPU time 1.81 seconds
Started Aug 10 05:58:27 PM PDT 24
Finished Aug 10 05:58:29 PM PDT 24
Peak memory 200484 kb
Host smart-4ba65f13-958a-4bf7-acc0-9114a9d033c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282830831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.4282830831
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.4150284689
Short name T1303
Test name
Test status
Simulation time 183935678 ps
CPU time 0.94 seconds
Started Aug 10 05:58:20 PM PDT 24
Finished Aug 10 05:58:21 PM PDT 24
Peak memory 199068 kb
Host smart-c33809d9-83d5-452a-9b44-8416ed7eb13a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150284689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.4150284689
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1048911698
Short name T1278
Test name
Test status
Simulation time 105925390 ps
CPU time 0.8 seconds
Started Aug 10 05:58:27 PM PDT 24
Finished Aug 10 05:58:28 PM PDT 24
Peak memory 199932 kb
Host smart-d85de39d-e994-4fc6-a695-1126a02271fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048911698 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1048911698
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.2586327476
Short name T1301
Test name
Test status
Simulation time 33615694 ps
CPU time 0.64 seconds
Started Aug 10 05:58:25 PM PDT 24
Finished Aug 10 05:58:26 PM PDT 24
Peak memory 196032 kb
Host smart-4f9a2119-5c20-4582-8484-10d4b8c99c99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586327476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2586327476
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.1311990066
Short name T1290
Test name
Test status
Simulation time 15907261 ps
CPU time 0.58 seconds
Started Aug 10 05:58:18 PM PDT 24
Finished Aug 10 05:58:19 PM PDT 24
Peak memory 194768 kb
Host smart-48b9fa6b-154f-423e-a4a1-8e7d8d354e0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311990066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.1311990066
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1515263355
Short name T1215
Test name
Test status
Simulation time 21945857 ps
CPU time 0.67 seconds
Started Aug 10 05:58:20 PM PDT 24
Finished Aug 10 05:58:21 PM PDT 24
Peak memory 197088 kb
Host smart-e215731b-69da-4fd5-bc24-38e8c1e20138
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515263355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1515263355
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2283364185
Short name T1254
Test name
Test status
Simulation time 44581585 ps
CPU time 1.29 seconds
Started Aug 10 05:58:20 PM PDT 24
Finished Aug 10 05:58:21 PM PDT 24
Peak memory 200440 kb
Host smart-3409a47f-6236-4263-92b1-f28154b666f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283364185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2283364185
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1842096750
Short name T129
Test name
Test status
Simulation time 385832332 ps
CPU time 1.32 seconds
Started Aug 10 05:58:21 PM PDT 24
Finished Aug 10 05:58:22 PM PDT 24
Peak memory 199896 kb
Host smart-9a164c10-0554-4827-8d26-fd044ed15f93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842096750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1842096750
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.969657181
Short name T1229
Test name
Test status
Simulation time 24551583 ps
CPU time 0.73 seconds
Started Aug 10 05:58:25 PM PDT 24
Finished Aug 10 05:58:26 PM PDT 24
Peak memory 198532 kb
Host smart-04586734-01d3-42b7-ad0d-50a55fa66005
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969657181 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.969657181
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2637350335
Short name T65
Test name
Test status
Simulation time 19486694 ps
CPU time 0.63 seconds
Started Aug 10 05:58:21 PM PDT 24
Finished Aug 10 05:58:22 PM PDT 24
Peak memory 195772 kb
Host smart-34fb1889-18fc-41c0-82c1-325057a790ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637350335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2637350335
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.295966420
Short name T1238
Test name
Test status
Simulation time 28521797 ps
CPU time 0.55 seconds
Started Aug 10 05:58:19 PM PDT 24
Finished Aug 10 05:58:20 PM PDT 24
Peak memory 194792 kb
Host smart-d838d697-5f72-4ed8-9760-1cbbf2efabc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295966420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.295966420
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1505758733
Short name T1253
Test name
Test status
Simulation time 49947319 ps
CPU time 0.73 seconds
Started Aug 10 05:58:25 PM PDT 24
Finished Aug 10 05:58:26 PM PDT 24
Peak memory 196336 kb
Host smart-5306908f-d267-4391-af85-b93da002c647
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505758733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1505758733
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1207501432
Short name T1240
Test name
Test status
Simulation time 433434308 ps
CPU time 2.31 seconds
Started Aug 10 05:58:19 PM PDT 24
Finished Aug 10 05:58:22 PM PDT 24
Peak memory 200468 kb
Host smart-40dc0aff-66e5-4c30-937a-224e0edd2257
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207501432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1207501432
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.848470821
Short name T84
Test name
Test status
Simulation time 97221161 ps
CPU time 1.35 seconds
Started Aug 10 05:58:36 PM PDT 24
Finished Aug 10 05:58:37 PM PDT 24
Peak memory 199796 kb
Host smart-988a81ed-6a70-448e-a836-37ebdbc2d1f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848470821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.848470821
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1841368371
Short name T1208
Test name
Test status
Simulation time 27286786 ps
CPU time 1.08 seconds
Started Aug 10 05:58:19 PM PDT 24
Finished Aug 10 05:58:20 PM PDT 24
Peak memory 200376 kb
Host smart-d4681f19-c6e4-476b-8442-b8fee7354ddd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841368371 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1841368371
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2507266205
Short name T1242
Test name
Test status
Simulation time 34212032 ps
CPU time 0.56 seconds
Started Aug 10 05:58:25 PM PDT 24
Finished Aug 10 05:58:26 PM PDT 24
Peak memory 195836 kb
Host smart-43c471ae-9c0d-4da8-9ee9-f7016f1ae617
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507266205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2507266205
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.277572634
Short name T1276
Test name
Test status
Simulation time 16263889 ps
CPU time 0.6 seconds
Started Aug 10 05:58:20 PM PDT 24
Finished Aug 10 05:58:21 PM PDT 24
Peak memory 194760 kb
Host smart-d036ca2b-5bcc-4105-90f8-0637ecea7b3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277572634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.277572634
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.150677999
Short name T1224
Test name
Test status
Simulation time 13655249 ps
CPU time 0.64 seconds
Started Aug 10 05:58:24 PM PDT 24
Finished Aug 10 05:58:30 PM PDT 24
Peak memory 196816 kb
Host smart-2841446a-c321-4558-bd3f-d88c856985d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150677999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.150677999
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.871053014
Short name T1315
Test name
Test status
Simulation time 53517397 ps
CPU time 1.13 seconds
Started Aug 10 05:58:26 PM PDT 24
Finished Aug 10 05:58:27 PM PDT 24
Peak memory 200376 kb
Host smart-fc10bd75-716b-4979-b030-b1d97b244f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871053014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.871053014
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1988118441
Short name T87
Test name
Test status
Simulation time 77957074 ps
CPU time 1.25 seconds
Started Aug 10 05:58:25 PM PDT 24
Finished Aug 10 05:58:27 PM PDT 24
Peak memory 199860 kb
Host smart-0ec73eef-6d09-4e37-87db-ef62794f29d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988118441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1988118441
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3467474803
Short name T1193
Test name
Test status
Simulation time 32904639 ps
CPU time 0.88 seconds
Started Aug 10 05:58:26 PM PDT 24
Finished Aug 10 05:58:28 PM PDT 24
Peak memory 200228 kb
Host smart-ef61f2cd-a71d-49bc-b208-57f003cf4df7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467474803 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3467474803
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.1396678124
Short name T71
Test name
Test status
Simulation time 19806928 ps
CPU time 0.65 seconds
Started Aug 10 05:58:25 PM PDT 24
Finished Aug 10 05:58:26 PM PDT 24
Peak memory 195944 kb
Host smart-36664a51-2e96-4768-b204-30ca50184b0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396678124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1396678124
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3059317328
Short name T1185
Test name
Test status
Simulation time 36331386 ps
CPU time 0.56 seconds
Started Aug 10 05:58:21 PM PDT 24
Finished Aug 10 05:58:22 PM PDT 24
Peak memory 194800 kb
Host smart-410f0e66-669f-471c-925c-88db7c175e42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059317328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3059317328
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.281724640
Short name T1266
Test name
Test status
Simulation time 240196619 ps
CPU time 0.64 seconds
Started Aug 10 05:58:26 PM PDT 24
Finished Aug 10 05:58:27 PM PDT 24
Peak memory 195796 kb
Host smart-139ff7d9-dfce-4485-aac5-00dd84421aad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281724640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr
_outstanding.281724640
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.178166143
Short name T1272
Test name
Test status
Simulation time 86613657 ps
CPU time 1.4 seconds
Started Aug 10 05:58:18 PM PDT 24
Finished Aug 10 05:58:20 PM PDT 24
Peak memory 200468 kb
Host smart-dacfdeb2-2a49-43ef-9844-3ccfb551068d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178166143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.178166143
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3757223711
Short name T1268
Test name
Test status
Simulation time 156148964 ps
CPU time 1.31 seconds
Started Aug 10 05:58:22 PM PDT 24
Finished Aug 10 05:58:23 PM PDT 24
Peak memory 199704 kb
Host smart-3bb3ca88-4cf9-4e62-b4f6-6dfbfd8dca99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757223711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3757223711
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3004792622
Short name T1191
Test name
Test status
Simulation time 103113491 ps
CPU time 0.83 seconds
Started Aug 10 05:58:47 PM PDT 24
Finished Aug 10 05:58:48 PM PDT 24
Peak memory 200252 kb
Host smart-29e71bda-08ae-41a0-a4b4-8d95d660ea9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004792622 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3004792622
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2361608285
Short name T70
Test name
Test status
Simulation time 15271123 ps
CPU time 0.58 seconds
Started Aug 10 05:58:28 PM PDT 24
Finished Aug 10 05:58:29 PM PDT 24
Peak memory 195844 kb
Host smart-acea0ca1-cab8-4f79-9230-120b0d742ead
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361608285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2361608285
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3902940085
Short name T1297
Test name
Test status
Simulation time 21020488 ps
CPU time 0.55 seconds
Started Aug 10 05:58:51 PM PDT 24
Finished Aug 10 05:58:51 PM PDT 24
Peak memory 194776 kb
Host smart-adb036a9-5d96-4000-a54e-7a44400091a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902940085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3902940085
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.4127613239
Short name T1221
Test name
Test status
Simulation time 25483412 ps
CPU time 0.75 seconds
Started Aug 10 05:58:27 PM PDT 24
Finished Aug 10 05:58:28 PM PDT 24
Peak memory 198020 kb
Host smart-4f7ec0b2-8a4f-4ca8-ab69-99b107b485a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127613239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.4127613239
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2290642360
Short name T1261
Test name
Test status
Simulation time 27498083 ps
CPU time 1.51 seconds
Started Aug 10 05:58:49 PM PDT 24
Finished Aug 10 05:58:51 PM PDT 24
Peak memory 200416 kb
Host smart-85321036-0296-4453-a794-c2c98ac8f5db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290642360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2290642360
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3519044196
Short name T128
Test name
Test status
Simulation time 200111872 ps
CPU time 0.98 seconds
Started Aug 10 05:58:41 PM PDT 24
Finished Aug 10 05:58:42 PM PDT 24
Peak memory 199456 kb
Host smart-b457d4cb-45d1-4ab9-bc05-faf4f282fd28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519044196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3519044196
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3245022805
Short name T1289
Test name
Test status
Simulation time 15035436 ps
CPU time 0.75 seconds
Started Aug 10 05:58:03 PM PDT 24
Finished Aug 10 05:58:04 PM PDT 24
Peak memory 196780 kb
Host smart-0fdc51d6-d9f1-4e53-9af9-2b3b4384c4e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245022805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3245022805
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3268811032
Short name T1212
Test name
Test status
Simulation time 348859463 ps
CPU time 2.35 seconds
Started Aug 10 05:58:05 PM PDT 24
Finished Aug 10 05:58:07 PM PDT 24
Peak memory 197588 kb
Host smart-d841c981-973e-49da-a985-f862fa715c15
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268811032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3268811032
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2415693325
Short name T1249
Test name
Test status
Simulation time 1039444976 ps
CPU time 1.34 seconds
Started Aug 10 05:58:03 PM PDT 24
Finished Aug 10 05:58:05 PM PDT 24
Peak memory 195744 kb
Host smart-1c4a0265-00b3-4e8f-b152-4037d6b49f3f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415693325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2415693325
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1174463277
Short name T1243
Test name
Test status
Simulation time 19917995 ps
CPU time 0.93 seconds
Started Aug 10 05:58:06 PM PDT 24
Finished Aug 10 05:58:07 PM PDT 24
Peak memory 200192 kb
Host smart-1ac68985-d743-4fe3-b474-6016ca041e70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174463277 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1174463277
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.4104608307
Short name T1277
Test name
Test status
Simulation time 12639685 ps
CPU time 0.63 seconds
Started Aug 10 05:58:04 PM PDT 24
Finished Aug 10 05:58:05 PM PDT 24
Peak memory 196136 kb
Host smart-af52cd33-1409-4c9d-aed7-07df2e02ee19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104608307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.4104608307
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3494115566
Short name T1269
Test name
Test status
Simulation time 15023283 ps
CPU time 0.57 seconds
Started Aug 10 05:58:07 PM PDT 24
Finished Aug 10 05:58:07 PM PDT 24
Peak memory 194800 kb
Host smart-afffde82-bced-4173-ac6c-ed3917e3d89e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494115566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3494115566
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.751589075
Short name T74
Test name
Test status
Simulation time 54265171 ps
CPU time 0.66 seconds
Started Aug 10 05:58:03 PM PDT 24
Finished Aug 10 05:58:04 PM PDT 24
Peak memory 196024 kb
Host smart-dc51a13d-071c-4efe-90f7-38d09457e9da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751589075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_
outstanding.751589075
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.867719229
Short name T1259
Test name
Test status
Simulation time 500479033 ps
CPU time 2.26 seconds
Started Aug 10 05:58:04 PM PDT 24
Finished Aug 10 05:58:06 PM PDT 24
Peak memory 200440 kb
Host smart-937a168c-9454-481d-a777-ec18b711756f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867719229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.867719229
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3645600624
Short name T83
Test name
Test status
Simulation time 44899554 ps
CPU time 0.99 seconds
Started Aug 10 05:58:05 PM PDT 24
Finished Aug 10 05:58:06 PM PDT 24
Peak memory 199452 kb
Host smart-7b6e8849-2499-4662-85eb-9919fee89716
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645600624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3645600624
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.1863045249
Short name T1260
Test name
Test status
Simulation time 11431085 ps
CPU time 0.59 seconds
Started Aug 10 05:58:52 PM PDT 24
Finished Aug 10 05:58:53 PM PDT 24
Peak memory 194792 kb
Host smart-b220d83d-68ee-4130-b718-7ec5332cb883
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863045249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1863045249
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2644385953
Short name T1257
Test name
Test status
Simulation time 46034876 ps
CPU time 0.54 seconds
Started Aug 10 05:58:36 PM PDT 24
Finished Aug 10 05:58:36 PM PDT 24
Peak memory 194760 kb
Host smart-18a0261e-30d6-4f08-a51c-a5f4e3e20ed1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644385953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2644385953
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1815360889
Short name T1251
Test name
Test status
Simulation time 15938320 ps
CPU time 0.55 seconds
Started Aug 10 05:58:25 PM PDT 24
Finished Aug 10 05:58:26 PM PDT 24
Peak memory 194804 kb
Host smart-596773ca-584e-4612-8bdc-8a0893a2abb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815360889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1815360889
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2775525748
Short name T1202
Test name
Test status
Simulation time 14246557 ps
CPU time 0.55 seconds
Started Aug 10 05:58:30 PM PDT 24
Finished Aug 10 05:58:31 PM PDT 24
Peak memory 194720 kb
Host smart-12b9482f-4168-4a2b-8826-a005e526ee50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775525748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2775525748
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2686294962
Short name T1199
Test name
Test status
Simulation time 45087872 ps
CPU time 0.56 seconds
Started Aug 10 05:58:30 PM PDT 24
Finished Aug 10 05:58:30 PM PDT 24
Peak memory 194828 kb
Host smart-5f2ee576-24d6-470e-b01e-d54a7a3a9da8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686294962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2686294962
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.6990542
Short name T1194
Test name
Test status
Simulation time 27935366 ps
CPU time 0.55 seconds
Started Aug 10 05:58:43 PM PDT 24
Finished Aug 10 05:58:43 PM PDT 24
Peak memory 194744 kb
Host smart-12902fab-2be0-4d62-b4bd-b220944ee12c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6990542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.6990542
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1597777983
Short name T1284
Test name
Test status
Simulation time 35336757 ps
CPU time 0.58 seconds
Started Aug 10 05:58:32 PM PDT 24
Finished Aug 10 05:58:33 PM PDT 24
Peak memory 194748 kb
Host smart-e062266b-e7d4-424b-b194-1bbbcd3c0f54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597777983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1597777983
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3460693415
Short name T1195
Test name
Test status
Simulation time 11691139 ps
CPU time 0.58 seconds
Started Aug 10 05:58:29 PM PDT 24
Finished Aug 10 05:58:30 PM PDT 24
Peak memory 194800 kb
Host smart-d186bc04-0dd9-46ce-a4ef-9b1963559c89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460693415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3460693415
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.1302496458
Short name T1273
Test name
Test status
Simulation time 15834882 ps
CPU time 0.57 seconds
Started Aug 10 05:58:48 PM PDT 24
Finished Aug 10 05:58:49 PM PDT 24
Peak memory 194760 kb
Host smart-03b0bafd-edd1-4fbc-a61a-1bf8812cf660
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302496458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1302496458
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.806485248
Short name T1258
Test name
Test status
Simulation time 17737957 ps
CPU time 0.58 seconds
Started Aug 10 05:58:34 PM PDT 24
Finished Aug 10 05:58:35 PM PDT 24
Peak memory 194668 kb
Host smart-6fa49d6e-d842-4445-ab3b-8932dc60362e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806485248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.806485248
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1593780313
Short name T1300
Test name
Test status
Simulation time 135539630 ps
CPU time 0.67 seconds
Started Aug 10 05:58:02 PM PDT 24
Finished Aug 10 05:58:03 PM PDT 24
Peak memory 195328 kb
Host smart-a3e568f1-65a8-49b0-95b0-33d3a9d0f1f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593780313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1593780313
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2535357602
Short name T1264
Test name
Test status
Simulation time 148558248 ps
CPU time 1.56 seconds
Started Aug 10 05:58:02 PM PDT 24
Finished Aug 10 05:58:04 PM PDT 24
Peak memory 197732 kb
Host smart-1a0f9598-ce2e-45f9-8575-d8d8c3e49449
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535357602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2535357602
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3952745600
Short name T69
Test name
Test status
Simulation time 49077123 ps
CPU time 0.59 seconds
Started Aug 10 05:58:13 PM PDT 24
Finished Aug 10 05:58:14 PM PDT 24
Peak memory 195756 kb
Host smart-c606faf0-ff7f-4119-8f92-00a99497d624
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952745600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3952745600
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.207213991
Short name T1305
Test name
Test status
Simulation time 34586583 ps
CPU time 0.71 seconds
Started Aug 10 05:58:02 PM PDT 24
Finished Aug 10 05:58:03 PM PDT 24
Peak memory 198108 kb
Host smart-de6220e2-74db-40c5-be70-0de851759b7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207213991 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.207213991
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2673952841
Short name T67
Test name
Test status
Simulation time 24463932 ps
CPU time 0.57 seconds
Started Aug 10 05:58:14 PM PDT 24
Finished Aug 10 05:58:15 PM PDT 24
Peak memory 195764 kb
Host smart-71fcedf6-183e-40b0-94c5-46b5b350bafa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673952841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2673952841
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2424960196
Short name T1302
Test name
Test status
Simulation time 31468372 ps
CPU time 0.58 seconds
Started Aug 10 05:58:05 PM PDT 24
Finished Aug 10 05:58:06 PM PDT 24
Peak memory 194812 kb
Host smart-d2e26e13-8080-4979-8b52-c74f3b563af9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424960196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2424960196
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.436469836
Short name T80
Test name
Test status
Simulation time 109918999 ps
CPU time 0.77 seconds
Started Aug 10 05:58:05 PM PDT 24
Finished Aug 10 05:58:06 PM PDT 24
Peak memory 196516 kb
Host smart-8750d1f7-0243-4e65-9418-a4a472fe2ecc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436469836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_
outstanding.436469836
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.1766498396
Short name T1271
Test name
Test status
Simulation time 70806304 ps
CPU time 1.24 seconds
Started Aug 10 05:58:07 PM PDT 24
Finished Aug 10 05:58:09 PM PDT 24
Peak memory 200368 kb
Host smart-c4e9b6bf-894a-4d14-b9d1-7f50f7fb538e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766498396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1766498396
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3632593154
Short name T91
Test name
Test status
Simulation time 121739897 ps
CPU time 1.26 seconds
Started Aug 10 05:58:06 PM PDT 24
Finished Aug 10 05:58:08 PM PDT 24
Peak memory 199768 kb
Host smart-7f6bf0de-ec7d-4ebc-92e8-605124e0b0c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632593154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3632593154
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.283695705
Short name T1200
Test name
Test status
Simulation time 17586447 ps
CPU time 0.58 seconds
Started Aug 10 05:58:41 PM PDT 24
Finished Aug 10 05:58:42 PM PDT 24
Peak memory 194780 kb
Host smart-a6206d05-2fb6-46ae-87df-439a420f6f96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283695705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.283695705
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2759052736
Short name T1232
Test name
Test status
Simulation time 13688967 ps
CPU time 0.57 seconds
Started Aug 10 05:58:27 PM PDT 24
Finished Aug 10 05:58:28 PM PDT 24
Peak memory 194796 kb
Host smart-97c52027-10e1-480a-9524-405836b267ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759052736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2759052736
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.3050343117
Short name T1189
Test name
Test status
Simulation time 64311428 ps
CPU time 0.58 seconds
Started Aug 10 05:58:50 PM PDT 24
Finished Aug 10 05:58:51 PM PDT 24
Peak memory 194788 kb
Host smart-db497be1-d56c-462c-9c8d-d8a9346119a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050343117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3050343117
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.1085015335
Short name T1230
Test name
Test status
Simulation time 102348193 ps
CPU time 0.58 seconds
Started Aug 10 05:58:36 PM PDT 24
Finished Aug 10 05:58:36 PM PDT 24
Peak memory 194732 kb
Host smart-7c57dc81-c83b-4bec-adc8-83f8f71a7f69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085015335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1085015335
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.1911450364
Short name T1298
Test name
Test status
Simulation time 20639664 ps
CPU time 0.54 seconds
Started Aug 10 05:58:40 PM PDT 24
Finished Aug 10 05:58:41 PM PDT 24
Peak memory 194780 kb
Host smart-427a8496-521b-4fbf-b9e0-4aa798cda3bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911450364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1911450364
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.840000323
Short name T1197
Test name
Test status
Simulation time 167492089 ps
CPU time 0.6 seconds
Started Aug 10 05:58:49 PM PDT 24
Finished Aug 10 05:58:50 PM PDT 24
Peak memory 194808 kb
Host smart-a09a08cb-b4a0-438f-9f90-caf575e67935
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840000323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.840000323
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1622500955
Short name T1299
Test name
Test status
Simulation time 47505671 ps
CPU time 0.56 seconds
Started Aug 10 05:58:29 PM PDT 24
Finished Aug 10 05:58:29 PM PDT 24
Peak memory 194768 kb
Host smart-c1a74f23-51e1-4d2d-9a9d-1c3195fac35d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622500955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1622500955
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.350376896
Short name T1190
Test name
Test status
Simulation time 60482747 ps
CPU time 0.58 seconds
Started Aug 10 05:58:28 PM PDT 24
Finished Aug 10 05:58:29 PM PDT 24
Peak memory 194792 kb
Host smart-3a27058f-2bbd-4405-ae6a-a614227290ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350376896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.350376896
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.782694812
Short name T1227
Test name
Test status
Simulation time 16861885 ps
CPU time 0.54 seconds
Started Aug 10 05:58:26 PM PDT 24
Finished Aug 10 05:58:27 PM PDT 24
Peak memory 194776 kb
Host smart-60174f75-dd86-4490-9240-afd12844b50d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782694812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.782694812
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1143186908
Short name T1204
Test name
Test status
Simulation time 17658669 ps
CPU time 0.61 seconds
Started Aug 10 05:58:28 PM PDT 24
Finished Aug 10 05:58:29 PM PDT 24
Peak memory 194704 kb
Host smart-dd7d76ae-f0ae-4e60-a39a-90e33f23c0ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143186908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1143186908
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1376272666
Short name T1214
Test name
Test status
Simulation time 13260278 ps
CPU time 0.66 seconds
Started Aug 10 05:58:13 PM PDT 24
Finished Aug 10 05:58:14 PM PDT 24
Peak memory 195496 kb
Host smart-7964c602-1379-4714-8cdb-9e7b2480a79d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376272666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1376272666
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3873425925
Short name T1211
Test name
Test status
Simulation time 252032165 ps
CPU time 1.61 seconds
Started Aug 10 05:58:16 PM PDT 24
Finished Aug 10 05:58:17 PM PDT 24
Peak memory 198396 kb
Host smart-f91af4a7-b32e-4c1f-a31d-de4936eab7c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873425925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3873425925
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.4154680602
Short name T1313
Test name
Test status
Simulation time 16246314 ps
CPU time 0.6 seconds
Started Aug 10 05:58:24 PM PDT 24
Finished Aug 10 05:58:25 PM PDT 24
Peak memory 195756 kb
Host smart-506b6807-268d-4f8d-b2dd-bd3a52cb991f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154680602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.4154680602
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.4188231708
Short name T1267
Test name
Test status
Simulation time 38470688 ps
CPU time 0.7 seconds
Started Aug 10 05:58:09 PM PDT 24
Finished Aug 10 05:58:10 PM PDT 24
Peak memory 199108 kb
Host smart-f6301a61-d5e0-4e5e-b91b-284ebba5163e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188231708 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.4188231708
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.4125097805
Short name T75
Test name
Test status
Simulation time 13262500 ps
CPU time 0.57 seconds
Started Aug 10 05:58:17 PM PDT 24
Finished Aug 10 05:58:18 PM PDT 24
Peak memory 195856 kb
Host smart-d7b6e273-7911-49ce-9eec-94e57d903a38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125097805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.4125097805
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.2472884923
Short name T1314
Test name
Test status
Simulation time 43276439 ps
CPU time 0.57 seconds
Started Aug 10 05:58:10 PM PDT 24
Finished Aug 10 05:58:10 PM PDT 24
Peak memory 194744 kb
Host smart-f0073cf4-c4f4-4689-98a1-f932354ad33e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472884923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2472884923
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4089049377
Short name T1226
Test name
Test status
Simulation time 32608512 ps
CPU time 0.62 seconds
Started Aug 10 05:58:14 PM PDT 24
Finished Aug 10 05:58:15 PM PDT 24
Peak memory 195360 kb
Host smart-de83b98a-bc77-41cd-ab80-08cb3ac7a461
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089049377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.4089049377
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1393156071
Short name T1283
Test name
Test status
Simulation time 287158868 ps
CPU time 1.78 seconds
Started Aug 10 05:58:07 PM PDT 24
Finished Aug 10 05:58:09 PM PDT 24
Peak memory 200480 kb
Host smart-df0b004a-d07d-4dcd-842b-e336fb1670d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393156071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1393156071
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3685072841
Short name T1291
Test name
Test status
Simulation time 92449452 ps
CPU time 1.28 seconds
Started Aug 10 05:58:09 PM PDT 24
Finished Aug 10 05:58:10 PM PDT 24
Peak memory 199572 kb
Host smart-2e1a3e82-17fc-4991-b1db-bd13f3592dfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685072841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3685072841
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3140196253
Short name T1274
Test name
Test status
Simulation time 12375584 ps
CPU time 0.59 seconds
Started Aug 10 05:58:46 PM PDT 24
Finished Aug 10 05:58:47 PM PDT 24
Peak memory 194748 kb
Host smart-71687adc-d603-41f1-8128-568e7acb1b39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140196253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3140196253
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1973289796
Short name T1263
Test name
Test status
Simulation time 41445929 ps
CPU time 0.57 seconds
Started Aug 10 05:58:41 PM PDT 24
Finished Aug 10 05:58:42 PM PDT 24
Peak memory 194672 kb
Host smart-8a7cdb85-c8ac-495e-a4f5-31ebe8c73f3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973289796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1973289796
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1525744464
Short name T1239
Test name
Test status
Simulation time 20942981 ps
CPU time 0.53 seconds
Started Aug 10 05:58:52 PM PDT 24
Finished Aug 10 05:58:52 PM PDT 24
Peak memory 194740 kb
Host smart-86d59461-5c6f-407f-96e8-a56182a40030
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525744464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1525744464
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.4271207316
Short name T1275
Test name
Test status
Simulation time 25217496 ps
CPU time 0.61 seconds
Started Aug 10 05:58:29 PM PDT 24
Finished Aug 10 05:58:30 PM PDT 24
Peak memory 194828 kb
Host smart-30242489-7d88-4c9c-8498-3649a5d7c2a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271207316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.4271207316
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2314643965
Short name T1198
Test name
Test status
Simulation time 19297881 ps
CPU time 0.57 seconds
Started Aug 10 05:58:43 PM PDT 24
Finished Aug 10 05:58:44 PM PDT 24
Peak memory 194748 kb
Host smart-a58e05e9-b8ce-4c24-995c-2b114ee96d7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314643965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2314643965
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.1330580677
Short name T1228
Test name
Test status
Simulation time 23867205 ps
CPU time 0.56 seconds
Started Aug 10 05:58:28 PM PDT 24
Finished Aug 10 05:58:29 PM PDT 24
Peak memory 194676 kb
Host smart-f1122d94-080d-4736-8752-4a3f8087fce5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330580677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1330580677
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.408495142
Short name T1265
Test name
Test status
Simulation time 55303811 ps
CPU time 0.59 seconds
Started Aug 10 05:58:27 PM PDT 24
Finished Aug 10 05:58:28 PM PDT 24
Peak memory 194732 kb
Host smart-2b380ed4-0183-4ed9-9f1c-63f2acbb73cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408495142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.408495142
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.1244486377
Short name T1307
Test name
Test status
Simulation time 16568157 ps
CPU time 0.6 seconds
Started Aug 10 05:58:47 PM PDT 24
Finished Aug 10 05:58:48 PM PDT 24
Peak memory 194808 kb
Host smart-84bead35-29b7-49b0-8870-4695ccc20055
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244486377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1244486377
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.429277628
Short name T1279
Test name
Test status
Simulation time 14154099 ps
CPU time 0.55 seconds
Started Aug 10 05:58:28 PM PDT 24
Finished Aug 10 05:58:29 PM PDT 24
Peak memory 194676 kb
Host smart-fbbf30c3-b791-4c31-a9cc-15e1d46792aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429277628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.429277628
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.239965521
Short name T1205
Test name
Test status
Simulation time 36663955 ps
CPU time 0.55 seconds
Started Aug 10 05:58:44 PM PDT 24
Finished Aug 10 05:58:44 PM PDT 24
Peak memory 194812 kb
Host smart-58f841c2-c638-4cdf-b01d-67e7d9596428
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239965521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.239965521
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3573113543
Short name T1223
Test name
Test status
Simulation time 15146184 ps
CPU time 0.65 seconds
Started Aug 10 05:58:17 PM PDT 24
Finished Aug 10 05:58:18 PM PDT 24
Peak memory 197668 kb
Host smart-d3fa6d70-bae3-46be-a82d-4b9fe880b651
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573113543 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3573113543
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.944637918
Short name T73
Test name
Test status
Simulation time 19575662 ps
CPU time 0.59 seconds
Started Aug 10 05:58:10 PM PDT 24
Finished Aug 10 05:58:11 PM PDT 24
Peak memory 195808 kb
Host smart-f3d32d67-2437-4167-a36e-cb4b5200bfa8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944637918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.944637918
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.1904513815
Short name T1250
Test name
Test status
Simulation time 21777364 ps
CPU time 0.6 seconds
Started Aug 10 05:58:12 PM PDT 24
Finished Aug 10 05:58:13 PM PDT 24
Peak memory 194804 kb
Host smart-ff212b7e-a58b-48a9-9d2a-a943c05044eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904513815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1904513815
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1538462711
Short name T1282
Test name
Test status
Simulation time 17047866 ps
CPU time 0.66 seconds
Started Aug 10 05:58:17 PM PDT 24
Finished Aug 10 05:58:18 PM PDT 24
Peak memory 196972 kb
Host smart-d5fdca1b-36cb-4156-8174-f39bf9a60131
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538462711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.1538462711
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.173246955
Short name T1183
Test name
Test status
Simulation time 260743089 ps
CPU time 1.62 seconds
Started Aug 10 05:58:14 PM PDT 24
Finished Aug 10 05:58:16 PM PDT 24
Peak memory 200440 kb
Host smart-6f97e1e6-9207-43cd-bee7-53907ac0d3f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173246955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.173246955
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1921967981
Short name T89
Test name
Test status
Simulation time 46988771 ps
CPU time 0.93 seconds
Started Aug 10 05:58:14 PM PDT 24
Finished Aug 10 05:58:15 PM PDT 24
Peak memory 199056 kb
Host smart-019e9695-ddfa-40f4-b4f0-1f42de744a38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921967981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1921967981
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2165498432
Short name T1186
Test name
Test status
Simulation time 68849898 ps
CPU time 0.72 seconds
Started Aug 10 05:58:22 PM PDT 24
Finished Aug 10 05:58:22 PM PDT 24
Peak memory 197576 kb
Host smart-6fc53f52-b2a1-4cc7-a5e3-c2c7b81f4061
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165498432 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2165498432
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.2172451044
Short name T1225
Test name
Test status
Simulation time 166206021 ps
CPU time 0.58 seconds
Started Aug 10 05:58:22 PM PDT 24
Finished Aug 10 05:58:23 PM PDT 24
Peak memory 195060 kb
Host smart-1e2c9fcc-f4d4-40b7-ba33-da8822cc42a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172451044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2172451044
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3745976546
Short name T1217
Test name
Test status
Simulation time 43254125 ps
CPU time 0.56 seconds
Started Aug 10 05:58:10 PM PDT 24
Finished Aug 10 05:58:10 PM PDT 24
Peak memory 194800 kb
Host smart-24a0b914-331f-4ee9-89ed-46c3ab093b62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745976546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3745976546
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2479383467
Short name T77
Test name
Test status
Simulation time 54480678 ps
CPU time 0.71 seconds
Started Aug 10 05:58:11 PM PDT 24
Finished Aug 10 05:58:12 PM PDT 24
Peak memory 197468 kb
Host smart-c2be34a5-93a2-46fa-bcb2-dca2c9faedcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479383467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.2479383467
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1660370784
Short name T1196
Test name
Test status
Simulation time 71343584 ps
CPU time 1.11 seconds
Started Aug 10 05:58:10 PM PDT 24
Finished Aug 10 05:58:11 PM PDT 24
Peak memory 200232 kb
Host smart-acc2ce8c-7cde-4362-b8ac-078ce0cd7aa8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660370784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1660370784
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.16802291
Short name T1311
Test name
Test status
Simulation time 20287850 ps
CPU time 0.7 seconds
Started Aug 10 05:58:17 PM PDT 24
Finished Aug 10 05:58:18 PM PDT 24
Peak memory 198300 kb
Host smart-10aa90bb-78f3-4f75-bf55-26ae8fca5f68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16802291 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.16802291
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.2105749397
Short name T1246
Test name
Test status
Simulation time 129617381 ps
CPU time 0.61 seconds
Started Aug 10 05:58:14 PM PDT 24
Finished Aug 10 05:58:15 PM PDT 24
Peak memory 195800 kb
Host smart-cdfd4447-a9c9-4f10-a7b8-84956f197a06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105749397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.2105749397
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2017435419
Short name T1287
Test name
Test status
Simulation time 27345796 ps
CPU time 0.56 seconds
Started Aug 10 05:58:12 PM PDT 24
Finished Aug 10 05:58:13 PM PDT 24
Peak memory 194796 kb
Host smart-e7728e84-2a4c-4e2a-9a0a-8e9008aaceaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017435419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2017435419
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2578515327
Short name T1293
Test name
Test status
Simulation time 21175340 ps
CPU time 0.66 seconds
Started Aug 10 05:58:14 PM PDT 24
Finished Aug 10 05:58:15 PM PDT 24
Peak memory 195116 kb
Host smart-8448d1f0-6eec-4795-90ee-37a2bf81df70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578515327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2578515327
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.3533410210
Short name T1234
Test name
Test status
Simulation time 236806754 ps
CPU time 2.25 seconds
Started Aug 10 05:58:13 PM PDT 24
Finished Aug 10 05:58:15 PM PDT 24
Peak memory 200500 kb
Host smart-6aaf892d-cb4b-42fa-9075-9fec23a475b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533410210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.3533410210
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1799951543
Short name T86
Test name
Test status
Simulation time 223623781 ps
CPU time 0.99 seconds
Started Aug 10 05:58:13 PM PDT 24
Finished Aug 10 05:58:14 PM PDT 24
Peak memory 199628 kb
Host smart-0a32b6e0-e849-478c-b015-6c3450e1320f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799951543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1799951543
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1357431347
Short name T1207
Test name
Test status
Simulation time 61405734 ps
CPU time 0.91 seconds
Started Aug 10 05:58:10 PM PDT 24
Finished Aug 10 05:58:11 PM PDT 24
Peak memory 200248 kb
Host smart-21315712-5b04-41b0-96a1-a4cc9a76c583
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357431347 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1357431347
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.2513320790
Short name T64
Test name
Test status
Simulation time 17972179 ps
CPU time 0.64 seconds
Started Aug 10 05:58:12 PM PDT 24
Finished Aug 10 05:58:13 PM PDT 24
Peak memory 196164 kb
Host smart-cc9d77d9-9b6c-497d-8854-80fb0dbbe696
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513320790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2513320790
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.1262114496
Short name T1288
Test name
Test status
Simulation time 28542737 ps
CPU time 0.57 seconds
Started Aug 10 05:58:25 PM PDT 24
Finished Aug 10 05:58:26 PM PDT 24
Peak memory 194796 kb
Host smart-f616f8b9-b280-4003-b759-53c1871d2713
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262114496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1262114496
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1532556499
Short name T1309
Test name
Test status
Simulation time 32950499 ps
CPU time 0.75 seconds
Started Aug 10 05:58:12 PM PDT 24
Finished Aug 10 05:58:13 PM PDT 24
Peak memory 197296 kb
Host smart-6e14e5d6-f68f-420f-9c8c-11d7460479c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532556499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1532556499
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3168224972
Short name T1244
Test name
Test status
Simulation time 255955055 ps
CPU time 1.35 seconds
Started Aug 10 05:58:10 PM PDT 24
Finished Aug 10 05:58:11 PM PDT 24
Peak memory 200476 kb
Host smart-d46b3c3e-2e57-43cb-a87a-1cdb8bf68702
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168224972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3168224972
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1074389896
Short name T126
Test name
Test status
Simulation time 97836534 ps
CPU time 1 seconds
Started Aug 10 05:58:14 PM PDT 24
Finished Aug 10 05:58:15 PM PDT 24
Peak memory 199548 kb
Host smart-8d29436e-ebce-48b1-a504-63be2b52b7a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074389896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1074389896
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2278424372
Short name T1237
Test name
Test status
Simulation time 20352918 ps
CPU time 0.68 seconds
Started Aug 10 05:58:24 PM PDT 24
Finished Aug 10 05:58:25 PM PDT 24
Peak memory 198044 kb
Host smart-95f16edc-e6ee-406f-9539-397a3e74c77d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278424372 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2278424372
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2442598978
Short name T1241
Test name
Test status
Simulation time 12410127 ps
CPU time 0.61 seconds
Started Aug 10 05:58:21 PM PDT 24
Finished Aug 10 05:58:21 PM PDT 24
Peak memory 195744 kb
Host smart-d26fdf89-5143-43b4-b597-f28a2e3a8bd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442598978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2442598978
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1746013038
Short name T1235
Test name
Test status
Simulation time 45546973 ps
CPU time 0.65 seconds
Started Aug 10 05:58:12 PM PDT 24
Finished Aug 10 05:58:13 PM PDT 24
Peak memory 194744 kb
Host smart-3d1df629-87d1-4ac6-9f34-3ed4e044dbf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746013038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1746013038
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3226501028
Short name T79
Test name
Test status
Simulation time 83567449 ps
CPU time 0.66 seconds
Started Aug 10 05:58:20 PM PDT 24
Finished Aug 10 05:58:21 PM PDT 24
Peak memory 196036 kb
Host smart-e5079e82-6d1e-4385-896e-64aff3a77d96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226501028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.3226501028
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1086353508
Short name T1256
Test name
Test status
Simulation time 35693636 ps
CPU time 1.84 seconds
Started Aug 10 05:58:11 PM PDT 24
Finished Aug 10 05:58:13 PM PDT 24
Peak memory 200500 kb
Host smart-b05197dc-7a2d-4701-96dd-f2c954a491ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086353508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1086353508
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3922664267
Short name T127
Test name
Test status
Simulation time 215839668 ps
CPU time 1 seconds
Started Aug 10 05:58:09 PM PDT 24
Finished Aug 10 05:58:10 PM PDT 24
Peak memory 199488 kb
Host smart-57c5e5d6-01ba-42c1-937b-78306f585678
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922664267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3922664267
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2541208884
Short name T739
Test name
Test status
Simulation time 14796602 ps
CPU time 0.54 seconds
Started Aug 10 06:08:30 PM PDT 24
Finished Aug 10 06:08:30 PM PDT 24
Peak memory 195580 kb
Host smart-7ef8bc98-38ba-456b-aece-d677f7929bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541208884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2541208884
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2273466653
Short name T917
Test name
Test status
Simulation time 117680222203 ps
CPU time 72.57 seconds
Started Aug 10 06:08:13 PM PDT 24
Finished Aug 10 06:09:25 PM PDT 24
Peak memory 200152 kb
Host smart-f923453f-a0be-4f48-bbab-9cc4c305ecab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273466653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2273466653
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.2512521906
Short name T153
Test name
Test status
Simulation time 76972828666 ps
CPU time 21.01 seconds
Started Aug 10 06:08:13 PM PDT 24
Finished Aug 10 06:08:34 PM PDT 24
Peak memory 199936 kb
Host smart-40e67784-56f8-4009-b98d-4b0b4510abb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512521906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.2512521906
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_intr.3825706450
Short name T464
Test name
Test status
Simulation time 49414433413 ps
CPU time 42.15 seconds
Started Aug 10 06:08:26 PM PDT 24
Finished Aug 10 06:09:08 PM PDT 24
Peak memory 199924 kb
Host smart-e2697c50-3c28-46cd-b914-59d895467199
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825706450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3825706450
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.3845585065
Short name T770
Test name
Test status
Simulation time 84287441035 ps
CPU time 157.92 seconds
Started Aug 10 06:08:31 PM PDT 24
Finished Aug 10 06:11:09 PM PDT 24
Peak memory 199844 kb
Host smart-a9de50f8-ea36-443f-9e7c-ddff6b9214b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3845585065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3845585065
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.4018986434
Short name T1042
Test name
Test status
Simulation time 2560612475 ps
CPU time 1.53 seconds
Started Aug 10 06:08:21 PM PDT 24
Finished Aug 10 06:08:22 PM PDT 24
Peak memory 197504 kb
Host smart-6896283f-ac36-47b9-bf76-2d90bd7160d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018986434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.4018986434
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.188962653
Short name T705
Test name
Test status
Simulation time 43991491979 ps
CPU time 71.52 seconds
Started Aug 10 06:08:21 PM PDT 24
Finished Aug 10 06:09:32 PM PDT 24
Peak memory 199376 kb
Host smart-6e92564b-2ea6-408f-ab60-da053febaa1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188962653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.188962653
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.420741902
Short name T796
Test name
Test status
Simulation time 21628816734 ps
CPU time 296.79 seconds
Started Aug 10 06:08:22 PM PDT 24
Finished Aug 10 06:13:19 PM PDT 24
Peak memory 199960 kb
Host smart-b3cf103f-2680-4d47-a245-51c71507176d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=420741902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.420741902
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.2305425862
Short name T834
Test name
Test status
Simulation time 3575081448 ps
CPU time 11.63 seconds
Started Aug 10 06:08:21 PM PDT 24
Finished Aug 10 06:08:33 PM PDT 24
Peak memory 198980 kb
Host smart-7fb31a77-dec7-4c66-875d-eb889093efa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2305425862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2305425862
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.363407985
Short name T524
Test name
Test status
Simulation time 40290816460 ps
CPU time 56.46 seconds
Started Aug 10 06:08:22 PM PDT 24
Finished Aug 10 06:09:19 PM PDT 24
Peak memory 199892 kb
Host smart-d1b2e52e-0d91-4fec-90da-c87f90132dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363407985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.363407985
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.2597253915
Short name T397
Test name
Test status
Simulation time 2808704663 ps
CPU time 4.71 seconds
Started Aug 10 06:08:25 PM PDT 24
Finished Aug 10 06:08:30 PM PDT 24
Peak memory 196416 kb
Host smart-37bc988d-36d1-48ae-aed1-63f26f823d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597253915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2597253915
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.1849751375
Short name T434
Test name
Test status
Simulation time 5772794159 ps
CPU time 8.77 seconds
Started Aug 10 06:08:13 PM PDT 24
Finished Aug 10 06:08:21 PM PDT 24
Peak memory 199712 kb
Host smart-56386ea9-d4e5-4f15-97d3-aa50ec0216cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849751375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1849751375
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.897839789
Short name T162
Test name
Test status
Simulation time 452316399822 ps
CPU time 257.25 seconds
Started Aug 10 06:08:31 PM PDT 24
Finished Aug 10 06:12:49 PM PDT 24
Peak memory 199924 kb
Host smart-a856058a-10ca-41a5-b543-0a193bc3cdb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897839789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.897839789
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.1154952022
Short name T1125
Test name
Test status
Simulation time 147314909352 ps
CPU time 930.06 seconds
Started Aug 10 06:08:28 PM PDT 24
Finished Aug 10 06:23:59 PM PDT 24
Peak memory 224808 kb
Host smart-2d06618b-a9eb-471f-80d7-800d0fc9f701
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154952022 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.1154952022
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2858075494
Short name T806
Test name
Test status
Simulation time 6656059147 ps
CPU time 19.86 seconds
Started Aug 10 06:08:21 PM PDT 24
Finished Aug 10 06:08:41 PM PDT 24
Peak memory 199924 kb
Host smart-2d1edc28-47f0-48e9-b4c7-3ce87ca323c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858075494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2858075494
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.3634246379
Short name T535
Test name
Test status
Simulation time 63615742964 ps
CPU time 47 seconds
Started Aug 10 06:08:12 PM PDT 24
Finished Aug 10 06:08:59 PM PDT 24
Peak memory 199884 kb
Host smart-bfeef158-a3c5-430b-b4be-b97de44f4d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634246379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3634246379
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.199152027
Short name T1147
Test name
Test status
Simulation time 35650640 ps
CPU time 0.56 seconds
Started Aug 10 06:08:36 PM PDT 24
Finished Aug 10 06:08:37 PM PDT 24
Peak memory 195360 kb
Host smart-2bd26f40-16ac-4bd5-a731-c974268c7c18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199152027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.199152027
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.4077148484
Short name T1004
Test name
Test status
Simulation time 61744126976 ps
CPU time 98.16 seconds
Started Aug 10 06:08:31 PM PDT 24
Finished Aug 10 06:10:09 PM PDT 24
Peak memory 199900 kb
Host smart-61c45c1d-4f51-4477-aaea-ddd6049eb495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077148484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.4077148484
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.3195950529
Short name T167
Test name
Test status
Simulation time 51292441938 ps
CPU time 41.53 seconds
Started Aug 10 06:08:37 PM PDT 24
Finished Aug 10 06:09:18 PM PDT 24
Peak memory 199876 kb
Host smart-43659d2d-b122-4559-a571-4e47f39e7890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195950529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3195950529
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2116472708
Short name T903
Test name
Test status
Simulation time 138504641196 ps
CPU time 191.24 seconds
Started Aug 10 06:08:40 PM PDT 24
Finished Aug 10 06:11:52 PM PDT 24
Peak memory 199832 kb
Host smart-c846bd10-06e5-44bd-9d07-347ba2375cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116472708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2116472708
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3298989767
Short name T720
Test name
Test status
Simulation time 61344214329 ps
CPU time 190.66 seconds
Started Aug 10 06:08:37 PM PDT 24
Finished Aug 10 06:11:48 PM PDT 24
Peak memory 200000 kb
Host smart-d980e0ad-001f-46d4-b87c-6e7ddc636d56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3298989767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3298989767
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3843317203
Short name T1034
Test name
Test status
Simulation time 9566757585 ps
CPU time 17.62 seconds
Started Aug 10 06:08:37 PM PDT 24
Finished Aug 10 06:08:55 PM PDT 24
Peak memory 199216 kb
Host smart-02a2a7d5-b87c-4e6e-bbcd-52602e213f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843317203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3843317203
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.1220524559
Short name T353
Test name
Test status
Simulation time 102129799089 ps
CPU time 153.7 seconds
Started Aug 10 06:08:37 PM PDT 24
Finished Aug 10 06:11:11 PM PDT 24
Peak memory 200088 kb
Host smart-7b7b10e1-6236-4c5e-b3c6-4f12c325f908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220524559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1220524559
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.1712047534
Short name T773
Test name
Test status
Simulation time 10547054661 ps
CPU time 406.92 seconds
Started Aug 10 06:08:38 PM PDT 24
Finished Aug 10 06:15:25 PM PDT 24
Peak memory 199992 kb
Host smart-876022c5-3fe4-4a5d-b0bd-e5ed8e46c32f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1712047534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1712047534
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.3038382815
Short name T100
Test name
Test status
Simulation time 2310870216 ps
CPU time 7.69 seconds
Started Aug 10 06:08:36 PM PDT 24
Finished Aug 10 06:08:44 PM PDT 24
Peak memory 198024 kb
Host smart-5e23670b-0bde-44ee-b931-956cb16649a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3038382815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3038382815
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.1621839260
Short name T134
Test name
Test status
Simulation time 25700044359 ps
CPU time 11.73 seconds
Started Aug 10 06:08:37 PM PDT 24
Finished Aug 10 06:08:49 PM PDT 24
Peak memory 199952 kb
Host smart-4ade155b-ee6c-4ab3-8441-163992711122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621839260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1621839260
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.1639438386
Short name T420
Test name
Test status
Simulation time 875512511 ps
CPU time 0.97 seconds
Started Aug 10 06:08:40 PM PDT 24
Finished Aug 10 06:08:41 PM PDT 24
Peak memory 195428 kb
Host smart-e15a3376-04aa-4059-8374-3b67e6c93671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639438386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1639438386
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.2470166805
Short name T92
Test name
Test status
Simulation time 123785171 ps
CPU time 0.84 seconds
Started Aug 10 06:08:35 PM PDT 24
Finished Aug 10 06:08:36 PM PDT 24
Peak memory 218476 kb
Host smart-b5269bb3-530c-48df-bf4f-73723cce25ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470166805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2470166805
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3633908904
Short name T930
Test name
Test status
Simulation time 6040508865 ps
CPU time 9.74 seconds
Started Aug 10 06:08:28 PM PDT 24
Finished Aug 10 06:08:38 PM PDT 24
Peak memory 199796 kb
Host smart-cc35f8d6-3136-4a0e-bc42-bfe289550ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633908904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3633908904
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.170253046
Short name T938
Test name
Test status
Simulation time 128499060324 ps
CPU time 610.86 seconds
Started Aug 10 06:08:36 PM PDT 24
Finished Aug 10 06:18:48 PM PDT 24
Peak memory 216552 kb
Host smart-7f6296a9-f559-43ee-ac89-b5d1f0859ef7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170253046 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.170253046
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.1976193645
Short name T783
Test name
Test status
Simulation time 488026988 ps
CPU time 2.18 seconds
Started Aug 10 06:08:37 PM PDT 24
Finished Aug 10 06:08:39 PM PDT 24
Peak memory 198536 kb
Host smart-0742c343-7875-48d9-a878-2a1e58d49093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976193645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1976193645
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1874590664
Short name T351
Test name
Test status
Simulation time 12305240463 ps
CPU time 20.27 seconds
Started Aug 10 06:08:28 PM PDT 24
Finished Aug 10 06:08:48 PM PDT 24
Peak memory 197032 kb
Host smart-c48b85d7-a7be-48a6-a56b-65d6f3ef37ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874590664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1874590664
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.1433794705
Short name T765
Test name
Test status
Simulation time 20822822 ps
CPU time 0.54 seconds
Started Aug 10 06:10:18 PM PDT 24
Finished Aug 10 06:10:18 PM PDT 24
Peak memory 194592 kb
Host smart-bb14d230-8282-4bd3-9ed7-bec8a60924eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433794705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1433794705
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.1347647457
Short name T601
Test name
Test status
Simulation time 50351149892 ps
CPU time 70.97 seconds
Started Aug 10 06:10:10 PM PDT 24
Finished Aug 10 06:11:21 PM PDT 24
Peak memory 199968 kb
Host smart-8c250e3d-eaed-43c0-ae97-f659b31147bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347647457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1347647457
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.4036658023
Short name T1081
Test name
Test status
Simulation time 78617247327 ps
CPU time 35.78 seconds
Started Aug 10 06:10:13 PM PDT 24
Finished Aug 10 06:10:48 PM PDT 24
Peak memory 199888 kb
Host smart-cb623b14-9bb6-4017-87f0-10969c46a79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036658023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.4036658023
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_intr.2288259410
Short name T661
Test name
Test status
Simulation time 83765616238 ps
CPU time 143.62 seconds
Started Aug 10 06:10:10 PM PDT 24
Finished Aug 10 06:12:34 PM PDT 24
Peak memory 199968 kb
Host smart-009374a9-1fcc-46da-878e-88b387de2866
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288259410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2288259410
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_loopback.1362676527
Short name T379
Test name
Test status
Simulation time 7575919776 ps
CPU time 20.1 seconds
Started Aug 10 06:10:12 PM PDT 24
Finished Aug 10 06:10:32 PM PDT 24
Peak memory 199884 kb
Host smart-1f2d57dd-3db9-47a7-a016-d243de965ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362676527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1362676527
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.3368960397
Short name T1066
Test name
Test status
Simulation time 43527880212 ps
CPU time 18.12 seconds
Started Aug 10 06:10:10 PM PDT 24
Finished Aug 10 06:10:29 PM PDT 24
Peak memory 195116 kb
Host smart-74dd34ac-6298-48d3-8a96-abd793503d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368960397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3368960397
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.414515552
Short name T387
Test name
Test status
Simulation time 11929901600 ps
CPU time 611.59 seconds
Started Aug 10 06:10:10 PM PDT 24
Finished Aug 10 06:20:22 PM PDT 24
Peak memory 200068 kb
Host smart-824ef51f-563e-4ad0-b5b7-645d976d43c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=414515552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.414515552
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2636081525
Short name T759
Test name
Test status
Simulation time 6850131459 ps
CPU time 14.75 seconds
Started Aug 10 06:10:10 PM PDT 24
Finished Aug 10 06:10:25 PM PDT 24
Peak memory 198088 kb
Host smart-26766a69-9774-40e5-af81-4cc63d59105e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2636081525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2636081525
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.226830659
Short name T101
Test name
Test status
Simulation time 73078450814 ps
CPU time 45.51 seconds
Started Aug 10 06:10:09 PM PDT 24
Finished Aug 10 06:10:55 PM PDT 24
Peak memory 200008 kb
Host smart-515416d8-0e99-4ce8-b54f-b3a297b5f947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226830659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.226830659
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.426843462
Short name T757
Test name
Test status
Simulation time 37164807663 ps
CPU time 50.58 seconds
Started Aug 10 06:10:10 PM PDT 24
Finished Aug 10 06:11:01 PM PDT 24
Peak memory 196028 kb
Host smart-d0ecbf70-8e65-4463-8c5f-ce08ef93219c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426843462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.426843462
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2118953792
Short name T1012
Test name
Test status
Simulation time 730914646 ps
CPU time 1.34 seconds
Started Aug 10 06:10:03 PM PDT 24
Finished Aug 10 06:10:04 PM PDT 24
Peak memory 198312 kb
Host smart-7570071d-1105-4a4c-8a24-4b8eb6d35dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118953792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2118953792
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.451684062
Short name T996
Test name
Test status
Simulation time 268325728895 ps
CPU time 106.75 seconds
Started Aug 10 06:10:19 PM PDT 24
Finished Aug 10 06:12:06 PM PDT 24
Peak memory 200304 kb
Host smart-c348a10a-3bf7-4bdd-be17-d86749d32959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451684062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.451684062
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1019268920
Short name T7
Test name
Test status
Simulation time 1369560954 ps
CPU time 1.71 seconds
Started Aug 10 06:10:11 PM PDT 24
Finished Aug 10 06:10:13 PM PDT 24
Peak memory 198272 kb
Host smart-ff1e0f96-95a3-4515-bcb5-ee25d9db5f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019268920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1019268920
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.1100481667
Short name T688
Test name
Test status
Simulation time 113420213783 ps
CPU time 74.37 seconds
Started Aug 10 06:10:11 PM PDT 24
Finished Aug 10 06:11:25 PM PDT 24
Peak memory 199948 kb
Host smart-c715f9cf-de1c-4c95-9c24-5413edd0d018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100481667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1100481667
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.1074069257
Short name T503
Test name
Test status
Simulation time 177318306779 ps
CPU time 19.63 seconds
Started Aug 10 06:15:05 PM PDT 24
Finished Aug 10 06:15:24 PM PDT 24
Peak memory 199976 kb
Host smart-5d93f263-f2c6-4e86-a914-87afb950b56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074069257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1074069257
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.2839817320
Short name T248
Test name
Test status
Simulation time 59598266323 ps
CPU time 106.42 seconds
Started Aug 10 06:15:03 PM PDT 24
Finished Aug 10 06:16:50 PM PDT 24
Peak memory 199952 kb
Host smart-0694779b-42e9-4637-a067-7b0b557ef018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839817320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2839817320
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1886349710
Short name T190
Test name
Test status
Simulation time 100363641596 ps
CPU time 34.9 seconds
Started Aug 10 06:15:04 PM PDT 24
Finished Aug 10 06:15:39 PM PDT 24
Peak memory 199936 kb
Host smart-358f1fab-5d2a-4323-9dfe-bc4da06e990b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886349710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1886349710
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.3192048819
Short name T209
Test name
Test status
Simulation time 23634875490 ps
CPU time 18.94 seconds
Started Aug 10 06:15:05 PM PDT 24
Finished Aug 10 06:15:24 PM PDT 24
Peak memory 199792 kb
Host smart-5da09184-be38-4a7a-bd55-caab99ac2195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192048819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3192048819
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.544347868
Short name T217
Test name
Test status
Simulation time 166082963356 ps
CPU time 179.98 seconds
Started Aug 10 06:15:04 PM PDT 24
Finished Aug 10 06:18:04 PM PDT 24
Peak memory 198672 kb
Host smart-8f3e8174-8a51-4317-a8e5-08307982413b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544347868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.544347868
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2240356551
Short name T272
Test name
Test status
Simulation time 87454351495 ps
CPU time 31.26 seconds
Started Aug 10 06:15:11 PM PDT 24
Finished Aug 10 06:15:42 PM PDT 24
Peak memory 199976 kb
Host smart-0b7f93d5-7e4e-4c8c-8bb6-09ad0d59f44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240356551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2240356551
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2247832836
Short name T863
Test name
Test status
Simulation time 158979856828 ps
CPU time 67.07 seconds
Started Aug 10 06:10:25 PM PDT 24
Finished Aug 10 06:11:32 PM PDT 24
Peak memory 199964 kb
Host smart-29cc4938-53b1-485f-ad51-b9dd24741114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247832836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2247832836
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.2079676425
Short name T761
Test name
Test status
Simulation time 91451761937 ps
CPU time 124.21 seconds
Started Aug 10 06:10:18 PM PDT 24
Finished Aug 10 06:12:23 PM PDT 24
Peak memory 199884 kb
Host smart-a4906d0e-c0fa-47ac-a757-13ad5494a6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079676425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2079676425
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.3545780966
Short name T81
Test name
Test status
Simulation time 10589695151 ps
CPU time 98.48 seconds
Started Aug 10 06:10:17 PM PDT 24
Finished Aug 10 06:11:55 PM PDT 24
Peak memory 199840 kb
Host smart-12e58b12-1ffb-4d3d-acda-0b51c0a86bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545780966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3545780966
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.159401675
Short name T819
Test name
Test status
Simulation time 17947727108 ps
CPU time 17.02 seconds
Started Aug 10 06:10:17 PM PDT 24
Finished Aug 10 06:10:34 PM PDT 24
Peak memory 199928 kb
Host smart-6b40f5c8-1bf2-467a-96f8-9f6275eb13fe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159401675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.159401675
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_loopback.2577719020
Short name T342
Test name
Test status
Simulation time 7006952571 ps
CPU time 4.04 seconds
Started Aug 10 06:10:18 PM PDT 24
Finished Aug 10 06:10:23 PM PDT 24
Peak memory 198356 kb
Host smart-4dfc8949-70c7-47be-afc5-70514bff351d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577719020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2577719020
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.3459217874
Short name T698
Test name
Test status
Simulation time 75122401775 ps
CPU time 108.46 seconds
Started Aug 10 06:10:17 PM PDT 24
Finished Aug 10 06:12:06 PM PDT 24
Peak memory 199864 kb
Host smart-667fcce8-5ba2-4f4d-a592-4aed1754f363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459217874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3459217874
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.3665407888
Short name T480
Test name
Test status
Simulation time 8594498143 ps
CPU time 421.35 seconds
Started Aug 10 06:10:17 PM PDT 24
Finished Aug 10 06:17:19 PM PDT 24
Peak memory 199964 kb
Host smart-5f53fb9f-55e3-4d68-8953-94387b12acc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3665407888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3665407888
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3910450683
Short name T517
Test name
Test status
Simulation time 5243756618 ps
CPU time 21.31 seconds
Started Aug 10 06:10:19 PM PDT 24
Finished Aug 10 06:10:40 PM PDT 24
Peak memory 199064 kb
Host smart-30662e52-29dd-4bf6-acd9-9cd711761da7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3910450683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3910450683
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.4110047858
Short name T788
Test name
Test status
Simulation time 131790393831 ps
CPU time 51.14 seconds
Started Aug 10 06:10:18 PM PDT 24
Finished Aug 10 06:11:09 PM PDT 24
Peak memory 199872 kb
Host smart-268b956b-4af9-493b-9391-a6df66a672c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110047858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.4110047858
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.4021874791
Short name T860
Test name
Test status
Simulation time 40880977396 ps
CPU time 30.52 seconds
Started Aug 10 06:10:19 PM PDT 24
Finished Aug 10 06:10:50 PM PDT 24
Peak memory 195860 kb
Host smart-0a8d4d8e-9d32-4a94-92e3-430575dd49cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021874791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.4021874791
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.86621228
Short name T401
Test name
Test status
Simulation time 291973906 ps
CPU time 0.96 seconds
Started Aug 10 06:10:18 PM PDT 24
Finished Aug 10 06:10:19 PM PDT 24
Peak memory 198452 kb
Host smart-7a0b4671-f101-4944-850b-e878f1da634d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86621228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.86621228
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.493521934
Short name T611
Test name
Test status
Simulation time 269283355619 ps
CPU time 56.22 seconds
Started Aug 10 06:10:25 PM PDT 24
Finished Aug 10 06:11:22 PM PDT 24
Peak memory 199900 kb
Host smart-f441f441-c5ba-4cbd-96f7-a323e66ed75b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493521934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.493521934
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3459016544
Short name T810
Test name
Test status
Simulation time 284703334340 ps
CPU time 691.37 seconds
Started Aug 10 06:10:18 PM PDT 24
Finished Aug 10 06:21:50 PM PDT 24
Peak memory 216496 kb
Host smart-1f5a964e-e29f-46d9-b467-d4838f166f27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459016544 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3459016544
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.3075257582
Short name T1014
Test name
Test status
Simulation time 803057907 ps
CPU time 1.4 seconds
Started Aug 10 06:10:16 PM PDT 24
Finished Aug 10 06:10:18 PM PDT 24
Peak memory 197568 kb
Host smart-4a1bd88b-7a77-4c7d-a103-e9ebb6d3d141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075257582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3075257582
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.2660528042
Short name T724
Test name
Test status
Simulation time 59569653154 ps
CPU time 8.98 seconds
Started Aug 10 06:10:26 PM PDT 24
Finished Aug 10 06:10:35 PM PDT 24
Peak memory 199888 kb
Host smart-75b39050-5992-41e7-8d47-07a55d300a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660528042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2660528042
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.2711459265
Short name T549
Test name
Test status
Simulation time 83032856419 ps
CPU time 34.19 seconds
Started Aug 10 06:15:11 PM PDT 24
Finished Aug 10 06:15:45 PM PDT 24
Peak memory 199996 kb
Host smart-4d6cd138-7b92-45d0-8c45-745ddaabc76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711459265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2711459265
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.164878127
Short name T978
Test name
Test status
Simulation time 154120552083 ps
CPU time 225.76 seconds
Started Aug 10 06:15:12 PM PDT 24
Finished Aug 10 06:18:57 PM PDT 24
Peak memory 199952 kb
Host smart-207375c4-e2c5-455e-b401-73f1ff2ae52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164878127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.164878127
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2615522781
Short name T871
Test name
Test status
Simulation time 27515359774 ps
CPU time 51.49 seconds
Started Aug 10 06:15:13 PM PDT 24
Finished Aug 10 06:16:04 PM PDT 24
Peak memory 199868 kb
Host smart-ce868d26-0149-4e4e-9f55-4a5f4fe46dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615522781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2615522781
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2029659214
Short name T99
Test name
Test status
Simulation time 154389236998 ps
CPU time 105.39 seconds
Started Aug 10 06:15:11 PM PDT 24
Finished Aug 10 06:16:56 PM PDT 24
Peak memory 199856 kb
Host smart-9c11817f-4b96-40d7-b9d8-923dc8f8df99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029659214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2029659214
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.2963853313
Short name T793
Test name
Test status
Simulation time 42181564663 ps
CPU time 60.81 seconds
Started Aug 10 06:15:10 PM PDT 24
Finished Aug 10 06:16:11 PM PDT 24
Peak memory 199876 kb
Host smart-24b46c2e-12a1-4d1a-971e-b32aaa20cbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963853313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2963853313
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1545648842
Short name T646
Test name
Test status
Simulation time 20469044323 ps
CPU time 19.79 seconds
Started Aug 10 06:15:13 PM PDT 24
Finished Aug 10 06:15:33 PM PDT 24
Peak memory 199928 kb
Host smart-09e3f90f-01a8-43e2-9611-ce7626a467d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545648842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1545648842
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2123937947
Short name T310
Test name
Test status
Simulation time 167305945147 ps
CPU time 128.97 seconds
Started Aug 10 06:15:10 PM PDT 24
Finished Aug 10 06:17:19 PM PDT 24
Peak memory 199792 kb
Host smart-d901d0c0-6b68-4b86-9b1d-e67d39fb11dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123937947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2123937947
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2600331604
Short name T778
Test name
Test status
Simulation time 25243700671 ps
CPU time 22.14 seconds
Started Aug 10 06:15:11 PM PDT 24
Finished Aug 10 06:15:33 PM PDT 24
Peak memory 199360 kb
Host smart-c47880b4-ba6a-4ee5-a2e7-4c4d22f42062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600331604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2600331604
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2325094088
Short name T1020
Test name
Test status
Simulation time 59526605 ps
CPU time 0.55 seconds
Started Aug 10 06:10:28 PM PDT 24
Finished Aug 10 06:10:29 PM PDT 24
Peak memory 195636 kb
Host smart-d32decd3-99e8-463d-b561-a32216340fea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325094088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2325094088
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.1701742170
Short name T966
Test name
Test status
Simulation time 260444223218 ps
CPU time 94.9 seconds
Started Aug 10 06:10:28 PM PDT 24
Finished Aug 10 06:12:03 PM PDT 24
Peak memory 199900 kb
Host smart-c3166bf4-87e1-4616-8bdd-9ca6c2d83ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701742170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1701742170
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2711832671
Short name T553
Test name
Test status
Simulation time 108043863271 ps
CPU time 173.88 seconds
Started Aug 10 06:10:30 PM PDT 24
Finished Aug 10 06:13:24 PM PDT 24
Peak memory 199976 kb
Host smart-59ccc1a5-1538-4141-8c3b-81ccc3e81592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711832671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2711832671
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_intr.2215075589
Short name T1112
Test name
Test status
Simulation time 89821741130 ps
CPU time 20.74 seconds
Started Aug 10 06:10:26 PM PDT 24
Finished Aug 10 06:10:47 PM PDT 24
Peak memory 199652 kb
Host smart-e9637089-185f-45f0-9515-2a7952af16b5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215075589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2215075589
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.753979234
Short name T1079
Test name
Test status
Simulation time 102340518323 ps
CPU time 431 seconds
Started Aug 10 06:10:26 PM PDT 24
Finished Aug 10 06:17:37 PM PDT 24
Peak memory 199972 kb
Host smart-086e058f-f494-43ae-b17d-fd8296ee42f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=753979234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.753979234
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.2173726443
Short name T51
Test name
Test status
Simulation time 9016553989 ps
CPU time 12.9 seconds
Started Aug 10 06:10:27 PM PDT 24
Finished Aug 10 06:10:40 PM PDT 24
Peak memory 199760 kb
Host smart-1f8d06dd-2862-4c74-8d13-d2088e8d6211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173726443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2173726443
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.132812604
Short name T610
Test name
Test status
Simulation time 67424926110 ps
CPU time 60.11 seconds
Started Aug 10 06:10:27 PM PDT 24
Finished Aug 10 06:11:27 PM PDT 24
Peak memory 208124 kb
Host smart-d40ab0ea-bdcf-46b3-971d-0feafd62e613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132812604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.132812604
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.2845492352
Short name T548
Test name
Test status
Simulation time 27539482061 ps
CPU time 162.16 seconds
Started Aug 10 06:10:27 PM PDT 24
Finished Aug 10 06:13:09 PM PDT 24
Peak memory 199784 kb
Host smart-a05c020d-7784-4995-967a-4a721b4e9028
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2845492352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2845492352
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.270922475
Short name T433
Test name
Test status
Simulation time 6681604128 ps
CPU time 5.63 seconds
Started Aug 10 06:10:27 PM PDT 24
Finished Aug 10 06:10:33 PM PDT 24
Peak memory 199212 kb
Host smart-0ef23e6a-7e3b-4052-a77e-39f68c4ce71c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=270922475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.270922475
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.3062031650
Short name T975
Test name
Test status
Simulation time 56790665817 ps
CPU time 85.01 seconds
Started Aug 10 06:10:27 PM PDT 24
Finished Aug 10 06:11:53 PM PDT 24
Peak memory 199956 kb
Host smart-674d8013-dc76-4260-8db2-7fd45f9e723c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062031650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3062031650
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.216836652
Short name T280
Test name
Test status
Simulation time 33187159182 ps
CPU time 11.75 seconds
Started Aug 10 06:10:27 PM PDT 24
Finished Aug 10 06:10:39 PM PDT 24
Peak memory 195848 kb
Host smart-2a2842a0-b97a-4a4c-8af7-0a62bfbfdbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216836652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.216836652
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.165545818
Short name T1137
Test name
Test status
Simulation time 6054945752 ps
CPU time 12.05 seconds
Started Aug 10 06:10:27 PM PDT 24
Finished Aug 10 06:10:39 PM PDT 24
Peak memory 199112 kb
Host smart-b67e85a7-8d27-4155-af4c-6e35646bfec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165545818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.165545818
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.4070949422
Short name T991
Test name
Test status
Simulation time 117499634601 ps
CPU time 75.53 seconds
Started Aug 10 06:10:27 PM PDT 24
Finished Aug 10 06:11:42 PM PDT 24
Peak memory 199992 kb
Host smart-63853d4e-3ded-4faa-aa6d-47cb8d62c5a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070949422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.4070949422
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.2898006918
Short name T989
Test name
Test status
Simulation time 319063643852 ps
CPU time 728.92 seconds
Started Aug 10 06:10:27 PM PDT 24
Finished Aug 10 06:22:36 PM PDT 24
Peak memory 224840 kb
Host smart-ce14ed68-413e-4c26-9e0a-215f2824458b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898006918 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.2898006918
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3827376078
Short name T974
Test name
Test status
Simulation time 971342100 ps
CPU time 3.47 seconds
Started Aug 10 06:10:28 PM PDT 24
Finished Aug 10 06:10:32 PM PDT 24
Peak memory 198224 kb
Host smart-168948ba-98b8-429f-82b9-472bf971f8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827376078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3827376078
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1753001034
Short name T349
Test name
Test status
Simulation time 189612516553 ps
CPU time 200.4 seconds
Started Aug 10 06:10:27 PM PDT 24
Finished Aug 10 06:13:48 PM PDT 24
Peak memory 199908 kb
Host smart-a4335022-71f5-4e46-84dd-679c745f37e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753001034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1753001034
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3167341501
Short name T901
Test name
Test status
Simulation time 62882514000 ps
CPU time 52.42 seconds
Started Aug 10 06:15:11 PM PDT 24
Finished Aug 10 06:16:04 PM PDT 24
Peak memory 199868 kb
Host smart-799837fe-93ca-4591-a0d1-536d1574bc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167341501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3167341501
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1631024874
Short name T140
Test name
Test status
Simulation time 55521718511 ps
CPU time 47.38 seconds
Started Aug 10 06:15:10 PM PDT 24
Finished Aug 10 06:15:58 PM PDT 24
Peak memory 199872 kb
Host smart-072f09b9-ae29-444e-93fc-9c570d839226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631024874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1631024874
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.4234305296
Short name T206
Test name
Test status
Simulation time 23381090082 ps
CPU time 32.92 seconds
Started Aug 10 06:15:12 PM PDT 24
Finished Aug 10 06:15:45 PM PDT 24
Peak memory 199868 kb
Host smart-929ba06d-29ec-40a4-bbe1-0863cf993472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234305296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.4234305296
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.478415269
Short name T133
Test name
Test status
Simulation time 32099813226 ps
CPU time 13.58 seconds
Started Aug 10 06:15:21 PM PDT 24
Finished Aug 10 06:15:35 PM PDT 24
Peak memory 199968 kb
Host smart-f76c6554-f152-4aac-9332-951068bc82f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478415269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.478415269
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.904224049
Short name T987
Test name
Test status
Simulation time 35095205234 ps
CPU time 20.24 seconds
Started Aug 10 06:15:18 PM PDT 24
Finished Aug 10 06:15:38 PM PDT 24
Peak memory 199952 kb
Host smart-4f5c0b4c-4cc1-45be-8ecd-6f1e4e23e437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904224049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.904224049
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2995932006
Short name T131
Test name
Test status
Simulation time 41732818653 ps
CPU time 59.69 seconds
Started Aug 10 06:15:16 PM PDT 24
Finished Aug 10 06:16:16 PM PDT 24
Peak memory 199920 kb
Host smart-9d362dad-6e49-4fb2-8eb0-17930884c550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995932006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2995932006
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.1898936562
Short name T829
Test name
Test status
Simulation time 53144775116 ps
CPU time 18.7 seconds
Started Aug 10 06:15:17 PM PDT 24
Finished Aug 10 06:15:36 PM PDT 24
Peak memory 199724 kb
Host smart-ac20d662-9cbb-43f2-84ac-1f8d375bafcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898936562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1898936562
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.594760700
Short name T717
Test name
Test status
Simulation time 299397388360 ps
CPU time 25.92 seconds
Started Aug 10 06:15:17 PM PDT 24
Finished Aug 10 06:15:43 PM PDT 24
Peak memory 199748 kb
Host smart-b92b48cb-5c40-4ff4-b166-a0bf3d21b26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594760700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.594760700
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1824013241
Short name T1168
Test name
Test status
Simulation time 13590806 ps
CPU time 0.54 seconds
Started Aug 10 06:10:35 PM PDT 24
Finished Aug 10 06:10:35 PM PDT 24
Peak memory 195172 kb
Host smart-45cd40c8-2236-41f6-8067-598debd06e7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824013241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1824013241
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.3908364652
Short name T588
Test name
Test status
Simulation time 29819960293 ps
CPU time 20.92 seconds
Started Aug 10 06:10:28 PM PDT 24
Finished Aug 10 06:10:49 PM PDT 24
Peak memory 199944 kb
Host smart-7185c5f0-7475-4d42-988d-be4d342b83b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908364652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3908364652
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2340836591
Short name T132
Test name
Test status
Simulation time 74901946308 ps
CPU time 131.75 seconds
Started Aug 10 06:10:27 PM PDT 24
Finished Aug 10 06:12:39 PM PDT 24
Peak memory 199824 kb
Host smart-9df0ebcb-f713-427e-b433-5e931d026af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340836591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2340836591
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1085051624
Short name T230
Test name
Test status
Simulation time 107951187979 ps
CPU time 62.33 seconds
Started Aug 10 06:10:38 PM PDT 24
Finished Aug 10 06:11:41 PM PDT 24
Peak memory 199912 kb
Host smart-d5af6c54-f4eb-4116-9146-a56ede0fecf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085051624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1085051624
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2585248778
Short name T125
Test name
Test status
Simulation time 28140185915 ps
CPU time 46.33 seconds
Started Aug 10 06:10:36 PM PDT 24
Finished Aug 10 06:11:23 PM PDT 24
Peak memory 199860 kb
Host smart-ac3049c7-3ffb-4fbc-b4c0-dbe71d3512dd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585248778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2585248778
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.267681924
Short name T457
Test name
Test status
Simulation time 91137357706 ps
CPU time 307.63 seconds
Started Aug 10 06:10:40 PM PDT 24
Finished Aug 10 06:15:48 PM PDT 24
Peak memory 199980 kb
Host smart-276203a5-56a9-43a5-bbfc-b3773559f017
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=267681924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.267681924
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1121735559
Short name T1174
Test name
Test status
Simulation time 2159111972 ps
CPU time 4.87 seconds
Started Aug 10 06:10:36 PM PDT 24
Finished Aug 10 06:10:41 PM PDT 24
Peak memory 198804 kb
Host smart-0be7c5e6-2977-4d8e-97de-94cf14c3feb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121735559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1121735559
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.3483553700
Short name T343
Test name
Test status
Simulation time 22966377479 ps
CPU time 24.04 seconds
Started Aug 10 06:10:35 PM PDT 24
Finished Aug 10 06:10:59 PM PDT 24
Peak memory 198776 kb
Host smart-09c863a7-f293-4694-b4d0-bf2f4d358a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483553700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3483553700
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.1474082509
Short name T296
Test name
Test status
Simulation time 15166538541 ps
CPU time 420.56 seconds
Started Aug 10 06:10:36 PM PDT 24
Finished Aug 10 06:17:37 PM PDT 24
Peak memory 199836 kb
Host smart-4e6a8eb3-8df3-47a9-8544-e11ef38f85ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1474082509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1474082509
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.1583558535
Short name T458
Test name
Test status
Simulation time 4102665673 ps
CPU time 22.23 seconds
Started Aug 10 06:10:39 PM PDT 24
Finished Aug 10 06:11:01 PM PDT 24
Peak memory 199412 kb
Host smart-723c626d-db5a-4ce8-931a-8e94bf217633
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1583558535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1583558535
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3955081077
Short name T485
Test name
Test status
Simulation time 33873812534 ps
CPU time 15.08 seconds
Started Aug 10 06:10:38 PM PDT 24
Finished Aug 10 06:10:53 PM PDT 24
Peak memory 199732 kb
Host smart-2e54fa6d-8c37-4869-bbbe-5cc9b64b57d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955081077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3955081077
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.302536172
Short name T437
Test name
Test status
Simulation time 3789374224 ps
CPU time 1.82 seconds
Started Aug 10 06:10:38 PM PDT 24
Finished Aug 10 06:10:40 PM PDT 24
Peak memory 196432 kb
Host smart-f8424083-e17f-4778-99dd-d34d8ba00bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302536172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.302536172
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.273479900
Short name T35
Test name
Test status
Simulation time 648264322 ps
CPU time 2.93 seconds
Started Aug 10 06:10:28 PM PDT 24
Finished Aug 10 06:10:31 PM PDT 24
Peak memory 199744 kb
Host smart-788b03fc-5056-428c-881d-fd9e1aec46fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273479900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.273479900
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.2615656936
Short name T920
Test name
Test status
Simulation time 306486695014 ps
CPU time 800.36 seconds
Started Aug 10 06:10:40 PM PDT 24
Finished Aug 10 06:24:00 PM PDT 24
Peak memory 200008 kb
Host smart-2cc93751-b451-49a7-86cc-f4aa46672aaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615656936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2615656936
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.742894716
Short name T105
Test name
Test status
Simulation time 73422257955 ps
CPU time 214.9 seconds
Started Aug 10 06:10:35 PM PDT 24
Finished Aug 10 06:14:10 PM PDT 24
Peak memory 216612 kb
Host smart-d068b78e-5a28-4ed1-8b36-a61e416c84c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742894716 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.742894716
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.2309986366
Short name T1097
Test name
Test status
Simulation time 8175003874 ps
CPU time 11.08 seconds
Started Aug 10 06:10:35 PM PDT 24
Finished Aug 10 06:10:46 PM PDT 24
Peak memory 199980 kb
Host smart-26396449-da7c-4be4-87cf-0cdad527a23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309986366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2309986366
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.343584855
Short name T957
Test name
Test status
Simulation time 160223785188 ps
CPU time 460.86 seconds
Started Aug 10 06:10:28 PM PDT 24
Finished Aug 10 06:18:09 PM PDT 24
Peak memory 199976 kb
Host smart-e839b618-3ac6-4e3d-ab9d-f84c1884141d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343584855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.343584855
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.1294354238
Short name T754
Test name
Test status
Simulation time 69301940004 ps
CPU time 29.64 seconds
Started Aug 10 06:15:15 PM PDT 24
Finished Aug 10 06:15:45 PM PDT 24
Peak memory 199916 kb
Host smart-a36d5c91-e507-448f-830b-d432d2ee81f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294354238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1294354238
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.3719835304
Short name T112
Test name
Test status
Simulation time 35766972235 ps
CPU time 13.94 seconds
Started Aug 10 06:15:16 PM PDT 24
Finished Aug 10 06:15:30 PM PDT 24
Peak memory 199868 kb
Host smart-69d10fd9-aa2d-4e58-9003-be937a1f6743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719835304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3719835304
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3371377272
Short name T47
Test name
Test status
Simulation time 43839533862 ps
CPU time 35.87 seconds
Started Aug 10 06:15:18 PM PDT 24
Finished Aug 10 06:15:54 PM PDT 24
Peak memory 199712 kb
Host smart-2b1e2f8b-7d1d-4b17-9737-106af367b433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371377272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3371377272
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1621140842
Short name T833
Test name
Test status
Simulation time 33085152384 ps
CPU time 52.98 seconds
Started Aug 10 06:15:17 PM PDT 24
Finished Aug 10 06:16:10 PM PDT 24
Peak memory 199820 kb
Host smart-602aa82a-6ded-4d2b-affb-121161676888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621140842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1621140842
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.656614582
Short name T189
Test name
Test status
Simulation time 129832120915 ps
CPU time 26.64 seconds
Started Aug 10 06:15:18 PM PDT 24
Finished Aug 10 06:15:45 PM PDT 24
Peak memory 199976 kb
Host smart-0d98d17c-4159-4cb6-97dd-9655190ac6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656614582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.656614582
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.71940759
Short name T237
Test name
Test status
Simulation time 36372323297 ps
CPU time 20.49 seconds
Started Aug 10 06:15:20 PM PDT 24
Finished Aug 10 06:15:40 PM PDT 24
Peak memory 199976 kb
Host smart-592c21ee-9cfd-488d-b1d2-16a06db99590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71940759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.71940759
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.1618113644
Short name T252
Test name
Test status
Simulation time 50535044368 ps
CPU time 20.38 seconds
Started Aug 10 06:15:27 PM PDT 24
Finished Aug 10 06:15:48 PM PDT 24
Peak memory 199660 kb
Host smart-47d762f5-8376-4aaa-ab9b-456d2fb68b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618113644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1618113644
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1651072084
Short name T1024
Test name
Test status
Simulation time 116392752862 ps
CPU time 47 seconds
Started Aug 10 06:15:24 PM PDT 24
Finished Aug 10 06:16:11 PM PDT 24
Peak memory 199888 kb
Host smart-8ec90ba4-b557-48c7-9723-672e8266893a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651072084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1651072084
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.864775816
Short name T1146
Test name
Test status
Simulation time 64536463632 ps
CPU time 29.71 seconds
Started Aug 10 06:15:24 PM PDT 24
Finished Aug 10 06:15:54 PM PDT 24
Peak memory 199940 kb
Host smart-beb0969a-a9b7-42bd-b094-8f21b37c91fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864775816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.864775816
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.4233430878
Short name T370
Test name
Test status
Simulation time 35360922 ps
CPU time 0.55 seconds
Started Aug 10 06:10:41 PM PDT 24
Finished Aug 10 06:10:42 PM PDT 24
Peak memory 195392 kb
Host smart-ce92bba6-d4ed-4666-9fd1-e89b1a2f17c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233430878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.4233430878
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2953372266
Short name T756
Test name
Test status
Simulation time 60857965005 ps
CPU time 25.78 seconds
Started Aug 10 06:10:37 PM PDT 24
Finished Aug 10 06:11:03 PM PDT 24
Peak memory 199848 kb
Host smart-8d529469-9c79-49c2-83d5-05794126ff45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953372266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2953372266
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.851365786
Short name T959
Test name
Test status
Simulation time 83421174348 ps
CPU time 118.03 seconds
Started Aug 10 06:10:38 PM PDT 24
Finished Aug 10 06:12:37 PM PDT 24
Peak memory 200000 kb
Host smart-f25a3f97-668d-4b31-b133-ac02ff1f08cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851365786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.851365786
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.2728662127
Short name T284
Test name
Test status
Simulation time 43022179681 ps
CPU time 59.74 seconds
Started Aug 10 06:10:47 PM PDT 24
Finished Aug 10 06:11:47 PM PDT 24
Peak memory 199908 kb
Host smart-e1e99c5e-1dc5-4e46-a96c-46d424fe5b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728662127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2728662127
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.3352197073
Short name T1078
Test name
Test status
Simulation time 188069356691 ps
CPU time 115.93 seconds
Started Aug 10 06:10:44 PM PDT 24
Finished Aug 10 06:12:40 PM PDT 24
Peak memory 199852 kb
Host smart-18ace8ae-40ca-411d-8860-bb548b8f6f34
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352197073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3352197073
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.3745348930
Short name T478
Test name
Test status
Simulation time 141630518332 ps
CPU time 216.68 seconds
Started Aug 10 06:10:45 PM PDT 24
Finished Aug 10 06:14:22 PM PDT 24
Peak memory 199900 kb
Host smart-6ed3e3c7-5e29-4954-b4e0-3deb25f54b3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3745348930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3745348930
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3955199151
Short name T19
Test name
Test status
Simulation time 5988331492 ps
CPU time 7.84 seconds
Started Aug 10 06:10:42 PM PDT 24
Finished Aug 10 06:10:49 PM PDT 24
Peak memory 199856 kb
Host smart-32a3b79d-62ea-466f-9df2-81ac9b076278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955199151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3955199151
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.773472667
Short name T841
Test name
Test status
Simulation time 16255783000 ps
CPU time 15.42 seconds
Started Aug 10 06:10:42 PM PDT 24
Finished Aug 10 06:10:58 PM PDT 24
Peak memory 197728 kb
Host smart-6fa50f94-5f92-4da5-9d34-97a07bc2ddc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773472667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.773472667
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.4110943557
Short name T531
Test name
Test status
Simulation time 5984844933 ps
CPU time 347.21 seconds
Started Aug 10 06:10:43 PM PDT 24
Finished Aug 10 06:16:31 PM PDT 24
Peak memory 199836 kb
Host smart-009b36e6-a3d2-40cf-b9ff-83aeadfb5db2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4110943557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.4110943557
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1911620753
Short name T731
Test name
Test status
Simulation time 1821906144 ps
CPU time 2.54 seconds
Started Aug 10 06:10:42 PM PDT 24
Finished Aug 10 06:10:45 PM PDT 24
Peak memory 197644 kb
Host smart-d2837492-ea88-428e-b698-0ae4dfcabb14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1911620753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1911620753
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.374902437
Short name T306
Test name
Test status
Simulation time 112213512225 ps
CPU time 27.38 seconds
Started Aug 10 06:10:43 PM PDT 24
Finished Aug 10 06:11:11 PM PDT 24
Peak memory 199920 kb
Host smart-5f52a8c3-bb9c-4498-9082-0c61f57e03ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374902437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.374902437
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3397638265
Short name T525
Test name
Test status
Simulation time 54679969444 ps
CPU time 87.94 seconds
Started Aug 10 06:10:44 PM PDT 24
Finished Aug 10 06:12:12 PM PDT 24
Peak memory 195888 kb
Host smart-b862a279-56d8-4df9-a59c-9058e9f6e5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397638265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3397638265
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3353483184
Short name T672
Test name
Test status
Simulation time 5376652037 ps
CPU time 16.09 seconds
Started Aug 10 06:10:36 PM PDT 24
Finished Aug 10 06:10:52 PM PDT 24
Peak memory 199264 kb
Host smart-dd2b947a-b95d-46ca-8ebe-29c6dd9c3e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353483184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3353483184
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.276874729
Short name T477
Test name
Test status
Simulation time 124018703547 ps
CPU time 1369.86 seconds
Started Aug 10 06:10:45 PM PDT 24
Finished Aug 10 06:33:35 PM PDT 24
Peak memory 199992 kb
Host smart-38c91192-dba3-4abb-be4b-dfb4010ecc7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276874729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.276874729
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1982778214
Short name T563
Test name
Test status
Simulation time 181812739899 ps
CPU time 449.47 seconds
Started Aug 10 06:10:47 PM PDT 24
Finished Aug 10 06:18:17 PM PDT 24
Peak memory 224836 kb
Host smart-e605ee3b-2bf8-48de-b8dc-bd21eedbbe73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982778214 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1982778214
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1533064223
Short name T313
Test name
Test status
Simulation time 9814672136 ps
CPU time 3.36 seconds
Started Aug 10 06:10:45 PM PDT 24
Finished Aug 10 06:10:48 PM PDT 24
Peak memory 200000 kb
Host smart-5003d980-f9f0-483d-b33b-db9dbff2fb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533064223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1533064223
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3377097463
Short name T461
Test name
Test status
Simulation time 43671324232 ps
CPU time 17.11 seconds
Started Aug 10 06:10:39 PM PDT 24
Finished Aug 10 06:10:56 PM PDT 24
Peak memory 199928 kb
Host smart-83672738-4c27-4743-9c32-ae1c6be27986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377097463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3377097463
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.328342896
Short name T867
Test name
Test status
Simulation time 45380162155 ps
CPU time 21.04 seconds
Started Aug 10 06:15:27 PM PDT 24
Finished Aug 10 06:15:48 PM PDT 24
Peak memory 199808 kb
Host smart-3880968f-eb72-4e6e-905e-49e5ca300e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328342896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.328342896
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3742265528
Short name T890
Test name
Test status
Simulation time 137396285020 ps
CPU time 58.54 seconds
Started Aug 10 06:15:25 PM PDT 24
Finished Aug 10 06:16:24 PM PDT 24
Peak memory 199848 kb
Host smart-020e4a3c-075c-42bb-be47-a2c25840017f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742265528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3742265528
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.2432278642
Short name T415
Test name
Test status
Simulation time 220720454371 ps
CPU time 36.55 seconds
Started Aug 10 06:15:27 PM PDT 24
Finished Aug 10 06:16:03 PM PDT 24
Peak memory 199928 kb
Host smart-0b26a4f7-a244-4190-bc30-0344aea3b9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432278642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2432278642
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3092229298
Short name T809
Test name
Test status
Simulation time 24819018186 ps
CPU time 36.99 seconds
Started Aug 10 06:15:26 PM PDT 24
Finished Aug 10 06:16:03 PM PDT 24
Peak memory 199992 kb
Host smart-1d9dbdce-6d63-4407-9eb3-3a1077c39487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092229298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3092229298
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.4282963156
Short name T644
Test name
Test status
Simulation time 80838992559 ps
CPU time 61.92 seconds
Started Aug 10 06:15:28 PM PDT 24
Finished Aug 10 06:16:30 PM PDT 24
Peak memory 199920 kb
Host smart-ebdfe41a-bc61-48ca-88ba-f8fe821ba81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282963156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.4282963156
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2695118271
Short name T967
Test name
Test status
Simulation time 138487405588 ps
CPU time 21.46 seconds
Started Aug 10 06:15:27 PM PDT 24
Finished Aug 10 06:15:48 PM PDT 24
Peak memory 199964 kb
Host smart-8a7d6c46-85e6-45e0-86ea-41d809aa3ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695118271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2695118271
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1579335650
Short name T631
Test name
Test status
Simulation time 95343797699 ps
CPU time 76.29 seconds
Started Aug 10 06:15:25 PM PDT 24
Finished Aug 10 06:16:42 PM PDT 24
Peak memory 199980 kb
Host smart-d90a2041-7fd8-4985-a6e7-410215b2a7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579335650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1579335650
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.2881222269
Short name T786
Test name
Test status
Simulation time 15042558974 ps
CPU time 30.28 seconds
Started Aug 10 06:15:26 PM PDT 24
Finished Aug 10 06:15:56 PM PDT 24
Peak memory 199980 kb
Host smart-06c6aade-cbd2-4351-b2b3-0ea3a26c1f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881222269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2881222269
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.1974806677
Short name T936
Test name
Test status
Simulation time 87789058441 ps
CPU time 40.99 seconds
Started Aug 10 06:15:26 PM PDT 24
Finished Aug 10 06:16:07 PM PDT 24
Peak memory 199916 kb
Host smart-c749a3e8-28f6-431c-ab40-bf9ae29d4905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974806677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1974806677
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3518740366
Short name T388
Test name
Test status
Simulation time 21219443 ps
CPU time 0.53 seconds
Started Aug 10 06:10:49 PM PDT 24
Finished Aug 10 06:10:50 PM PDT 24
Peak memory 194288 kb
Host smart-572c737d-8611-459f-b4bc-8ffdb4405995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518740366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3518740366
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2326865256
Short name T513
Test name
Test status
Simulation time 103643267358 ps
CPU time 25.03 seconds
Started Aug 10 06:10:42 PM PDT 24
Finished Aug 10 06:11:07 PM PDT 24
Peak memory 199876 kb
Host smart-66a5f035-2e85-45b8-a881-b3e6e391987c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326865256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2326865256
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1677372098
Short name T148
Test name
Test status
Simulation time 87976644466 ps
CPU time 35.89 seconds
Started Aug 10 06:10:43 PM PDT 24
Finished Aug 10 06:11:19 PM PDT 24
Peak memory 199940 kb
Host smart-33f0e97c-397e-421b-8f1b-ee77f93153dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677372098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1677372098
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2972699171
Short name T165
Test name
Test status
Simulation time 84059948596 ps
CPU time 14.14 seconds
Started Aug 10 06:10:45 PM PDT 24
Finished Aug 10 06:11:00 PM PDT 24
Peak memory 199968 kb
Host smart-3f07f572-a4f0-4a41-9cb0-83e5690d373a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972699171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2972699171
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.2823603672
Short name T95
Test name
Test status
Simulation time 19184812856 ps
CPU time 12.02 seconds
Started Aug 10 06:10:50 PM PDT 24
Finished Aug 10 06:11:02 PM PDT 24
Peak memory 199928 kb
Host smart-c90c71e3-8357-46cc-9393-5ac208aacf68
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823603672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2823603672
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2011736580
Short name T1041
Test name
Test status
Simulation time 219735437735 ps
CPU time 142.01 seconds
Started Aug 10 06:10:52 PM PDT 24
Finished Aug 10 06:13:14 PM PDT 24
Peak memory 199716 kb
Host smart-a262995a-dc7f-422c-9032-2f8e8025662a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2011736580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2011736580
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.1689746804
Short name T1141
Test name
Test status
Simulation time 9618432174 ps
CPU time 9.76 seconds
Started Aug 10 06:10:49 PM PDT 24
Finished Aug 10 06:10:59 PM PDT 24
Peak memory 199540 kb
Host smart-20632ea4-48c1-47b7-84a6-f07d45d6191d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689746804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1689746804
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.2358661042
Short name T314
Test name
Test status
Simulation time 58306773074 ps
CPU time 82.26 seconds
Started Aug 10 06:10:52 PM PDT 24
Finished Aug 10 06:12:14 PM PDT 24
Peak memory 200100 kb
Host smart-c4267437-b4bc-413f-834e-939679a8abc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358661042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.2358661042
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.4254722919
Short name T323
Test name
Test status
Simulation time 9858224214 ps
CPU time 148.45 seconds
Started Aug 10 06:10:51 PM PDT 24
Finished Aug 10 06:13:20 PM PDT 24
Peak memory 199972 kb
Host smart-cc6157bf-a115-47b0-b290-d12bdeb88f1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4254722919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.4254722919
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3282714995
Short name T687
Test name
Test status
Simulation time 5616168972 ps
CPU time 58.34 seconds
Started Aug 10 06:10:51 PM PDT 24
Finished Aug 10 06:11:49 PM PDT 24
Peak memory 198340 kb
Host smart-fbc516a1-b9ab-42b4-bd43-4151c36f7f94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3282714995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3282714995
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.544272055
Short name T697
Test name
Test status
Simulation time 8403083520 ps
CPU time 15.24 seconds
Started Aug 10 06:10:53 PM PDT 24
Finished Aug 10 06:11:08 PM PDT 24
Peak memory 199932 kb
Host smart-a93993d6-c291-4be9-a6c7-7de3ec48d722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544272055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.544272055
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.908985654
Short name T389
Test name
Test status
Simulation time 5747275303 ps
CPU time 1.39 seconds
Started Aug 10 06:10:52 PM PDT 24
Finished Aug 10 06:10:54 PM PDT 24
Peak memory 196756 kb
Host smart-b53b5c32-4223-4c1b-a080-247f45321844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908985654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.908985654
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1728043000
Short name T597
Test name
Test status
Simulation time 718147357 ps
CPU time 1.69 seconds
Started Aug 10 06:10:42 PM PDT 24
Finished Aug 10 06:10:44 PM PDT 24
Peak memory 199888 kb
Host smart-4a7f646a-76f0-441d-909a-10b68443e95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728043000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1728043000
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.1990567409
Short name T60
Test name
Test status
Simulation time 105961764770 ps
CPU time 741.49 seconds
Started Aug 10 06:10:51 PM PDT 24
Finished Aug 10 06:23:13 PM PDT 24
Peak memory 216468 kb
Host smart-48d47374-2463-49bb-8ca9-7ddd5fa5ff3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990567409 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.1990567409
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.4204881622
Short name T862
Test name
Test status
Simulation time 1242610685 ps
CPU time 3.97 seconds
Started Aug 10 06:10:49 PM PDT 24
Finished Aug 10 06:10:54 PM PDT 24
Peak memory 198800 kb
Host smart-888afdac-f18f-4377-a386-17074685580c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204881622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.4204881622
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3115753965
Short name T521
Test name
Test status
Simulation time 36023774596 ps
CPU time 23.89 seconds
Started Aug 10 06:10:44 PM PDT 24
Finished Aug 10 06:11:08 PM PDT 24
Peak memory 199972 kb
Host smart-f6555d77-ef79-4c70-a911-9020a91acd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115753965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3115753965
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.2376680114
Short name T905
Test name
Test status
Simulation time 36215860554 ps
CPU time 16.54 seconds
Started Aug 10 06:15:26 PM PDT 24
Finished Aug 10 06:15:43 PM PDT 24
Peak memory 199816 kb
Host smart-75eb279f-a8db-4784-8996-c08a0b6c3935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376680114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2376680114
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.433371475
Short name T886
Test name
Test status
Simulation time 36937576798 ps
CPU time 27.04 seconds
Started Aug 10 06:15:35 PM PDT 24
Finished Aug 10 06:16:02 PM PDT 24
Peak memory 199916 kb
Host smart-dd1857a7-413f-42be-a849-09b0c92aa5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433371475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.433371475
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2706802743
Short name T780
Test name
Test status
Simulation time 115244889834 ps
CPU time 48.21 seconds
Started Aug 10 06:15:34 PM PDT 24
Finished Aug 10 06:16:23 PM PDT 24
Peak memory 199916 kb
Host smart-27e344f9-17cf-443f-bc86-95365bcd48d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706802743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2706802743
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.4223481671
Short name T844
Test name
Test status
Simulation time 26846419225 ps
CPU time 42.39 seconds
Started Aug 10 06:15:33 PM PDT 24
Finished Aug 10 06:16:16 PM PDT 24
Peak memory 199932 kb
Host smart-dd44394b-7dd2-4725-87a7-95dacc0a58f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223481671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.4223481671
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.31481268
Short name T218
Test name
Test status
Simulation time 16169893259 ps
CPU time 17.61 seconds
Started Aug 10 06:15:35 PM PDT 24
Finished Aug 10 06:15:52 PM PDT 24
Peak memory 200032 kb
Host smart-fd0ca6f8-23c0-45e7-aec9-b3a9a7600bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31481268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.31481268
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1899177830
Short name T352
Test name
Test status
Simulation time 31969261594 ps
CPU time 44.81 seconds
Started Aug 10 06:15:32 PM PDT 24
Finished Aug 10 06:16:17 PM PDT 24
Peak memory 199972 kb
Host smart-24ac671f-e2d4-4fc6-a94f-e2c26d6814fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899177830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1899177830
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1150492318
Short name T921
Test name
Test status
Simulation time 45561796690 ps
CPU time 16.25 seconds
Started Aug 10 06:15:34 PM PDT 24
Finished Aug 10 06:15:50 PM PDT 24
Peak memory 199636 kb
Host smart-2adb5252-5847-4669-96d6-7b256a06e20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150492318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1150492318
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.4168424958
Short name T584
Test name
Test status
Simulation time 9606218684 ps
CPU time 17 seconds
Started Aug 10 06:15:33 PM PDT 24
Finished Aug 10 06:15:50 PM PDT 24
Peak memory 199788 kb
Host smart-36c73ffb-a807-4d0c-8681-ea4c64aa816b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168424958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.4168424958
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2508696339
Short name T1104
Test name
Test status
Simulation time 98502725357 ps
CPU time 228.1 seconds
Started Aug 10 06:15:35 PM PDT 24
Finished Aug 10 06:19:23 PM PDT 24
Peak memory 199816 kb
Host smart-0bbb1a20-caed-4061-aa26-de5715a13bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508696339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2508696339
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.3679715777
Short name T424
Test name
Test status
Simulation time 25045679 ps
CPU time 0.56 seconds
Started Aug 10 06:11:00 PM PDT 24
Finished Aug 10 06:11:01 PM PDT 24
Peak memory 195360 kb
Host smart-a717528a-19b4-43dc-8256-c6af24b954e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679715777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3679715777
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3072495248
Short name T892
Test name
Test status
Simulation time 101472579791 ps
CPU time 153.98 seconds
Started Aug 10 06:10:53 PM PDT 24
Finished Aug 10 06:13:27 PM PDT 24
Peak memory 199880 kb
Host smart-92f84078-18dc-436d-a4e1-81ff4ac0956e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072495248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3072495248
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2218509702
Short name T1116
Test name
Test status
Simulation time 101766437254 ps
CPU time 82.09 seconds
Started Aug 10 06:10:53 PM PDT 24
Finished Aug 10 06:12:15 PM PDT 24
Peak memory 199800 kb
Host smart-d4d2e28a-e8af-455f-802a-db426e4c8d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218509702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2218509702
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3304900371
Short name T969
Test name
Test status
Simulation time 120318381235 ps
CPU time 87.41 seconds
Started Aug 10 06:10:52 PM PDT 24
Finished Aug 10 06:12:19 PM PDT 24
Peak memory 199916 kb
Host smart-fee95cfc-36e7-4244-9f92-bcf304a5ab6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304900371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3304900371
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.2027243791
Short name T463
Test name
Test status
Simulation time 12444524880 ps
CPU time 13.38 seconds
Started Aug 10 06:11:01 PM PDT 24
Finished Aug 10 06:11:14 PM PDT 24
Peak memory 199828 kb
Host smart-1f2dfcc0-9611-412e-a336-994364517ac7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027243791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2027243791
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.2044350979
Short name T417
Test name
Test status
Simulation time 70129727901 ps
CPU time 407.04 seconds
Started Aug 10 06:11:03 PM PDT 24
Finished Aug 10 06:17:50 PM PDT 24
Peak memory 199956 kb
Host smart-1273dd38-e2e4-4647-a89e-c5bf5ce5044c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2044350979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2044350979
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.842191151
Short name T937
Test name
Test status
Simulation time 9921285972 ps
CPU time 3.3 seconds
Started Aug 10 06:11:01 PM PDT 24
Finished Aug 10 06:11:04 PM PDT 24
Peak memory 199884 kb
Host smart-c3a2337c-46d2-4b40-a4c3-3a62e09b5d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842191151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.842191151
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.2908014144
Short name T965
Test name
Test status
Simulation time 26183595077 ps
CPU time 42.37 seconds
Started Aug 10 06:11:03 PM PDT 24
Finished Aug 10 06:11:46 PM PDT 24
Peak memory 200088 kb
Host smart-dfc776a3-24b1-4760-9058-f6b891d746ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908014144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2908014144
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.4125254115
Short name T514
Test name
Test status
Simulation time 7476309648 ps
CPU time 428.56 seconds
Started Aug 10 06:11:03 PM PDT 24
Finished Aug 10 06:18:12 PM PDT 24
Peak memory 199880 kb
Host smart-dac5166a-dbbe-4cae-bc62-16eb273b7592
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4125254115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.4125254115
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.3235237978
Short name T824
Test name
Test status
Simulation time 3314835861 ps
CPU time 5.78 seconds
Started Aug 10 06:11:02 PM PDT 24
Finished Aug 10 06:11:08 PM PDT 24
Peak memory 198084 kb
Host smart-3ca81fc6-b180-41f7-9ee0-dafafb93b171
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3235237978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3235237978
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1260970626
Short name T1082
Test name
Test status
Simulation time 2985703747 ps
CPU time 1.87 seconds
Started Aug 10 06:11:01 PM PDT 24
Finished Aug 10 06:11:03 PM PDT 24
Peak memory 196560 kb
Host smart-eed7bb0c-d7fd-4f68-a779-90373eb4cb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260970626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1260970626
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.3362405601
Short name T565
Test name
Test status
Simulation time 452059787 ps
CPU time 2.02 seconds
Started Aug 10 06:10:51 PM PDT 24
Finished Aug 10 06:10:53 PM PDT 24
Peak memory 199816 kb
Host smart-b79e68f8-1095-4914-a090-fb70ee8c41b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362405601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.3362405601
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.4166224761
Short name T1133
Test name
Test status
Simulation time 169136514095 ps
CPU time 123.03 seconds
Started Aug 10 06:11:02 PM PDT 24
Finished Aug 10 06:13:06 PM PDT 24
Peak memory 216380 kb
Host smart-38f0a7c8-99bd-4321-af38-efa03da338ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166224761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.4166224761
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3823981242
Short name T814
Test name
Test status
Simulation time 23531562390 ps
CPU time 294.1 seconds
Started Aug 10 06:11:01 PM PDT 24
Finished Aug 10 06:15:56 PM PDT 24
Peak memory 216196 kb
Host smart-88481fa4-819f-4ad7-8d5c-03e38ff8b713
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823981242 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3823981242
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2267451989
Short name T1145
Test name
Test status
Simulation time 1351615403 ps
CPU time 4.65 seconds
Started Aug 10 06:11:04 PM PDT 24
Finished Aug 10 06:11:09 PM PDT 24
Peak memory 198416 kb
Host smart-2194aa44-4ef7-4c0e-9cb1-dedbaa6e1ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267451989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2267451989
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3813654143
Short name T539
Test name
Test status
Simulation time 52786705301 ps
CPU time 90.3 seconds
Started Aug 10 06:10:52 PM PDT 24
Finished Aug 10 06:12:23 PM PDT 24
Peak memory 199912 kb
Host smart-9c5b9385-2e65-4064-9a9d-2d46ec472a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813654143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3813654143
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.3496283377
Short name T1080
Test name
Test status
Simulation time 89246825205 ps
CPU time 149.75 seconds
Started Aug 10 06:15:35 PM PDT 24
Finished Aug 10 06:18:04 PM PDT 24
Peak memory 199892 kb
Host smart-fa9c282f-fc7e-4b65-992b-1a340698b8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496283377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3496283377
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.881508483
Short name T214
Test name
Test status
Simulation time 253636844255 ps
CPU time 508.66 seconds
Started Aug 10 06:15:35 PM PDT 24
Finished Aug 10 06:24:04 PM PDT 24
Peak memory 199968 kb
Host smart-294c4e32-a250-4832-b2db-c046715d3e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881508483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.881508483
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2108341582
Short name T318
Test name
Test status
Simulation time 41029569653 ps
CPU time 67.51 seconds
Started Aug 10 06:15:35 PM PDT 24
Finished Aug 10 06:16:43 PM PDT 24
Peak memory 199828 kb
Host smart-1f11c458-a580-4081-9fa9-c76613cc8b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108341582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2108341582
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.2128798148
Short name T215
Test name
Test status
Simulation time 35624600245 ps
CPU time 25.04 seconds
Started Aug 10 06:15:35 PM PDT 24
Finished Aug 10 06:16:00 PM PDT 24
Peak memory 199988 kb
Host smart-ab8aded1-5e89-4149-a1ce-146cdef9d2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128798148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2128798148
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3181463036
Short name T240
Test name
Test status
Simulation time 100937994362 ps
CPU time 34.22 seconds
Started Aug 10 06:15:33 PM PDT 24
Finished Aug 10 06:16:07 PM PDT 24
Peak memory 199584 kb
Host smart-9caedc18-dcad-425c-8433-9df9bacc0fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181463036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3181463036
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2219496277
Short name T1128
Test name
Test status
Simulation time 23667548054 ps
CPU time 38.01 seconds
Started Aug 10 06:15:37 PM PDT 24
Finished Aug 10 06:16:16 PM PDT 24
Peak memory 199896 kb
Host smart-54574521-31c2-49f3-b293-d43e0cc74860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219496277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2219496277
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2601098526
Short name T505
Test name
Test status
Simulation time 96807014005 ps
CPU time 85.63 seconds
Started Aug 10 06:15:34 PM PDT 24
Finished Aug 10 06:16:59 PM PDT 24
Peak memory 199900 kb
Host smart-e160aa21-ff10-4315-b04d-a99e5d5a2050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601098526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2601098526
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.1095506285
Short name T198
Test name
Test status
Simulation time 105343253073 ps
CPU time 200.68 seconds
Started Aug 10 06:15:34 PM PDT 24
Finished Aug 10 06:18:55 PM PDT 24
Peak memory 199904 kb
Host smart-b0761ff0-50a8-4f3b-b522-9e0679895bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095506285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1095506285
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.675534488
Short name T381
Test name
Test status
Simulation time 12613863 ps
CPU time 0.52 seconds
Started Aug 10 06:11:09 PM PDT 24
Finished Aug 10 06:11:10 PM PDT 24
Peak memory 194336 kb
Host smart-25e8e59c-ab1a-4732-b393-4d68c7b59575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675534488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.675534488
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1878422942
Short name T585
Test name
Test status
Simulation time 208726101078 ps
CPU time 299.2 seconds
Started Aug 10 06:11:01 PM PDT 24
Finished Aug 10 06:16:00 PM PDT 24
Peak memory 199916 kb
Host smart-4e3b13bd-2514-4c18-adf6-56ead38f6fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878422942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1878422942
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3114528312
Short name T828
Test name
Test status
Simulation time 169370644186 ps
CPU time 66.38 seconds
Started Aug 10 06:11:00 PM PDT 24
Finished Aug 10 06:12:06 PM PDT 24
Peak memory 199908 kb
Host smart-3d14c791-5eb5-497a-a587-ebc3003defc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114528312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3114528312
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.1483287436
Short name T954
Test name
Test status
Simulation time 12880257906 ps
CPU time 2.68 seconds
Started Aug 10 06:11:08 PM PDT 24
Finished Aug 10 06:11:11 PM PDT 24
Peak memory 196616 kb
Host smart-cb663b75-efde-4041-bb56-544b67c442c7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483287436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1483287436
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2012153963
Short name T932
Test name
Test status
Simulation time 36820956542 ps
CPU time 97.06 seconds
Started Aug 10 06:11:09 PM PDT 24
Finished Aug 10 06:12:46 PM PDT 24
Peak memory 199984 kb
Host smart-389e0033-3352-40ed-a5cd-cf861690fc20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2012153963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2012153963
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.99002292
Short name T1093
Test name
Test status
Simulation time 7097301518 ps
CPU time 14.74 seconds
Started Aug 10 06:11:10 PM PDT 24
Finished Aug 10 06:11:25 PM PDT 24
Peak memory 199916 kb
Host smart-8ec9b0aa-8046-475e-9442-714ef699f7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99002292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.99002292
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.2220315512
Short name T621
Test name
Test status
Simulation time 114157709531 ps
CPU time 232.04 seconds
Started Aug 10 06:11:10 PM PDT 24
Finished Aug 10 06:15:02 PM PDT 24
Peak memory 199168 kb
Host smart-91494bbf-3057-413a-88ce-72bcfdf635cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220315512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2220315512
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.1531549735
Short name T1158
Test name
Test status
Simulation time 10513551115 ps
CPU time 218.24 seconds
Started Aug 10 06:11:09 PM PDT 24
Finished Aug 10 06:14:48 PM PDT 24
Peak memory 199896 kb
Host smart-5f4d0254-50f7-4353-b8cc-930942c38185
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1531549735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1531549735
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.3024450101
Short name T798
Test name
Test status
Simulation time 7248724878 ps
CPU time 68.42 seconds
Started Aug 10 06:11:10 PM PDT 24
Finished Aug 10 06:12:18 PM PDT 24
Peak memory 198324 kb
Host smart-dfd4610b-12ab-4076-a706-db8aef1cb027
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3024450101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3024450101
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3996363195
Short name T558
Test name
Test status
Simulation time 43798270421 ps
CPU time 70.54 seconds
Started Aug 10 06:11:11 PM PDT 24
Finished Aug 10 06:12:22 PM PDT 24
Peak memory 199700 kb
Host smart-0f009b6e-bcc6-4b5b-a995-bc07707d2a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996363195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3996363195
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.2144589290
Short name T303
Test name
Test status
Simulation time 3089817341 ps
CPU time 1.55 seconds
Started Aug 10 06:11:11 PM PDT 24
Finished Aug 10 06:11:13 PM PDT 24
Peak memory 195936 kb
Host smart-52360449-85e1-4361-99de-96f0ff62ff2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144589290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2144589290
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.534040542
Short name T859
Test name
Test status
Simulation time 554179947 ps
CPU time 1.6 seconds
Started Aug 10 06:11:01 PM PDT 24
Finished Aug 10 06:11:03 PM PDT 24
Peak memory 199388 kb
Host smart-9515b2fc-472c-4d6d-bc4a-635898044138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534040542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.534040542
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.453184849
Short name T12
Test name
Test status
Simulation time 63510393918 ps
CPU time 719.85 seconds
Started Aug 10 06:11:11 PM PDT 24
Finished Aug 10 06:23:11 PM PDT 24
Peak memory 224936 kb
Host smart-05016253-58cb-49f0-9a4f-06aae28ab41f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453184849 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.453184849
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.281244585
Short name T416
Test name
Test status
Simulation time 644264395 ps
CPU time 2.88 seconds
Started Aug 10 06:11:11 PM PDT 24
Finished Aug 10 06:11:14 PM PDT 24
Peak memory 199552 kb
Host smart-df60530c-5e0e-4f6b-8bb7-d9248b7f62e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281244585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.281244585
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1487014523
Short name T291
Test name
Test status
Simulation time 219180598440 ps
CPU time 54.92 seconds
Started Aug 10 06:11:01 PM PDT 24
Finished Aug 10 06:11:56 PM PDT 24
Peak memory 200020 kb
Host smart-d17f7fb5-7ba0-4e2f-907e-c8b2ba5c5183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487014523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1487014523
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.3164536479
Short name T40
Test name
Test status
Simulation time 26104637075 ps
CPU time 12.44 seconds
Started Aug 10 06:15:37 PM PDT 24
Finished Aug 10 06:15:50 PM PDT 24
Peak memory 199980 kb
Host smart-43b2aa7a-d4ac-4f98-b968-7bdc4372ae87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164536479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3164536479
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.117692294
Short name T935
Test name
Test status
Simulation time 97122365062 ps
CPU time 83.19 seconds
Started Aug 10 06:15:35 PM PDT 24
Finished Aug 10 06:16:58 PM PDT 24
Peak memory 199836 kb
Host smart-b9326ce4-df4d-4fa2-a98d-bca5765aa57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117692294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.117692294
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.190453971
Short name T722
Test name
Test status
Simulation time 40219222923 ps
CPU time 26.52 seconds
Started Aug 10 06:15:35 PM PDT 24
Finished Aug 10 06:16:02 PM PDT 24
Peak memory 199620 kb
Host smart-4065341b-cf61-4a5b-ab4c-2b95f26573dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190453971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.190453971
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.434648163
Short name T544
Test name
Test status
Simulation time 142787892772 ps
CPU time 218.31 seconds
Started Aug 10 06:15:35 PM PDT 24
Finished Aug 10 06:19:13 PM PDT 24
Peak memory 199956 kb
Host smart-2c3bbfc6-da95-4be3-9e17-a70d6f414f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434648163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.434648163
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3941368876
Short name T1105
Test name
Test status
Simulation time 36314529410 ps
CPU time 44.79 seconds
Started Aug 10 06:15:36 PM PDT 24
Finished Aug 10 06:16:21 PM PDT 24
Peak memory 199992 kb
Host smart-8bef9d18-6d19-45be-81c6-14d9b18367b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941368876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3941368876
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2671321411
Short name T1051
Test name
Test status
Simulation time 64560598590 ps
CPU time 25.04 seconds
Started Aug 10 06:15:42 PM PDT 24
Finished Aug 10 06:16:07 PM PDT 24
Peak memory 199904 kb
Host smart-fa830134-f020-490e-96e6-a0d4c4a0cae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671321411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2671321411
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.3180989667
Short name T614
Test name
Test status
Simulation time 105983909456 ps
CPU time 76.75 seconds
Started Aug 10 06:15:43 PM PDT 24
Finished Aug 10 06:17:00 PM PDT 24
Peak memory 199732 kb
Host smart-6fd27100-53e8-4b84-bc90-29de33633aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180989667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3180989667
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.2790935510
Short name T460
Test name
Test status
Simulation time 41230459 ps
CPU time 0.54 seconds
Started Aug 10 06:11:19 PM PDT 24
Finished Aug 10 06:11:20 PM PDT 24
Peak memory 195364 kb
Host smart-7c9b78fb-7e76-462a-9697-f2019372a9a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790935510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2790935510
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.877026321
Short name T500
Test name
Test status
Simulation time 46625092822 ps
CPU time 66.76 seconds
Started Aug 10 06:11:11 PM PDT 24
Finished Aug 10 06:12:18 PM PDT 24
Peak memory 199968 kb
Host smart-3a97519c-6a4b-459a-a7e4-3eb1352820c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877026321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.877026321
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2252570709
Short name T570
Test name
Test status
Simulation time 31155949137 ps
CPU time 48.3 seconds
Started Aug 10 06:11:10 PM PDT 24
Finished Aug 10 06:11:59 PM PDT 24
Peak memory 199928 kb
Host smart-fad30ef8-f759-40af-8584-8753adc42855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252570709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2252570709
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.4102174784
Short name T1016
Test name
Test status
Simulation time 24444553127 ps
CPU time 26.86 seconds
Started Aug 10 06:11:09 PM PDT 24
Finished Aug 10 06:11:36 PM PDT 24
Peak memory 199864 kb
Host smart-726cbe22-032a-478f-bcd2-4e3289170b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102174784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.4102174784
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.3627757654
Short name T620
Test name
Test status
Simulation time 62232276057 ps
CPU time 25.3 seconds
Started Aug 10 06:11:20 PM PDT 24
Finished Aug 10 06:11:45 PM PDT 24
Peak memory 199924 kb
Host smart-f3933b1a-0bae-4968-9386-b5d373935f01
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627757654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3627757654
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.730918564
Short name T1095
Test name
Test status
Simulation time 133492475695 ps
CPU time 1063.39 seconds
Started Aug 10 06:11:20 PM PDT 24
Finished Aug 10 06:29:03 PM PDT 24
Peak memory 199856 kb
Host smart-f0666181-dc06-4a74-a8b2-89610b6bf79d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=730918564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.730918564
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2587257249
Short name T1071
Test name
Test status
Simulation time 3697994441 ps
CPU time 6.78 seconds
Started Aug 10 06:11:19 PM PDT 24
Finished Aug 10 06:11:26 PM PDT 24
Peak memory 199108 kb
Host smart-1f642a66-02c4-4147-94e2-e3296445bb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587257249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2587257249
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.3636077656
Short name T993
Test name
Test status
Simulation time 66055309933 ps
CPU time 113.16 seconds
Started Aug 10 06:11:22 PM PDT 24
Finished Aug 10 06:13:15 PM PDT 24
Peak memory 200052 kb
Host smart-d92f8008-2cd9-4f1d-8740-934af4241942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636077656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3636077656
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.3574286480
Short name T685
Test name
Test status
Simulation time 21102768074 ps
CPU time 993.61 seconds
Started Aug 10 06:11:18 PM PDT 24
Finished Aug 10 06:27:52 PM PDT 24
Peak memory 200004 kb
Host smart-92b2be21-1f83-49cb-8478-c03de1bd5e58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3574286480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3574286480
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.3089716678
Short name T472
Test name
Test status
Simulation time 5477166526 ps
CPU time 12.88 seconds
Started Aug 10 06:11:21 PM PDT 24
Finished Aug 10 06:11:34 PM PDT 24
Peak memory 199140 kb
Host smart-2c5c122b-772b-44c4-8c84-e9f96ffb2403
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3089716678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3089716678
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.4203157608
Short name T262
Test name
Test status
Simulation time 133725601136 ps
CPU time 72.39 seconds
Started Aug 10 06:11:19 PM PDT 24
Finished Aug 10 06:12:32 PM PDT 24
Peak memory 199932 kb
Host smart-6d49c152-8b50-4e65-a11d-6b694f3f612a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203157608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.4203157608
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.826477360
Short name T619
Test name
Test status
Simulation time 3400539689 ps
CPU time 2.07 seconds
Started Aug 10 06:11:20 PM PDT 24
Finished Aug 10 06:11:22 PM PDT 24
Peak memory 196488 kb
Host smart-7b256e26-209d-4e0b-a67e-c68142ca7404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826477360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.826477360
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2743973448
Short name T483
Test name
Test status
Simulation time 298558575 ps
CPU time 1.28 seconds
Started Aug 10 06:11:11 PM PDT 24
Finished Aug 10 06:11:13 PM PDT 24
Peak memory 198316 kb
Host smart-6f9c2ebf-e712-4e3d-83b8-1c844b5d6914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743973448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2743973448
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.3121854552
Short name T1062
Test name
Test status
Simulation time 104897790231 ps
CPU time 209 seconds
Started Aug 10 06:11:22 PM PDT 24
Finished Aug 10 06:14:51 PM PDT 24
Peak memory 216572 kb
Host smart-2682949c-9302-47a6-a7fe-82d7183a5f44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121854552 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3121854552
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1045333124
Short name T669
Test name
Test status
Simulation time 6758981437 ps
CPU time 13.97 seconds
Started Aug 10 06:11:20 PM PDT 24
Finished Aug 10 06:11:34 PM PDT 24
Peak memory 199824 kb
Host smart-8cf7f38b-829a-4faf-be03-c214a5d2961a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045333124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1045333124
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.3106209400
Short name T356
Test name
Test status
Simulation time 60802169720 ps
CPU time 96.07 seconds
Started Aug 10 06:11:10 PM PDT 24
Finished Aug 10 06:12:46 PM PDT 24
Peak memory 199984 kb
Host smart-607e751c-c89a-4a04-a9e8-a10179070f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106209400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3106209400
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.3540653053
Short name T301
Test name
Test status
Simulation time 199980117839 ps
CPU time 319.82 seconds
Started Aug 10 06:15:44 PM PDT 24
Finished Aug 10 06:21:04 PM PDT 24
Peak memory 199928 kb
Host smart-0b6fc3df-60e8-4a49-a13b-4c13ddcb050d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540653053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3540653053
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1699650283
Short name T658
Test name
Test status
Simulation time 140366229032 ps
CPU time 124.77 seconds
Started Aug 10 06:15:41 PM PDT 24
Finished Aug 10 06:17:46 PM PDT 24
Peak memory 199960 kb
Host smart-c2dbb8cd-3044-4580-829b-60e5d9929596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699650283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1699650283
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1480295484
Short name T681
Test name
Test status
Simulation time 30618522471 ps
CPU time 44.86 seconds
Started Aug 10 06:15:43 PM PDT 24
Finished Aug 10 06:16:28 PM PDT 24
Peak memory 199964 kb
Host smart-f6279973-ea95-4872-8e5f-bd577f103c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480295484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1480295484
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3120196222
Short name T891
Test name
Test status
Simulation time 48798222528 ps
CPU time 54.37 seconds
Started Aug 10 06:15:42 PM PDT 24
Finished Aug 10 06:16:36 PM PDT 24
Peak memory 199888 kb
Host smart-61ffd71c-a152-46eb-b26d-76458e4d3ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120196222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3120196222
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.186458684
Short name T716
Test name
Test status
Simulation time 42647786264 ps
CPU time 34.69 seconds
Started Aug 10 06:15:41 PM PDT 24
Finished Aug 10 06:16:16 PM PDT 24
Peak memory 199968 kb
Host smart-b50b83ac-6bc9-47b0-bc65-a52f75043d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186458684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.186458684
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2112556058
Short name T680
Test name
Test status
Simulation time 215513401061 ps
CPU time 107.22 seconds
Started Aug 10 06:15:42 PM PDT 24
Finished Aug 10 06:17:29 PM PDT 24
Peak memory 199860 kb
Host smart-9bfd6a76-35a0-4475-8d1b-213f8a68da52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112556058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2112556058
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.4233370845
Short name T572
Test name
Test status
Simulation time 40623990066 ps
CPU time 16.27 seconds
Started Aug 10 06:15:42 PM PDT 24
Finished Aug 10 06:15:59 PM PDT 24
Peak memory 199936 kb
Host smart-d6483964-d3e6-4d7b-b1d4-db1f5257be9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233370845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.4233370845
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.2479961446
Short name T900
Test name
Test status
Simulation time 88518085069 ps
CPU time 71.47 seconds
Started Aug 10 06:15:44 PM PDT 24
Finished Aug 10 06:16:55 PM PDT 24
Peak memory 199976 kb
Host smart-1631f259-6ca6-467e-acf8-11e08733a1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479961446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2479961446
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.4048350338
Short name T357
Test name
Test status
Simulation time 9347784220 ps
CPU time 13.79 seconds
Started Aug 10 06:15:43 PM PDT 24
Finished Aug 10 06:15:56 PM PDT 24
Peak memory 199984 kb
Host smart-6dadeff0-0859-4408-90d5-a032077facf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048350338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.4048350338
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1587827501
Short name T1073
Test name
Test status
Simulation time 25329759 ps
CPU time 0.53 seconds
Started Aug 10 06:11:29 PM PDT 24
Finished Aug 10 06:11:30 PM PDT 24
Peak memory 194324 kb
Host smart-bf90067d-866c-4935-9d20-ff7c60df02d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587827501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1587827501
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.1116596005
Short name T1175
Test name
Test status
Simulation time 2376575297 ps
CPU time 4.28 seconds
Started Aug 10 06:11:19 PM PDT 24
Finished Aug 10 06:11:24 PM PDT 24
Peak memory 198904 kb
Host smart-72c445e6-6080-4c5b-97df-0c47ae404bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116596005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1116596005
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.743131960
Short name T166
Test name
Test status
Simulation time 112040683427 ps
CPU time 78.37 seconds
Started Aug 10 06:11:18 PM PDT 24
Finished Aug 10 06:12:37 PM PDT 24
Peak memory 199944 kb
Host smart-15893d99-54e9-495b-a042-cf327a0d2d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743131960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.743131960
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2882347510
Short name T411
Test name
Test status
Simulation time 255611153995 ps
CPU time 31.22 seconds
Started Aug 10 06:11:19 PM PDT 24
Finished Aug 10 06:11:51 PM PDT 24
Peak memory 199976 kb
Host smart-f2aaff1a-c735-4cb1-9fb7-d3e86148afc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882347510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2882347510
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.4063999145
Short name T13
Test name
Test status
Simulation time 52744796134 ps
CPU time 97.66 seconds
Started Aug 10 06:11:32 PM PDT 24
Finished Aug 10 06:13:09 PM PDT 24
Peak memory 199956 kb
Host smart-d38210f7-c07f-423e-a402-3d51e86ff773
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063999145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.4063999145
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.600470420
Short name T581
Test name
Test status
Simulation time 82766439234 ps
CPU time 642.26 seconds
Started Aug 10 06:11:27 PM PDT 24
Finished Aug 10 06:22:09 PM PDT 24
Peak memory 199976 kb
Host smart-a54254ca-60d8-498d-931c-e06e904a3691
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=600470420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.600470420
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.1069568021
Short name T1169
Test name
Test status
Simulation time 6284584516 ps
CPU time 8.26 seconds
Started Aug 10 06:11:29 PM PDT 24
Finished Aug 10 06:11:38 PM PDT 24
Peak memory 199048 kb
Host smart-b5ce0c8c-4a39-4938-9d1c-cc6e9d6c0348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069568021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1069568021
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.1079777081
Short name T468
Test name
Test status
Simulation time 132336627973 ps
CPU time 66.69 seconds
Started Aug 10 06:11:30 PM PDT 24
Finished Aug 10 06:12:37 PM PDT 24
Peak memory 199964 kb
Host smart-96192ded-d321-4957-bd04-017e9db38238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079777081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1079777081
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.2177684275
Short name T555
Test name
Test status
Simulation time 9096207482 ps
CPU time 202.89 seconds
Started Aug 10 06:11:29 PM PDT 24
Finished Aug 10 06:14:52 PM PDT 24
Peak memory 199988 kb
Host smart-ac9249b0-16b4-4dae-a8d5-9cca2ea17caf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2177684275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.2177684275
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.372550265
Short name T504
Test name
Test status
Simulation time 7032374595 ps
CPU time 17.86 seconds
Started Aug 10 06:11:19 PM PDT 24
Finished Aug 10 06:11:38 PM PDT 24
Peak memory 199268 kb
Host smart-ad2c23f1-26da-4d7e-9d89-b9e844d77001
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=372550265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.372550265
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.4126491014
Short name T139
Test name
Test status
Simulation time 51606425449 ps
CPU time 42.45 seconds
Started Aug 10 06:11:29 PM PDT 24
Finished Aug 10 06:12:12 PM PDT 24
Peak memory 199904 kb
Host smart-bafd9494-ac9e-48ac-834d-9ac9b0a3e74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126491014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.4126491014
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1068622410
Short name T753
Test name
Test status
Simulation time 4473376342 ps
CPU time 1.57 seconds
Started Aug 10 06:11:29 PM PDT 24
Finished Aug 10 06:11:31 PM PDT 24
Peak memory 196136 kb
Host smart-d87e186a-9d79-4834-b199-6d18101f0d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068622410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1068622410
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2945127484
Short name T1178
Test name
Test status
Simulation time 891121126 ps
CPU time 3.04 seconds
Started Aug 10 06:11:19 PM PDT 24
Finished Aug 10 06:11:23 PM PDT 24
Peak memory 198796 kb
Host smart-da3c202e-7408-4fde-83b8-1586ff4cca5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945127484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2945127484
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.589358509
Short name T269
Test name
Test status
Simulation time 116145049029 ps
CPU time 248.81 seconds
Started Aug 10 06:11:26 PM PDT 24
Finished Aug 10 06:15:35 PM PDT 24
Peak memory 199920 kb
Host smart-5beef971-34a4-4f05-aae8-e038a3baac78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589358509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.589358509
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1016037148
Short name T59
Test name
Test status
Simulation time 159824098307 ps
CPU time 719.45 seconds
Started Aug 10 06:11:27 PM PDT 24
Finished Aug 10 06:23:27 PM PDT 24
Peak memory 224724 kb
Host smart-0d337de0-31c2-48d1-b6e8-a328b7caca5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016037148 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1016037148
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1625829536
Short name T648
Test name
Test status
Simulation time 655899436 ps
CPU time 3.29 seconds
Started Aug 10 06:11:27 PM PDT 24
Finished Aug 10 06:11:31 PM PDT 24
Peak memory 198320 kb
Host smart-bcdba955-b18f-445a-b4a0-61c7b58e0ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625829536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1625829536
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.1497825874
Short name T561
Test name
Test status
Simulation time 25865809231 ps
CPU time 56.21 seconds
Started Aug 10 06:11:20 PM PDT 24
Finished Aug 10 06:12:17 PM PDT 24
Peak memory 199956 kb
Host smart-edb27cf5-ffa6-4c2b-b8d6-0b85d64e6f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497825874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1497825874
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.105771019
Short name T257
Test name
Test status
Simulation time 42380020446 ps
CPU time 17.07 seconds
Started Aug 10 06:15:44 PM PDT 24
Finished Aug 10 06:16:01 PM PDT 24
Peak memory 199916 kb
Host smart-46ff35c6-9b5d-4048-b13f-baf46142ee11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105771019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.105771019
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1861706542
Short name T728
Test name
Test status
Simulation time 35284214064 ps
CPU time 36.52 seconds
Started Aug 10 06:15:43 PM PDT 24
Finished Aug 10 06:16:20 PM PDT 24
Peak memory 199992 kb
Host smart-6a265357-f25d-441f-9fcd-434ca70f2ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861706542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1861706542
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2587116615
Short name T150
Test name
Test status
Simulation time 23260907259 ps
CPU time 35.68 seconds
Started Aug 10 06:15:42 PM PDT 24
Finished Aug 10 06:16:18 PM PDT 24
Peak memory 199924 kb
Host smart-018a8257-8117-440a-ba3c-c6bbf8a4a3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587116615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2587116615
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.306619364
Short name T109
Test name
Test status
Simulation time 109865240112 ps
CPU time 21.05 seconds
Started Aug 10 06:15:42 PM PDT 24
Finished Aug 10 06:16:03 PM PDT 24
Peak memory 199864 kb
Host smart-69cfcd11-6170-4fc2-a3e2-4c35f31dfbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306619364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.306619364
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3461153529
Short name T216
Test name
Test status
Simulation time 22685050786 ps
CPU time 44.39 seconds
Started Aug 10 06:15:42 PM PDT 24
Finished Aug 10 06:16:26 PM PDT 24
Peak memory 199772 kb
Host smart-03be867a-9961-4e73-94c7-d202212e593c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461153529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3461153529
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.285810918
Short name T188
Test name
Test status
Simulation time 38520974621 ps
CPU time 15.85 seconds
Started Aug 10 06:15:44 PM PDT 24
Finished Aug 10 06:16:00 PM PDT 24
Peak memory 199968 kb
Host smart-e874c9ab-6bf8-4263-b4fc-0e0fb03ac78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285810918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.285810918
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3961188177
Short name T224
Test name
Test status
Simulation time 56401576906 ps
CPU time 78.74 seconds
Started Aug 10 06:15:41 PM PDT 24
Finished Aug 10 06:17:00 PM PDT 24
Peak memory 199988 kb
Host smart-a0bf6eb1-265c-4fe8-bddb-a5a64fd156a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961188177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3961188177
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.92785691
Short name T1171
Test name
Test status
Simulation time 83179316166 ps
CPU time 35.6 seconds
Started Aug 10 06:15:50 PM PDT 24
Finished Aug 10 06:16:26 PM PDT 24
Peak memory 199952 kb
Host smart-d9d62007-6d6c-4a6e-b35e-f767d9a2e3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92785691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.92785691
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.3879744485
Short name T423
Test name
Test status
Simulation time 16223031759 ps
CPU time 25.86 seconds
Started Aug 10 06:15:48 PM PDT 24
Finished Aug 10 06:16:14 PM PDT 24
Peak memory 199932 kb
Host smart-6b382969-ea38-42e7-affa-0d6058968d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879744485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3879744485
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3315243826
Short name T400
Test name
Test status
Simulation time 79560584 ps
CPU time 0.54 seconds
Started Aug 10 06:08:56 PM PDT 24
Finished Aug 10 06:08:57 PM PDT 24
Peak memory 195312 kb
Host smart-a780bcd5-3013-4cbb-a320-ee08914178bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315243826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3315243826
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.3469639633
Short name T856
Test name
Test status
Simulation time 71158736573 ps
CPU time 34.94 seconds
Started Aug 10 06:08:47 PM PDT 24
Finished Aug 10 06:09:22 PM PDT 24
Peak memory 199916 kb
Host smart-f1883b96-c7a0-4dbd-8939-79d44ee85fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469639633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3469639633
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.804836700
Short name T729
Test name
Test status
Simulation time 154508820956 ps
CPU time 55.69 seconds
Started Aug 10 06:08:47 PM PDT 24
Finished Aug 10 06:09:43 PM PDT 24
Peak memory 199880 kb
Host smart-e4a0f65c-a329-41e7-b1e3-2ee9e13e8fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804836700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.804836700
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.351410023
Short name T358
Test name
Test status
Simulation time 135014808386 ps
CPU time 185.15 seconds
Started Aug 10 06:08:47 PM PDT 24
Finished Aug 10 06:11:52 PM PDT 24
Peak memory 199976 kb
Host smart-28be0495-d331-42b3-8536-d44d5e2c1caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351410023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.351410023
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.1231720769
Short name T607
Test name
Test status
Simulation time 22100618873 ps
CPU time 6.2 seconds
Started Aug 10 06:08:47 PM PDT 24
Finished Aug 10 06:08:53 PM PDT 24
Peak memory 199884 kb
Host smart-22ca3484-3560-473d-8c6e-1fbc98c5da59
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231720769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1231720769
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.4070711700
Short name T260
Test name
Test status
Simulation time 130583938810 ps
CPU time 291.15 seconds
Started Aug 10 06:08:47 PM PDT 24
Finished Aug 10 06:13:38 PM PDT 24
Peak memory 199964 kb
Host smart-9bf59b97-c355-4dae-bf1e-767a8f01add6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4070711700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.4070711700
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.4127338188
Short name T414
Test name
Test status
Simulation time 5953289208 ps
CPU time 11.87 seconds
Started Aug 10 06:08:46 PM PDT 24
Finished Aug 10 06:08:57 PM PDT 24
Peak memory 198944 kb
Host smart-6fabfca4-5b14-4997-a5ba-471570203132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127338188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.4127338188
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.2624321790
Short name T551
Test name
Test status
Simulation time 47696103246 ps
CPU time 91.75 seconds
Started Aug 10 06:08:47 PM PDT 24
Finished Aug 10 06:10:19 PM PDT 24
Peak memory 200012 kb
Host smart-af93b696-bcf7-45c5-a017-d3b92f3f0bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624321790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2624321790
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3491931913
Short name T1032
Test name
Test status
Simulation time 15534690811 ps
CPU time 93.59 seconds
Started Aug 10 06:08:47 PM PDT 24
Finished Aug 10 06:10:20 PM PDT 24
Peak memory 199952 kb
Host smart-66e1f570-95e5-466e-b140-6cd2df097307
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3491931913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3491931913
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.1955565911
Short name T367
Test name
Test status
Simulation time 5242446960 ps
CPU time 47.01 seconds
Started Aug 10 06:08:49 PM PDT 24
Finished Aug 10 06:09:36 PM PDT 24
Peak memory 197872 kb
Host smart-3cf70359-6970-4db8-8ca8-351b515f3ade
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1955565911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1955565911
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3962558559
Short name T730
Test name
Test status
Simulation time 66873196406 ps
CPU time 90.56 seconds
Started Aug 10 06:08:50 PM PDT 24
Finished Aug 10 06:10:20 PM PDT 24
Peak memory 199948 kb
Host smart-91b3f7a2-d5a9-469b-a238-1eb0168ac48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962558559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3962558559
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2337409141
Short name T822
Test name
Test status
Simulation time 5938368128 ps
CPU time 1.03 seconds
Started Aug 10 06:08:50 PM PDT 24
Finished Aug 10 06:08:51 PM PDT 24
Peak memory 196092 kb
Host smart-c2e4ad5a-f4fd-4b23-b929-68b30dd577de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337409141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2337409141
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.344818695
Short name T93
Test name
Test status
Simulation time 939246092 ps
CPU time 0.84 seconds
Started Aug 10 06:08:55 PM PDT 24
Finished Aug 10 06:08:56 PM PDT 24
Peak memory 218488 kb
Host smart-044200d7-2f4b-462f-a436-ffecbc1dfa2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344818695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.344818695
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.1293728704
Short name T487
Test name
Test status
Simulation time 6245631857 ps
CPU time 11.81 seconds
Started Aug 10 06:08:47 PM PDT 24
Finished Aug 10 06:08:59 PM PDT 24
Peak memory 199780 kb
Host smart-edef9afc-178e-4e78-8ab9-d877f5487b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293728704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1293728704
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.2059274005
Short name T916
Test name
Test status
Simulation time 14640251522 ps
CPU time 23.8 seconds
Started Aug 10 06:08:55 PM PDT 24
Finished Aug 10 06:09:19 PM PDT 24
Peak memory 199960 kb
Host smart-d31c2b8d-00fd-4512-8647-974514a16231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059274005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2059274005
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3667625619
Short name T55
Test name
Test status
Simulation time 48719834924 ps
CPU time 387.48 seconds
Started Aug 10 06:08:55 PM PDT 24
Finished Aug 10 06:15:23 PM PDT 24
Peak memory 216576 kb
Host smart-b7871f6c-0709-41dc-9007-a0991e30fe79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667625619 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3667625619
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.2749398
Short name T315
Test name
Test status
Simulation time 1169519336 ps
CPU time 2.08 seconds
Started Aug 10 06:08:46 PM PDT 24
Finished Aug 10 06:08:48 PM PDT 24
Peak memory 199860 kb
Host smart-38576f55-aaf9-4421-8ea3-5e299f539336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2749398
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3340545480
Short name T479
Test name
Test status
Simulation time 47879206467 ps
CPU time 77.08 seconds
Started Aug 10 06:08:48 PM PDT 24
Finished Aug 10 06:10:05 PM PDT 24
Peak memory 199960 kb
Host smart-6d2b414a-a3ec-457c-9866-debde00b562b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340545480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3340545480
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.595782762
Short name T849
Test name
Test status
Simulation time 25984011 ps
CPU time 0.55 seconds
Started Aug 10 06:11:28 PM PDT 24
Finished Aug 10 06:11:28 PM PDT 24
Peak memory 195300 kb
Host smart-0be7a385-c800-4e58-bfae-58142bae6035
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595782762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.595782762
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1225065357
Short name T651
Test name
Test status
Simulation time 17210172070 ps
CPU time 18.6 seconds
Started Aug 10 06:11:30 PM PDT 24
Finished Aug 10 06:11:49 PM PDT 24
Peak memory 199940 kb
Host smart-151281c0-35b3-4bd7-ab98-ab452d473117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225065357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1225065357
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.4249391889
Short name T690
Test name
Test status
Simulation time 107915817151 ps
CPU time 249.62 seconds
Started Aug 10 06:11:27 PM PDT 24
Finished Aug 10 06:15:36 PM PDT 24
Peak memory 199764 kb
Host smart-400156e4-073c-48aa-951b-3fb15e594940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249391889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.4249391889
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1153489064
Short name T156
Test name
Test status
Simulation time 152700012351 ps
CPU time 53.3 seconds
Started Aug 10 06:11:28 PM PDT 24
Finished Aug 10 06:12:21 PM PDT 24
Peak memory 199968 kb
Host smart-c6ba3d33-303d-4318-b3f7-5949b9ab0dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153489064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1153489064
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.3842261737
Short name T1164
Test name
Test status
Simulation time 27192312452 ps
CPU time 22.83 seconds
Started Aug 10 06:11:28 PM PDT 24
Finished Aug 10 06:11:51 PM PDT 24
Peak memory 198356 kb
Host smart-2664bf55-4ae0-4dfc-bfcb-4879cdd8b051
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842261737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3842261737
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1433421275
Short name T613
Test name
Test status
Simulation time 117112762221 ps
CPU time 142.04 seconds
Started Aug 10 06:11:27 PM PDT 24
Finished Aug 10 06:13:49 PM PDT 24
Peak memory 199836 kb
Host smart-08fe871d-f845-45cb-ac2d-90a208c2a982
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1433421275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1433421275
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.914941963
Short name T922
Test name
Test status
Simulation time 7761372824 ps
CPU time 15.81 seconds
Started Aug 10 06:11:29 PM PDT 24
Finished Aug 10 06:11:45 PM PDT 24
Peak memory 199904 kb
Host smart-6c50fb3a-fd26-46f5-b73f-27c798473c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914941963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.914941963
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3890480115
Short name T255
Test name
Test status
Simulation time 72502680088 ps
CPU time 58.1 seconds
Started Aug 10 06:11:27 PM PDT 24
Finished Aug 10 06:12:26 PM PDT 24
Peak memory 199152 kb
Host smart-6dd7d2e6-f922-4870-996d-49a4943563b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890480115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3890480115
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.3388161707
Short name T888
Test name
Test status
Simulation time 5977550207 ps
CPU time 346.95 seconds
Started Aug 10 06:11:29 PM PDT 24
Finished Aug 10 06:17:16 PM PDT 24
Peak memory 199932 kb
Host smart-e540acda-78cf-4c05-9849-a0635126cab5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3388161707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3388161707
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.3971120835
Short name T115
Test name
Test status
Simulation time 2974091022 ps
CPU time 5.73 seconds
Started Aug 10 06:11:28 PM PDT 24
Finished Aug 10 06:11:34 PM PDT 24
Peak memory 198588 kb
Host smart-ef489f78-f898-4717-a909-e0dd5b80c682
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3971120835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3971120835
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1014280797
Short name T1072
Test name
Test status
Simulation time 21729804667 ps
CPU time 30.71 seconds
Started Aug 10 06:11:29 PM PDT 24
Finished Aug 10 06:12:00 PM PDT 24
Peak memory 199888 kb
Host smart-8f607e31-2434-4c39-a980-ce6ad3e34709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014280797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1014280797
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.4245645788
Short name T616
Test name
Test status
Simulation time 1925298219 ps
CPU time 1.08 seconds
Started Aug 10 06:11:29 PM PDT 24
Finished Aug 10 06:11:30 PM PDT 24
Peak memory 195488 kb
Host smart-ddb9137a-d9fc-4771-8e24-3b598692ece0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245645788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.4245645788
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3821101873
Short name T719
Test name
Test status
Simulation time 464250093 ps
CPU time 1.61 seconds
Started Aug 10 06:11:27 PM PDT 24
Finished Aug 10 06:11:29 PM PDT 24
Peak memory 198504 kb
Host smart-4d8e6301-e7a5-4081-a753-de44aaa40406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821101873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3821101873
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.347995370
Short name T107
Test name
Test status
Simulation time 60978581303 ps
CPU time 629.42 seconds
Started Aug 10 06:11:29 PM PDT 24
Finished Aug 10 06:21:59 PM PDT 24
Peak memory 216432 kb
Host smart-5b528161-4353-49db-8bc0-c007788d822a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347995370 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.347995370
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.1609255788
Short name T97
Test name
Test status
Simulation time 1610419894 ps
CPU time 1.48 seconds
Started Aug 10 06:11:29 PM PDT 24
Finished Aug 10 06:11:31 PM PDT 24
Peak memory 197852 kb
Host smart-92039c9a-4570-4767-a997-f826be5dea48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609255788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1609255788
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.1299674958
Short name T329
Test name
Test status
Simulation time 52863615644 ps
CPU time 12.63 seconds
Started Aug 10 06:11:30 PM PDT 24
Finished Aug 10 06:11:42 PM PDT 24
Peak memory 199892 kb
Host smart-dc8ca700-b3b6-4dd7-a911-48bf461c759b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299674958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1299674958
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.2683376342
Short name T94
Test name
Test status
Simulation time 104223238252 ps
CPU time 41.34 seconds
Started Aug 10 06:15:49 PM PDT 24
Finished Aug 10 06:16:30 PM PDT 24
Peak memory 199956 kb
Host smart-539e49aa-605b-4dca-964e-dc2ee74db6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683376342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2683376342
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.94966228
Short name T946
Test name
Test status
Simulation time 157054534763 ps
CPU time 174.76 seconds
Started Aug 10 06:15:49 PM PDT 24
Finished Aug 10 06:18:44 PM PDT 24
Peak memory 199768 kb
Host smart-6327717e-0518-415a-ad60-ef3ba2471d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94966228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.94966228
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.958597299
Short name T963
Test name
Test status
Simulation time 64281003368 ps
CPU time 50.84 seconds
Started Aug 10 06:15:50 PM PDT 24
Finished Aug 10 06:16:41 PM PDT 24
Peak memory 199948 kb
Host smart-2d460d28-fa6e-4fc2-8582-c565f98afe3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958597299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.958597299
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2502381840
Short name T1157
Test name
Test status
Simulation time 74899742448 ps
CPU time 31.74 seconds
Started Aug 10 06:15:50 PM PDT 24
Finished Aug 10 06:16:22 PM PDT 24
Peak memory 199904 kb
Host smart-17f722c9-2479-439b-885c-b2ed3d51dbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502381840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2502381840
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.448217422
Short name T779
Test name
Test status
Simulation time 25270307085 ps
CPU time 41.49 seconds
Started Aug 10 06:15:47 PM PDT 24
Finished Aug 10 06:16:29 PM PDT 24
Peak memory 199776 kb
Host smart-0c215039-f197-4b75-a90c-719ad62ee31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448217422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.448217422
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3597182738
Short name T233
Test name
Test status
Simulation time 25456703202 ps
CPU time 37.13 seconds
Started Aug 10 06:15:48 PM PDT 24
Finished Aug 10 06:16:25 PM PDT 24
Peak memory 199900 kb
Host smart-d7fb779f-7dca-4efd-b6ea-c70b766b19a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597182738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3597182738
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.703152455
Short name T98
Test name
Test status
Simulation time 33201841953 ps
CPU time 16.64 seconds
Started Aug 10 06:15:49 PM PDT 24
Finished Aug 10 06:16:06 PM PDT 24
Peak memory 198612 kb
Host smart-c1248cf6-3cdb-4e60-bee7-4dd2d506c7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703152455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.703152455
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2606446572
Short name T751
Test name
Test status
Simulation time 26025099116 ps
CPU time 16.24 seconds
Started Aug 10 06:15:49 PM PDT 24
Finished Aug 10 06:16:05 PM PDT 24
Peak memory 200044 kb
Host smart-a330d2ec-e6bc-4dc1-ae21-0b8df42f2737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606446572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2606446572
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.898242240
Short name T154
Test name
Test status
Simulation time 186909406721 ps
CPU time 21.28 seconds
Started Aug 10 06:15:49 PM PDT 24
Finished Aug 10 06:16:11 PM PDT 24
Peak memory 200076 kb
Host smart-cdd7a4d8-0a64-48a4-9f03-94becb022735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898242240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.898242240
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.3146995818
Short name T355
Test name
Test status
Simulation time 22303262908 ps
CPU time 43.67 seconds
Started Aug 10 06:15:48 PM PDT 24
Finished Aug 10 06:16:32 PM PDT 24
Peak memory 199968 kb
Host smart-06d6c5a0-1b7a-4bc4-bd1d-6f61dcf4a2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146995818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3146995818
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1567680093
Short name T776
Test name
Test status
Simulation time 11634971 ps
CPU time 0.54 seconds
Started Aug 10 06:11:36 PM PDT 24
Finished Aug 10 06:11:37 PM PDT 24
Peak memory 195332 kb
Host smart-39e2de3b-caa0-44d1-9190-ea2830a891e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567680093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1567680093
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.368591611
Short name T519
Test name
Test status
Simulation time 56705805598 ps
CPU time 22.44 seconds
Started Aug 10 06:11:37 PM PDT 24
Finished Aug 10 06:11:59 PM PDT 24
Peak memory 199896 kb
Host smart-03caaabe-368a-4f39-b14d-37921d20ccf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368591611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.368591611
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.646502130
Short name T527
Test name
Test status
Simulation time 15157244368 ps
CPU time 26.38 seconds
Started Aug 10 06:11:38 PM PDT 24
Finished Aug 10 06:12:04 PM PDT 24
Peak memory 199976 kb
Host smart-2d6aa61d-4e03-4f32-880a-e76185b4d488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646502130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.646502130
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.1853003932
Short name T850
Test name
Test status
Simulation time 5318611819 ps
CPU time 3.09 seconds
Started Aug 10 06:11:36 PM PDT 24
Finished Aug 10 06:11:39 PM PDT 24
Peak memory 199740 kb
Host smart-016d297b-1445-4ed6-b48e-6274d3d0ab58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853003932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1853003932
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.2103912039
Short name T1028
Test name
Test status
Simulation time 19809487599 ps
CPU time 38.5 seconds
Started Aug 10 06:11:37 PM PDT 24
Finished Aug 10 06:12:16 PM PDT 24
Peak memory 199940 kb
Host smart-bfb49b24-d100-48f6-beff-f4279d6e83c7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103912039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2103912039
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3393125076
Short name T579
Test name
Test status
Simulation time 66409567028 ps
CPU time 443.31 seconds
Started Aug 10 06:11:36 PM PDT 24
Finished Aug 10 06:19:00 PM PDT 24
Peak memory 199984 kb
Host smart-627f87f8-ba47-4dcd-a328-155613f16ac0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3393125076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3393125076
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.3549364933
Short name T392
Test name
Test status
Simulation time 926671740 ps
CPU time 1.89 seconds
Started Aug 10 06:11:38 PM PDT 24
Finished Aug 10 06:11:40 PM PDT 24
Peak memory 195640 kb
Host smart-3d5fd8a9-24bb-4be4-ac81-e203d8f46ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549364933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3549364933
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_perf.4179680035
Short name T446
Test name
Test status
Simulation time 17259264047 ps
CPU time 88.28 seconds
Started Aug 10 06:11:37 PM PDT 24
Finished Aug 10 06:13:05 PM PDT 24
Peak memory 199804 kb
Host smart-c5e52350-df26-4366-81da-4747ce4dd592
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4179680035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.4179680035
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.1186939456
Short name T643
Test name
Test status
Simulation time 5835304050 ps
CPU time 23.64 seconds
Started Aug 10 06:11:37 PM PDT 24
Finished Aug 10 06:12:01 PM PDT 24
Peak memory 197804 kb
Host smart-ff931499-c77e-4fdc-b27e-f4033934dae3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1186939456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1186939456
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2418694974
Short name T1067
Test name
Test status
Simulation time 91944015733 ps
CPU time 124.54 seconds
Started Aug 10 06:11:40 PM PDT 24
Finished Aug 10 06:13:44 PM PDT 24
Peak memory 199928 kb
Host smart-c68dd96b-94ea-4e1c-814f-5df3e2b3cd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418694974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2418694974
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.41161139
Short name T481
Test name
Test status
Simulation time 2032375574 ps
CPU time 3.55 seconds
Started Aug 10 06:11:36 PM PDT 24
Finished Aug 10 06:11:40 PM PDT 24
Peak memory 195476 kb
Host smart-306830ce-57cd-43f8-a7b4-8e3cb0bb25be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41161139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.41161139
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.90467591
Short name T305
Test name
Test status
Simulation time 1035803835 ps
CPU time 1.31 seconds
Started Aug 10 06:11:32 PM PDT 24
Finished Aug 10 06:11:33 PM PDT 24
Peak memory 198772 kb
Host smart-b587449b-6ec1-4396-ab49-ad85c8f03c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90467591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.90467591
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.3809551420
Short name T964
Test name
Test status
Simulation time 275641633659 ps
CPU time 197.11 seconds
Started Aug 10 06:11:38 PM PDT 24
Finished Aug 10 06:14:55 PM PDT 24
Peak memory 200180 kb
Host smart-bcde6905-04aa-4238-8560-458fef0451c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809551420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.3809551420
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2197608885
Short name T1166
Test name
Test status
Simulation time 6231493258 ps
CPU time 10.38 seconds
Started Aug 10 06:11:36 PM PDT 24
Finished Aug 10 06:11:47 PM PDT 24
Peak memory 199324 kb
Host smart-28e110a7-b354-4349-ad26-14ad4b92f0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197608885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2197608885
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1040118169
Short name T571
Test name
Test status
Simulation time 44354244338 ps
CPU time 64.29 seconds
Started Aug 10 06:11:27 PM PDT 24
Finished Aug 10 06:12:32 PM PDT 24
Peak memory 200000 kb
Host smart-e0deb1ce-31a8-4d0a-b3a1-7307f10bf6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040118169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1040118169
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2606492703
Short name T324
Test name
Test status
Simulation time 38233572651 ps
CPU time 39.13 seconds
Started Aug 10 06:15:49 PM PDT 24
Finished Aug 10 06:16:28 PM PDT 24
Peak memory 199876 kb
Host smart-3b2f235c-337d-4673-b073-430b1f161400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606492703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2606492703
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2707556895
Short name T254
Test name
Test status
Simulation time 31484626934 ps
CPU time 13.73 seconds
Started Aug 10 06:15:49 PM PDT 24
Finished Aug 10 06:16:03 PM PDT 24
Peak memory 199952 kb
Host smart-033a744e-79f2-45de-8195-25b596bfd489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707556895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2707556895
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.4012163567
Short name T1106
Test name
Test status
Simulation time 67482265041 ps
CPU time 30.49 seconds
Started Aug 10 06:15:49 PM PDT 24
Finished Aug 10 06:16:20 PM PDT 24
Peak memory 199936 kb
Host smart-d5d8f972-1cc9-45da-be02-adf9b4a69cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012163567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.4012163567
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2477430855
Short name T520
Test name
Test status
Simulation time 113615806808 ps
CPU time 205.73 seconds
Started Aug 10 06:15:49 PM PDT 24
Finished Aug 10 06:19:14 PM PDT 24
Peak memory 199964 kb
Host smart-40587703-2b53-41c2-bf16-0d390245b177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477430855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2477430855
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1277702274
Short name T848
Test name
Test status
Simulation time 87034785122 ps
CPU time 52.93 seconds
Started Aug 10 06:15:56 PM PDT 24
Finished Aug 10 06:16:49 PM PDT 24
Peak memory 199980 kb
Host smart-957a796d-55a8-42dd-be8e-42b4f43fd176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277702274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1277702274
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.4255956081
Short name T962
Test name
Test status
Simulation time 91116430018 ps
CPU time 54.2 seconds
Started Aug 10 06:15:56 PM PDT 24
Finished Aug 10 06:16:50 PM PDT 24
Peak memory 200144 kb
Host smart-37b43ff9-dae4-4ff7-9786-30b87f586d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255956081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.4255956081
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.809092467
Short name T147
Test name
Test status
Simulation time 37848892323 ps
CPU time 31.91 seconds
Started Aug 10 06:15:58 PM PDT 24
Finished Aug 10 06:16:30 PM PDT 24
Peak memory 199864 kb
Host smart-19622f92-6a24-4046-8660-588d5eafe0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809092467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.809092467
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1031230476
Short name T181
Test name
Test status
Simulation time 53708740182 ps
CPU time 287.37 seconds
Started Aug 10 06:15:57 PM PDT 24
Finished Aug 10 06:20:45 PM PDT 24
Peak memory 199964 kb
Host smart-cd799787-cbbc-474a-9eac-952ca04b5316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031230476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1031230476
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.1996530847
Short name T573
Test name
Test status
Simulation time 23170248 ps
CPU time 0.56 seconds
Started Aug 10 06:11:46 PM PDT 24
Finished Aug 10 06:11:47 PM PDT 24
Peak memory 195292 kb
Host smart-5a274097-8338-4b24-b3e6-19affbe3f5ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996530847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1996530847
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3044346626
Short name T615
Test name
Test status
Simulation time 199082410689 ps
CPU time 315.59 seconds
Started Aug 10 06:11:37 PM PDT 24
Finished Aug 10 06:16:53 PM PDT 24
Peak memory 199884 kb
Host smart-921205a8-3907-4935-88e8-5dfc57a150c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044346626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3044346626
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.1234774679
Short name T273
Test name
Test status
Simulation time 119775058976 ps
CPU time 129.05 seconds
Started Aug 10 06:11:35 PM PDT 24
Finished Aug 10 06:13:44 PM PDT 24
Peak memory 199984 kb
Host smart-8375f30a-e0a2-416e-9a53-c86cd91d92a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234774679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.1234774679
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.4111982525
Short name T419
Test name
Test status
Simulation time 18813806086 ps
CPU time 12.81 seconds
Started Aug 10 06:11:40 PM PDT 24
Finished Aug 10 06:11:53 PM PDT 24
Peak memory 198848 kb
Host smart-c05c8768-2970-410b-a42f-055e75f4ce24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111982525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.4111982525
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.2125582058
Short name T476
Test name
Test status
Simulation time 97122815029 ps
CPU time 169.65 seconds
Started Aug 10 06:11:47 PM PDT 24
Finished Aug 10 06:14:36 PM PDT 24
Peak memory 199772 kb
Host smart-bcabcc05-7d13-45f9-b5f1-cb1108790a13
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125582058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2125582058
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.356721674
Short name T656
Test name
Test status
Simulation time 136568833061 ps
CPU time 301.84 seconds
Started Aug 10 06:11:47 PM PDT 24
Finished Aug 10 06:16:49 PM PDT 24
Peak memory 199900 kb
Host smart-09d05203-d76f-4fa5-afbe-2166fe1d0d77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=356721674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.356721674
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1583740989
Short name T835
Test name
Test status
Simulation time 2843054236 ps
CPU time 1.84 seconds
Started Aug 10 06:11:47 PM PDT 24
Finished Aug 10 06:11:49 PM PDT 24
Peak memory 199404 kb
Host smart-1192f3af-0fed-4f07-b0b6-ff5867ed8ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583740989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1583740989
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.453135120
Short name T36
Test name
Test status
Simulation time 102816381837 ps
CPU time 22.82 seconds
Started Aug 10 06:11:46 PM PDT 24
Finished Aug 10 06:12:09 PM PDT 24
Peak memory 198888 kb
Host smart-e5484676-76d7-4afa-935e-61ee5704e146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453135120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.453135120
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.1797620374
Short name T1087
Test name
Test status
Simulation time 6899428766 ps
CPU time 198.71 seconds
Started Aug 10 06:11:48 PM PDT 24
Finished Aug 10 06:15:07 PM PDT 24
Peak memory 199920 kb
Host smart-b3232321-3dca-42ad-b028-beb5dd857c1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1797620374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1797620374
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.2525601011
Short name T1152
Test name
Test status
Simulation time 4965800308 ps
CPU time 24.56 seconds
Started Aug 10 06:11:36 PM PDT 24
Finished Aug 10 06:12:00 PM PDT 24
Peak memory 198288 kb
Host smart-de4d8b34-77f9-499c-82ed-a2d7ae4d930d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2525601011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2525601011
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.4079145251
Short name T878
Test name
Test status
Simulation time 71421986317 ps
CPU time 86.02 seconds
Started Aug 10 06:11:50 PM PDT 24
Finished Aug 10 06:13:16 PM PDT 24
Peak memory 199948 kb
Host smart-e03c494e-9ad6-44ac-9e15-2709869a9dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079145251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.4079145251
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2534223760
Short name T840
Test name
Test status
Simulation time 1384676663 ps
CPU time 1.25 seconds
Started Aug 10 06:11:50 PM PDT 24
Finished Aug 10 06:11:51 PM PDT 24
Peak memory 195620 kb
Host smart-30f4323c-f1f1-4f3d-88ba-bc33eb9e0227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534223760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2534223760
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.776652763
Short name T696
Test name
Test status
Simulation time 89423154 ps
CPU time 0.85 seconds
Started Aug 10 06:11:39 PM PDT 24
Finished Aug 10 06:11:40 PM PDT 24
Peak memory 197760 kb
Host smart-25c1fc9f-37a7-47a9-9243-7f25fb157288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776652763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.776652763
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.706378116
Short name T368
Test name
Test status
Simulation time 56335470335 ps
CPU time 608.13 seconds
Started Aug 10 06:11:46 PM PDT 24
Finished Aug 10 06:21:55 PM PDT 24
Peak memory 200016 kb
Host smart-909d9983-a4a5-4da1-9107-8c42f112a0f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706378116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.706378116
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.3495089242
Short name T961
Test name
Test status
Simulation time 307715910 ps
CPU time 1.78 seconds
Started Aug 10 06:11:45 PM PDT 24
Finished Aug 10 06:11:47 PM PDT 24
Peak memory 199564 kb
Host smart-66573721-07d8-4227-8aaa-1029a533ef5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495089242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3495089242
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.277832285
Short name T1161
Test name
Test status
Simulation time 72854221994 ps
CPU time 53.54 seconds
Started Aug 10 06:11:37 PM PDT 24
Finished Aug 10 06:12:31 PM PDT 24
Peak memory 199936 kb
Host smart-7147ceeb-268c-4d73-89cf-01daf1565e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277832285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.277832285
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.2250571870
Short name T152
Test name
Test status
Simulation time 164244755417 ps
CPU time 55.84 seconds
Started Aug 10 06:15:58 PM PDT 24
Finished Aug 10 06:16:54 PM PDT 24
Peak memory 199936 kb
Host smart-ec7286f7-6481-429e-b108-a64cf8093648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250571870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.2250571870
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3411309034
Short name T659
Test name
Test status
Simulation time 23220849281 ps
CPU time 31.61 seconds
Started Aug 10 06:15:57 PM PDT 24
Finished Aug 10 06:16:28 PM PDT 24
Peak memory 199936 kb
Host smart-8cfecb55-b4be-4ec8-9962-a15c5a081374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411309034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3411309034
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.284356414
Short name T543
Test name
Test status
Simulation time 14415211754 ps
CPU time 23.33 seconds
Started Aug 10 06:15:55 PM PDT 24
Finished Aug 10 06:16:19 PM PDT 24
Peak memory 199844 kb
Host smart-4c62c8a8-a8ef-4437-836d-adfa3258fcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284356414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.284356414
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.786287932
Short name T642
Test name
Test status
Simulation time 91052404092 ps
CPU time 67.88 seconds
Started Aug 10 06:15:57 PM PDT 24
Finished Aug 10 06:17:05 PM PDT 24
Peak memory 199928 kb
Host smart-450882c8-37a1-45ef-b4d1-b796dd13b88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786287932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.786287932
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.332731471
Short name T1136
Test name
Test status
Simulation time 4731595749 ps
CPU time 7.71 seconds
Started Aug 10 06:15:56 PM PDT 24
Finished Aug 10 06:16:04 PM PDT 24
Peak memory 199924 kb
Host smart-5b464a35-78e1-4951-9537-24512f20633c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332731471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.332731471
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.158846354
Short name T197
Test name
Test status
Simulation time 78620215037 ps
CPU time 104.67 seconds
Started Aug 10 06:15:56 PM PDT 24
Finished Aug 10 06:17:40 PM PDT 24
Peak memory 199932 kb
Host smart-d18c7fcd-60b6-4513-9c64-51fe1b3f318e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158846354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.158846354
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2172289439
Short name T264
Test name
Test status
Simulation time 45083113451 ps
CPU time 22.85 seconds
Started Aug 10 06:15:56 PM PDT 24
Finished Aug 10 06:16:19 PM PDT 24
Peak memory 199844 kb
Host smart-c050cb30-f6c5-4795-bdb9-b0d6c26699c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172289439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2172289439
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.227077855
Short name T5
Test name
Test status
Simulation time 19228632257 ps
CPU time 54.15 seconds
Started Aug 10 06:15:56 PM PDT 24
Finished Aug 10 06:16:51 PM PDT 24
Peak memory 199868 kb
Host smart-b317c9a5-b43b-47d3-8bb4-19771719c49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227077855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.227077855
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3766525244
Short name T758
Test name
Test status
Simulation time 32802633540 ps
CPU time 50.72 seconds
Started Aug 10 06:15:55 PM PDT 24
Finished Aug 10 06:16:46 PM PDT 24
Peak memory 199992 kb
Host smart-393fdef5-8332-4139-8c15-f7bfb806b3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766525244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3766525244
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3753262399
Short name T612
Test name
Test status
Simulation time 112912992238 ps
CPU time 20.93 seconds
Started Aug 10 06:15:55 PM PDT 24
Finished Aug 10 06:16:16 PM PDT 24
Peak memory 199956 kb
Host smart-10c3a393-6b63-4265-8e95-4211bd788f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753262399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3753262399
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3040685246
Short name T562
Test name
Test status
Simulation time 44732470 ps
CPU time 0.56 seconds
Started Aug 10 06:11:54 PM PDT 24
Finished Aug 10 06:11:55 PM PDT 24
Peak memory 195008 kb
Host smart-15ab3755-93ea-48e4-a8c1-23f6d8b1bba5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040685246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3040685246
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2746394525
Short name T1077
Test name
Test status
Simulation time 22797872312 ps
CPU time 33.5 seconds
Started Aug 10 06:11:50 PM PDT 24
Finished Aug 10 06:12:23 PM PDT 24
Peak memory 199968 kb
Host smart-ad3b2c7f-0a9a-44be-a834-1e11f64a0e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746394525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2746394525
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3743899258
Short name T157
Test name
Test status
Simulation time 38964294692 ps
CPU time 64.95 seconds
Started Aug 10 06:11:48 PM PDT 24
Finished Aug 10 06:12:53 PM PDT 24
Peak memory 199908 kb
Host smart-7d641682-dfde-4767-8d77-5468edb977dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743899258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3743899258
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.582338506
Short name T1064
Test name
Test status
Simulation time 18740738693 ps
CPU time 13.86 seconds
Started Aug 10 06:11:46 PM PDT 24
Finished Aug 10 06:12:00 PM PDT 24
Peak memory 199972 kb
Host smart-8cbc3f30-b625-4a0c-8717-634b7f6859f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582338506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.582338506
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.3351938198
Short name T15
Test name
Test status
Simulation time 399945780719 ps
CPU time 369.86 seconds
Started Aug 10 06:11:50 PM PDT 24
Finished Aug 10 06:18:00 PM PDT 24
Peak memory 199868 kb
Host smart-b2d0403c-c466-4daa-97dc-64504ff3366e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351938198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3351938198
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.834975159
Short name T498
Test name
Test status
Simulation time 77609935625 ps
CPU time 730.02 seconds
Started Aug 10 06:11:53 PM PDT 24
Finished Aug 10 06:24:03 PM PDT 24
Peak memory 199928 kb
Host smart-fcab500a-b41c-486a-b313-3863fe400646
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=834975159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.834975159
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.2753126108
Short name T915
Test name
Test status
Simulation time 2267459134 ps
CPU time 2.8 seconds
Started Aug 10 06:11:53 PM PDT 24
Finished Aug 10 06:11:56 PM PDT 24
Peak memory 199248 kb
Host smart-4c4dbf16-0228-4e00-af3c-be29fe2fc8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753126108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2753126108
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_perf.3363034960
Short name T782
Test name
Test status
Simulation time 6885777971 ps
CPU time 167.72 seconds
Started Aug 10 06:11:58 PM PDT 24
Finished Aug 10 06:14:45 PM PDT 24
Peak memory 199964 kb
Host smart-55061038-914a-49c7-8431-498aad0241c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3363034960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3363034960
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.3770749710
Short name T369
Test name
Test status
Simulation time 2603066507 ps
CPU time 1.9 seconds
Started Aug 10 06:11:45 PM PDT 24
Finished Aug 10 06:11:47 PM PDT 24
Peak memory 197900 kb
Host smart-76a5f45a-bc87-4493-b62f-f263510602f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3770749710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3770749710
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.467435347
Short name T265
Test name
Test status
Simulation time 53105524515 ps
CPU time 20.13 seconds
Started Aug 10 06:11:50 PM PDT 24
Finished Aug 10 06:12:10 PM PDT 24
Peak memory 199972 kb
Host smart-2b4c317e-9fd4-497b-83d7-86871ec295f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467435347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.467435347
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.819991383
Short name T1003
Test name
Test status
Simulation time 46564959401 ps
CPU time 17.07 seconds
Started Aug 10 06:11:48 PM PDT 24
Finished Aug 10 06:12:05 PM PDT 24
Peak memory 195808 kb
Host smart-857e9513-8ac9-4d46-be4c-6a8c6406ac23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819991383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.819991383
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.2055560884
Short name T1005
Test name
Test status
Simulation time 6149330022 ps
CPU time 13.26 seconds
Started Aug 10 06:11:50 PM PDT 24
Finished Aug 10 06:12:04 PM PDT 24
Peak memory 199884 kb
Host smart-db53c5f1-9eff-4ecd-8f6b-382a5f3dc0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055560884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2055560884
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.1169992027
Short name T1027
Test name
Test status
Simulation time 37698877924 ps
CPU time 199.6 seconds
Started Aug 10 06:11:58 PM PDT 24
Finished Aug 10 06:15:17 PM PDT 24
Peak memory 199980 kb
Host smart-44157629-8ee5-4953-9d83-da4f1bb910e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169992027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1169992027
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.1304563914
Short name T211
Test name
Test status
Simulation time 92221745990 ps
CPU time 521.78 seconds
Started Aug 10 06:11:55 PM PDT 24
Finished Aug 10 06:20:37 PM PDT 24
Peak memory 216416 kb
Host smart-2c13f4ea-8acb-4927-a8fc-dd1be8a09024
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304563914 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.1304563914
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.929349948
Short name T708
Test name
Test status
Simulation time 2023888780 ps
CPU time 1.6 seconds
Started Aug 10 06:11:54 PM PDT 24
Finished Aug 10 06:11:55 PM PDT 24
Peak memory 199360 kb
Host smart-27dcf6f6-60d7-4655-aec5-57ec3c2781af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929349948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.929349948
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.2693702705
Short name T550
Test name
Test status
Simulation time 25418740638 ps
CPU time 12.17 seconds
Started Aug 10 06:11:47 PM PDT 24
Finished Aug 10 06:11:59 PM PDT 24
Peak memory 199804 kb
Host smart-b5bc2ccd-45b7-4666-9d72-3efa680b3763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693702705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.2693702705
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.3736562402
Short name T981
Test name
Test status
Simulation time 31849951684 ps
CPU time 24.39 seconds
Started Aug 10 06:15:55 PM PDT 24
Finished Aug 10 06:16:20 PM PDT 24
Peak memory 199916 kb
Host smart-6afe2288-bbd5-4713-80bb-8d907e241797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736562402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3736562402
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1532205594
Short name T1098
Test name
Test status
Simulation time 82447482185 ps
CPU time 23.89 seconds
Started Aug 10 06:16:07 PM PDT 24
Finished Aug 10 06:16:31 PM PDT 24
Peak memory 199936 kb
Host smart-73a2a6c7-bbad-4c54-8cdc-589d2f30c14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532205594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1532205594
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.3177514880
Short name T1006
Test name
Test status
Simulation time 28672280644 ps
CPU time 49.76 seconds
Started Aug 10 06:16:07 PM PDT 24
Finished Aug 10 06:16:57 PM PDT 24
Peak memory 199908 kb
Host smart-2a05619a-5dc7-4230-a944-be2c2edede23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177514880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3177514880
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3491216683
Short name T895
Test name
Test status
Simulation time 31807949240 ps
CPU time 14.53 seconds
Started Aug 10 06:16:08 PM PDT 24
Finished Aug 10 06:16:22 PM PDT 24
Peak memory 199912 kb
Host smart-59f651a3-d06b-4074-bd9f-f2de4d763174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491216683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3491216683
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3360462353
Short name T37
Test name
Test status
Simulation time 29617205240 ps
CPU time 46.94 seconds
Started Aug 10 06:16:06 PM PDT 24
Finished Aug 10 06:16:54 PM PDT 24
Peak memory 199876 kb
Host smart-29f27ccb-01f9-45a0-ba31-1e03425c2db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360462353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3360462353
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3607261981
Short name T534
Test name
Test status
Simulation time 79541604708 ps
CPU time 112.94 seconds
Started Aug 10 06:16:07 PM PDT 24
Finished Aug 10 06:18:00 PM PDT 24
Peak memory 199888 kb
Host smart-4927f191-23b2-40e4-944d-53ad566d909a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607261981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3607261981
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.4084799408
Short name T942
Test name
Test status
Simulation time 19763930220 ps
CPU time 15.37 seconds
Started Aug 10 06:16:07 PM PDT 24
Finished Aug 10 06:16:22 PM PDT 24
Peak memory 198544 kb
Host smart-102d5b31-0567-4bdd-bd7f-eb31d6eccf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084799408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.4084799408
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3370890792
Short name T195
Test name
Test status
Simulation time 32414601891 ps
CPU time 57.91 seconds
Started Aug 10 06:16:08 PM PDT 24
Finished Aug 10 06:17:06 PM PDT 24
Peak memory 199972 kb
Host smart-671cb5a0-5465-4151-95b8-329edeec0d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370890792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3370890792
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1940180150
Short name T359
Test name
Test status
Simulation time 12668257817 ps
CPU time 19.06 seconds
Started Aug 10 06:16:05 PM PDT 24
Finished Aug 10 06:16:24 PM PDT 24
Peak memory 199936 kb
Host smart-ae0203cc-5dea-4f58-a1c0-dbb1bf0c9366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940180150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1940180150
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2937591255
Short name T787
Test name
Test status
Simulation time 177671869487 ps
CPU time 68.31 seconds
Started Aug 10 06:16:07 PM PDT 24
Finished Aug 10 06:17:16 PM PDT 24
Peak memory 199972 kb
Host smart-7134b980-9071-4fa7-9454-78a410308b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937591255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2937591255
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3276485193
Short name T1170
Test name
Test status
Simulation time 14128333 ps
CPU time 0.54 seconds
Started Aug 10 06:12:00 PM PDT 24
Finished Aug 10 06:12:01 PM PDT 24
Peak memory 195448 kb
Host smart-736ae138-2304-4cfc-9bdc-c358526ea96a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276485193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3276485193
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2134660851
Short name T876
Test name
Test status
Simulation time 27803227437 ps
CPU time 25.87 seconds
Started Aug 10 06:11:54 PM PDT 24
Finished Aug 10 06:12:20 PM PDT 24
Peak memory 199904 kb
Host smart-cdbddf16-629c-4812-b3ce-8ae6a46916a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134660851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2134660851
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3843174519
Short name T939
Test name
Test status
Simulation time 81245865906 ps
CPU time 62.91 seconds
Started Aug 10 06:11:54 PM PDT 24
Finished Aug 10 06:12:57 PM PDT 24
Peak memory 199964 kb
Host smart-8d9b1e6b-dd98-481f-b21d-a784a957f838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843174519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3843174519
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1655247063
Short name T123
Test name
Test status
Simulation time 123166947973 ps
CPU time 59.36 seconds
Started Aug 10 06:11:54 PM PDT 24
Finished Aug 10 06:12:53 PM PDT 24
Peak memory 199956 kb
Host smart-d88f9fa7-90dd-4187-8d2a-655eabbde226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655247063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1655247063
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.4159519352
Short name T1076
Test name
Test status
Simulation time 55740544866 ps
CPU time 9.93 seconds
Started Aug 10 06:11:58 PM PDT 24
Finished Aug 10 06:12:08 PM PDT 24
Peak memory 199904 kb
Host smart-9370c139-d0b6-4544-8927-cefac5686fb2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159519352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.4159519352
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1607494747
Short name T564
Test name
Test status
Simulation time 51443162036 ps
CPU time 90.2 seconds
Started Aug 10 06:12:03 PM PDT 24
Finished Aug 10 06:13:33 PM PDT 24
Peak memory 199928 kb
Host smart-d59ca932-78e4-4016-bc05-6804d4b2f0c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1607494747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1607494747
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.2140611695
Short name T947
Test name
Test status
Simulation time 1746499179 ps
CPU time 1.3 seconds
Started Aug 10 06:12:02 PM PDT 24
Finished Aug 10 06:12:03 PM PDT 24
Peak memory 196948 kb
Host smart-bfbd54cc-d8a3-4a17-a5a0-e6805e9b7cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140611695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2140611695
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2299041862
Short name T713
Test name
Test status
Simulation time 29151796602 ps
CPU time 55.45 seconds
Started Aug 10 06:11:55 PM PDT 24
Finished Aug 10 06:12:51 PM PDT 24
Peak memory 198732 kb
Host smart-db03a02b-88ee-47ec-a1c7-c8fa1aea39dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299041862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2299041862
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3721444543
Short name T831
Test name
Test status
Simulation time 22080611505 ps
CPU time 1150.93 seconds
Started Aug 10 06:12:02 PM PDT 24
Finished Aug 10 06:31:14 PM PDT 24
Peak memory 199932 kb
Host smart-6b091659-3e7f-4c63-b45a-ffee6af254e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3721444543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3721444543
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1365427875
Short name T554
Test name
Test status
Simulation time 5580790927 ps
CPU time 25.79 seconds
Started Aug 10 06:11:55 PM PDT 24
Finished Aug 10 06:12:21 PM PDT 24
Peak memory 198076 kb
Host smart-8989ecc8-933b-43da-b053-8d8af06f7519
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1365427875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1365427875
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.3894791418
Short name T307
Test name
Test status
Simulation time 103923320714 ps
CPU time 182.79 seconds
Started Aug 10 06:11:54 PM PDT 24
Finished Aug 10 06:14:57 PM PDT 24
Peak memory 199988 kb
Host smart-e1103820-6c11-4b6a-8306-e843cd170814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894791418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3894791418
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2668437446
Short name T855
Test name
Test status
Simulation time 3100722640 ps
CPU time 5.56 seconds
Started Aug 10 06:11:54 PM PDT 24
Finished Aug 10 06:11:59 PM PDT 24
Peak memory 196032 kb
Host smart-41082479-ec3d-49ce-88dd-9ae8562dfc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668437446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2668437446
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3135180946
Short name T294
Test name
Test status
Simulation time 937892884 ps
CPU time 2.66 seconds
Started Aug 10 06:11:55 PM PDT 24
Finished Aug 10 06:11:57 PM PDT 24
Peak memory 199756 kb
Host smart-9ab73f72-f8fb-4035-8796-5edcf91f58da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135180946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3135180946
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.1642001925
Short name T1118
Test name
Test status
Simulation time 421811498929 ps
CPU time 493.75 seconds
Started Aug 10 06:12:02 PM PDT 24
Finished Aug 10 06:20:16 PM PDT 24
Peak memory 208336 kb
Host smart-b2cf23d4-b173-4801-b224-ba589c168c4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642001925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1642001925
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.683830177
Short name T1100
Test name
Test status
Simulation time 58778312419 ps
CPU time 1265.18 seconds
Started Aug 10 06:12:01 PM PDT 24
Finished Aug 10 06:33:07 PM PDT 24
Peak memory 224772 kb
Host smart-a749540d-4aeb-483f-b379-49d862ebb121
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683830177 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.683830177
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.4108576239
Short name T492
Test name
Test status
Simulation time 810595073 ps
CPU time 2.58 seconds
Started Aug 10 06:12:01 PM PDT 24
Finished Aug 10 06:12:04 PM PDT 24
Peak memory 199776 kb
Host smart-28f5e327-7b3f-4cc6-88fc-8a694130b553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108576239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.4108576239
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.178702787
Short name T1001
Test name
Test status
Simulation time 113504398901 ps
CPU time 17.6 seconds
Started Aug 10 06:11:56 PM PDT 24
Finished Aug 10 06:12:14 PM PDT 24
Peak memory 198668 kb
Host smart-7e30dc67-b733-451f-9527-fb2d1b924d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178702787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.178702787
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1193226839
Short name T1148
Test name
Test status
Simulation time 16745779110 ps
CPU time 24.65 seconds
Started Aug 10 06:16:07 PM PDT 24
Finished Aug 10 06:16:31 PM PDT 24
Peak memory 199908 kb
Host smart-bdb38f11-7f1b-4020-8e80-561945ef8e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193226839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1193226839
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.3610554668
Short name T1156
Test name
Test status
Simulation time 43995261265 ps
CPU time 32.06 seconds
Started Aug 10 06:16:08 PM PDT 24
Finished Aug 10 06:16:40 PM PDT 24
Peak memory 199888 kb
Host smart-64ddc1a8-4598-44fb-ba8b-d2413f99a45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610554668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.3610554668
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.1664218013
Short name T184
Test name
Test status
Simulation time 28571507234 ps
CPU time 46.41 seconds
Started Aug 10 06:16:06 PM PDT 24
Finished Aug 10 06:16:53 PM PDT 24
Peak memory 199908 kb
Host smart-c7f9f38c-93e0-4d49-820f-baa4e0faee96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664218013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1664218013
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1043940525
Short name T223
Test name
Test status
Simulation time 37735127930 ps
CPU time 22.03 seconds
Started Aug 10 06:16:07 PM PDT 24
Finished Aug 10 06:16:29 PM PDT 24
Peak memory 199788 kb
Host smart-19e1379a-f93e-40a0-a6b2-7a4d970a23b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043940525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1043940525
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2446611712
Short name T769
Test name
Test status
Simulation time 302178114310 ps
CPU time 354.96 seconds
Started Aug 10 06:16:07 PM PDT 24
Finished Aug 10 06:22:02 PM PDT 24
Peak memory 199984 kb
Host smart-b0c510c2-a51e-4fe5-8825-c3472e5814f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446611712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2446611712
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.35856701
Short name T249
Test name
Test status
Simulation time 164740055148 ps
CPU time 184.02 seconds
Started Aug 10 06:16:07 PM PDT 24
Finished Aug 10 06:19:11 PM PDT 24
Peak memory 199928 kb
Host smart-aab1b9df-22ed-4e2c-9058-001eb0bff3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35856701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.35856701
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.367266332
Short name T226
Test name
Test status
Simulation time 112398604439 ps
CPU time 133.06 seconds
Started Aug 10 06:16:09 PM PDT 24
Finished Aug 10 06:18:22 PM PDT 24
Peak memory 199944 kb
Host smart-27508aae-e5e6-4e6e-a39e-9898e467e346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367266332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.367266332
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2841101354
Short name T807
Test name
Test status
Simulation time 9945099758 ps
CPU time 16.24 seconds
Started Aug 10 06:16:14 PM PDT 24
Finished Aug 10 06:16:30 PM PDT 24
Peak memory 199980 kb
Host smart-90fe5911-4cc9-4861-8d1e-d7e170a4bfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841101354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2841101354
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1902797806
Short name T475
Test name
Test status
Simulation time 32575217 ps
CPU time 0.52 seconds
Started Aug 10 06:12:09 PM PDT 24
Finished Aug 10 06:12:09 PM PDT 24
Peak memory 195016 kb
Host smart-603d5e94-fb3a-4ae5-b249-cb13e1a29ebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902797806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1902797806
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1101301555
Short name T1
Test name
Test status
Simulation time 181441859006 ps
CPU time 447.85 seconds
Started Aug 10 06:12:02 PM PDT 24
Finished Aug 10 06:19:30 PM PDT 24
Peak memory 199960 kb
Host smart-cacaf73c-1234-46ef-8f88-8ffff3e840d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101301555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1101301555
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2564919537
Short name T138
Test name
Test status
Simulation time 198246528240 ps
CPU time 77.61 seconds
Started Aug 10 06:12:03 PM PDT 24
Finished Aug 10 06:13:21 PM PDT 24
Peak memory 199864 kb
Host smart-310d34ed-5b90-4658-9836-812fb244975b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564919537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2564919537
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2252631396
Short name T201
Test name
Test status
Simulation time 191206112552 ps
CPU time 18.71 seconds
Started Aug 10 06:12:02 PM PDT 24
Finished Aug 10 06:12:21 PM PDT 24
Peak memory 199944 kb
Host smart-31849bea-5fea-49f1-b4a2-d8fe6a12ff8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252631396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2252631396
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.215432309
Short name T928
Test name
Test status
Simulation time 174347039687 ps
CPU time 25.98 seconds
Started Aug 10 06:12:00 PM PDT 24
Finished Aug 10 06:12:26 PM PDT 24
Peak memory 200000 kb
Host smart-e1428417-09e7-48f5-b1f5-0ee524170937
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215432309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.215432309
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.1178952301
Short name T594
Test name
Test status
Simulation time 97277109036 ps
CPU time 231.39 seconds
Started Aug 10 06:12:10 PM PDT 24
Finished Aug 10 06:16:01 PM PDT 24
Peak memory 199924 kb
Host smart-0605adab-0b7d-4c52-8368-8ebde24455b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1178952301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.1178952301
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.3767810664
Short name T385
Test name
Test status
Simulation time 1675013800 ps
CPU time 5.39 seconds
Started Aug 10 06:12:08 PM PDT 24
Finished Aug 10 06:12:13 PM PDT 24
Peak memory 198372 kb
Host smart-555b7bbc-4989-4ed2-89aa-a3cb4200fe15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767810664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.3767810664
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3854419858
Short name T663
Test name
Test status
Simulation time 83725160128 ps
CPU time 176.88 seconds
Started Aug 10 06:12:02 PM PDT 24
Finished Aug 10 06:14:59 PM PDT 24
Peak memory 208024 kb
Host smart-b415db27-2859-4998-b6e8-a135ba7e6098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854419858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3854419858
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3133629067
Short name T453
Test name
Test status
Simulation time 7225685892 ps
CPU time 340.87 seconds
Started Aug 10 06:12:10 PM PDT 24
Finished Aug 10 06:17:51 PM PDT 24
Peak memory 199992 kb
Host smart-fecd13b2-de68-4b60-bfe8-8a5ede69dfa3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3133629067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3133629067
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1722478116
Short name T837
Test name
Test status
Simulation time 4115841699 ps
CPU time 4.93 seconds
Started Aug 10 06:12:02 PM PDT 24
Finished Aug 10 06:12:07 PM PDT 24
Peak memory 198712 kb
Host smart-b89ad62d-be5f-489d-8b98-a956ce0ce810
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1722478116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1722478116
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.4013586061
Short name T34
Test name
Test status
Simulation time 22625850422 ps
CPU time 45.09 seconds
Started Aug 10 06:12:03 PM PDT 24
Finished Aug 10 06:12:48 PM PDT 24
Peak memory 199944 kb
Host smart-dcf053ed-934d-47e2-8566-b93c25b8c71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013586061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.4013586061
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.20801867
Short name T308
Test name
Test status
Simulation time 49585873866 ps
CPU time 20.95 seconds
Started Aug 10 06:12:00 PM PDT 24
Finished Aug 10 06:12:21 PM PDT 24
Peak memory 195812 kb
Host smart-6a050d81-dfc4-4cda-8642-19674309a921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20801867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.20801867
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.3306346679
Short name T383
Test name
Test status
Simulation time 281690238 ps
CPU time 1.03 seconds
Started Aug 10 06:12:02 PM PDT 24
Finished Aug 10 06:12:03 PM PDT 24
Peak memory 198288 kb
Host smart-13895181-5578-4993-93bb-c92f3b4ecdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306346679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.3306346679
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.4174375248
Short name T1053
Test name
Test status
Simulation time 2495440052 ps
CPU time 2.09 seconds
Started Aug 10 06:12:01 PM PDT 24
Finished Aug 10 06:12:04 PM PDT 24
Peak memory 199892 kb
Host smart-f830d11a-9cb9-4a42-93dd-5312ca21bb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174375248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.4174375248
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2855312168
Short name T945
Test name
Test status
Simulation time 45431675797 ps
CPU time 74.54 seconds
Started Aug 10 06:12:03 PM PDT 24
Finished Aug 10 06:13:17 PM PDT 24
Peak memory 199988 kb
Host smart-0550467e-36b4-4bf2-8082-2fa737147821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855312168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2855312168
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2831668214
Short name T442
Test name
Test status
Simulation time 106308219861 ps
CPU time 160.84 seconds
Started Aug 10 06:16:14 PM PDT 24
Finished Aug 10 06:18:55 PM PDT 24
Peak memory 199992 kb
Host smart-7cca6d63-bfc7-4bc7-a9df-dc06248630d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831668214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2831668214
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.3865863964
Short name T113
Test name
Test status
Simulation time 57852954409 ps
CPU time 20.66 seconds
Started Aug 10 06:16:15 PM PDT 24
Finished Aug 10 06:16:36 PM PDT 24
Peak memory 199992 kb
Host smart-59eb0fbc-ca77-4bfb-9080-f9b32efd01c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865863964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3865863964
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.310056318
Short name T182
Test name
Test status
Simulation time 220681656237 ps
CPU time 93.02 seconds
Started Aug 10 06:16:17 PM PDT 24
Finished Aug 10 06:17:50 PM PDT 24
Peak memory 199776 kb
Host smart-450af083-fed4-4628-b288-7835ffea1cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310056318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.310056318
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.3015130339
Short name T567
Test name
Test status
Simulation time 33214352500 ps
CPU time 50.25 seconds
Started Aug 10 06:16:16 PM PDT 24
Finished Aug 10 06:17:06 PM PDT 24
Peak memory 199976 kb
Host smart-8fae88dc-6126-4266-9189-0049bb6e8f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015130339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3015130339
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.1251722488
Short name T203
Test name
Test status
Simulation time 76296529561 ps
CPU time 114.62 seconds
Started Aug 10 06:16:16 PM PDT 24
Finished Aug 10 06:18:11 PM PDT 24
Peak memory 199988 kb
Host smart-b4dadff7-2af3-4acc-820c-0a079e4015f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251722488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1251722488
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2655072664
Short name T202
Test name
Test status
Simulation time 115307959625 ps
CPU time 31.39 seconds
Started Aug 10 06:16:16 PM PDT 24
Finished Aug 10 06:16:48 PM PDT 24
Peak memory 199968 kb
Host smart-b9f5a3e3-cb5c-48ac-b8ae-f90c1de695ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655072664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2655072664
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.3358982767
Short name T299
Test name
Test status
Simulation time 114905888575 ps
CPU time 179.75 seconds
Started Aug 10 06:16:15 PM PDT 24
Finished Aug 10 06:19:15 PM PDT 24
Peak memory 200004 kb
Host smart-608df33f-58fd-451a-8bb1-04b22a644173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358982767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3358982767
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1724947815
Short name T187
Test name
Test status
Simulation time 172482053226 ps
CPU time 272.26 seconds
Started Aug 10 06:16:16 PM PDT 24
Finished Aug 10 06:20:48 PM PDT 24
Peak memory 199932 kb
Host smart-197b891b-7326-4568-824a-f3e631e667ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724947815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1724947815
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.177211016
Short name T496
Test name
Test status
Simulation time 33879562478 ps
CPU time 50.5 seconds
Started Aug 10 06:16:15 PM PDT 24
Finished Aug 10 06:17:05 PM PDT 24
Peak memory 199840 kb
Host smart-d1886754-2db1-410f-8c84-75201ae48956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177211016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.177211016
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.3221294725
Short name T376
Test name
Test status
Simulation time 18133228 ps
CPU time 0.56 seconds
Started Aug 10 06:12:16 PM PDT 24
Finished Aug 10 06:12:16 PM PDT 24
Peak memory 195636 kb
Host smart-c6f6ffc2-4d4d-49d7-a98b-a9e8611b3ffd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221294725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3221294725
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.730119298
Short name T587
Test name
Test status
Simulation time 40695001737 ps
CPU time 36.74 seconds
Started Aug 10 06:12:10 PM PDT 24
Finished Aug 10 06:12:47 PM PDT 24
Peak memory 199940 kb
Host smart-88d41a76-44a3-4bf2-8339-f26f2c1372d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730119298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.730119298
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.932915020
Short name T748
Test name
Test status
Simulation time 125570620636 ps
CPU time 40.74 seconds
Started Aug 10 06:12:08 PM PDT 24
Finished Aug 10 06:12:49 PM PDT 24
Peak memory 200000 kb
Host smart-fd0e4290-180c-4ab8-9d28-7ec0a2a7264c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932915020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.932915020
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1057933444
Short name T582
Test name
Test status
Simulation time 92139665383 ps
CPU time 103.39 seconds
Started Aug 10 06:12:10 PM PDT 24
Finished Aug 10 06:13:54 PM PDT 24
Peak memory 199824 kb
Host smart-796d5955-f357-4ede-bba6-2b4526c4ed73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057933444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1057933444
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.691113682
Short name T300
Test name
Test status
Simulation time 14257995739 ps
CPU time 6.47 seconds
Started Aug 10 06:12:09 PM PDT 24
Finished Aug 10 06:12:15 PM PDT 24
Peak memory 199944 kb
Host smart-88f600ee-8aa7-4e57-a3a9-626fe20e7d11
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691113682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.691113682
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.2146530831
Short name T710
Test name
Test status
Simulation time 112545348733 ps
CPU time 218.1 seconds
Started Aug 10 06:12:18 PM PDT 24
Finished Aug 10 06:15:57 PM PDT 24
Peak memory 199952 kb
Host smart-7c922d92-4638-4ccd-bb6c-1b67bd00dedd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2146530831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2146530831
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.2156449285
Short name T1045
Test name
Test status
Simulation time 7039746685 ps
CPU time 26.54 seconds
Started Aug 10 06:12:18 PM PDT 24
Finished Aug 10 06:12:45 PM PDT 24
Peak memory 199432 kb
Host smart-e415e792-733c-4df0-b835-1f6e222b13b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156449285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2156449285
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.2792446154
Short name T704
Test name
Test status
Simulation time 79197003840 ps
CPU time 74.98 seconds
Started Aug 10 06:12:10 PM PDT 24
Finished Aug 10 06:13:25 PM PDT 24
Peak memory 208064 kb
Host smart-6459cdf3-d260-435b-a28b-89c00851738d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792446154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.2792446154
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.2473065865
Short name T114
Test name
Test status
Simulation time 12044837857 ps
CPU time 721.88 seconds
Started Aug 10 06:12:17 PM PDT 24
Finished Aug 10 06:24:19 PM PDT 24
Peak memory 199980 kb
Host smart-bb6b5e55-0829-42da-b18b-e10702fb7409
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2473065865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2473065865
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.3519499115
Short name T877
Test name
Test status
Simulation time 5007310289 ps
CPU time 41.74 seconds
Started Aug 10 06:12:09 PM PDT 24
Finished Aug 10 06:12:51 PM PDT 24
Peak memory 198168 kb
Host smart-a8629337-8250-454d-8115-46c3c803884a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3519499115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3519499115
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2956814365
Short name T1074
Test name
Test status
Simulation time 95630628833 ps
CPU time 37.55 seconds
Started Aug 10 06:12:09 PM PDT 24
Finished Aug 10 06:12:47 PM PDT 24
Peak memory 199908 kb
Host smart-70db8e99-f8a7-4829-ad5d-99e4b28353f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956814365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2956814365
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.736331214
Short name T317
Test name
Test status
Simulation time 4026443355 ps
CPU time 5.95 seconds
Started Aug 10 06:12:08 PM PDT 24
Finished Aug 10 06:12:14 PM PDT 24
Peak memory 196084 kb
Host smart-ba41c20c-4078-4fc6-bd2d-fba2983d55de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736331214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.736331214
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.144265687
Short name T912
Test name
Test status
Simulation time 5729041933 ps
CPU time 16.23 seconds
Started Aug 10 06:12:09 PM PDT 24
Finished Aug 10 06:12:25 PM PDT 24
Peak memory 199844 kb
Host smart-6b932ab6-be97-487c-a2c3-6a7e2dfc79ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144265687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.144265687
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.407734517
Short name T682
Test name
Test status
Simulation time 276251635452 ps
CPU time 109.82 seconds
Started Aug 10 06:12:16 PM PDT 24
Finished Aug 10 06:14:06 PM PDT 24
Peak memory 200144 kb
Host smart-c4bf0c53-91e7-4efa-a4f1-d0607a012ee1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407734517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.407734517
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3679922019
Short name T689
Test name
Test status
Simulation time 198488585912 ps
CPU time 1656.06 seconds
Started Aug 10 06:12:18 PM PDT 24
Finished Aug 10 06:39:55 PM PDT 24
Peak memory 228380 kb
Host smart-d7238885-5848-43e2-9f42-a535a4813d6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679922019 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3679922019
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.1593826940
Short name T1050
Test name
Test status
Simulation time 3122413962 ps
CPU time 1.82 seconds
Started Aug 10 06:12:09 PM PDT 24
Finished Aug 10 06:12:11 PM PDT 24
Peak memory 199276 kb
Host smart-a2191b3c-44f3-4ed4-a250-3fe3887dc306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593826940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1593826940
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2858905441
Short name T1140
Test name
Test status
Simulation time 162997877202 ps
CPU time 31.4 seconds
Started Aug 10 06:12:10 PM PDT 24
Finished Aug 10 06:12:42 PM PDT 24
Peak memory 199832 kb
Host smart-c47d0f76-ab92-4fa7-bf7e-1e77c848ff8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858905441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2858905441
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.3001223891
Short name T409
Test name
Test status
Simulation time 124221094347 ps
CPU time 51.19 seconds
Started Aug 10 06:16:16 PM PDT 24
Finished Aug 10 06:17:07 PM PDT 24
Peak memory 199868 kb
Host smart-e41b96b1-fbed-4c14-880b-cc29cf1acc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001223891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3001223891
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.2566641302
Short name T179
Test name
Test status
Simulation time 123180042486 ps
CPU time 56.97 seconds
Started Aug 10 06:16:15 PM PDT 24
Finished Aug 10 06:17:12 PM PDT 24
Peak memory 199936 kb
Host smart-1d99f8f5-105b-4ef3-abe5-5950869686d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566641302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2566641302
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.2749320396
Short name T159
Test name
Test status
Simulation time 24995170690 ps
CPU time 20.58 seconds
Started Aug 10 06:16:17 PM PDT 24
Finished Aug 10 06:16:38 PM PDT 24
Peak memory 199876 kb
Host smart-c4257791-58c8-41fb-b53c-d8a2b7d378f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749320396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2749320396
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2361757950
Short name T1119
Test name
Test status
Simulation time 141186456789 ps
CPU time 51.7 seconds
Started Aug 10 06:16:16 PM PDT 24
Finished Aug 10 06:17:07 PM PDT 24
Peak memory 199724 kb
Host smart-ab376d13-2f5f-41f1-83db-a3ade5edac8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361757950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2361757950
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.239517975
Short name T1180
Test name
Test status
Simulation time 44528532047 ps
CPU time 20.67 seconds
Started Aug 10 06:16:17 PM PDT 24
Finished Aug 10 06:16:38 PM PDT 24
Peak memory 199980 kb
Host smart-4ee818f5-36d7-4462-8057-a8053df85a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239517975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.239517975
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3191670858
Short name T592
Test name
Test status
Simulation time 33768869107 ps
CPU time 11.62 seconds
Started Aug 10 06:16:16 PM PDT 24
Finished Aug 10 06:16:28 PM PDT 24
Peak memory 199532 kb
Host smart-ebbe4ec6-15d1-4d12-8f2f-70479852b3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191670858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3191670858
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3090151451
Short name T160
Test name
Test status
Simulation time 46201567933 ps
CPU time 16.78 seconds
Started Aug 10 06:16:16 PM PDT 24
Finished Aug 10 06:16:33 PM PDT 24
Peak memory 199772 kb
Host smart-1cb53946-77a7-4c09-9dbc-417a6e085b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090151451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3090151451
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1957234258
Short name T276
Test name
Test status
Simulation time 97324265303 ps
CPU time 75.33 seconds
Started Aug 10 06:16:15 PM PDT 24
Finished Aug 10 06:17:31 PM PDT 24
Peak memory 199672 kb
Host smart-c50e11d0-420c-4a08-a463-203f2cd178e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957234258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1957234258
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.1604210989
Short name T1102
Test name
Test status
Simulation time 34614272614 ps
CPU time 63.72 seconds
Started Aug 10 06:16:15 PM PDT 24
Finished Aug 10 06:17:19 PM PDT 24
Peak memory 199920 kb
Host smart-d3cef51c-f9ad-4825-b927-80721f2bc2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604210989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1604210989
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3873906499
Short name T45
Test name
Test status
Simulation time 50794258999 ps
CPU time 51.55 seconds
Started Aug 10 06:16:15 PM PDT 24
Finished Aug 10 06:17:07 PM PDT 24
Peak memory 199956 kb
Host smart-3d791385-bd5b-40a0-aee1-60d27aecd379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873906499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3873906499
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.624674450
Short name T1142
Test name
Test status
Simulation time 40451083 ps
CPU time 0.54 seconds
Started Aug 10 06:12:26 PM PDT 24
Finished Aug 10 06:12:27 PM PDT 24
Peak memory 194336 kb
Host smart-7a0e0fe3-1e5e-4891-ba5c-57f398be09c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624674450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.624674450
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.474339139
Short name T488
Test name
Test status
Simulation time 60865267950 ps
CPU time 25.06 seconds
Started Aug 10 06:12:18 PM PDT 24
Finished Aug 10 06:12:43 PM PDT 24
Peak memory 199920 kb
Host smart-04da8e02-239e-4933-8e33-1f355dac455a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474339139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.474339139
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1345945441
Short name T893
Test name
Test status
Simulation time 43620481095 ps
CPU time 73.51 seconds
Started Aug 10 06:12:17 PM PDT 24
Finished Aug 10 06:13:30 PM PDT 24
Peak memory 200000 kb
Host smart-549b25d1-d1a2-4fa6-9cd4-e7ba5aaa2ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345945441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1345945441
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.1004060988
Short name T33
Test name
Test status
Simulation time 8134477267 ps
CPU time 13.78 seconds
Started Aug 10 06:12:18 PM PDT 24
Finished Aug 10 06:12:31 PM PDT 24
Peak memory 199996 kb
Host smart-b1305b78-5361-49c0-88c7-8134200e4524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004060988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1004060988
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.3104708313
Short name T635
Test name
Test status
Simulation time 88157613618 ps
CPU time 197.7 seconds
Started Aug 10 06:12:16 PM PDT 24
Finished Aug 10 06:15:34 PM PDT 24
Peak memory 199964 kb
Host smart-f295b1e3-df05-47b2-a474-0b5207442c09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3104708313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3104708313
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2069997857
Short name T365
Test name
Test status
Simulation time 7442501323 ps
CPU time 13.74 seconds
Started Aug 10 06:12:17 PM PDT 24
Finished Aug 10 06:12:31 PM PDT 24
Peak memory 199664 kb
Host smart-713a37cb-228b-4058-b4c2-3ab1de4d6a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069997857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2069997857
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.1977509811
Short name T1103
Test name
Test status
Simulation time 48898254169 ps
CPU time 89.39 seconds
Started Aug 10 06:12:17 PM PDT 24
Finished Aug 10 06:13:46 PM PDT 24
Peak memory 200044 kb
Host smart-c3837bd3-4d9c-4d13-9968-8faa5674aaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977509811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.1977509811
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.1520126475
Short name T874
Test name
Test status
Simulation time 19878286631 ps
CPU time 396.87 seconds
Started Aug 10 06:12:16 PM PDT 24
Finished Aug 10 06:18:53 PM PDT 24
Peak memory 199992 kb
Host smart-8d835be9-a130-42d3-ab4e-bf6bddd090ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1520126475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1520126475
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1188869039
Short name T706
Test name
Test status
Simulation time 3183525327 ps
CPU time 12.29 seconds
Started Aug 10 06:12:17 PM PDT 24
Finished Aug 10 06:12:29 PM PDT 24
Peak memory 199048 kb
Host smart-307849d2-d0c4-4f8a-bb1b-88ac2a272570
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1188869039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1188869039
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.146683158
Short name T657
Test name
Test status
Simulation time 102104417538 ps
CPU time 94.37 seconds
Started Aug 10 06:12:19 PM PDT 24
Finished Aug 10 06:13:53 PM PDT 24
Peak memory 199960 kb
Host smart-26abc9cd-3e17-4e52-9ea4-809f4628f410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146683158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.146683158
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.2180440735
Short name T1029
Test name
Test status
Simulation time 2626243256 ps
CPU time 1.7 seconds
Started Aug 10 06:12:16 PM PDT 24
Finished Aug 10 06:12:18 PM PDT 24
Peak memory 196556 kb
Host smart-e9237f55-a67f-43f3-bf09-82ca70d411dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180440735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2180440735
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.863206979
Short name T774
Test name
Test status
Simulation time 6182474756 ps
CPU time 7.28 seconds
Started Aug 10 06:12:17 PM PDT 24
Finished Aug 10 06:12:25 PM PDT 24
Peak memory 199708 kb
Host smart-f589cdcd-1ead-4223-bef4-3328294dcd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863206979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.863206979
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1707064614
Short name T1122
Test name
Test status
Simulation time 235297578483 ps
CPU time 41.35 seconds
Started Aug 10 06:12:27 PM PDT 24
Finished Aug 10 06:13:08 PM PDT 24
Peak memory 199896 kb
Host smart-805315ca-0fd3-494e-8a4e-cb9369db59bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707064614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1707064614
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.819427072
Short name T784
Test name
Test status
Simulation time 29429156427 ps
CPU time 402.19 seconds
Started Aug 10 06:12:21 PM PDT 24
Finished Aug 10 06:19:03 PM PDT 24
Peak memory 215548 kb
Host smart-934cf70a-b4bc-4599-ae18-6c9479d873f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819427072 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.819427072
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.102316474
Short name T654
Test name
Test status
Simulation time 6764928983 ps
CPU time 74.33 seconds
Started Aug 10 06:12:17 PM PDT 24
Finished Aug 10 06:13:32 PM PDT 24
Peak memory 199348 kb
Host smart-e1d7ac74-d2f5-46b4-bc32-95e1dcbce41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102316474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.102316474
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.2402414540
Short name T925
Test name
Test status
Simulation time 40592121405 ps
CPU time 6.21 seconds
Started Aug 10 06:12:21 PM PDT 24
Finished Aug 10 06:12:27 PM PDT 24
Peak memory 197880 kb
Host smart-301ff904-79cc-412c-8eb1-40855b6556fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402414540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2402414540
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1237149987
Short name T1160
Test name
Test status
Simulation time 51046617524 ps
CPU time 89.27 seconds
Started Aug 10 06:16:15 PM PDT 24
Finished Aug 10 06:17:44 PM PDT 24
Peak memory 199936 kb
Host smart-5442be1d-ae32-4296-a93e-6b5dfbd32d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237149987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1237149987
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.4072870164
Short name T532
Test name
Test status
Simulation time 48843319364 ps
CPU time 23.28 seconds
Started Aug 10 06:16:17 PM PDT 24
Finished Aug 10 06:16:40 PM PDT 24
Peak memory 199976 kb
Host smart-1be8beb3-4713-4e6e-8be8-ddd1a221d38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072870164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.4072870164
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2517025532
Short name T235
Test name
Test status
Simulation time 11770369685 ps
CPU time 19.21 seconds
Started Aug 10 06:16:18 PM PDT 24
Finished Aug 10 06:16:37 PM PDT 24
Peak memory 199936 kb
Host smart-1c570700-a8de-499b-8dfa-fd516c49e2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517025532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2517025532
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.45756154
Short name T199
Test name
Test status
Simulation time 45176358247 ps
CPU time 72.14 seconds
Started Aug 10 06:16:24 PM PDT 24
Finished Aug 10 06:17:36 PM PDT 24
Peak memory 199956 kb
Host smart-e2e7a30e-28b7-4d7b-990f-9c7bc9d3c879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45756154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.45756154
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.1620242096
Short name T208
Test name
Test status
Simulation time 66351005534 ps
CPU time 64.02 seconds
Started Aug 10 06:16:23 PM PDT 24
Finished Aug 10 06:17:28 PM PDT 24
Peak memory 199980 kb
Host smart-f9c4f790-be8b-43fa-b05e-0bcc86099688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620242096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1620242096
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.727515440
Short name T229
Test name
Test status
Simulation time 42477171841 ps
CPU time 36.69 seconds
Started Aug 10 06:16:23 PM PDT 24
Finished Aug 10 06:17:00 PM PDT 24
Peak memory 199884 kb
Host smart-dacc6a0f-04bb-4a7c-b8fb-327deeb20659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727515440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.727515440
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2012898918
Short name T1162
Test name
Test status
Simulation time 16776325216 ps
CPU time 25.3 seconds
Started Aug 10 06:16:25 PM PDT 24
Finished Aug 10 06:16:51 PM PDT 24
Peak memory 199932 kb
Host smart-899f2a80-8719-4a9c-974d-f71eca6a5e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012898918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2012898918
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.3313391271
Short name T135
Test name
Test status
Simulation time 23380293642 ps
CPU time 36.14 seconds
Started Aug 10 06:16:24 PM PDT 24
Finished Aug 10 06:17:00 PM PDT 24
Peak memory 199944 kb
Host smart-fc748cab-d003-4428-aff1-62cd810a5b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313391271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3313391271
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3322098969
Short name T21
Test name
Test status
Simulation time 43610367 ps
CPU time 0.55 seconds
Started Aug 10 06:12:25 PM PDT 24
Finished Aug 10 06:12:26 PM PDT 24
Peak memory 195304 kb
Host smart-e491abf7-768c-4fec-943b-6d2ddd558cef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322098969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3322098969
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.1937938503
Short name T637
Test name
Test status
Simulation time 117002890449 ps
CPU time 212.37 seconds
Started Aug 10 06:12:24 PM PDT 24
Finished Aug 10 06:15:57 PM PDT 24
Peak memory 199884 kb
Host smart-6fc9dce7-dd73-4f9e-baef-dcd6402d9fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937938503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1937938503
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.20570661
Short name T911
Test name
Test status
Simulation time 135915351338 ps
CPU time 215.67 seconds
Started Aug 10 06:12:27 PM PDT 24
Finished Aug 10 06:16:02 PM PDT 24
Peak memory 199964 kb
Host smart-0a9542d3-4f1f-4342-a227-f972e5851036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20570661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.20570661
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.4138704393
Short name T212
Test name
Test status
Simulation time 16968984723 ps
CPU time 24.45 seconds
Started Aug 10 06:12:24 PM PDT 24
Finished Aug 10 06:12:49 PM PDT 24
Peak memory 199916 kb
Host smart-3c9d38f6-e83b-435b-b4a2-0b7efed9416d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138704393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.4138704393
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.3934080814
Short name T312
Test name
Test status
Simulation time 16500219758 ps
CPU time 25.59 seconds
Started Aug 10 06:12:27 PM PDT 24
Finished Aug 10 06:12:52 PM PDT 24
Peak memory 199236 kb
Host smart-c025c472-52ce-49dc-9d3c-9e5b369a8924
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934080814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3934080814
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.314658654
Short name T711
Test name
Test status
Simulation time 143421253485 ps
CPU time 824.62 seconds
Started Aug 10 06:12:25 PM PDT 24
Finished Aug 10 06:26:10 PM PDT 24
Peak memory 199896 kb
Host smart-81033b98-6a34-40ff-9ce0-5db6e73ce960
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=314658654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.314658654
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1694505176
Short name T363
Test name
Test status
Simulation time 7490453269 ps
CPU time 3.92 seconds
Started Aug 10 06:12:27 PM PDT 24
Finished Aug 10 06:12:31 PM PDT 24
Peak memory 198512 kb
Host smart-c2d8a83a-d51f-4d39-9a96-c3b57e18e778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694505176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1694505176
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.3539412207
Short name T482
Test name
Test status
Simulation time 13330111539 ps
CPU time 11.37 seconds
Started Aug 10 06:12:24 PM PDT 24
Finished Aug 10 06:12:35 PM PDT 24
Peak memory 194736 kb
Host smart-9c408ebe-ef1a-4b26-8317-895d0d9357c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539412207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.3539412207
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.2474515452
Short name T693
Test name
Test status
Simulation time 7704669318 ps
CPU time 397.66 seconds
Started Aug 10 06:12:24 PM PDT 24
Finished Aug 10 06:19:02 PM PDT 24
Peak memory 199840 kb
Host smart-c6d62eaa-c429-4502-8c77-5c9789de5503
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2474515452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2474515452
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.1219321155
Short name T474
Test name
Test status
Simulation time 1586967707 ps
CPU time 6.05 seconds
Started Aug 10 06:12:25 PM PDT 24
Finished Aug 10 06:12:31 PM PDT 24
Peak memory 197988 kb
Host smart-56f1f14e-9478-484b-8043-6bac3b8af550
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1219321155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1219321155
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.1413322302
Short name T471
Test name
Test status
Simulation time 114182663246 ps
CPU time 164.28 seconds
Started Aug 10 06:12:25 PM PDT 24
Finished Aug 10 06:15:09 PM PDT 24
Peak memory 199932 kb
Host smart-31ef20eb-e2af-42b7-9671-d8a5b8aec4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413322302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1413322302
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2628017534
Short name T1096
Test name
Test status
Simulation time 4597280121 ps
CPU time 7.56 seconds
Started Aug 10 06:12:26 PM PDT 24
Finished Aug 10 06:12:34 PM PDT 24
Peak memory 196296 kb
Host smart-cfed7859-f25a-4771-a24f-3f2c2b46ec79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628017534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2628017534
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.4168386687
Short name T516
Test name
Test status
Simulation time 291117161 ps
CPU time 1.65 seconds
Started Aug 10 06:12:26 PM PDT 24
Finished Aug 10 06:12:28 PM PDT 24
Peak memory 198276 kb
Host smart-0127d5ad-060b-4fdb-b3b8-b933d592f820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168386687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.4168386687
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.3191936364
Short name T955
Test name
Test status
Simulation time 304937301140 ps
CPU time 716.79 seconds
Started Aug 10 06:12:23 PM PDT 24
Finished Aug 10 06:24:20 PM PDT 24
Peak memory 199976 kb
Host smart-a9b04cac-ad1e-4f49-bda1-1c14365ce129
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191936364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3191936364
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1674973016
Short name T104
Test name
Test status
Simulation time 53675549284 ps
CPU time 458.53 seconds
Started Aug 10 06:12:25 PM PDT 24
Finished Aug 10 06:20:04 PM PDT 24
Peak memory 216620 kb
Host smart-806dac56-745e-48fe-9754-1afc23a6ab0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674973016 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1674973016
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.4054031196
Short name T1154
Test name
Test status
Simulation time 165986489 ps
CPU time 0.89 seconds
Started Aug 10 06:12:24 PM PDT 24
Finished Aug 10 06:12:25 PM PDT 24
Peak memory 197004 kb
Host smart-0cb6544c-90d8-4e29-8621-376afcb34cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054031196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.4054031196
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3343038896
Short name T430
Test name
Test status
Simulation time 2604281405 ps
CPU time 6.03 seconds
Started Aug 10 06:12:24 PM PDT 24
Finished Aug 10 06:12:30 PM PDT 24
Peak memory 199936 kb
Host smart-184d288a-caf3-4785-aec9-067e50d5bca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343038896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3343038896
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3512599290
Short name T1063
Test name
Test status
Simulation time 63675785737 ps
CPU time 23.66 seconds
Started Aug 10 06:16:24 PM PDT 24
Finished Aug 10 06:16:48 PM PDT 24
Peak memory 199976 kb
Host smart-0ea9e91a-6cfe-4d58-9ac2-576626ffa2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512599290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3512599290
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.880250435
Short name T792
Test name
Test status
Simulation time 79482235843 ps
CPU time 129.91 seconds
Started Aug 10 06:16:24 PM PDT 24
Finished Aug 10 06:18:34 PM PDT 24
Peak memory 199924 kb
Host smart-adbcc3e8-7709-465d-9b10-99657d7c2100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880250435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.880250435
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.899095497
Short name T950
Test name
Test status
Simulation time 14919125742 ps
CPU time 11.65 seconds
Started Aug 10 06:16:24 PM PDT 24
Finished Aug 10 06:16:36 PM PDT 24
Peak memory 199924 kb
Host smart-c637452b-6e31-4e1f-bc6b-19b84d5f12cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899095497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.899095497
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.2903584736
Short name T439
Test name
Test status
Simulation time 56030092838 ps
CPU time 24.81 seconds
Started Aug 10 06:16:25 PM PDT 24
Finished Aug 10 06:16:50 PM PDT 24
Peak memory 199876 kb
Host smart-03ab3b52-1b1d-4682-845c-8b11f54d80ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903584736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2903584736
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2432715930
Short name T797
Test name
Test status
Simulation time 34090959574 ps
CPU time 60.19 seconds
Started Aug 10 06:16:26 PM PDT 24
Finished Aug 10 06:17:27 PM PDT 24
Peak memory 199976 kb
Host smart-f28c40fc-200f-4b18-bda5-bfd3e5719f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432715930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2432715930
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3118437476
Short name T755
Test name
Test status
Simulation time 22714541555 ps
CPU time 8.88 seconds
Started Aug 10 06:16:27 PM PDT 24
Finished Aug 10 06:16:35 PM PDT 24
Peak memory 199932 kb
Host smart-acd46b51-9c07-406f-8f38-b9ce20ebad1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118437476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3118437476
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3513051872
Short name T606
Test name
Test status
Simulation time 18516184100 ps
CPU time 11.22 seconds
Started Aug 10 06:16:24 PM PDT 24
Finished Aug 10 06:16:35 PM PDT 24
Peak memory 199844 kb
Host smart-4d7b2126-abd0-48ba-a74d-6ea19a481e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513051872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3513051872
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1209455272
Short name T398
Test name
Test status
Simulation time 22005982909 ps
CPU time 34.49 seconds
Started Aug 10 06:16:25 PM PDT 24
Finished Aug 10 06:17:00 PM PDT 24
Peak memory 199192 kb
Host smart-91a44c7c-a0c0-4195-91a1-0286bd93ba24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209455272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1209455272
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.2775253174
Short name T336
Test name
Test status
Simulation time 27233541317 ps
CPU time 106.84 seconds
Started Aug 10 06:16:24 PM PDT 24
Finished Aug 10 06:18:11 PM PDT 24
Peak memory 199936 kb
Host smart-1b1c2b2f-cb71-4e91-ba9a-947399fa99a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775253174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2775253174
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2052079744
Short name T1040
Test name
Test status
Simulation time 143582466 ps
CPU time 0.55 seconds
Started Aug 10 06:12:35 PM PDT 24
Finished Aug 10 06:12:35 PM PDT 24
Peak memory 195352 kb
Host smart-e1c72df1-083f-404b-bc2e-72d1193b750b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052079744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2052079744
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2490447830
Short name T734
Test name
Test status
Simulation time 49261472110 ps
CPU time 20.99 seconds
Started Aug 10 06:12:34 PM PDT 24
Finished Aug 10 06:12:55 PM PDT 24
Peak memory 199952 kb
Host smart-254f0b09-36d2-491a-8253-4bae668a2488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490447830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2490447830
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3783150852
Short name T951
Test name
Test status
Simulation time 20352115476 ps
CPU time 9.2 seconds
Started Aug 10 06:12:36 PM PDT 24
Finished Aug 10 06:12:45 PM PDT 24
Peak memory 199888 kb
Host smart-70a1cce5-6719-459d-83c3-76bc5fc571d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783150852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3783150852
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.2606851915
Short name T1031
Test name
Test status
Simulation time 138214083551 ps
CPU time 54.68 seconds
Started Aug 10 06:12:33 PM PDT 24
Finished Aug 10 06:13:27 PM PDT 24
Peak memory 200000 kb
Host smart-b185c598-0c49-4584-814b-b0f1035560fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606851915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2606851915
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1758683424
Short name T992
Test name
Test status
Simulation time 53445068861 ps
CPU time 85.89 seconds
Started Aug 10 06:12:35 PM PDT 24
Finished Aug 10 06:14:01 PM PDT 24
Peak memory 199532 kb
Host smart-67872eb6-64db-4804-a753-c6ed8820141b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758683424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1758683424
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.714484599
Short name T1163
Test name
Test status
Simulation time 104554622562 ps
CPU time 180.81 seconds
Started Aug 10 06:12:34 PM PDT 24
Finished Aug 10 06:15:35 PM PDT 24
Peak memory 199932 kb
Host smart-66c0b15e-d22b-4dcd-92e9-6c67ce8a07cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=714484599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.714484599
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.4002834824
Short name T896
Test name
Test status
Simulation time 530462536 ps
CPU time 1.06 seconds
Started Aug 10 06:12:34 PM PDT 24
Finished Aug 10 06:12:35 PM PDT 24
Peak memory 197120 kb
Host smart-2c480b6c-53c5-45ad-81c8-0121fbfe6070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002834824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.4002834824
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.3431879292
Short name T1091
Test name
Test status
Simulation time 246920810031 ps
CPU time 304.87 seconds
Started Aug 10 06:12:34 PM PDT 24
Finished Aug 10 06:17:39 PM PDT 24
Peak memory 200068 kb
Host smart-f0f1f5e0-526e-4354-911b-9357b38d4fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431879292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3431879292
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.448478350
Short name T275
Test name
Test status
Simulation time 17193356252 ps
CPU time 263.15 seconds
Started Aug 10 06:12:36 PM PDT 24
Finished Aug 10 06:16:59 PM PDT 24
Peak memory 199840 kb
Host smart-cc824eed-e0d0-4465-a62d-abf96d4d010d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448478350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.448478350
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1586335243
Short name T377
Test name
Test status
Simulation time 1887738248 ps
CPU time 5.94 seconds
Started Aug 10 06:12:34 PM PDT 24
Finished Aug 10 06:12:40 PM PDT 24
Peak memory 197876 kb
Host smart-ea1ff4ad-a670-4231-ad0b-27e3fff00ae7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1586335243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1586335243
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.3301653780
Short name T4
Test name
Test status
Simulation time 61709981288 ps
CPU time 33.65 seconds
Started Aug 10 06:12:34 PM PDT 24
Finished Aug 10 06:13:07 PM PDT 24
Peak memory 199964 kb
Host smart-1dbbc83f-49bb-496a-bac1-65d0cbe9dc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301653780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3301653780
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2383387579
Short name T1123
Test name
Test status
Simulation time 753940671 ps
CPU time 1.81 seconds
Started Aug 10 06:12:36 PM PDT 24
Finished Aug 10 06:12:37 PM PDT 24
Peak memory 195600 kb
Host smart-3e39c3cd-31fb-48db-a9dc-9241439c2e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383387579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2383387579
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1165023613
Short name T1153
Test name
Test status
Simulation time 490661054 ps
CPU time 1.15 seconds
Started Aug 10 06:12:36 PM PDT 24
Finished Aug 10 06:12:37 PM PDT 24
Peak memory 199824 kb
Host smart-ead88290-bf40-4736-9b13-3f9f55116f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165023613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1165023613
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.1119753337
Short name T1046
Test name
Test status
Simulation time 541697832462 ps
CPU time 356.69 seconds
Started Aug 10 06:12:36 PM PDT 24
Finished Aug 10 06:18:33 PM PDT 24
Peak memory 208316 kb
Host smart-ff1974c0-7af9-4332-a9e0-8e8d1100b6d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119753337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1119753337
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.2980809235
Short name T980
Test name
Test status
Simulation time 145824284284 ps
CPU time 301.8 seconds
Started Aug 10 06:12:33 PM PDT 24
Finished Aug 10 06:17:35 PM PDT 24
Peak memory 216732 kb
Host smart-8594289f-97d2-46e3-ac08-f0ce7b71b16d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980809235 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.2980809235
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1654537843
Short name T576
Test name
Test status
Simulation time 12849150750 ps
CPU time 23.32 seconds
Started Aug 10 06:12:33 PM PDT 24
Finished Aug 10 06:12:57 PM PDT 24
Peak memory 199992 kb
Host smart-0989a80e-bc2b-4fee-b673-4db718358608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654537843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1654537843
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3169721808
Short name T331
Test name
Test status
Simulation time 46293126838 ps
CPU time 76.99 seconds
Started Aug 10 06:12:35 PM PDT 24
Finished Aug 10 06:13:53 PM PDT 24
Peak memory 199868 kb
Host smart-27c1b1d5-3b66-4119-bea6-e1f95c7ded32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169721808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3169721808
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1257335179
Short name T805
Test name
Test status
Simulation time 46114456998 ps
CPU time 62.91 seconds
Started Aug 10 06:16:24 PM PDT 24
Finished Aug 10 06:17:27 PM PDT 24
Peak memory 199048 kb
Host smart-4c8246fd-7fde-47ca-8964-91ffe7266e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257335179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1257335179
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.2165577505
Short name T1126
Test name
Test status
Simulation time 15149251418 ps
CPU time 21.94 seconds
Started Aug 10 06:16:27 PM PDT 24
Finished Aug 10 06:16:49 PM PDT 24
Peak memory 199880 kb
Host smart-e9aedc5f-d78b-46f2-aced-3be977d97894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165577505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2165577505
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1360121499
Short name T1092
Test name
Test status
Simulation time 41052827033 ps
CPU time 27.22 seconds
Started Aug 10 06:16:24 PM PDT 24
Finished Aug 10 06:16:51 PM PDT 24
Peak memory 199976 kb
Host smart-94a2b444-58a4-49a2-af69-5ef89a255db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360121499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1360121499
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1184004032
Short name T1124
Test name
Test status
Simulation time 66884506726 ps
CPU time 34.99 seconds
Started Aug 10 06:16:23 PM PDT 24
Finished Aug 10 06:16:58 PM PDT 24
Peak memory 199912 kb
Host smart-f7bf823f-9c3a-4004-9690-d7b025701ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184004032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1184004032
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.186864106
Short name T225
Test name
Test status
Simulation time 127143373808 ps
CPU time 48.07 seconds
Started Aug 10 06:16:33 PM PDT 24
Finished Aug 10 06:17:22 PM PDT 24
Peak memory 199868 kb
Host smart-edfa346f-80be-4057-9c43-e4b40bbf074b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186864106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.186864106
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1228398139
Short name T934
Test name
Test status
Simulation time 41871618297 ps
CPU time 32.64 seconds
Started Aug 10 06:16:32 PM PDT 24
Finished Aug 10 06:17:04 PM PDT 24
Peak memory 199908 kb
Host smart-7b301a11-5bbb-4746-87c6-a4ae2ab9d506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228398139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1228398139
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.926874416
Short name T1155
Test name
Test status
Simulation time 94590907467 ps
CPU time 24.86 seconds
Started Aug 10 06:16:30 PM PDT 24
Finished Aug 10 06:16:55 PM PDT 24
Peak memory 199968 kb
Host smart-2e95a771-bce1-42b2-933d-facac81ec60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926874416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.926874416
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1720142836
Short name T1049
Test name
Test status
Simulation time 14522968831 ps
CPU time 21.97 seconds
Started Aug 10 06:16:30 PM PDT 24
Finished Aug 10 06:16:52 PM PDT 24
Peak memory 199808 kb
Host smart-70078a44-1cbf-46f0-b1fe-44ff33a1e136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720142836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1720142836
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3975907314
Short name T354
Test name
Test status
Simulation time 140873090780 ps
CPU time 53.59 seconds
Started Aug 10 06:16:30 PM PDT 24
Finished Aug 10 06:17:24 PM PDT 24
Peak memory 199904 kb
Host smart-37267b90-9e6a-41ec-bffe-4440ec5cf174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975907314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3975907314
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3023466807
Short name T180
Test name
Test status
Simulation time 118455971176 ps
CPU time 122.3 seconds
Started Aug 10 06:16:30 PM PDT 24
Finished Aug 10 06:18:32 PM PDT 24
Peak memory 199992 kb
Host smart-b5c2dfbe-44fb-4ed3-91f4-871a8462f1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023466807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3023466807
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.702878440
Short name T526
Test name
Test status
Simulation time 127991893 ps
CPU time 0.54 seconds
Started Aug 10 06:09:13 PM PDT 24
Finished Aug 10 06:09:13 PM PDT 24
Peak memory 195316 kb
Host smart-160d3763-7fc1-4b24-8888-b327518f579c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702878440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.702878440
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1476360732
Short name T509
Test name
Test status
Simulation time 121448013421 ps
CPU time 48.08 seconds
Started Aug 10 06:08:55 PM PDT 24
Finished Aug 10 06:09:43 PM PDT 24
Peak memory 199964 kb
Host smart-fc2d65af-24af-455b-b975-f3426f7e3e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476360732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1476360732
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.1724207248
Short name T141
Test name
Test status
Simulation time 18795880735 ps
CPU time 18.63 seconds
Started Aug 10 06:08:54 PM PDT 24
Finished Aug 10 06:09:13 PM PDT 24
Peak memory 199992 kb
Host smart-a33b5727-31cf-4834-9a35-1d497c0e9db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724207248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1724207248
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1326045755
Short name T448
Test name
Test status
Simulation time 15663818340 ps
CPU time 19.12 seconds
Started Aug 10 06:08:55 PM PDT 24
Finished Aug 10 06:09:14 PM PDT 24
Peak memory 199896 kb
Host smart-5c4c1444-6840-437b-b0fb-34701004c92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326045755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1326045755
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.2054736254
Short name T96
Test name
Test status
Simulation time 77175342953 ps
CPU time 67.01 seconds
Started Aug 10 06:09:03 PM PDT 24
Finished Aug 10 06:10:11 PM PDT 24
Peak memory 199940 kb
Host smart-f3bc1914-e566-4c54-9473-346511acf36f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054736254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2054736254
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3518727756
Short name T530
Test name
Test status
Simulation time 102362239847 ps
CPU time 711.13 seconds
Started Aug 10 06:09:04 PM PDT 24
Finished Aug 10 06:20:55 PM PDT 24
Peak memory 199948 kb
Host smart-c87c05fd-dcd5-4f6f-88a8-2519575e287a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3518727756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3518727756
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1696883581
Short name T371
Test name
Test status
Simulation time 477882521 ps
CPU time 1.29 seconds
Started Aug 10 06:09:06 PM PDT 24
Finished Aug 10 06:09:08 PM PDT 24
Peak memory 196012 kb
Host smart-527cf516-408b-4147-b868-72fcc1370695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696883581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1696883581
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.960378518
Short name T872
Test name
Test status
Simulation time 512335241483 ps
CPU time 68.09 seconds
Started Aug 10 06:09:03 PM PDT 24
Finished Aug 10 06:10:11 PM PDT 24
Peak memory 209464 kb
Host smart-97cabe86-aed2-41f9-b0e3-e4cc5a303b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960378518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.960378518
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.806028137
Short name T906
Test name
Test status
Simulation time 19435478884 ps
CPU time 796.79 seconds
Started Aug 10 06:09:02 PM PDT 24
Finished Aug 10 06:22:19 PM PDT 24
Peak memory 199908 kb
Host smart-f3277c85-2eba-498d-b31a-dbf100a18f0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=806028137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.806028137
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3003630130
Short name T973
Test name
Test status
Simulation time 2436748162 ps
CPU time 16.73 seconds
Started Aug 10 06:09:02 PM PDT 24
Finished Aug 10 06:09:19 PM PDT 24
Peak memory 199068 kb
Host smart-5d55c34a-a5e3-4fa6-aefc-05f4bb8cfabd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3003630130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3003630130
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.1513326776
Short name T290
Test name
Test status
Simulation time 40281540296 ps
CPU time 12.06 seconds
Started Aug 10 06:09:02 PM PDT 24
Finished Aug 10 06:09:14 PM PDT 24
Peak memory 196172 kb
Host smart-ea5c72d0-db74-4e7d-aea1-3423b941253a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513326776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1513326776
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1804583001
Short name T25
Test name
Test status
Simulation time 32866597 ps
CPU time 0.76 seconds
Started Aug 10 06:09:12 PM PDT 24
Finished Aug 10 06:09:13 PM PDT 24
Peak memory 218396 kb
Host smart-fdb8804a-6790-4c5f-a8e8-a811923b8633
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804583001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1804583001
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.810110850
Short name T743
Test name
Test status
Simulation time 267202375 ps
CPU time 1.48 seconds
Started Aug 10 06:08:54 PM PDT 24
Finished Aug 10 06:08:55 PM PDT 24
Peak memory 199272 kb
Host smart-36d2c9a2-a4a0-4ad3-8d96-d23ee990cb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810110850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.810110850
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.262950991
Short name T1120
Test name
Test status
Simulation time 39942621866 ps
CPU time 59.07 seconds
Started Aug 10 06:09:03 PM PDT 24
Finished Aug 10 06:10:02 PM PDT 24
Peak memory 200008 kb
Host smart-7e38505b-8cdd-4e19-bf70-919f372ac75a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262950991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.262950991
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.1963073454
Short name T499
Test name
Test status
Simulation time 45504758973 ps
CPU time 144.44 seconds
Started Aug 10 06:09:03 PM PDT 24
Finished Aug 10 06:11:27 PM PDT 24
Peak memory 215856 kb
Host smart-3c1e645c-6198-49e8-a78e-0e70faffc34a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963073454 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.1963073454
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.840512888
Short name T853
Test name
Test status
Simulation time 1564309233 ps
CPU time 2.95 seconds
Started Aug 10 06:09:06 PM PDT 24
Finished Aug 10 06:09:09 PM PDT 24
Peak memory 199792 kb
Host smart-8f5cc06b-9de3-45c5-908e-8119a3ed5d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840512888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.840512888
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2518391014
Short name T593
Test name
Test status
Simulation time 127300087135 ps
CPU time 63.65 seconds
Started Aug 10 06:08:54 PM PDT 24
Finished Aug 10 06:09:57 PM PDT 24
Peak memory 199972 kb
Host smart-5aefc817-d775-48b3-88bf-d1f7375e8312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518391014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2518391014
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.2187181523
Short name T506
Test name
Test status
Simulation time 30610799 ps
CPU time 0.53 seconds
Started Aug 10 06:12:43 PM PDT 24
Finished Aug 10 06:12:44 PM PDT 24
Peak memory 195732 kb
Host smart-42f6747e-35c2-4bbf-b5d8-5ab05380e711
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187181523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2187181523
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.2363812134
Short name T120
Test name
Test status
Simulation time 133282147010 ps
CPU time 99.67 seconds
Started Aug 10 06:12:32 PM PDT 24
Finished Aug 10 06:14:12 PM PDT 24
Peak memory 199752 kb
Host smart-0555baa5-1226-4d60-ad9f-566df98d0f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363812134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2363812134
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1861966661
Short name T1043
Test name
Test status
Simulation time 52992525348 ps
CPU time 37.03 seconds
Started Aug 10 06:12:34 PM PDT 24
Finished Aug 10 06:13:11 PM PDT 24
Peak memory 199884 kb
Host smart-81a29d04-e07a-40d8-81bf-90a7c5566bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861966661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1861966661
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1836908580
Short name T374
Test name
Test status
Simulation time 9520581258 ps
CPU time 13.77 seconds
Started Aug 10 06:12:43 PM PDT 24
Finished Aug 10 06:12:57 PM PDT 24
Peak memory 199932 kb
Host smart-e2c34bba-9975-4836-a15f-922759e5ce38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836908580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1836908580
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.1573697301
Short name T396
Test name
Test status
Simulation time 39998420897 ps
CPU time 15.17 seconds
Started Aug 10 06:12:43 PM PDT 24
Finished Aug 10 06:12:58 PM PDT 24
Peak memory 199876 kb
Host smart-95982356-66a4-40ca-886d-f8de1ff2a00e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573697301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1573697301
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.76247747
Short name T258
Test name
Test status
Simulation time 220839376332 ps
CPU time 161.32 seconds
Started Aug 10 06:12:42 PM PDT 24
Finished Aug 10 06:15:23 PM PDT 24
Peak memory 199804 kb
Host smart-295f5d85-a2d1-4a41-809d-b0d64010a64c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=76247747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.76247747
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3150655131
Short name T970
Test name
Test status
Simulation time 2505654460 ps
CPU time 4.58 seconds
Started Aug 10 06:12:42 PM PDT 24
Finished Aug 10 06:12:46 PM PDT 24
Peak memory 195788 kb
Host smart-75f266f7-4648-40ed-ba64-0ae055244da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150655131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3150655131
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.3891996468
Short name T653
Test name
Test status
Simulation time 39379337568 ps
CPU time 59.14 seconds
Started Aug 10 06:12:42 PM PDT 24
Finished Aug 10 06:13:42 PM PDT 24
Peak memory 200092 kb
Host smart-370e04cc-37f0-4d44-890d-9191f7b5dee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891996468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3891996468
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.3751480689
Short name T742
Test name
Test status
Simulation time 4154291946 ps
CPU time 117.03 seconds
Started Aug 10 06:12:42 PM PDT 24
Finished Aug 10 06:14:40 PM PDT 24
Peak memory 199724 kb
Host smart-ea433e6b-ab20-4632-a8a6-dbce9c714263
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3751480689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.3751480689
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.582690707
Short name T771
Test name
Test status
Simulation time 6907042397 ps
CPU time 16.8 seconds
Started Aug 10 06:12:43 PM PDT 24
Finished Aug 10 06:13:00 PM PDT 24
Peak memory 199376 kb
Host smart-a29569e4-cfb9-4c26-9076-324f2ad479e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=582690707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.582690707
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.165102455
Short name T518
Test name
Test status
Simulation time 10077071669 ps
CPU time 5.11 seconds
Started Aug 10 06:12:42 PM PDT 24
Finished Aug 10 06:12:47 PM PDT 24
Peak memory 199876 kb
Host smart-d54dc8b6-97ee-448e-a0df-9f6473cfa6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165102455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.165102455
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1212566958
Short name T335
Test name
Test status
Simulation time 2641417086 ps
CPU time 2.66 seconds
Started Aug 10 06:12:44 PM PDT 24
Finished Aug 10 06:12:47 PM PDT 24
Peak memory 196020 kb
Host smart-ba06f179-131c-40c1-9d5d-bd1e0e7fcc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212566958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1212566958
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2859143601
Short name T452
Test name
Test status
Simulation time 802117480 ps
CPU time 0.89 seconds
Started Aug 10 06:12:34 PM PDT 24
Finished Aug 10 06:12:35 PM PDT 24
Peak memory 198144 kb
Host smart-3acd0ccb-deeb-46f3-94b4-cce2db9a36e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859143601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2859143601
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.3154579374
Short name T604
Test name
Test status
Simulation time 511053462282 ps
CPU time 128.99 seconds
Started Aug 10 06:12:41 PM PDT 24
Finished Aug 10 06:14:50 PM PDT 24
Peak memory 208316 kb
Host smart-e4445e4c-e6a3-408f-96a0-b58507a98c63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154579374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3154579374
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.792850319
Short name T999
Test name
Test status
Simulation time 40366745670 ps
CPU time 232.77 seconds
Started Aug 10 06:12:42 PM PDT 24
Finished Aug 10 06:16:35 PM PDT 24
Peak memory 215732 kb
Host smart-d5ecbb5a-0604-4841-be8f-9af1fd034995
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792850319 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.792850319
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.4128969713
Short name T931
Test name
Test status
Simulation time 6350222468 ps
CPU time 18.69 seconds
Started Aug 10 06:12:41 PM PDT 24
Finished Aug 10 06:13:00 PM PDT 24
Peak memory 199960 kb
Host smart-5514ccf8-6eb4-40da-9900-210b8ce7d573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128969713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.4128969713
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.1187433313
Short name T885
Test name
Test status
Simulation time 29854412125 ps
CPU time 47.63 seconds
Started Aug 10 06:12:34 PM PDT 24
Finished Aug 10 06:13:22 PM PDT 24
Peak memory 199808 kb
Host smart-78793bb7-bcae-49a0-acf2-55e1d4abf619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187433313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1187433313
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.2884299415
Short name T366
Test name
Test status
Simulation time 18893042 ps
CPU time 0.54 seconds
Started Aug 10 06:12:42 PM PDT 24
Finished Aug 10 06:12:43 PM PDT 24
Peak memory 194608 kb
Host smart-edff95f4-3db6-49bc-a5f1-446b61741801
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884299415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2884299415
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1401856817
Short name T676
Test name
Test status
Simulation time 263941539354 ps
CPU time 60.42 seconds
Started Aug 10 06:12:40 PM PDT 24
Finished Aug 10 06:13:40 PM PDT 24
Peak memory 199948 kb
Host smart-6418e684-6356-4934-ab49-5b47ee47b887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401856817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1401856817
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1924305786
Short name T512
Test name
Test status
Simulation time 134937234760 ps
CPU time 24.1 seconds
Started Aug 10 06:12:45 PM PDT 24
Finished Aug 10 06:13:09 PM PDT 24
Peak memory 199820 kb
Host smart-d9d7e221-5677-4ce7-aea4-1f46b1f79166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924305786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1924305786
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_intr.2791662154
Short name T49
Test name
Test status
Simulation time 183392058242 ps
CPU time 222.83 seconds
Started Aug 10 06:12:41 PM PDT 24
Finished Aug 10 06:16:24 PM PDT 24
Peak memory 199944 kb
Host smart-7f032f63-79d6-45c2-85a1-bde25b6d4f9d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791662154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2791662154
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.3279545131
Short name T425
Test name
Test status
Simulation time 84681286893 ps
CPU time 428.74 seconds
Started Aug 10 06:12:45 PM PDT 24
Finished Aug 10 06:19:53 PM PDT 24
Peak memory 199844 kb
Host smart-e967fd67-bf79-4d7c-bd73-f591ec9111b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3279545131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3279545131
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2624621085
Short name T431
Test name
Test status
Simulation time 1124653208 ps
CPU time 1.46 seconds
Started Aug 10 06:12:42 PM PDT 24
Finished Aug 10 06:12:44 PM PDT 24
Peak memory 198524 kb
Host smart-635a6e2e-2fb0-49d9-ac44-e7f44d08addc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624621085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2624621085
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3871580207
Short name T330
Test name
Test status
Simulation time 21561052949 ps
CPU time 18.1 seconds
Started Aug 10 06:12:43 PM PDT 24
Finished Aug 10 06:13:02 PM PDT 24
Peak memory 198836 kb
Host smart-b2a2b867-e1b1-4b74-9d02-ae7a58576189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871580207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3871580207
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.2099243456
Short name T956
Test name
Test status
Simulation time 15210609963 ps
CPU time 40.75 seconds
Started Aug 10 06:12:44 PM PDT 24
Finished Aug 10 06:13:25 PM PDT 24
Peak memory 199928 kb
Host smart-484b8cf7-6821-4db1-b91f-bcc0bb58275d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2099243456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2099243456
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.3448664868
Short name T695
Test name
Test status
Simulation time 3628047781 ps
CPU time 6.64 seconds
Started Aug 10 06:12:42 PM PDT 24
Finished Aug 10 06:12:49 PM PDT 24
Peak memory 199108 kb
Host smart-affa3589-02b5-4041-a84c-f3d1a30612fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3448664868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3448664868
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.2646964258
Short name T924
Test name
Test status
Simulation time 73026553097 ps
CPU time 58.81 seconds
Started Aug 10 06:12:43 PM PDT 24
Finished Aug 10 06:13:42 PM PDT 24
Peak memory 199852 kb
Host smart-069d8a7f-a119-4282-85c8-000cdbbfaa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646964258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.2646964258
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2939631318
Short name T470
Test name
Test status
Simulation time 31720253385 ps
CPU time 44.54 seconds
Started Aug 10 06:12:43 PM PDT 24
Finished Aug 10 06:13:28 PM PDT 24
Peak memory 195836 kb
Host smart-5270e396-f7b8-4881-9cbb-c941b18e63bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939631318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2939631318
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1564154058
Short name T1000
Test name
Test status
Simulation time 474720072 ps
CPU time 1.54 seconds
Started Aug 10 06:12:42 PM PDT 24
Finished Aug 10 06:12:43 PM PDT 24
Peak memory 198196 kb
Host smart-5debffa4-b5ad-4c94-bf0f-d6ec384b1822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564154058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1564154058
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.2108293401
Short name T952
Test name
Test status
Simulation time 287226385474 ps
CPU time 88.02 seconds
Started Aug 10 06:12:42 PM PDT 24
Finished Aug 10 06:14:11 PM PDT 24
Peak memory 199976 kb
Host smart-9e7693cd-8988-47d9-972a-26c92c2b85bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108293401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2108293401
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.560818898
Short name T27
Test name
Test status
Simulation time 10562274858 ps
CPU time 147.84 seconds
Started Aug 10 06:12:43 PM PDT 24
Finished Aug 10 06:15:11 PM PDT 24
Peak memory 208276 kb
Host smart-496854aa-d583-47bc-a1a5-dc8d90aed85d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560818898 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.560818898
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1829432563
Short name T740
Test name
Test status
Simulation time 6228914400 ps
CPU time 18.33 seconds
Started Aug 10 06:12:43 PM PDT 24
Finished Aug 10 06:13:01 PM PDT 24
Peak memory 199776 kb
Host smart-21df7f43-b495-42c5-9f81-c6b36a51232c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829432563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1829432563
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.850093138
Short name T633
Test name
Test status
Simulation time 37828500123 ps
CPU time 16.87 seconds
Started Aug 10 06:12:43 PM PDT 24
Finished Aug 10 06:13:00 PM PDT 24
Peak memory 199916 kb
Host smart-415d371d-7c11-495a-8dce-97c0a5f41c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850093138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.850093138
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.3459623651
Short name T449
Test name
Test status
Simulation time 31656480 ps
CPU time 0.53 seconds
Started Aug 10 06:12:49 PM PDT 24
Finished Aug 10 06:12:49 PM PDT 24
Peak memory 194324 kb
Host smart-d329e6a1-ce0f-40e0-8f3e-a6bf0b9aa8a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459623651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.3459623651
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.4216165078
Short name T486
Test name
Test status
Simulation time 46532615084 ps
CPU time 22.74 seconds
Started Aug 10 06:12:51 PM PDT 24
Finished Aug 10 06:13:14 PM PDT 24
Peak memory 199532 kb
Host smart-0a79b209-f334-4d16-b098-9885a028e862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216165078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.4216165078
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2874664292
Short name T971
Test name
Test status
Simulation time 30269972652 ps
CPU time 49.01 seconds
Started Aug 10 06:12:52 PM PDT 24
Finished Aug 10 06:13:41 PM PDT 24
Peak memory 199640 kb
Host smart-4f566c9c-1dfa-404f-a9a5-a2f9567376fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874664292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2874664292
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.2289469324
Short name T733
Test name
Test status
Simulation time 145149370954 ps
CPU time 51.2 seconds
Started Aug 10 06:12:50 PM PDT 24
Finished Aug 10 06:13:42 PM PDT 24
Peak memory 199712 kb
Host smart-81397647-ec8a-4839-9d49-91d07e19d244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289469324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2289469324
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1420147736
Short name T122
Test name
Test status
Simulation time 4049173060 ps
CPU time 6.51 seconds
Started Aug 10 06:12:50 PM PDT 24
Finished Aug 10 06:12:56 PM PDT 24
Peak memory 195900 kb
Host smart-3cb216d6-6dc3-4867-b997-65d47a4e55b5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420147736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1420147736
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.3148155170
Short name T652
Test name
Test status
Simulation time 237583752780 ps
CPU time 341.21 seconds
Started Aug 10 06:12:52 PM PDT 24
Finished Aug 10 06:18:33 PM PDT 24
Peak memory 199984 kb
Host smart-8c4b8622-9591-4e7f-a49b-986e98097d09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3148155170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3148155170
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1640862392
Short name T46
Test name
Test status
Simulation time 7991867876 ps
CPU time 11.65 seconds
Started Aug 10 06:12:50 PM PDT 24
Finished Aug 10 06:13:02 PM PDT 24
Peak memory 199868 kb
Host smart-ae00106e-362a-490e-af7f-8ab0a53e3d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640862392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1640862392
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1889886290
Short name T666
Test name
Test status
Simulation time 56768831043 ps
CPU time 26.8 seconds
Started Aug 10 06:12:50 PM PDT 24
Finished Aug 10 06:13:17 PM PDT 24
Peak memory 200040 kb
Host smart-c756c95f-5371-4508-9a54-bc3ef9b3a2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889886290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1889886290
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2913698294
Short name T726
Test name
Test status
Simulation time 4399368633 ps
CPU time 63.57 seconds
Started Aug 10 06:12:50 PM PDT 24
Finished Aug 10 06:13:53 PM PDT 24
Peak memory 199896 kb
Host smart-b8a6163b-bc87-4558-982d-0b829d89ab49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2913698294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2913698294
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.1984016125
Short name T678
Test name
Test status
Simulation time 3047700229 ps
CPU time 25.19 seconds
Started Aug 10 06:12:50 PM PDT 24
Finished Aug 10 06:13:15 PM PDT 24
Peak memory 199024 kb
Host smart-57a77944-5aa0-47b1-9cb1-637cbd6003d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1984016125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1984016125
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1753103085
Short name T590
Test name
Test status
Simulation time 204891824132 ps
CPU time 314.32 seconds
Started Aug 10 06:12:51 PM PDT 24
Finished Aug 10 06:18:06 PM PDT 24
Peak memory 199892 kb
Host smart-28b98414-d131-4417-b196-e19390f3eb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753103085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1753103085
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3942703906
Short name T701
Test name
Test status
Simulation time 6776439354 ps
CPU time 9.77 seconds
Started Aug 10 06:12:49 PM PDT 24
Finished Aug 10 06:12:59 PM PDT 24
Peak memory 196028 kb
Host smart-884f2a08-8d5f-419d-bca3-c25bd72abd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942703906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3942703906
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.1000369740
Short name T497
Test name
Test status
Simulation time 5364654342 ps
CPU time 33.42 seconds
Started Aug 10 06:12:49 PM PDT 24
Finished Aug 10 06:13:22 PM PDT 24
Peak memory 199956 kb
Host smart-ae1ca5fa-f0d6-47c1-9ab6-4eed250175bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000369740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1000369740
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.511564938
Short name T691
Test name
Test status
Simulation time 340611395876 ps
CPU time 1185.57 seconds
Started Aug 10 06:12:51 PM PDT 24
Finished Aug 10 06:32:37 PM PDT 24
Peak memory 199948 kb
Host smart-75d6cef5-74ac-4e4a-8598-7d0cdf0f17f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511564938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.511564938
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.575856926
Short name T625
Test name
Test status
Simulation time 28050157511 ps
CPU time 354.26 seconds
Started Aug 10 06:12:52 PM PDT 24
Finished Aug 10 06:18:46 PM PDT 24
Peak memory 216584 kb
Host smart-7e84956c-d94c-4d75-90f9-f19851ec1466
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575856926 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.575856926
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2249178022
Short name T1108
Test name
Test status
Simulation time 6287278313 ps
CPU time 14.76 seconds
Started Aug 10 06:12:51 PM PDT 24
Finished Aug 10 06:13:06 PM PDT 24
Peak memory 199892 kb
Host smart-2c34224c-b22b-4a30-ace1-80bfc144831e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249178022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2249178022
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3513059716
Short name T465
Test name
Test status
Simulation time 40591459397 ps
CPU time 32.41 seconds
Started Aug 10 06:12:52 PM PDT 24
Finished Aug 10 06:13:25 PM PDT 24
Peak memory 199860 kb
Host smart-565c9853-feea-4abe-a2e6-cf7450f6b1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513059716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3513059716
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.1776401508
Short name T441
Test name
Test status
Simulation time 37570170 ps
CPU time 0.57 seconds
Started Aug 10 06:12:59 PM PDT 24
Finished Aug 10 06:13:00 PM PDT 24
Peak memory 195220 kb
Host smart-3fb5a4c0-a87d-4b45-abb4-26f9d06fb11b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776401508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1776401508
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2103636018
Short name T278
Test name
Test status
Simulation time 43538580867 ps
CPU time 73.51 seconds
Started Aug 10 06:13:00 PM PDT 24
Finished Aug 10 06:14:14 PM PDT 24
Peak memory 199972 kb
Host smart-0945dd7f-f65c-4d6a-a674-af4648ccf283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103636018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2103636018
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.4142943969
Short name T1150
Test name
Test status
Simulation time 174307801772 ps
CPU time 76.64 seconds
Started Aug 10 06:13:00 PM PDT 24
Finished Aug 10 06:14:17 PM PDT 24
Peak memory 199996 kb
Host smart-aae1eee0-0a42-42b8-830a-8d3ba939c879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142943969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.4142943969
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_intr.3860846188
Short name T744
Test name
Test status
Simulation time 50650164316 ps
CPU time 84 seconds
Started Aug 10 06:13:00 PM PDT 24
Finished Aug 10 06:14:25 PM PDT 24
Peak memory 199840 kb
Host smart-43398c5e-724d-4c20-9adc-ba4694ff8985
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860846188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3860846188
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.768724429
Short name T1121
Test name
Test status
Simulation time 106289742825 ps
CPU time 705.43 seconds
Started Aug 10 06:13:00 PM PDT 24
Finished Aug 10 06:24:46 PM PDT 24
Peak memory 199964 kb
Host smart-93bd42d2-1076-4754-ac4b-57c567fa28c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=768724429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.768724429
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.1036200429
Short name T1090
Test name
Test status
Simulation time 4763210562 ps
CPU time 5.52 seconds
Started Aug 10 06:13:01 PM PDT 24
Finished Aug 10 06:13:06 PM PDT 24
Peak memory 199844 kb
Host smart-c06c0d91-f64f-4b38-9ded-64f33c82aa3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036200429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1036200429
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.2100601885
Short name T405
Test name
Test status
Simulation time 58147862265 ps
CPU time 26.04 seconds
Started Aug 10 06:12:58 PM PDT 24
Finished Aug 10 06:13:24 PM PDT 24
Peak memory 199604 kb
Host smart-6a16580b-2861-4699-a9a5-dc5674482739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100601885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2100601885
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2551167349
Short name T493
Test name
Test status
Simulation time 10852774981 ps
CPU time 644.15 seconds
Started Aug 10 06:12:59 PM PDT 24
Finished Aug 10 06:23:43 PM PDT 24
Peak memory 199804 kb
Host smart-4f23797f-3dbd-442f-895b-c3b2ce5c1945
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2551167349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2551167349
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.1605130049
Short name T818
Test name
Test status
Simulation time 1792664868 ps
CPU time 4.36 seconds
Started Aug 10 06:13:01 PM PDT 24
Finished Aug 10 06:13:05 PM PDT 24
Peak memory 197708 kb
Host smart-424a0928-ff30-44e4-ac3b-b8e3168c446e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1605130049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1605130049
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.740373670
Short name T533
Test name
Test status
Simulation time 23955309963 ps
CPU time 40.29 seconds
Started Aug 10 06:13:01 PM PDT 24
Finished Aug 10 06:13:41 PM PDT 24
Peak memory 199920 kb
Host smart-c6507034-4004-47c1-93ee-87216d60175c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740373670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.740373670
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.2370948656
Short name T949
Test name
Test status
Simulation time 34593124506 ps
CPU time 8.21 seconds
Started Aug 10 06:13:00 PM PDT 24
Finished Aug 10 06:13:09 PM PDT 24
Peak memory 195852 kb
Host smart-232fd983-b355-4a84-84c0-f69702241b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370948656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2370948656
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3183037060
Short name T541
Test name
Test status
Simulation time 332319065 ps
CPU time 1.03 seconds
Started Aug 10 06:12:51 PM PDT 24
Finished Aug 10 06:12:52 PM PDT 24
Peak memory 199272 kb
Host smart-e27445b0-606b-4f6a-86d1-804e4d41ffb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183037060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3183037060
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.2284536970
Short name T919
Test name
Test status
Simulation time 375114997369 ps
CPU time 154.34 seconds
Started Aug 10 06:13:00 PM PDT 24
Finished Aug 10 06:15:34 PM PDT 24
Peak memory 200000 kb
Host smart-e117cc7a-514b-4683-956b-76ee2ce824a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284536970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2284536970
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.626553006
Short name T1044
Test name
Test status
Simulation time 305391826868 ps
CPU time 758.68 seconds
Started Aug 10 06:12:59 PM PDT 24
Finished Aug 10 06:25:38 PM PDT 24
Peak memory 224776 kb
Host smart-165c3c8c-d622-43e1-9a49-a700c7bbc1e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626553006 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.626553006
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2437164536
Short name T608
Test name
Test status
Simulation time 2710076890 ps
CPU time 1.93 seconds
Started Aug 10 06:12:58 PM PDT 24
Finished Aug 10 06:13:01 PM PDT 24
Peak memory 198756 kb
Host smart-0849f79c-8565-48ab-8376-2f837d1c739e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437164536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2437164536
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1894266248
Short name T745
Test name
Test status
Simulation time 38314354012 ps
CPU time 34.14 seconds
Started Aug 10 06:12:58 PM PDT 24
Finished Aug 10 06:13:32 PM PDT 24
Peak memory 199972 kb
Host smart-5d98ccbf-6b27-427f-8a88-2d734728c5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894266248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1894266248
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1998123818
Short name T1059
Test name
Test status
Simulation time 32797924 ps
CPU time 0.54 seconds
Started Aug 10 06:13:10 PM PDT 24
Finished Aug 10 06:13:11 PM PDT 24
Peak memory 195636 kb
Host smart-51e94e63-4f85-4d47-8d91-67d5ea5baa45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998123818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1998123818
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1844637300
Short name T589
Test name
Test status
Simulation time 96373845362 ps
CPU time 75.56 seconds
Started Aug 10 06:13:00 PM PDT 24
Finished Aug 10 06:14:16 PM PDT 24
Peak memory 199964 kb
Host smart-3ba32ba3-5573-457c-b3bb-44b7c4604ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844637300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1844637300
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3278868298
Short name T169
Test name
Test status
Simulation time 85514809871 ps
CPU time 19.03 seconds
Started Aug 10 06:12:59 PM PDT 24
Finished Aug 10 06:13:18 PM PDT 24
Peak memory 199908 kb
Host smart-f02b86b1-cec6-4d36-96bc-d9b91692471f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278868298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3278868298
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.3521716205
Short name T1139
Test name
Test status
Simulation time 28972221676 ps
CPU time 39.84 seconds
Started Aug 10 06:12:59 PM PDT 24
Finished Aug 10 06:13:39 PM PDT 24
Peak memory 199856 kb
Host smart-f4715232-885c-47d3-8d85-8480294933a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521716205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3521716205
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.2077545249
Short name T1088
Test name
Test status
Simulation time 294634675537 ps
CPU time 119.47 seconds
Started Aug 10 06:13:00 PM PDT 24
Finished Aug 10 06:15:00 PM PDT 24
Peak memory 199876 kb
Host smart-f4011d31-758f-4598-bb77-e0fd53f4d52a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077545249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.2077545249
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3444466759
Short name T995
Test name
Test status
Simulation time 147360086185 ps
CPU time 323.49 seconds
Started Aug 10 06:13:09 PM PDT 24
Finished Aug 10 06:18:32 PM PDT 24
Peak memory 199868 kb
Host smart-9359832e-d708-4bf3-9604-a338dde63d3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3444466759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3444466759
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.1722631279
Short name T883
Test name
Test status
Simulation time 56359316 ps
CPU time 0.73 seconds
Started Aug 10 06:13:07 PM PDT 24
Finished Aug 10 06:13:08 PM PDT 24
Peak memory 195792 kb
Host smart-7539a922-c59b-418a-9f37-0f69c3bf9ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722631279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1722631279
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.3490635841
Short name T450
Test name
Test status
Simulation time 37824202959 ps
CPU time 55.47 seconds
Started Aug 10 06:12:59 PM PDT 24
Finished Aug 10 06:13:55 PM PDT 24
Peak memory 198568 kb
Host smart-a573f3c1-8eec-4fff-a828-8b34da09f593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490635841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3490635841
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.627713713
Short name T6
Test name
Test status
Simulation time 1403789367 ps
CPU time 60.62 seconds
Started Aug 10 06:13:10 PM PDT 24
Finished Aug 10 06:14:10 PM PDT 24
Peak memory 199896 kb
Host smart-f26be204-46da-4f3d-a11d-4482e7929026
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=627713713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.627713713
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.434554328
Short name T591
Test name
Test status
Simulation time 6411793920 ps
CPU time 12.73 seconds
Started Aug 10 06:13:01 PM PDT 24
Finished Aug 10 06:13:14 PM PDT 24
Peak memory 199284 kb
Host smart-cf047d69-ebf3-4771-855f-a7103f94f121
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=434554328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.434554328
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.2010062671
Short name T161
Test name
Test status
Simulation time 72982834308 ps
CPU time 81.52 seconds
Started Aug 10 06:13:10 PM PDT 24
Finished Aug 10 06:14:32 PM PDT 24
Peak memory 199916 kb
Host smart-1bb25963-a2f6-434c-9676-dcabfa1f6a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010062671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2010062671
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.194082753
Short name T426
Test name
Test status
Simulation time 44152021537 ps
CPU time 32.32 seconds
Started Aug 10 06:13:01 PM PDT 24
Finished Aug 10 06:13:34 PM PDT 24
Peak memory 196460 kb
Host smart-8768e17d-813b-43de-8d6b-fcddc3062413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194082753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.194082753
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.1574960016
Short name T948
Test name
Test status
Simulation time 713494257 ps
CPU time 2.69 seconds
Started Aug 10 06:12:59 PM PDT 24
Finished Aug 10 06:13:02 PM PDT 24
Peak memory 198684 kb
Host smart-25c0ea2a-6253-454f-95ef-485a187387aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574960016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1574960016
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.850060318
Short name T801
Test name
Test status
Simulation time 61482431280 ps
CPU time 896.26 seconds
Started Aug 10 06:13:07 PM PDT 24
Finished Aug 10 06:28:03 PM PDT 24
Peak memory 224836 kb
Host smart-d3a562d5-4612-4d37-9284-fd8ab4c01f49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850060318 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.850060318
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1114606152
Short name T953
Test name
Test status
Simulation time 1290077959 ps
CPU time 2.65 seconds
Started Aug 10 06:13:09 PM PDT 24
Finished Aug 10 06:13:12 PM PDT 24
Peak memory 198408 kb
Host smart-ddda0f12-bf07-4ac1-ba4f-55bd2ddb14af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114606152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1114606152
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3742764525
Short name T274
Test name
Test status
Simulation time 36107815733 ps
CPU time 12.83 seconds
Started Aug 10 06:12:57 PM PDT 24
Finished Aug 10 06:13:09 PM PDT 24
Peak memory 199924 kb
Host smart-4d408ab1-9d07-4fbf-bc50-77f3d2d69296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742764525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3742764525
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3816149663
Short name T386
Test name
Test status
Simulation time 35842698 ps
CPU time 0.56 seconds
Started Aug 10 06:13:16 PM PDT 24
Finished Aug 10 06:13:16 PM PDT 24
Peak memory 194604 kb
Host smart-07ca588f-9a4e-4713-8c1f-f79abd1822fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816149663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3816149663
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.556883902
Short name T566
Test name
Test status
Simulation time 151759540417 ps
CPU time 433.23 seconds
Started Aug 10 06:13:09 PM PDT 24
Finished Aug 10 06:20:22 PM PDT 24
Peak memory 199940 kb
Host smart-66f5caf7-d787-470c-949b-c0cf3fbb5f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556883902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.556883902
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1913655902
Short name T623
Test name
Test status
Simulation time 23070047025 ps
CPU time 24.7 seconds
Started Aug 10 06:13:10 PM PDT 24
Finished Aug 10 06:13:34 PM PDT 24
Peak memory 199800 kb
Host smart-3a37310d-39a2-4d8e-b582-9b7a7770e3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913655902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1913655902
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2353381673
Short name T583
Test name
Test status
Simulation time 295095599647 ps
CPU time 54.43 seconds
Started Aug 10 06:13:08 PM PDT 24
Finished Aug 10 06:14:03 PM PDT 24
Peak memory 199960 kb
Host smart-80edfb31-faa1-427f-b1aa-aac178dc906c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353381673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2353381673
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.2296849266
Short name T845
Test name
Test status
Simulation time 52278297112 ps
CPU time 15.09 seconds
Started Aug 10 06:13:09 PM PDT 24
Finished Aug 10 06:13:24 PM PDT 24
Peak memory 199896 kb
Host smart-e88e9175-e5ff-4dfa-9f70-f2010e3b8fb3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296849266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2296849266
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.4123359816
Short name T838
Test name
Test status
Simulation time 92410653338 ps
CPU time 241.04 seconds
Started Aug 10 06:13:09 PM PDT 24
Finished Aug 10 06:17:10 PM PDT 24
Peak memory 200004 kb
Host smart-5a8320d8-d55a-4641-a372-99341267764b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4123359816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.4123359816
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3380860695
Short name T556
Test name
Test status
Simulation time 757065845 ps
CPU time 1.95 seconds
Started Aug 10 06:13:07 PM PDT 24
Finished Aug 10 06:13:09 PM PDT 24
Peak memory 195648 kb
Host smart-b910fe46-454a-471f-8f97-8bc7108f1d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380860695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3380860695
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.441778995
Short name T511
Test name
Test status
Simulation time 55369760101 ps
CPU time 21.62 seconds
Started Aug 10 06:13:08 PM PDT 24
Finished Aug 10 06:13:29 PM PDT 24
Peak memory 200112 kb
Host smart-64a7b14a-9467-4c8c-b49f-029213f3e96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441778995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.441778995
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.3154794566
Short name T302
Test name
Test status
Simulation time 20770641760 ps
CPU time 254.4 seconds
Started Aug 10 06:13:09 PM PDT 24
Finished Aug 10 06:17:23 PM PDT 24
Peak memory 199968 kb
Host smart-d4137730-d3db-4ea0-bfc1-efda5aaca118
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3154794566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3154794566
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3703511253
Short name T914
Test name
Test status
Simulation time 5040933319 ps
CPU time 39.9 seconds
Started Aug 10 06:13:10 PM PDT 24
Finished Aug 10 06:13:50 PM PDT 24
Peak memory 198836 kb
Host smart-1433fc67-9048-417b-bbee-6fcd0fd18780
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3703511253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3703511253
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.3403829387
Short name T456
Test name
Test status
Simulation time 14392361700 ps
CPU time 23.36 seconds
Started Aug 10 06:13:10 PM PDT 24
Finished Aug 10 06:13:34 PM PDT 24
Peak memory 199976 kb
Host smart-39682420-3a65-4d87-85d0-a6984f4fa3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403829387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3403829387
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.102254974
Short name T9
Test name
Test status
Simulation time 51163205730 ps
CPU time 19.67 seconds
Started Aug 10 06:13:08 PM PDT 24
Finished Aug 10 06:13:28 PM PDT 24
Peak memory 196024 kb
Host smart-8ba56fc3-33a9-4832-a458-9a8ea8ee08c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102254974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.102254974
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1092067613
Short name T843
Test name
Test status
Simulation time 139568300 ps
CPU time 0.76 seconds
Started Aug 10 06:13:08 PM PDT 24
Finished Aug 10 06:13:09 PM PDT 24
Peak memory 197212 kb
Host smart-2a292c46-c37b-4256-8aaa-26688a42887e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092067613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1092067613
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.453159141
Short name T117
Test name
Test status
Simulation time 388275044779 ps
CPU time 677.48 seconds
Started Aug 10 06:13:10 PM PDT 24
Finished Aug 10 06:24:28 PM PDT 24
Peak memory 200104 kb
Host smart-d6b5d64a-75ef-4458-9b72-9af2fdd09e50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453159141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.453159141
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2121598397
Short name T341
Test name
Test status
Simulation time 18641423896 ps
CPU time 339.95 seconds
Started Aug 10 06:13:09 PM PDT 24
Finished Aug 10 06:18:49 PM PDT 24
Peak memory 216632 kb
Host smart-69961e0e-3940-4afb-be62-7cb30f44d69f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121598397 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2121598397
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.1986210297
Short name T647
Test name
Test status
Simulation time 4942261799 ps
CPU time 2.4 seconds
Started Aug 10 06:13:09 PM PDT 24
Finished Aug 10 06:13:11 PM PDT 24
Peak memory 199640 kb
Host smart-d66d1bf4-5381-466a-a044-bcb33794e3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986210297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.1986210297
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1636150264
Short name T923
Test name
Test status
Simulation time 39069329498 ps
CPU time 61.65 seconds
Started Aug 10 06:13:08 PM PDT 24
Finished Aug 10 06:14:09 PM PDT 24
Peak memory 199868 kb
Host smart-853e4ba8-4239-4207-9a1c-b0b95a54c165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636150264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1636150264
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.16773355
Short name T1019
Test name
Test status
Simulation time 23461018 ps
CPU time 0.53 seconds
Started Aug 10 06:13:15 PM PDT 24
Finished Aug 10 06:13:15 PM PDT 24
Peak memory 194280 kb
Host smart-836bbfc5-5603-46ef-9f6a-8354744ee02b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16773355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.16773355
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.934257043
Short name T679
Test name
Test status
Simulation time 49447299633 ps
CPU time 19.98 seconds
Started Aug 10 06:13:17 PM PDT 24
Finished Aug 10 06:13:37 PM PDT 24
Peak memory 199840 kb
Host smart-b7e3e101-f5b5-4029-a8fe-9585c92722c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934257043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.934257043
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3099091815
Short name T799
Test name
Test status
Simulation time 93897781361 ps
CPU time 46.98 seconds
Started Aug 10 06:13:16 PM PDT 24
Finished Aug 10 06:14:03 PM PDT 24
Peak memory 199964 kb
Host smart-98647369-9b8d-4287-9aff-21d3afe84251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099091815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3099091815
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.2617172236
Short name T467
Test name
Test status
Simulation time 188502293899 ps
CPU time 82.61 seconds
Started Aug 10 06:13:16 PM PDT 24
Finished Aug 10 06:14:39 PM PDT 24
Peak memory 199976 kb
Host smart-5b6f0447-bb34-43bb-85f1-0ca8eee6e911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617172236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2617172236
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3081976067
Short name T673
Test name
Test status
Simulation time 13762495226 ps
CPU time 9.44 seconds
Started Aug 10 06:13:16 PM PDT 24
Finished Aug 10 06:13:26 PM PDT 24
Peak memory 196844 kb
Host smart-9a18be4d-8615-495e-8aa6-9431e00ad4db
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081976067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3081976067
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1446279946
Short name T994
Test name
Test status
Simulation time 202996758300 ps
CPU time 95.99 seconds
Started Aug 10 06:13:15 PM PDT 24
Finished Aug 10 06:14:51 PM PDT 24
Peak memory 199868 kb
Host smart-85551ff0-5429-44fe-ad35-5d11b46591a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1446279946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1446279946
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1342748465
Short name T560
Test name
Test status
Simulation time 8007650458 ps
CPU time 8.65 seconds
Started Aug 10 06:13:15 PM PDT 24
Finished Aug 10 06:13:24 PM PDT 24
Peak memory 199916 kb
Host smart-5645148c-efbd-4921-85ba-fe68fe5ccb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342748465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1342748465
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.4244011496
Short name T821
Test name
Test status
Simulation time 23002431575 ps
CPU time 8.68 seconds
Started Aug 10 06:13:15 PM PDT 24
Finished Aug 10 06:13:24 PM PDT 24
Peak memory 198172 kb
Host smart-8fe27376-4c6f-4253-b9e5-a05fefcd917a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244011496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.4244011496
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.682373249
Short name T668
Test name
Test status
Simulation time 19466671836 ps
CPU time 536.28 seconds
Started Aug 10 06:13:15 PM PDT 24
Finished Aug 10 06:22:11 PM PDT 24
Peak memory 199892 kb
Host smart-93d0b6cb-dae4-49f4-8a93-1a413040b5b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=682373249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.682373249
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3756677832
Short name T364
Test name
Test status
Simulation time 3838015865 ps
CPU time 30.23 seconds
Started Aug 10 06:13:18 PM PDT 24
Finished Aug 10 06:13:48 PM PDT 24
Peak memory 197824 kb
Host smart-211bbf2c-a2a8-47e9-a916-d87c999ebaa3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3756677832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3756677832
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2260193232
Short name T1039
Test name
Test status
Simulation time 115954889249 ps
CPU time 165.86 seconds
Started Aug 10 06:13:17 PM PDT 24
Finished Aug 10 06:16:03 PM PDT 24
Peak memory 199752 kb
Host smart-bb3de2cd-8264-49c8-84c9-ab6eef28187f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260193232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2260193232
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.4159592878
Short name T977
Test name
Test status
Simulation time 40689548725 ps
CPU time 6.12 seconds
Started Aug 10 06:13:15 PM PDT 24
Finished Aug 10 06:13:21 PM PDT 24
Peak memory 195812 kb
Host smart-f56c7239-763d-4168-83e4-0bb9e9298287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159592878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.4159592878
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3167302120
Short name T1008
Test name
Test status
Simulation time 5449927292 ps
CPU time 12.78 seconds
Started Aug 10 06:13:15 PM PDT 24
Finished Aug 10 06:13:28 PM PDT 24
Peak memory 199096 kb
Host smart-478e82f1-fadb-4706-a19c-bf55b4fd654d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167302120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3167302120
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.4210341712
Short name T502
Test name
Test status
Simulation time 80915160292 ps
CPU time 117.92 seconds
Started Aug 10 06:13:17 PM PDT 24
Finished Aug 10 06:15:15 PM PDT 24
Peak memory 199924 kb
Host smart-d4f3fc5c-342d-4f1a-9611-368fc46a4217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210341712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.4210341712
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3297728108
Short name T321
Test name
Test status
Simulation time 1423777379 ps
CPU time 4.39 seconds
Started Aug 10 06:13:16 PM PDT 24
Finished Aug 10 06:13:20 PM PDT 24
Peak memory 199628 kb
Host smart-1b5cf4ff-4840-4e52-a49e-f04c061d1a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297728108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3297728108
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_alert_test.1173038345
Short name T22
Test name
Test status
Simulation time 13234846 ps
CPU time 0.55 seconds
Started Aug 10 06:13:23 PM PDT 24
Finished Aug 10 06:13:24 PM PDT 24
Peak memory 195364 kb
Host smart-ebc9136b-e77b-4fbd-81d3-bdabe00b1732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173038345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1173038345
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.21188297
Short name T622
Test name
Test status
Simulation time 42759044201 ps
CPU time 36.52 seconds
Started Aug 10 06:13:24 PM PDT 24
Finished Aug 10 06:14:01 PM PDT 24
Peak memory 199904 kb
Host smart-61323ae2-3599-49e5-8baa-ce827737a6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21188297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.21188297
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.365292247
Short name T391
Test name
Test status
Simulation time 43071689450 ps
CPU time 15.11 seconds
Started Aug 10 06:13:24 PM PDT 24
Finished Aug 10 06:13:39 PM PDT 24
Peak memory 199912 kb
Host smart-0c68d5b0-81c0-476a-b24e-9fe4ea5da41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365292247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.365292247
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1748841499
Short name T1135
Test name
Test status
Simulation time 129655552659 ps
CPU time 178.41 seconds
Started Aug 10 06:13:23 PM PDT 24
Finished Aug 10 06:16:21 PM PDT 24
Peak memory 199996 kb
Host smart-354bfd8a-1cb1-4ec6-8e44-95ea3cb5462f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748841499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1748841499
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.3871478406
Short name T309
Test name
Test status
Simulation time 31768098831 ps
CPU time 15.16 seconds
Started Aug 10 06:13:23 PM PDT 24
Finished Aug 10 06:13:38 PM PDT 24
Peak memory 199720 kb
Host smart-a6045c8b-ea68-454c-b902-1d8a42373c7c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871478406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.3871478406
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2472872432
Short name T1132
Test name
Test status
Simulation time 108158047925 ps
CPU time 262.74 seconds
Started Aug 10 06:13:27 PM PDT 24
Finished Aug 10 06:17:50 PM PDT 24
Peak memory 199844 kb
Host smart-8d326eae-e66e-4ade-83dd-81741c429bcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2472872432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2472872432
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2746799759
Short name T684
Test name
Test status
Simulation time 1449165100 ps
CPU time 3.1 seconds
Started Aug 10 06:13:24 PM PDT 24
Finished Aug 10 06:13:27 PM PDT 24
Peak memory 197540 kb
Host smart-c0ecb1b0-5d95-4f65-b276-1f156b4d63aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746799759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2746799759
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.3189244007
Short name T638
Test name
Test status
Simulation time 208344547081 ps
CPU time 129.38 seconds
Started Aug 10 06:13:23 PM PDT 24
Finished Aug 10 06:15:33 PM PDT 24
Peak memory 200068 kb
Host smart-c600c078-4014-4585-b36f-11524d8e2997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189244007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3189244007
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.1433204034
Short name T649
Test name
Test status
Simulation time 2809703017 ps
CPU time 36.86 seconds
Started Aug 10 06:13:24 PM PDT 24
Finished Aug 10 06:14:01 PM PDT 24
Peak memory 199932 kb
Host smart-badbcf39-1a44-4fa3-8367-fd3b2e6c9a3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1433204034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1433204034
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.1590857062
Short name T879
Test name
Test status
Simulation time 2882570883 ps
CPU time 6.13 seconds
Started Aug 10 06:13:27 PM PDT 24
Finished Aug 10 06:13:33 PM PDT 24
Peak memory 198064 kb
Host smart-34d11027-8d12-4065-8f2a-72713a4b6a2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1590857062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.1590857062
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3607326884
Short name T82
Test name
Test status
Simulation time 43599664825 ps
CPU time 32.85 seconds
Started Aug 10 06:13:23 PM PDT 24
Finished Aug 10 06:13:56 PM PDT 24
Peak memory 199612 kb
Host smart-1f26b1d7-d6f8-4e45-946e-354d2d22cdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607326884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3607326884
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3199715602
Short name T624
Test name
Test status
Simulation time 4517313718 ps
CPU time 2.49 seconds
Started Aug 10 06:13:24 PM PDT 24
Finished Aug 10 06:13:26 PM PDT 24
Peak memory 196264 kb
Host smart-141fc55e-ee31-4124-9353-4d2b58459177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199715602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3199715602
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1467627444
Short name T1129
Test name
Test status
Simulation time 629072980 ps
CPU time 0.8 seconds
Started Aug 10 06:13:16 PM PDT 24
Finished Aug 10 06:13:17 PM PDT 24
Peak memory 197708 kb
Host smart-f212053e-2f89-44b3-bc20-34486cccf5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467627444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1467627444
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2738099241
Short name T61
Test name
Test status
Simulation time 30317145239 ps
CPU time 94.57 seconds
Started Aug 10 06:13:22 PM PDT 24
Finished Aug 10 06:14:57 PM PDT 24
Peak memory 215600 kb
Host smart-dabfe8ca-9be7-42fc-aa87-7acf2b1d2975
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738099241 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2738099241
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.335349888
Short name T839
Test name
Test status
Simulation time 1322064945 ps
CPU time 1.49 seconds
Started Aug 10 06:13:24 PM PDT 24
Finished Aug 10 06:13:26 PM PDT 24
Peak memory 199204 kb
Host smart-f6e8989c-5822-4d74-857a-537e174a68f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335349888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.335349888
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.664140980
Short name T820
Test name
Test status
Simulation time 43578935524 ps
CPU time 73.38 seconds
Started Aug 10 06:13:18 PM PDT 24
Finished Aug 10 06:14:31 PM PDT 24
Peak memory 199832 kb
Host smart-40e5a97b-9a8c-4f0e-afb2-bdb3e5f13d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664140980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.664140980
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.242058553
Short name T447
Test name
Test status
Simulation time 42840607 ps
CPU time 0.55 seconds
Started Aug 10 06:13:32 PM PDT 24
Finished Aug 10 06:13:33 PM PDT 24
Peak memory 194796 kb
Host smart-1cbed246-a3b3-4c7f-bbf2-1f82f9cbb83d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242058553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.242058553
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.1079112796
Short name T630
Test name
Test status
Simulation time 156851391228 ps
CPU time 53.46 seconds
Started Aug 10 06:13:25 PM PDT 24
Finished Aug 10 06:14:18 PM PDT 24
Peak memory 199924 kb
Host smart-1b8b683c-0b58-4421-a096-ea9aa4704ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079112796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1079112796
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.130393347
Short name T177
Test name
Test status
Simulation time 93182555918 ps
CPU time 79.68 seconds
Started Aug 10 06:13:24 PM PDT 24
Finished Aug 10 06:14:44 PM PDT 24
Peak memory 199936 kb
Host smart-800a3d21-cd12-47eb-b801-3c10aca1e280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130393347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.130393347
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3744426887
Short name T1084
Test name
Test status
Simulation time 12964955196 ps
CPU time 18.5 seconds
Started Aug 10 06:13:23 PM PDT 24
Finished Aug 10 06:13:42 PM PDT 24
Peak memory 199952 kb
Host smart-1b1eaa0d-b2a3-40d7-9a92-2bcea796ea56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744426887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3744426887
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.1548450784
Short name T410
Test name
Test status
Simulation time 351083493068 ps
CPU time 151.09 seconds
Started Aug 10 06:13:24 PM PDT 24
Finished Aug 10 06:15:55 PM PDT 24
Peak memory 199312 kb
Host smart-1cd03a1b-8140-446c-8b1d-a9b1553b3e9b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548450784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.1548450784
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1329416944
Short name T618
Test name
Test status
Simulation time 162554538360 ps
CPU time 991.17 seconds
Started Aug 10 06:13:31 PM PDT 24
Finished Aug 10 06:30:02 PM PDT 24
Peak memory 199952 kb
Host smart-1d3f4277-a0b8-40ac-a7b5-3cb857f8ef13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1329416944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1329416944
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.2089685323
Short name T889
Test name
Test status
Simulation time 6661789513 ps
CPU time 11.05 seconds
Started Aug 10 06:13:33 PM PDT 24
Finished Aug 10 06:13:44 PM PDT 24
Peak memory 199812 kb
Host smart-78e35959-cec8-4f8f-8ea3-20cc1ac573be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089685323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2089685323
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.2718928492
Short name T1065
Test name
Test status
Simulation time 91163081858 ps
CPU time 38.68 seconds
Started Aug 10 06:13:23 PM PDT 24
Finished Aug 10 06:14:02 PM PDT 24
Peak memory 199856 kb
Host smart-c2d49e84-98bc-4cc1-b2e4-9dd6e5cc5555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718928492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.2718928492
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.2958876019
Short name T857
Test name
Test status
Simulation time 11153431049 ps
CPU time 107.24 seconds
Started Aug 10 06:13:31 PM PDT 24
Finished Aug 10 06:15:18 PM PDT 24
Peak memory 199992 kb
Host smart-071f1781-4730-45fc-b705-7cd1acd8f6b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2958876019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2958876019
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.73226745
Short name T435
Test name
Test status
Simulation time 6325238114 ps
CPU time 24.01 seconds
Started Aug 10 06:13:25 PM PDT 24
Finished Aug 10 06:13:49 PM PDT 24
Peak memory 198676 kb
Host smart-4c78314d-3c4d-4a09-a212-f2231ef32536
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=73226745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.73226745
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2971298901
Short name T933
Test name
Test status
Simulation time 107173591882 ps
CPU time 147.98 seconds
Started Aug 10 06:13:31 PM PDT 24
Finished Aug 10 06:15:59 PM PDT 24
Peak memory 199848 kb
Host smart-4823a27c-48d3-4835-95c0-f6f0a5781a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971298901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2971298901
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.806645104
Short name T692
Test name
Test status
Simulation time 3037308149 ps
CPU time 1.13 seconds
Started Aug 10 06:13:31 PM PDT 24
Finished Aug 10 06:13:32 PM PDT 24
Peak memory 196028 kb
Host smart-355273f2-a679-4f1e-98c5-05b05d6bbe06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806645104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.806645104
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2100944922
Short name T427
Test name
Test status
Simulation time 6040977211 ps
CPU time 8.14 seconds
Started Aug 10 06:13:23 PM PDT 24
Finished Aug 10 06:13:31 PM PDT 24
Peak memory 199428 kb
Host smart-fdc98d39-60a6-4771-b456-c78192ba9486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100944922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2100944922
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.3894960951
Short name T241
Test name
Test status
Simulation time 44116604898 ps
CPU time 73.27 seconds
Started Aug 10 06:13:30 PM PDT 24
Finished Aug 10 06:14:43 PM PDT 24
Peak memory 200056 kb
Host smart-064d04e9-e515-4c08-8ce6-34bb6bc8d475
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894960951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3894960951
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.3265257798
Short name T58
Test name
Test status
Simulation time 44484050339 ps
CPU time 416.42 seconds
Started Aug 10 06:13:33 PM PDT 24
Finished Aug 10 06:20:30 PM PDT 24
Peak memory 216460 kb
Host smart-19854fc4-1ed0-4e34-a944-4c9faee1c587
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265257798 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3265257798
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1344421751
Short name T767
Test name
Test status
Simulation time 757999455 ps
CPU time 1.61 seconds
Started Aug 10 06:13:33 PM PDT 24
Finished Aug 10 06:13:34 PM PDT 24
Peak memory 198872 kb
Host smart-b1953a07-c79a-4f68-b316-04b69c2afe0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344421751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1344421751
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.1376097226
Short name T775
Test name
Test status
Simulation time 71402021722 ps
CPU time 28.65 seconds
Started Aug 10 06:13:22 PM PDT 24
Finished Aug 10 06:13:51 PM PDT 24
Peak memory 199924 kb
Host smart-bb26434c-eba9-4fa6-a7ec-4904a3f5f24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376097226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1376097226
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2971359700
Short name T102
Test name
Test status
Simulation time 21829174 ps
CPU time 0.55 seconds
Started Aug 10 06:13:39 PM PDT 24
Finished Aug 10 06:13:39 PM PDT 24
Peak memory 194780 kb
Host smart-bbb93b4e-3afb-4c18-b524-d97c2a57e8d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971359700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2971359700
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.537002302
Short name T904
Test name
Test status
Simulation time 128557999187 ps
CPU time 240.8 seconds
Started Aug 10 06:13:30 PM PDT 24
Finished Aug 10 06:17:31 PM PDT 24
Peak memory 199948 kb
Host smart-ba2e92f5-1ac4-47a8-b684-59198b302dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537002302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.537002302
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.266583377
Short name T1015
Test name
Test status
Simulation time 89879201409 ps
CPU time 29.13 seconds
Started Aug 10 06:13:32 PM PDT 24
Finished Aug 10 06:14:02 PM PDT 24
Peak memory 199952 kb
Host smart-4c104c5a-3d7c-4326-8d05-af606901e68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266583377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.266583377
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.3400214628
Short name T347
Test name
Test status
Simulation time 91418103310 ps
CPU time 87.37 seconds
Started Aug 10 06:13:31 PM PDT 24
Finished Aug 10 06:14:59 PM PDT 24
Peak memory 199864 kb
Host smart-ea0f9844-432a-422e-b833-70d95d0ac72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400214628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3400214628
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.627355052
Short name T580
Test name
Test status
Simulation time 62643314042 ps
CPU time 22.66 seconds
Started Aug 10 06:13:32 PM PDT 24
Finished Aug 10 06:13:55 PM PDT 24
Peak memory 199984 kb
Host smart-92a0d20a-09dd-4654-a147-fd3e0113459c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627355052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.627355052
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2969598586
Short name T319
Test name
Test status
Simulation time 67866307707 ps
CPU time 468.96 seconds
Started Aug 10 06:13:42 PM PDT 24
Finished Aug 10 06:21:31 PM PDT 24
Peak memory 199928 kb
Host smart-8c009fc0-6241-443e-a019-2a3ef1a3aab6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2969598586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2969598586
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.538042814
Short name T702
Test name
Test status
Simulation time 7570996041 ps
CPU time 4.13 seconds
Started Aug 10 06:13:30 PM PDT 24
Finished Aug 10 06:13:34 PM PDT 24
Peak memory 198828 kb
Host smart-0cd2919e-8972-42ab-8046-bc829f4f953b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538042814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.538042814
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.4008120393
Short name T910
Test name
Test status
Simulation time 28380064120 ps
CPU time 11.42 seconds
Started Aug 10 06:13:34 PM PDT 24
Finished Aug 10 06:13:45 PM PDT 24
Peak memory 197136 kb
Host smart-260a780c-b22b-427d-b5ad-70a7572919f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008120393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.4008120393
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.4157382025
Short name T52
Test name
Test status
Simulation time 14977582212 ps
CPU time 727.53 seconds
Started Aug 10 06:13:30 PM PDT 24
Finished Aug 10 06:25:38 PM PDT 24
Peak memory 199904 kb
Host smart-51797299-65e5-4661-bfc7-c2c5870c803e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4157382025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.4157382025
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1331598201
Short name T16
Test name
Test status
Simulation time 6206779709 ps
CPU time 7.03 seconds
Started Aug 10 06:13:32 PM PDT 24
Finished Aug 10 06:13:39 PM PDT 24
Peak memory 198860 kb
Host smart-09c358b4-c159-4953-9e81-20db512f7e99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1331598201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1331598201
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2456844178
Short name T725
Test name
Test status
Simulation time 50652335361 ps
CPU time 43.32 seconds
Started Aug 10 06:13:30 PM PDT 24
Finished Aug 10 06:14:14 PM PDT 24
Peak memory 199848 kb
Host smart-f80bd926-2701-4d78-aacd-8a0fab008125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456844178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2456844178
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.3992503649
Short name T528
Test name
Test status
Simulation time 3617364560 ps
CPU time 1.87 seconds
Started Aug 10 06:13:32 PM PDT 24
Finished Aug 10 06:13:34 PM PDT 24
Peak memory 196112 kb
Host smart-87737b68-7bec-4e91-8cfa-3a6e3c3f63d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992503649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3992503649
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.254155860
Short name T418
Test name
Test status
Simulation time 268965699 ps
CPU time 1.02 seconds
Started Aug 10 06:13:32 PM PDT 24
Finished Aug 10 06:13:34 PM PDT 24
Peak memory 198464 kb
Host smart-9ad63042-0021-4b35-ac68-77ad0b652746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254155860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.254155860
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.536968175
Short name T137
Test name
Test status
Simulation time 62918075244 ps
CPU time 103.73 seconds
Started Aug 10 06:13:37 PM PDT 24
Finished Aug 10 06:15:21 PM PDT 24
Peak memory 199996 kb
Host smart-9982bf1c-345a-4f87-8e9a-ddff36d68abf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536968175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.536968175
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3929369899
Short name T438
Test name
Test status
Simulation time 964951038 ps
CPU time 2.19 seconds
Started Aug 10 06:13:33 PM PDT 24
Finished Aug 10 06:13:36 PM PDT 24
Peak memory 198368 kb
Host smart-3fcff823-9e06-49c7-a48e-85180b404851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929369899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3929369899
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1465754380
Short name T559
Test name
Test status
Simulation time 80084480926 ps
CPU time 39.83 seconds
Started Aug 10 06:13:32 PM PDT 24
Finished Aug 10 06:14:12 PM PDT 24
Peak memory 199968 kb
Host smart-812d365b-56d4-47d3-96e0-652c622eb732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465754380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1465754380
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.4123578759
Short name T110
Test name
Test status
Simulation time 73804367 ps
CPU time 0.55 seconds
Started Aug 10 06:09:18 PM PDT 24
Finished Aug 10 06:09:19 PM PDT 24
Peak memory 195644 kb
Host smart-ac8ddd9f-4831-4efc-ac23-0083f3786818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123578759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.4123578759
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1077978703
Short name T574
Test name
Test status
Simulation time 43835381610 ps
CPU time 64.24 seconds
Started Aug 10 06:09:12 PM PDT 24
Finished Aug 10 06:10:16 PM PDT 24
Peak memory 199908 kb
Host smart-f21a1524-a6b9-4976-9fe0-3e1afd72de04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077978703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1077978703
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.614626778
Short name T412
Test name
Test status
Simulation time 21156445953 ps
CPU time 32.79 seconds
Started Aug 10 06:09:13 PM PDT 24
Finished Aug 10 06:09:46 PM PDT 24
Peak memory 199648 kb
Host smart-17e368fd-5199-49e4-bc7a-17be1bd232eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614626778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.614626778
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.4254575550
Short name T508
Test name
Test status
Simulation time 35217949403 ps
CPU time 27.03 seconds
Started Aug 10 06:09:12 PM PDT 24
Finished Aug 10 06:09:40 PM PDT 24
Peak memory 199736 kb
Host smart-d2e2fdda-0fe5-4b43-b13f-c95692d32358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254575550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.4254575550
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.3746087720
Short name T960
Test name
Test status
Simulation time 63838118135 ps
CPU time 97.07 seconds
Started Aug 10 06:09:13 PM PDT 24
Finished Aug 10 06:10:50 PM PDT 24
Peak memory 199928 kb
Host smart-b28bb229-bd2c-4bce-a92b-d18c6948eca4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746087720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3746087720
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.288269293
Short name T408
Test name
Test status
Simulation time 95846885783 ps
CPU time 361.55 seconds
Started Aug 10 06:09:18 PM PDT 24
Finished Aug 10 06:15:19 PM PDT 24
Peak memory 199996 kb
Host smart-42794744-640e-44eb-90a1-ac9e0fd2f151
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=288269293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.288269293
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2280437785
Short name T445
Test name
Test status
Simulation time 7492150836 ps
CPU time 12.72 seconds
Started Aug 10 06:09:19 PM PDT 24
Finished Aug 10 06:09:32 PM PDT 24
Peak memory 199960 kb
Host smart-a968514c-cefd-4c51-8d7b-623b36fdbce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280437785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2280437785
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.3768365211
Short name T984
Test name
Test status
Simulation time 235351575502 ps
CPU time 131.59 seconds
Started Aug 10 06:09:13 PM PDT 24
Finished Aug 10 06:11:24 PM PDT 24
Peak memory 208116 kb
Host smart-4e1cc291-f03d-4859-b106-757e73ded7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768365211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3768365211
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.951203298
Short name T811
Test name
Test status
Simulation time 10361924102 ps
CPU time 287.08 seconds
Started Aug 10 06:09:20 PM PDT 24
Finished Aug 10 06:14:07 PM PDT 24
Peak memory 199908 kb
Host smart-cccc6c8a-b476-482e-ab03-5dce9f0b3d99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=951203298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.951203298
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.3962932756
Short name T714
Test name
Test status
Simulation time 6545517217 ps
CPU time 27.82 seconds
Started Aug 10 06:09:13 PM PDT 24
Finished Aug 10 06:09:41 PM PDT 24
Peak memory 198852 kb
Host smart-138473d5-5806-474d-9f46-6608c9980502
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3962932756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.3962932756
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2951254120
Short name T360
Test name
Test status
Simulation time 148088319325 ps
CPU time 70.19 seconds
Started Aug 10 06:09:19 PM PDT 24
Finished Aug 10 06:10:30 PM PDT 24
Peak memory 199872 kb
Host smart-e0fb03f7-980e-4669-8977-d67311c1aa94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951254120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2951254120
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.601918442
Short name T466
Test name
Test status
Simulation time 3039712727 ps
CPU time 1.63 seconds
Started Aug 10 06:09:13 PM PDT 24
Finished Aug 10 06:09:14 PM PDT 24
Peak memory 196996 kb
Host smart-f5f3a0fb-f472-41ce-a6a4-be27f849f96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601918442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.601918442
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.967178388
Short name T24
Test name
Test status
Simulation time 268966005 ps
CPU time 0.82 seconds
Started Aug 10 06:09:19 PM PDT 24
Finished Aug 10 06:09:20 PM PDT 24
Peak memory 218372 kb
Host smart-24560eb2-e47b-4d5a-adb8-fbeb6db83407
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967178388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.967178388
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.108219947
Short name T1013
Test name
Test status
Simulation time 541158481 ps
CPU time 1.38 seconds
Started Aug 10 06:09:13 PM PDT 24
Finished Aug 10 06:09:15 PM PDT 24
Peak memory 198844 kb
Host smart-6cf45407-347a-40d5-b88d-b56a023522aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108219947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.108219947
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.1228270243
Short name T660
Test name
Test status
Simulation time 59774412650 ps
CPU time 953.92 seconds
Started Aug 10 06:09:18 PM PDT 24
Finished Aug 10 06:25:12 PM PDT 24
Peak memory 224828 kb
Host smart-2267a0e9-d58d-4f7e-8c5c-07f37ebceb54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228270243 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1228270243
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.406283985
Short name T781
Test name
Test status
Simulation time 884133592 ps
CPU time 2.71 seconds
Started Aug 10 06:09:18 PM PDT 24
Finished Aug 10 06:09:21 PM PDT 24
Peak memory 199528 kb
Host smart-5ab97537-ce0d-48bb-93c4-e3af639b4abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406283985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.406283985
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1407087827
Short name T617
Test name
Test status
Simulation time 17938038597 ps
CPU time 27.91 seconds
Started Aug 10 06:09:13 PM PDT 24
Finished Aug 10 06:09:41 PM PDT 24
Peak memory 199916 kb
Host smart-51b8ec58-97dc-4ac7-98ce-b21a10bb046d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407087827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1407087827
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.872275402
Short name T1058
Test name
Test status
Simulation time 42327770 ps
CPU time 0.55 seconds
Started Aug 10 06:13:47 PM PDT 24
Finished Aug 10 06:13:48 PM PDT 24
Peak memory 195344 kb
Host smart-83fbd8db-120f-42d8-b6b3-d784dad7a83f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872275402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.872275402
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.1863681562
Short name T173
Test name
Test status
Simulation time 33326088886 ps
CPU time 13.97 seconds
Started Aug 10 06:13:39 PM PDT 24
Finished Aug 10 06:13:53 PM PDT 24
Peak memory 199972 kb
Host smart-f7916b8c-41e1-4443-8021-7158395cdc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863681562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1863681562
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.4110462421
Short name T490
Test name
Test status
Simulation time 76175154651 ps
CPU time 36.18 seconds
Started Aug 10 06:13:37 PM PDT 24
Finished Aug 10 06:14:13 PM PDT 24
Peak memory 199952 kb
Host smart-97682fd7-7d76-4aca-a1c5-ddfdd9704c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110462421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.4110462421
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3963571366
Short name T111
Test name
Test status
Simulation time 74800605669 ps
CPU time 104.38 seconds
Started Aug 10 06:13:37 PM PDT 24
Finished Aug 10 06:15:21 PM PDT 24
Peak memory 199924 kb
Host smart-0e96e800-bc43-4e12-b662-fe15b939981b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963571366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3963571366
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.405363844
Short name T344
Test name
Test status
Simulation time 84128277266 ps
CPU time 35.59 seconds
Started Aug 10 06:13:39 PM PDT 24
Finished Aug 10 06:14:15 PM PDT 24
Peak memory 200000 kb
Host smart-6eb1480e-518a-45bf-93af-f7d61ab4c0f2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405363844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.405363844
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.689534078
Short name T827
Test name
Test status
Simulation time 31098145817 ps
CPU time 124.11 seconds
Started Aug 10 06:13:38 PM PDT 24
Finished Aug 10 06:15:43 PM PDT 24
Peak memory 199956 kb
Host smart-ee68a646-e983-49c3-93ae-4a4c93801992
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=689534078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.689534078
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2329228
Short name T462
Test name
Test status
Simulation time 9061599510 ps
CPU time 6.66 seconds
Started Aug 10 06:13:39 PM PDT 24
Finished Aug 10 06:13:46 PM PDT 24
Peak memory 198708 kb
Host smart-3122fd5b-a64f-4620-9c83-1b15f9144798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2329228
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.743507656
Short name T282
Test name
Test status
Simulation time 97449527961 ps
CPU time 191.57 seconds
Started Aug 10 06:13:43 PM PDT 24
Finished Aug 10 06:16:55 PM PDT 24
Peak memory 199692 kb
Host smart-59e611b2-ac3a-4d54-9d79-a73506d01435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743507656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.743507656
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.486590444
Short name T929
Test name
Test status
Simulation time 29695621263 ps
CPU time 311.55 seconds
Started Aug 10 06:13:38 PM PDT 24
Finished Aug 10 06:18:50 PM PDT 24
Peak memory 199904 kb
Host smart-52112cb3-1789-4510-8620-67db753b4fa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=486590444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.486590444
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1985671899
Short name T432
Test name
Test status
Simulation time 5807989488 ps
CPU time 11.51 seconds
Started Aug 10 06:13:37 PM PDT 24
Finished Aug 10 06:13:49 PM PDT 24
Peak memory 199260 kb
Host smart-3ccf026e-424d-45fa-ba61-c53d5ffece77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1985671899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1985671899
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2279383535
Short name T557
Test name
Test status
Simulation time 107975594113 ps
CPU time 56.06 seconds
Started Aug 10 06:13:39 PM PDT 24
Finished Aug 10 06:14:36 PM PDT 24
Peak memory 199880 kb
Host smart-b5c1a4aa-8b5f-40e0-b341-525c9f8db0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279383535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2279383535
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.3790444572
Short name T1007
Test name
Test status
Simulation time 2029413999 ps
CPU time 3.59 seconds
Started Aug 10 06:13:37 PM PDT 24
Finished Aug 10 06:13:41 PM PDT 24
Peak memory 195528 kb
Host smart-8bc717a7-ba7b-48e1-bd4d-b9dccbb21860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790444572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.3790444572
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3047216494
Short name T804
Test name
Test status
Simulation time 6213023964 ps
CPU time 15.36 seconds
Started Aug 10 06:13:38 PM PDT 24
Finished Aug 10 06:13:54 PM PDT 24
Peak memory 199868 kb
Host smart-acfd33bb-309a-423b-a726-b3b09c2cd0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047216494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3047216494
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.467760008
Short name T709
Test name
Test status
Simulation time 35999331794 ps
CPU time 32.29 seconds
Started Aug 10 06:13:47 PM PDT 24
Finished Aug 10 06:14:19 PM PDT 24
Peak memory 199904 kb
Host smart-14cbda98-a09d-4d44-bb7c-cb84bd14fdec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467760008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.467760008
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.4003718965
Short name T791
Test name
Test status
Simulation time 909131660 ps
CPU time 2.27 seconds
Started Aug 10 06:13:38 PM PDT 24
Finished Aug 10 06:13:41 PM PDT 24
Peak memory 198784 kb
Host smart-51cfd533-e5a8-4106-8272-7078ed0122f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003718965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.4003718965
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.95987685
Short name T451
Test name
Test status
Simulation time 66098459295 ps
CPU time 24.12 seconds
Started Aug 10 06:13:38 PM PDT 24
Finished Aug 10 06:14:03 PM PDT 24
Peak memory 199972 kb
Host smart-19595bf8-c176-4209-b34b-4518fe94a0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95987685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.95987685
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2400571700
Short name T664
Test name
Test status
Simulation time 11927388 ps
CPU time 0.54 seconds
Started Aug 10 06:13:55 PM PDT 24
Finished Aug 10 06:13:55 PM PDT 24
Peak memory 195372 kb
Host smart-48f39617-7491-481b-8d96-414688ad7c5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400571700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2400571700
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3416713150
Short name T738
Test name
Test status
Simulation time 33433185627 ps
CPU time 12.47 seconds
Started Aug 10 06:13:46 PM PDT 24
Finished Aug 10 06:13:59 PM PDT 24
Peak memory 199904 kb
Host smart-425f2f04-30ea-454b-9c90-e3be67865cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416713150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3416713150
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.1306572633
Short name T812
Test name
Test status
Simulation time 27375694142 ps
CPU time 5.63 seconds
Started Aug 10 06:13:46 PM PDT 24
Finished Aug 10 06:13:52 PM PDT 24
Peak memory 199952 kb
Host smart-e9cdb3f9-93e0-46bc-8f70-59f4200a0a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306572633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1306572633
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3965249490
Short name T183
Test name
Test status
Simulation time 19236910719 ps
CPU time 25.18 seconds
Started Aug 10 06:13:46 PM PDT 24
Finished Aug 10 06:14:11 PM PDT 24
Peak memory 199964 kb
Host smart-f8bd1fc7-53da-4db9-be9e-0dc175a02c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965249490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3965249490
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.3682637204
Short name T870
Test name
Test status
Simulation time 312035178250 ps
CPU time 514.83 seconds
Started Aug 10 06:13:46 PM PDT 24
Finished Aug 10 06:22:21 PM PDT 24
Peak memory 199900 kb
Host smart-299630e9-304c-4650-81f0-bbdccfbeada4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682637204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3682637204
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3602717908
Short name T598
Test name
Test status
Simulation time 96955536731 ps
CPU time 163.05 seconds
Started Aug 10 06:13:48 PM PDT 24
Finished Aug 10 06:16:31 PM PDT 24
Peak memory 199900 kb
Host smart-2c53c126-1d22-4990-a721-3a402ed778cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3602717908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3602717908
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1628717448
Short name T394
Test name
Test status
Simulation time 1215495029 ps
CPU time 1.34 seconds
Started Aug 10 06:13:46 PM PDT 24
Finished Aug 10 06:13:48 PM PDT 24
Peak memory 197184 kb
Host smart-03465c6b-b38e-4601-8c75-60a341efe063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628717448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1628717448
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.292184974
Short name T650
Test name
Test status
Simulation time 54172032596 ps
CPU time 101.97 seconds
Started Aug 10 06:13:54 PM PDT 24
Finished Aug 10 06:15:36 PM PDT 24
Peak memory 200108 kb
Host smart-1ce48050-3028-4733-9524-598b5a46e1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292184974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.292184974
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.4081256494
Short name T639
Test name
Test status
Simulation time 20481482737 ps
CPU time 370.87 seconds
Started Aug 10 06:13:49 PM PDT 24
Finished Aug 10 06:20:00 PM PDT 24
Peak memory 199888 kb
Host smart-f79fea73-60ae-467a-b30b-690b3a6fa932
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4081256494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.4081256494
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.273565898
Short name T927
Test name
Test status
Simulation time 4681216940 ps
CPU time 5.16 seconds
Started Aug 10 06:13:45 PM PDT 24
Finished Aug 10 06:13:51 PM PDT 24
Peak memory 198000 kb
Host smart-db242ddb-b244-4750-9080-1066525ea266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=273565898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.273565898
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2183323505
Short name T627
Test name
Test status
Simulation time 187447074721 ps
CPU time 198.31 seconds
Started Aug 10 06:13:47 PM PDT 24
Finished Aug 10 06:17:05 PM PDT 24
Peak memory 199664 kb
Host smart-c9d1cbaa-b993-434b-b2ba-ae2900e5eee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183323505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2183323505
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.466045555
Short name T1038
Test name
Test status
Simulation time 2270970557 ps
CPU time 1.39 seconds
Started Aug 10 06:13:46 PM PDT 24
Finished Aug 10 06:13:47 PM PDT 24
Peak memory 195524 kb
Host smart-777b21e4-d121-4dee-abfc-d63eec10f592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466045555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.466045555
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.116673054
Short name T1054
Test name
Test status
Simulation time 321327199 ps
CPU time 0.84 seconds
Started Aug 10 06:13:47 PM PDT 24
Finished Aug 10 06:13:48 PM PDT 24
Peak memory 198260 kb
Host smart-c3841e4d-4966-4796-a363-e3d9c276134b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116673054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.116673054
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.3184934762
Short name T320
Test name
Test status
Simulation time 225588912653 ps
CPU time 1050.57 seconds
Started Aug 10 06:13:54 PM PDT 24
Finished Aug 10 06:31:25 PM PDT 24
Peak memory 200004 kb
Host smart-a8f1cf7d-25fa-4ae1-aab2-df884222a7bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184934762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3184934762
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.1107243750
Short name T854
Test name
Test status
Simulation time 122383027103 ps
CPU time 404.09 seconds
Started Aug 10 06:13:55 PM PDT 24
Finished Aug 10 06:20:39 PM PDT 24
Peak memory 224844 kb
Host smart-7d98c54b-464d-44b0-aae2-90dc9990c526
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107243750 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.1107243750
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1442953375
Short name T1138
Test name
Test status
Simulation time 949998855 ps
CPU time 1.9 seconds
Started Aug 10 06:13:47 PM PDT 24
Finished Aug 10 06:13:49 PM PDT 24
Peak memory 198712 kb
Host smart-fe20ba0e-d900-4a59-8ffb-69a6a11bace4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442953375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1442953375
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2359523804
Short name T289
Test name
Test status
Simulation time 7530015506 ps
CPU time 12.19 seconds
Started Aug 10 06:13:44 PM PDT 24
Finished Aug 10 06:13:56 PM PDT 24
Peak memory 198348 kb
Host smart-282908e8-b41d-46c5-acaf-0ecdf2ffa905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359523804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2359523804
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.4013311392
Short name T777
Test name
Test status
Simulation time 88288974 ps
CPU time 0.56 seconds
Started Aug 10 06:13:54 PM PDT 24
Finished Aug 10 06:13:54 PM PDT 24
Peak memory 194816 kb
Host smart-fbff7e58-6db8-4445-98e1-d7323e4df0b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013311392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.4013311392
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2971245298
Short name T469
Test name
Test status
Simulation time 23136569169 ps
CPU time 9.74 seconds
Started Aug 10 06:13:47 PM PDT 24
Finished Aug 10 06:13:57 PM PDT 24
Peak memory 199672 kb
Host smart-f69e6698-0939-4c77-9a1b-19043367696e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971245298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2971245298
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1720351152
Short name T683
Test name
Test status
Simulation time 55163701901 ps
CPU time 35.69 seconds
Started Aug 10 06:13:47 PM PDT 24
Finished Aug 10 06:14:23 PM PDT 24
Peak memory 199908 kb
Host smart-c61d0252-4232-4914-a77b-270b043451c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720351152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1720351152
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.2630871163
Short name T1130
Test name
Test status
Simulation time 111800184386 ps
CPU time 176.46 seconds
Started Aug 10 06:13:59 PM PDT 24
Finished Aug 10 06:16:56 PM PDT 24
Peak memory 200008 kb
Host smart-6b3b1a47-ad1c-4e43-9c20-f8c521477793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630871163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2630871163
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.1764680608
Short name T1069
Test name
Test status
Simulation time 31032427965 ps
CPU time 3.85 seconds
Started Aug 10 06:13:59 PM PDT 24
Finished Aug 10 06:14:03 PM PDT 24
Peak memory 198628 kb
Host smart-85f53ede-a923-4c44-ab26-51206fbcc6ea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764680608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1764680608
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.1679514468
Short name T677
Test name
Test status
Simulation time 177559543756 ps
CPU time 198.4 seconds
Started Aug 10 06:13:55 PM PDT 24
Finished Aug 10 06:17:13 PM PDT 24
Peak memory 199848 kb
Host smart-12ccae31-4bf2-41ac-b600-dd79bcd29515
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1679514468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1679514468
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.805083425
Short name T1111
Test name
Test status
Simulation time 5180326168 ps
CPU time 13.01 seconds
Started Aug 10 06:13:56 PM PDT 24
Finished Aug 10 06:14:09 PM PDT 24
Peak memory 198416 kb
Host smart-0c4dc954-a193-4b59-bbe6-d5370644bfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805083425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.805083425
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3270927796
Short name T902
Test name
Test status
Simulation time 26002131199 ps
CPU time 46.07 seconds
Started Aug 10 06:13:54 PM PDT 24
Finished Aug 10 06:14:40 PM PDT 24
Peak memory 199028 kb
Host smart-4c18765b-0ac5-4d80-afa4-ad176198b213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270927796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3270927796
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.1651400147
Short name T1149
Test name
Test status
Simulation time 15202023505 ps
CPU time 180.11 seconds
Started Aug 10 06:13:55 PM PDT 24
Finished Aug 10 06:16:55 PM PDT 24
Peak memory 199776 kb
Host smart-47b6598f-f2cb-4248-8260-0ad99ebf1680
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1651400147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1651400147
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.4151417439
Short name T361
Test name
Test status
Simulation time 5333785899 ps
CPU time 4.73 seconds
Started Aug 10 06:13:57 PM PDT 24
Finished Aug 10 06:14:02 PM PDT 24
Peak memory 198340 kb
Host smart-42062eb4-1224-4d5c-988f-a8bcd2eff5ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4151417439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.4151417439
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3050397815
Short name T790
Test name
Test status
Simulation time 158590722623 ps
CPU time 141.77 seconds
Started Aug 10 06:13:54 PM PDT 24
Finished Aug 10 06:16:16 PM PDT 24
Peak memory 199908 kb
Host smart-6895f585-4344-4b7a-9119-a0fbbbf6b937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050397815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3050397815
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1585893056
Short name T846
Test name
Test status
Simulation time 4304270050 ps
CPU time 2.35 seconds
Started Aug 10 06:13:54 PM PDT 24
Finished Aug 10 06:13:56 PM PDT 24
Peak memory 196236 kb
Host smart-dbab25fb-4524-4487-8914-e9d056ad804d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585893056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1585893056
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.767358741
Short name T297
Test name
Test status
Simulation time 734021151 ps
CPU time 3.53 seconds
Started Aug 10 06:13:47 PM PDT 24
Finished Aug 10 06:13:51 PM PDT 24
Peak memory 198956 kb
Host smart-9c6d3880-f22d-41d4-9d37-c5ff448786d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767358741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.767358741
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.536616149
Short name T988
Test name
Test status
Simulation time 516337160470 ps
CPU time 1168.33 seconds
Started Aug 10 06:13:54 PM PDT 24
Finished Aug 10 06:33:23 PM PDT 24
Peak memory 216188 kb
Host smart-887ca87a-4a2f-4084-9d22-8541d1a22bc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536616149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.536616149
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3205725280
Short name T864
Test name
Test status
Simulation time 254538761481 ps
CPU time 959.97 seconds
Started Aug 10 06:13:58 PM PDT 24
Finished Aug 10 06:29:58 PM PDT 24
Peak memory 224840 kb
Host smart-9e6fc7d4-22f0-44fb-9535-66b6af2e6184
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205725280 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3205725280
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1684065921
Short name T429
Test name
Test status
Simulation time 1986339261 ps
CPU time 2.15 seconds
Started Aug 10 06:13:55 PM PDT 24
Finished Aug 10 06:13:57 PM PDT 24
Peak memory 198392 kb
Host smart-9c9c7302-071a-40aa-91b5-09ea013850a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684065921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1684065921
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.730140130
Short name T421
Test name
Test status
Simulation time 75420752191 ps
CPU time 51.81 seconds
Started Aug 10 06:13:45 PM PDT 24
Finished Aug 10 06:14:37 PM PDT 24
Peak memory 199988 kb
Host smart-6fa57a2c-e7dc-4228-ad05-b367b1bbbc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730140130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.730140130
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1483523221
Short name T495
Test name
Test status
Simulation time 26295518 ps
CPU time 0.57 seconds
Started Aug 10 06:14:04 PM PDT 24
Finished Aug 10 06:14:04 PM PDT 24
Peak memory 194272 kb
Host smart-e3000084-55c4-40d0-a91b-6f2f9770cecf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483523221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1483523221
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.3320164867
Short name T976
Test name
Test status
Simulation time 145007990708 ps
CPU time 58.87 seconds
Started Aug 10 06:13:58 PM PDT 24
Finished Aug 10 06:14:57 PM PDT 24
Peak memory 199916 kb
Host smart-ac3ddc66-1691-4793-8a39-fac7b5d8a707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320164867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3320164867
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3726262088
Short name T261
Test name
Test status
Simulation time 128404248493 ps
CPU time 242.24 seconds
Started Aug 10 06:13:55 PM PDT 24
Finished Aug 10 06:17:57 PM PDT 24
Peak memory 199960 kb
Host smart-5763932d-c48b-4f41-b771-19b48e5c43e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726262088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3726262088
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3997833230
Short name T670
Test name
Test status
Simulation time 14524303427 ps
CPU time 28.16 seconds
Started Aug 10 06:13:53 PM PDT 24
Finished Aug 10 06:14:21 PM PDT 24
Peak memory 199984 kb
Host smart-41c292e3-2ebf-4d61-807f-8122bd7e8406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997833230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3997833230
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3635343062
Short name T2
Test name
Test status
Simulation time 38079235271 ps
CPU time 71.2 seconds
Started Aug 10 06:13:54 PM PDT 24
Finished Aug 10 06:15:05 PM PDT 24
Peak memory 199792 kb
Host smart-f21a685f-7f47-4652-89a7-160085aa9989
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635343062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3635343062
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.737411505
Short name T990
Test name
Test status
Simulation time 130314537434 ps
CPU time 1021.1 seconds
Started Aug 10 06:14:03 PM PDT 24
Finished Aug 10 06:31:04 PM PDT 24
Peak memory 199412 kb
Host smart-e52e4715-9431-413c-85a1-d3f7178ee326
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=737411505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.737411505
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.2887764026
Short name T473
Test name
Test status
Simulation time 1296634875 ps
CPU time 2.63 seconds
Started Aug 10 06:14:01 PM PDT 24
Finished Aug 10 06:14:04 PM PDT 24
Peak memory 195656 kb
Host smart-0db01e08-5547-46f2-bf34-8a82adb762e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887764026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2887764026
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.605639964
Short name T542
Test name
Test status
Simulation time 124539408963 ps
CPU time 56.31 seconds
Started Aug 10 06:13:56 PM PDT 24
Finished Aug 10 06:14:53 PM PDT 24
Peak memory 200044 kb
Host smart-905b05da-9905-4eaf-8f41-aa5be51f2d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605639964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.605639964
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1005382647
Short name T852
Test name
Test status
Simulation time 10076084123 ps
CPU time 384.22 seconds
Started Aug 10 06:14:03 PM PDT 24
Finished Aug 10 06:20:28 PM PDT 24
Peak memory 199932 kb
Host smart-59b64db0-bb8f-4fcc-86d0-a523c30e1289
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1005382647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1005382647
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.815008245
Short name T662
Test name
Test status
Simulation time 6281099992 ps
CPU time 56.68 seconds
Started Aug 10 06:13:57 PM PDT 24
Finished Aug 10 06:14:54 PM PDT 24
Peak memory 199424 kb
Host smart-585d410a-41bd-4eae-8328-45758bb1eb4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=815008245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.815008245
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1914988442
Short name T851
Test name
Test status
Simulation time 39806727472 ps
CPU time 17.1 seconds
Started Aug 10 06:14:03 PM PDT 24
Finished Aug 10 06:14:20 PM PDT 24
Peak memory 198324 kb
Host smart-550bc21d-648f-4c70-a02f-b18a805d74ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914988442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1914988442
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.53593872
Short name T998
Test name
Test status
Simulation time 5294365040 ps
CPU time 8.39 seconds
Started Aug 10 06:13:55 PM PDT 24
Finished Aug 10 06:14:04 PM PDT 24
Peak memory 196452 kb
Host smart-1bbd063d-80a9-4180-b608-b21ce8e39e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53593872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.53593872
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.195462716
Short name T1035
Test name
Test status
Simulation time 272488477 ps
CPU time 1.05 seconds
Started Aug 10 06:13:53 PM PDT 24
Finished Aug 10 06:13:54 PM PDT 24
Peak memory 198496 kb
Host smart-47cdc358-9125-486b-93e5-0343b6a1a005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195462716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.195462716
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2430041226
Short name T869
Test name
Test status
Simulation time 78594385035 ps
CPU time 274.87 seconds
Started Aug 10 06:14:03 PM PDT 24
Finished Aug 10 06:18:38 PM PDT 24
Peak memory 199948 kb
Host smart-057d31d2-6093-4fc4-8920-693c0838a20e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430041226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2430041226
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.3381891331
Short name T176
Test name
Test status
Simulation time 74483921132 ps
CPU time 851.97 seconds
Started Aug 10 06:14:01 PM PDT 24
Finished Aug 10 06:28:13 PM PDT 24
Peak memory 216524 kb
Host smart-ff8be38a-b9da-4a47-85ae-c81c8276bd2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381891331 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.3381891331
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.1566076018
Short name T402
Test name
Test status
Simulation time 6272881866 ps
CPU time 19.79 seconds
Started Aug 10 06:14:02 PM PDT 24
Finished Aug 10 06:14:21 PM PDT 24
Peak memory 199752 kb
Host smart-a2c694e1-1d9a-4fcd-8986-9d397eb3071f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566076018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1566076018
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.715943349
Short name T11
Test name
Test status
Simulation time 186741369962 ps
CPU time 57.94 seconds
Started Aug 10 06:13:56 PM PDT 24
Finished Aug 10 06:14:54 PM PDT 24
Peak memory 199964 kb
Host smart-84a5a29c-11a8-475f-8984-2d3d1b75c177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715943349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.715943349
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.3285577583
Short name T789
Test name
Test status
Simulation time 32595572 ps
CPU time 0.56 seconds
Started Aug 10 06:14:03 PM PDT 24
Finished Aug 10 06:14:03 PM PDT 24
Peak memory 195232 kb
Host smart-54cf03f9-d2da-48dc-ba5c-2db0880a565e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285577583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3285577583
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.2914069896
Short name T1101
Test name
Test status
Simulation time 29011190425 ps
CPU time 41.41 seconds
Started Aug 10 06:14:02 PM PDT 24
Finished Aug 10 06:14:43 PM PDT 24
Peak memory 199800 kb
Host smart-d40c8a4e-ca73-4b2e-b91d-681989758134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914069896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.2914069896
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1623021701
Short name T1109
Test name
Test status
Simulation time 147763744183 ps
CPU time 97.38 seconds
Started Aug 10 06:14:03 PM PDT 24
Finished Aug 10 06:15:40 PM PDT 24
Peak memory 199964 kb
Host smart-db80b6f4-967d-4d43-b423-f230acc07c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623021701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1623021701
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_intr.799208873
Short name T1037
Test name
Test status
Simulation time 44471283696 ps
CPU time 77.47 seconds
Started Aug 10 06:14:01 PM PDT 24
Finished Aug 10 06:15:18 PM PDT 24
Peak memory 199940 kb
Host smart-b735d7ff-4bb2-4fa6-be56-91259fd3f294
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799208873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.799208873
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.3515066130
Short name T529
Test name
Test status
Simulation time 90487020608 ps
CPU time 467.35 seconds
Started Aug 10 06:14:00 PM PDT 24
Finished Aug 10 06:21:47 PM PDT 24
Peak memory 199984 kb
Host smart-d13848fa-4ee6-438b-ba25-1735429ad4c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3515066130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3515066130
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.261021153
Short name T1176
Test name
Test status
Simulation time 3782460370 ps
CPU time 3.03 seconds
Started Aug 10 06:14:08 PM PDT 24
Finished Aug 10 06:14:11 PM PDT 24
Peak memory 197200 kb
Host smart-215960fb-ec04-4b1c-a175-0bb13f78058c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261021153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.261021153
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.1894655269
Short name T116
Test name
Test status
Simulation time 27818060852 ps
CPU time 43.06 seconds
Started Aug 10 06:14:01 PM PDT 24
Finished Aug 10 06:14:44 PM PDT 24
Peak memory 197560 kb
Host smart-c0a7038b-4330-4130-97c7-36e79d9d8e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894655269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1894655269
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.3196558494
Short name T785
Test name
Test status
Simulation time 31979321584 ps
CPU time 151.89 seconds
Started Aug 10 06:14:03 PM PDT 24
Finished Aug 10 06:16:35 PM PDT 24
Peak memory 199860 kb
Host smart-8f816368-fc91-4ed5-989d-e682c5805a84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3196558494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3196558494
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.4104583891
Short name T484
Test name
Test status
Simulation time 5495823794 ps
CPU time 13.21 seconds
Started Aug 10 06:14:03 PM PDT 24
Finished Aug 10 06:14:16 PM PDT 24
Peak memory 198356 kb
Host smart-b1d9d195-dc13-4799-8d53-7067e8fa3bbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4104583891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.4104583891
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.2705044976
Short name T913
Test name
Test status
Simulation time 26476873238 ps
CPU time 13.59 seconds
Started Aug 10 06:14:00 PM PDT 24
Finished Aug 10 06:14:14 PM PDT 24
Peak memory 199956 kb
Host smart-49a42448-bf35-4f63-bd73-0b8f2e5540dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705044976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2705044976
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.3876576982
Short name T327
Test name
Test status
Simulation time 4702697052 ps
CPU time 2.4 seconds
Started Aug 10 06:14:03 PM PDT 24
Finished Aug 10 06:14:05 PM PDT 24
Peak memory 196144 kb
Host smart-0e935e11-209d-489e-9056-d213fd2d70db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876576982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3876576982
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.412178710
Short name T603
Test name
Test status
Simulation time 757621587 ps
CPU time 1.8 seconds
Started Aug 10 06:14:01 PM PDT 24
Finished Aug 10 06:14:03 PM PDT 24
Peak memory 198244 kb
Host smart-6087cb63-4447-4262-8b93-e877e9089db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412178710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.412178710
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.1133169540
Short name T721
Test name
Test status
Simulation time 131289401713 ps
CPU time 543.62 seconds
Started Aug 10 06:14:07 PM PDT 24
Finished Aug 10 06:23:11 PM PDT 24
Peak memory 199936 kb
Host smart-0e319434-c9d7-4d79-a77a-806bfc4df6f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133169540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1133169540
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.2703460714
Short name T54
Test name
Test status
Simulation time 47283281452 ps
CPU time 188.8 seconds
Started Aug 10 06:14:03 PM PDT 24
Finished Aug 10 06:17:12 PM PDT 24
Peak memory 216456 kb
Host smart-934a50e6-6411-4758-8229-181ff19c40e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703460714 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.2703460714
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.325578360
Short name T44
Test name
Test status
Simulation time 706042074 ps
CPU time 2.08 seconds
Started Aug 10 06:14:07 PM PDT 24
Finished Aug 10 06:14:09 PM PDT 24
Peak memory 198304 kb
Host smart-05f11e73-038b-49bb-98ad-852366030729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325578360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.325578360
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.654167064
Short name T596
Test name
Test status
Simulation time 14843827714 ps
CPU time 22.93 seconds
Started Aug 10 06:14:06 PM PDT 24
Finished Aug 10 06:14:29 PM PDT 24
Peak memory 199972 kb
Host smart-a003cba5-714d-47bd-a2b9-b075ee6260d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654167064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.654167064
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3922361124
Short name T522
Test name
Test status
Simulation time 22209949 ps
CPU time 0.55 seconds
Started Aug 10 06:14:11 PM PDT 24
Finished Aug 10 06:14:11 PM PDT 24
Peak memory 195336 kb
Host smart-bee5d7f4-35e6-4378-95ae-bdbb316fe143
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922361124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3922361124
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.1859217349
Short name T943
Test name
Test status
Simulation time 72858152665 ps
CPU time 27.54 seconds
Started Aug 10 06:14:02 PM PDT 24
Finished Aug 10 06:14:30 PM PDT 24
Peak memory 199844 kb
Host smart-d4913bb7-29f8-45ab-8622-378e0d070537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859217349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1859217349
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3141867855
Short name T399
Test name
Test status
Simulation time 111544667281 ps
CPU time 48.23 seconds
Started Aug 10 06:14:01 PM PDT 24
Finished Aug 10 06:14:49 PM PDT 24
Peak memory 199908 kb
Host smart-ce6e9e78-5b24-4e82-883a-b63cbc7358c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141867855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3141867855
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2112128819
Short name T175
Test name
Test status
Simulation time 85203688581 ps
CPU time 102.76 seconds
Started Aug 10 06:14:00 PM PDT 24
Finished Aug 10 06:15:43 PM PDT 24
Peak memory 199964 kb
Host smart-44380817-311b-4cc5-9c01-7945d7a23145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112128819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2112128819
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.1213362690
Short name T124
Test name
Test status
Simulation time 33637761806 ps
CPU time 34.86 seconds
Started Aug 10 06:14:14 PM PDT 24
Finished Aug 10 06:14:49 PM PDT 24
Peak memory 199804 kb
Host smart-2da6d76f-29e5-4cfa-8aed-086708957279
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213362690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1213362690
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1207949148
Short name T380
Test name
Test status
Simulation time 81946200797 ps
CPU time 109.37 seconds
Started Aug 10 06:14:13 PM PDT 24
Finished Aug 10 06:16:03 PM PDT 24
Peak memory 199780 kb
Host smart-d54813cd-deaa-41d6-8a47-a4d2a9c5b19a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1207949148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1207949148
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.2472276033
Short name T882
Test name
Test status
Simulation time 5821889896 ps
CPU time 3.21 seconds
Started Aug 10 06:14:08 PM PDT 24
Finished Aug 10 06:14:12 PM PDT 24
Peak memory 195780 kb
Host smart-673ad0c0-9efc-47ed-8f77-7c910e12104a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472276033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2472276033
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_perf.3752683564
Short name T1127
Test name
Test status
Simulation time 8144450462 ps
CPU time 124.05 seconds
Started Aug 10 06:14:10 PM PDT 24
Finished Aug 10 06:16:14 PM PDT 24
Peak memory 199956 kb
Host smart-1923dc33-7258-492d-955b-42388b569af9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3752683564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3752683564
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.713596945
Short name T1009
Test name
Test status
Simulation time 3686715872 ps
CPU time 28.99 seconds
Started Aug 10 06:14:03 PM PDT 24
Finished Aug 10 06:14:32 PM PDT 24
Peak memory 199272 kb
Host smart-2db37533-8298-4586-8200-0226661cfae1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=713596945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.713596945
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.337198384
Short name T699
Test name
Test status
Simulation time 72852998367 ps
CPU time 147.06 seconds
Started Aug 10 06:14:13 PM PDT 24
Finished Aug 10 06:16:40 PM PDT 24
Peak memory 199808 kb
Host smart-fe30f3fa-4673-4641-a9f3-829f463a34aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337198384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.337198384
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2753628586
Short name T609
Test name
Test status
Simulation time 33496192150 ps
CPU time 9.74 seconds
Started Aug 10 06:14:09 PM PDT 24
Finished Aug 10 06:14:19 PM PDT 24
Peak memory 196852 kb
Host smart-0e92366e-c32c-4c6d-92e8-d05b629a7131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753628586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2753628586
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.1164704558
Short name T723
Test name
Test status
Simulation time 90217824 ps
CPU time 0.87 seconds
Started Aug 10 06:14:01 PM PDT 24
Finished Aug 10 06:14:02 PM PDT 24
Peak memory 197784 kb
Host smart-cb570b9f-8f04-453c-a525-c5526bf52f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164704558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1164704558
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.339004996
Short name T1056
Test name
Test status
Simulation time 6769168419 ps
CPU time 22.11 seconds
Started Aug 10 06:14:09 PM PDT 24
Finished Aug 10 06:14:31 PM PDT 24
Peak memory 199536 kb
Host smart-820dcfce-bb18-4dca-8798-9e26d82b2fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339004996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.339004996
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2578037055
Short name T1172
Test name
Test status
Simulation time 123333670199 ps
CPU time 55.67 seconds
Started Aug 10 06:14:01 PM PDT 24
Finished Aug 10 06:14:57 PM PDT 24
Peak memory 199980 kb
Host smart-4023f3d3-b621-4647-9a0d-34f184e0e65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578037055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2578037055
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2655797140
Short name T23
Test name
Test status
Simulation time 11116634 ps
CPU time 0.55 seconds
Started Aug 10 06:14:14 PM PDT 24
Finished Aug 10 06:14:14 PM PDT 24
Peak memory 194784 kb
Host smart-b60de342-a2d7-426f-983d-14452c3d9839
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655797140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2655797140
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.4245116684
Short name T626
Test name
Test status
Simulation time 114915910802 ps
CPU time 171.28 seconds
Started Aug 10 06:14:09 PM PDT 24
Finished Aug 10 06:17:01 PM PDT 24
Peak memory 199960 kb
Host smart-502f1315-8ab0-4756-8b37-625dd71caaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245116684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.4245116684
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.38753773
Short name T634
Test name
Test status
Simulation time 125545184585 ps
CPU time 262.89 seconds
Started Aug 10 06:14:10 PM PDT 24
Finished Aug 10 06:18:33 PM PDT 24
Peak memory 199884 kb
Host smart-d1f8e8f0-65a7-48ee-a5f3-d39ca773b376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38753773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.38753773
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3709466164
Short name T172
Test name
Test status
Simulation time 130127290357 ps
CPU time 48.69 seconds
Started Aug 10 06:14:08 PM PDT 24
Finished Aug 10 06:14:56 PM PDT 24
Peak memory 199788 kb
Host smart-d754f9ae-bb75-403b-bb10-98d123deb73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709466164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3709466164
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.314771049
Short name T712
Test name
Test status
Simulation time 14603894991 ps
CPU time 3.05 seconds
Started Aug 10 06:14:08 PM PDT 24
Finished Aug 10 06:14:11 PM PDT 24
Peak memory 199912 kb
Host smart-900f0abf-ed0c-4ec8-8119-4e20184b06ec
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314771049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.314771049
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3556848907
Short name T873
Test name
Test status
Simulation time 46325550532 ps
CPU time 325.17 seconds
Started Aug 10 06:14:17 PM PDT 24
Finished Aug 10 06:19:42 PM PDT 24
Peak memory 199988 kb
Host smart-504a77b4-4d5f-4e9e-aa96-2dfae682f8a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3556848907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3556848907
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.619982885
Short name T823
Test name
Test status
Simulation time 7399944170 ps
CPU time 5.51 seconds
Started Aug 10 06:14:16 PM PDT 24
Finished Aug 10 06:14:22 PM PDT 24
Peak memory 198816 kb
Host smart-3ae687d1-a796-407d-8db1-c35a4844e249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619982885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.619982885
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.2851336129
Short name T1089
Test name
Test status
Simulation time 7436564452 ps
CPU time 6.78 seconds
Started Aug 10 06:14:13 PM PDT 24
Finished Aug 10 06:14:20 PM PDT 24
Peak memory 194432 kb
Host smart-de9766b0-dcc6-4ff5-b46b-d716f6e73ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851336129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2851336129
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.4182583032
Short name T455
Test name
Test status
Simulation time 6641045281 ps
CPU time 294.15 seconds
Started Aug 10 06:14:15 PM PDT 24
Finished Aug 10 06:19:10 PM PDT 24
Peak memory 199968 kb
Host smart-bd53481c-28a1-4dea-865a-f63fddde0053
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182583032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.4182583032
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2284514432
Short name T375
Test name
Test status
Simulation time 3083089520 ps
CPU time 23.8 seconds
Started Aug 10 06:14:10 PM PDT 24
Finished Aug 10 06:14:33 PM PDT 24
Peak memory 199088 kb
Host smart-e8772c4b-831e-4b89-8eab-4766a5e86d51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2284514432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2284514432
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.3332168818
Short name T868
Test name
Test status
Simulation time 103784418186 ps
CPU time 448.43 seconds
Started Aug 10 06:14:09 PM PDT 24
Finished Aug 10 06:21:37 PM PDT 24
Peak memory 199916 kb
Host smart-16a69083-4057-441c-9d2e-42cf246e021b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332168818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3332168818
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3229359418
Short name T940
Test name
Test status
Simulation time 40689005900 ps
CPU time 29.2 seconds
Started Aug 10 06:14:09 PM PDT 24
Finished Aug 10 06:14:38 PM PDT 24
Peak memory 196080 kb
Host smart-28abea1f-d543-4ca7-a994-e0bdaa4e79ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229359418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3229359418
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.2049052653
Short name T1094
Test name
Test status
Simulation time 711870119 ps
CPU time 2.39 seconds
Started Aug 10 06:14:08 PM PDT 24
Finished Aug 10 06:14:11 PM PDT 24
Peak memory 198296 kb
Host smart-3171d2aa-cbdd-4abf-9761-99e2fdbe5666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049052653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2049052653
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.4177880590
Short name T118
Test name
Test status
Simulation time 72849242625 ps
CPU time 16.33 seconds
Started Aug 10 06:14:16 PM PDT 24
Finished Aug 10 06:14:32 PM PDT 24
Peak memory 199880 kb
Host smart-a5741963-9492-429c-89cc-789945f2ad4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177880590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.4177880590
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.960193908
Short name T326
Test name
Test status
Simulation time 27466168420 ps
CPU time 265.65 seconds
Started Aug 10 06:14:17 PM PDT 24
Finished Aug 10 06:18:43 PM PDT 24
Peak memory 212648 kb
Host smart-8a90f513-b679-49c6-9125-38056647b9bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960193908 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.960193908
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.1853968563
Short name T384
Test name
Test status
Simulation time 411012851 ps
CPU time 1.38 seconds
Started Aug 10 06:14:15 PM PDT 24
Finished Aug 10 06:14:16 PM PDT 24
Peak memory 197004 kb
Host smart-63590c81-e0db-403b-aaaa-fed375fc206d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853968563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1853968563
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1144902911
Short name T1117
Test name
Test status
Simulation time 82319743339 ps
CPU time 166.11 seconds
Started Aug 10 06:14:11 PM PDT 24
Finished Aug 10 06:16:57 PM PDT 24
Peak memory 199860 kb
Host smart-be1453a5-7ab5-409f-8ea8-b9b15daf75e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144902911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1144902911
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1395825302
Short name T378
Test name
Test status
Simulation time 33677110 ps
CPU time 0.56 seconds
Started Aug 10 06:14:18 PM PDT 24
Finished Aug 10 06:14:18 PM PDT 24
Peak memory 195304 kb
Host smart-e62b86c4-6f36-443e-ab7a-54437d9604e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395825302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1395825302
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.1375276712
Short name T38
Test name
Test status
Simulation time 32208360285 ps
CPU time 45.04 seconds
Started Aug 10 06:14:15 PM PDT 24
Finished Aug 10 06:15:01 PM PDT 24
Peak memory 199844 kb
Host smart-9ee1ac28-274a-46a3-bb36-e94bf573add4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375276712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1375276712
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2222926186
Short name T295
Test name
Test status
Simulation time 21849443744 ps
CPU time 36.75 seconds
Started Aug 10 06:14:16 PM PDT 24
Finished Aug 10 06:14:53 PM PDT 24
Peak memory 199904 kb
Host smart-641b8e2d-b344-4d55-a5ec-993dde977a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222926186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2222926186
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_intr.2421896602
Short name T537
Test name
Test status
Simulation time 52751676980 ps
CPU time 20.85 seconds
Started Aug 10 06:14:16 PM PDT 24
Finished Aug 10 06:14:37 PM PDT 24
Peak memory 199920 kb
Host smart-594ac26d-72db-4666-a070-c2e2827273c0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421896602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2421896602
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.546489288
Short name T322
Test name
Test status
Simulation time 72495480806 ps
CPU time 84.07 seconds
Started Aug 10 06:14:17 PM PDT 24
Finished Aug 10 06:15:41 PM PDT 24
Peak memory 199952 kb
Host smart-ed11a3d3-fa45-49f9-92f0-a2f37d3e0bae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=546489288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.546489288
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3663327335
Short name T1075
Test name
Test status
Simulation time 3432235722 ps
CPU time 6.42 seconds
Started Aug 10 06:14:15 PM PDT 24
Finished Aug 10 06:14:21 PM PDT 24
Peak memory 196340 kb
Host smart-d6179f4a-85e7-4573-ac65-c48c95b1b86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663327335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3663327335
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2825430144
Short name T1048
Test name
Test status
Simulation time 51766038292 ps
CPU time 88.78 seconds
Started Aug 10 06:14:17 PM PDT 24
Finished Aug 10 06:15:46 PM PDT 24
Peak memory 200020 kb
Host smart-a8c7f2a2-c39d-4d8b-b6d3-2439a26ea5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825430144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2825430144
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.2890102132
Short name T586
Test name
Test status
Simulation time 10279022465 ps
CPU time 105.34 seconds
Started Aug 10 06:14:13 PM PDT 24
Finished Aug 10 06:15:59 PM PDT 24
Peak memory 199960 kb
Host smart-7ee50a90-3342-4ed2-9806-85ea07e89281
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2890102132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2890102132
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.982217002
Short name T671
Test name
Test status
Simulation time 3085693739 ps
CPU time 6.35 seconds
Started Aug 10 06:14:15 PM PDT 24
Finished Aug 10 06:14:22 PM PDT 24
Peak memory 199248 kb
Host smart-52fa662e-ed67-42ea-8454-2a0257242807
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=982217002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.982217002
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3728868867
Short name T640
Test name
Test status
Simulation time 135102931069 ps
CPU time 55.86 seconds
Started Aug 10 06:14:17 PM PDT 24
Finished Aug 10 06:15:13 PM PDT 24
Peak memory 199964 kb
Host smart-6c4f5f70-a5fa-4b67-b6a0-6c4e69896475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728868867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3728868867
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.4078093625
Short name T1021
Test name
Test status
Simulation time 2886171855 ps
CPU time 1.89 seconds
Started Aug 10 06:14:15 PM PDT 24
Finished Aug 10 06:14:17 PM PDT 24
Peak memory 195996 kb
Host smart-b1968043-12d1-4aaa-afab-dd170566294e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078093625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.4078093625
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3778929440
Short name T813
Test name
Test status
Simulation time 417669705 ps
CPU time 1.8 seconds
Started Aug 10 06:14:13 PM PDT 24
Finished Aug 10 06:14:15 PM PDT 24
Peak memory 198088 kb
Host smart-8b7e0788-6bbb-4027-91fe-ec5f81f820a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778929440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3778929440
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.3731799910
Short name T1107
Test name
Test status
Simulation time 239850096727 ps
CPU time 1026.13 seconds
Started Aug 10 06:14:16 PM PDT 24
Finished Aug 10 06:31:23 PM PDT 24
Peak memory 199852 kb
Host smart-fe676d60-98ac-48cc-910a-0b47e114aba5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731799910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3731799910
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.3474320361
Short name T57
Test name
Test status
Simulation time 194651317088 ps
CPU time 356.32 seconds
Started Aug 10 06:14:18 PM PDT 24
Finished Aug 10 06:20:14 PM PDT 24
Peak memory 216564 kb
Host smart-f5173161-0c26-40de-a45c-8f2871b6a1bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474320361 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3474320361
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.3982570949
Short name T985
Test name
Test status
Simulation time 1000501787 ps
CPU time 1.82 seconds
Started Aug 10 06:14:14 PM PDT 24
Finished Aug 10 06:14:17 PM PDT 24
Peak memory 198784 kb
Host smart-96e80def-f444-4789-9003-fade4eba8162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982570949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3982570949
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.3373124204
Short name T715
Test name
Test status
Simulation time 80709215901 ps
CPU time 30.83 seconds
Started Aug 10 06:14:15 PM PDT 24
Finished Aug 10 06:14:46 PM PDT 24
Peak memory 199804 kb
Host smart-bbe58178-3d86-4ebf-8a8a-9c4457b22a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373124204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.3373124204
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3675310956
Short name T382
Test name
Test status
Simulation time 15165281 ps
CPU time 0.57 seconds
Started Aug 10 06:14:22 PM PDT 24
Finished Aug 10 06:14:23 PM PDT 24
Peak memory 195348 kb
Host smart-b5ecc7f4-5228-4230-94d5-99dda82cc22f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675310956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3675310956
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2301780013
Short name T259
Test name
Test status
Simulation time 7678773772 ps
CPU time 3.98 seconds
Started Aug 10 06:14:28 PM PDT 24
Finished Aug 10 06:14:32 PM PDT 24
Peak memory 199924 kb
Host smart-7ab18580-e4f0-4f00-99bc-1f529850cb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301780013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2301780013
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1626241444
Short name T655
Test name
Test status
Simulation time 80151580983 ps
CPU time 41.68 seconds
Started Aug 10 06:14:21 PM PDT 24
Finished Aug 10 06:15:03 PM PDT 24
Peak memory 200004 kb
Host smart-fff047dd-d77a-4071-bb84-4d27adf702bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626241444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1626241444
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.4119171498
Short name T600
Test name
Test status
Simulation time 218998205043 ps
CPU time 47.96 seconds
Started Aug 10 06:14:30 PM PDT 24
Finished Aug 10 06:15:18 PM PDT 24
Peak memory 199964 kb
Host smart-69aab89d-a1e3-4586-909b-01a18414ac7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119171498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.4119171498
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1902726183
Short name T826
Test name
Test status
Simulation time 9866208670 ps
CPU time 5.19 seconds
Started Aug 10 06:14:30 PM PDT 24
Finished Aug 10 06:14:35 PM PDT 24
Peak memory 199904 kb
Host smart-4d1fdb41-c7dc-4a7a-a0db-ee5fef94b1e0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902726183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1902726183
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.3498836069
Short name T958
Test name
Test status
Simulation time 64989775841 ps
CPU time 398.37 seconds
Started Aug 10 06:14:29 PM PDT 24
Finished Aug 10 06:21:08 PM PDT 24
Peak memory 199964 kb
Host smart-dd497e40-125c-4b80-8044-ed09ee5acaa8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3498836069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3498836069
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1404038933
Short name T1036
Test name
Test status
Simulation time 7534064416 ps
CPU time 21.28 seconds
Started Aug 10 06:14:29 PM PDT 24
Finished Aug 10 06:14:51 PM PDT 24
Peak memory 199892 kb
Host smart-ceee1143-b2d2-4a75-8d3d-8d8de6396a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404038933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1404038933
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.721182760
Short name T545
Test name
Test status
Simulation time 131120541533 ps
CPU time 53.6 seconds
Started Aug 10 06:14:20 PM PDT 24
Finished Aug 10 06:15:13 PM PDT 24
Peak memory 198804 kb
Host smart-d43a51ed-2707-4a3d-a17e-0bedc0487615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721182760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.721182760
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.1117917033
Short name T325
Test name
Test status
Simulation time 11096099954 ps
CPU time 122.81 seconds
Started Aug 10 06:14:27 PM PDT 24
Finished Aug 10 06:16:30 PM PDT 24
Peak memory 199904 kb
Host smart-08e2f974-e265-4d42-9b7c-5eca85a641a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1117917033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.1117917033
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.3072085511
Short name T1115
Test name
Test status
Simulation time 7211181476 ps
CPU time 59.86 seconds
Started Aug 10 06:14:29 PM PDT 24
Finished Aug 10 06:15:29 PM PDT 24
Peak memory 198032 kb
Host smart-917ebdbe-659f-4273-a6b0-eb786a9dc0a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3072085511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3072085511
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2273441345
Short name T772
Test name
Test status
Simulation time 84519009052 ps
CPU time 136.7 seconds
Started Aug 10 06:14:29 PM PDT 24
Finished Aug 10 06:16:46 PM PDT 24
Peak memory 199892 kb
Host smart-00228045-c309-4fa1-9981-167aa3a2d50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273441345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2273441345
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.248198657
Short name T858
Test name
Test status
Simulation time 607148285 ps
CPU time 1.57 seconds
Started Aug 10 06:14:31 PM PDT 24
Finished Aug 10 06:14:33 PM PDT 24
Peak memory 195584 kb
Host smart-6cfb3ccb-9586-4845-b608-c22578fb2543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248198657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.248198657
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3401827240
Short name T1055
Test name
Test status
Simulation time 721329792 ps
CPU time 1.47 seconds
Started Aug 10 06:14:14 PM PDT 24
Finished Aug 10 06:14:16 PM PDT 24
Peak memory 198252 kb
Host smart-f2f0151b-550b-4fa3-8470-4504384a672d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401827240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3401827240
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.872629473
Short name T750
Test name
Test status
Simulation time 83145201381 ps
CPU time 36.33 seconds
Started Aug 10 06:14:27 PM PDT 24
Finished Aug 10 06:15:04 PM PDT 24
Peak memory 199976 kb
Host smart-dc9a5c60-b160-493d-9163-30f073214e4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872629473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.872629473
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1594556490
Short name T18
Test name
Test status
Simulation time 20547441956 ps
CPU time 203.28 seconds
Started Aug 10 06:14:22 PM PDT 24
Finished Aug 10 06:17:45 PM PDT 24
Peak memory 216448 kb
Host smart-adc01e6d-c19e-41fe-9260-25a1280740e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594556490 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1594556490
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.672295802
Short name T1047
Test name
Test status
Simulation time 1051638528 ps
CPU time 3.17 seconds
Started Aug 10 06:14:25 PM PDT 24
Finished Aug 10 06:14:28 PM PDT 24
Peak memory 199652 kb
Host smart-1831ed73-daca-417c-acd5-cd952cf745ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672295802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.672295802
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1648695611
Short name T1131
Test name
Test status
Simulation time 83966396158 ps
CPU time 65.19 seconds
Started Aug 10 06:14:27 PM PDT 24
Finished Aug 10 06:15:33 PM PDT 24
Peak memory 199876 kb
Host smart-dde2204c-c930-4d90-be66-7dfd484f1a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648695611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1648695611
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.267476343
Short name T749
Test name
Test status
Simulation time 17314135 ps
CPU time 0.53 seconds
Started Aug 10 06:14:27 PM PDT 24
Finished Aug 10 06:14:28 PM PDT 24
Peak memory 194808 kb
Host smart-80257f45-a556-45e0-a7cb-f357bf431314
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267476343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.267476343
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3786065034
Short name T763
Test name
Test status
Simulation time 74535075107 ps
CPU time 11.67 seconds
Started Aug 10 06:14:25 PM PDT 24
Finished Aug 10 06:14:37 PM PDT 24
Peak memory 199812 kb
Host smart-fe2385fe-2241-49d1-9144-88a7419bd0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786065034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3786065034
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.1544445334
Short name T489
Test name
Test status
Simulation time 89999739689 ps
CPU time 89.22 seconds
Started Aug 10 06:14:23 PM PDT 24
Finished Aug 10 06:15:52 PM PDT 24
Peak memory 199996 kb
Host smart-1cb43d67-b48e-48bd-97b8-4a58af599b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544445334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1544445334
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.65648249
Short name T1144
Test name
Test status
Simulation time 104229456549 ps
CPU time 41.63 seconds
Started Aug 10 06:14:22 PM PDT 24
Finished Aug 10 06:15:04 PM PDT 24
Peak memory 199976 kb
Host smart-40082134-4cad-4af5-abce-582637c57bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65648249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.65648249
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.752194599
Short name T121
Test name
Test status
Simulation time 44415162438 ps
CPU time 41.95 seconds
Started Aug 10 06:14:28 PM PDT 24
Finished Aug 10 06:15:10 PM PDT 24
Peak memory 199944 kb
Host smart-8b5b799a-5811-4543-9ca3-2dab2bbd2696
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752194599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.752194599
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1167373256
Short name T491
Test name
Test status
Simulation time 50389125917 ps
CPU time 341.21 seconds
Started Aug 10 06:14:29 PM PDT 24
Finished Aug 10 06:20:10 PM PDT 24
Peak memory 199984 kb
Host smart-7d54c031-74b2-49a8-a369-c697764e5769
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1167373256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1167373256
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.3597917702
Short name T390
Test name
Test status
Simulation time 8136636102 ps
CPU time 14.94 seconds
Started Aug 10 06:14:27 PM PDT 24
Finished Aug 10 06:14:42 PM PDT 24
Peak memory 199924 kb
Host smart-ff857502-34fd-4e29-b127-b3fcd98309a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597917702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3597917702
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.3169860117
Short name T287
Test name
Test status
Simulation time 311602632027 ps
CPU time 83.24 seconds
Started Aug 10 06:14:28 PM PDT 24
Finished Aug 10 06:15:52 PM PDT 24
Peak memory 208248 kb
Host smart-384a721b-aac5-45fd-8f03-82975d961598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169860117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3169860117
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.4028226281
Short name T735
Test name
Test status
Simulation time 3771062389 ps
CPU time 54.29 seconds
Started Aug 10 06:14:32 PM PDT 24
Finished Aug 10 06:15:26 PM PDT 24
Peak memory 199944 kb
Host smart-575a7076-f6e8-43e6-bbd7-d45d1afa4e32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4028226281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.4028226281
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.681497306
Short name T459
Test name
Test status
Simulation time 4064906734 ps
CPU time 17.48 seconds
Started Aug 10 06:14:29 PM PDT 24
Finished Aug 10 06:14:46 PM PDT 24
Peak memory 198088 kb
Host smart-ec3b81dd-4165-4a25-af27-5c8432eaca6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=681497306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.681497306
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2262612643
Short name T149
Test name
Test status
Simulation time 12646225829 ps
CPU time 33.18 seconds
Started Aug 10 06:14:31 PM PDT 24
Finished Aug 10 06:15:05 PM PDT 24
Peak memory 199900 kb
Host smart-585ed434-2340-4a8d-8abc-d2c243988213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262612643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2262612643
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.2155222196
Short name T404
Test name
Test status
Simulation time 5857257408 ps
CPU time 8.5 seconds
Started Aug 10 06:14:29 PM PDT 24
Finished Aug 10 06:14:38 PM PDT 24
Peak memory 196164 kb
Host smart-8329dfa2-81b2-4d7c-82d0-56edab52ce94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155222196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2155222196
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.1289837099
Short name T899
Test name
Test status
Simulation time 89667997 ps
CPU time 0.92 seconds
Started Aug 10 06:14:31 PM PDT 24
Finished Aug 10 06:14:32 PM PDT 24
Peak memory 199176 kb
Host smart-35369a0b-2342-4262-ac8d-5870aa32ef19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289837099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1289837099
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.1535667772
Short name T747
Test name
Test status
Simulation time 194171907777 ps
CPU time 266.58 seconds
Started Aug 10 06:14:30 PM PDT 24
Finished Aug 10 06:18:57 PM PDT 24
Peak memory 199980 kb
Host smart-9bc80ed5-8dad-47f8-a54e-c43e5b3d5716
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535667772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1535667772
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.237433849
Short name T1060
Test name
Test status
Simulation time 33549735019 ps
CPU time 197.71 seconds
Started Aug 10 06:14:30 PM PDT 24
Finished Aug 10 06:17:48 PM PDT 24
Peak memory 208268 kb
Host smart-9ef4b365-fe2d-481b-a8bd-ced8c0fec678
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237433849 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.237433849
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.3073077868
Short name T941
Test name
Test status
Simulation time 6877072881 ps
CPU time 19.26 seconds
Started Aug 10 06:14:28 PM PDT 24
Finished Aug 10 06:14:47 PM PDT 24
Peak memory 199912 kb
Host smart-92cc7525-4ebd-4af3-9089-d7512842f424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073077868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.3073077868
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.3139791589
Short name T263
Test name
Test status
Simulation time 168940604070 ps
CPU time 64.11 seconds
Started Aug 10 06:14:27 PM PDT 24
Finished Aug 10 06:15:31 PM PDT 24
Peak memory 199872 kb
Host smart-0d3d5896-49b4-4711-bee8-34d351a0022c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139791589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3139791589
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.2110643452
Short name T569
Test name
Test status
Simulation time 65778763 ps
CPU time 0.52 seconds
Started Aug 10 06:09:29 PM PDT 24
Finished Aug 10 06:09:30 PM PDT 24
Peak memory 194808 kb
Host smart-86aac6f4-bd80-4596-80c6-709ef40d675e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110643452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2110643452
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1121445134
Short name T832
Test name
Test status
Simulation time 65051443998 ps
CPU time 92.45 seconds
Started Aug 10 06:09:20 PM PDT 24
Finished Aug 10 06:10:52 PM PDT 24
Peak memory 199908 kb
Host smart-3fc23293-d7c4-463f-9511-4a41f0fbed68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121445134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1121445134
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.4220346542
Short name T752
Test name
Test status
Simulation time 124487299100 ps
CPU time 101.32 seconds
Started Aug 10 06:09:18 PM PDT 24
Finished Aug 10 06:11:00 PM PDT 24
Peak memory 199948 kb
Host smart-b70eedaf-da03-49b6-8cd7-de69b84d3e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220346542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.4220346542
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3801989551
Short name T762
Test name
Test status
Simulation time 22822694169 ps
CPU time 45.96 seconds
Started Aug 10 06:09:18 PM PDT 24
Finished Aug 10 06:10:04 PM PDT 24
Peak memory 199900 kb
Host smart-059b50a2-4c08-42a5-8e91-967d7625131a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801989551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3801989551
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1858516704
Short name T898
Test name
Test status
Simulation time 5871606099 ps
CPU time 9.2 seconds
Started Aug 10 06:09:29 PM PDT 24
Finished Aug 10 06:09:38 PM PDT 24
Peak memory 199900 kb
Host smart-eebc9802-ebba-4e71-bceb-3c3bdad3ec67
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858516704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1858516704
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.3520859866
Short name T595
Test name
Test status
Simulation time 135463666063 ps
CPU time 884.62 seconds
Started Aug 10 06:09:27 PM PDT 24
Finished Aug 10 06:24:12 PM PDT 24
Peak memory 199956 kb
Host smart-af86a0f7-36a1-4ab2-9633-dafffe9a6b8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3520859866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3520859866
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.2531340641
Short name T428
Test name
Test status
Simulation time 7449578030 ps
CPU time 16.34 seconds
Started Aug 10 06:09:28 PM PDT 24
Finished Aug 10 06:09:45 PM PDT 24
Peak memory 198412 kb
Host smart-5bce7f1a-4c92-4360-a70e-e4d8301f92c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531340641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2531340641
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.336760070
Short name T629
Test name
Test status
Simulation time 94002585819 ps
CPU time 39.75 seconds
Started Aug 10 06:09:30 PM PDT 24
Finished Aug 10 06:10:10 PM PDT 24
Peak memory 199928 kb
Host smart-ad6197cc-1a05-4039-bf90-acc0fc144edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336760070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.336760070
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2280455136
Short name T1018
Test name
Test status
Simulation time 9390600655 ps
CPU time 291.53 seconds
Started Aug 10 06:09:29 PM PDT 24
Finished Aug 10 06:14:20 PM PDT 24
Peak memory 199920 kb
Host smart-ff14795a-4729-4de3-8672-e00878c676d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2280455136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2280455136
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.903636565
Short name T406
Test name
Test status
Simulation time 3379691228 ps
CPU time 6.84 seconds
Started Aug 10 06:09:28 PM PDT 24
Finished Aug 10 06:09:35 PM PDT 24
Peak memory 199136 kb
Host smart-0a872e9a-fbb3-49dd-aad9-6629d54001db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=903636565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.903636565
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1757855120
Short name T861
Test name
Test status
Simulation time 126177517473 ps
CPU time 171.44 seconds
Started Aug 10 06:09:28 PM PDT 24
Finished Aug 10 06:12:20 PM PDT 24
Peak memory 199948 kb
Host smart-90ee97fc-d96c-4446-8ee5-48670333837e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757855120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1757855120
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1258696165
Short name T1052
Test name
Test status
Simulation time 38968140146 ps
CPU time 52.3 seconds
Started Aug 10 06:09:29 PM PDT 24
Finished Aug 10 06:10:22 PM PDT 24
Peak memory 196024 kb
Host smart-d97a8e8e-1172-4e14-847d-facdbcbf349b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258696165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1258696165
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2731100553
Short name T1181
Test name
Test status
Simulation time 5960051143 ps
CPU time 6.55 seconds
Started Aug 10 06:09:18 PM PDT 24
Finished Aug 10 06:09:25 PM PDT 24
Peak memory 199116 kb
Host smart-9b3f6f02-1f2e-4e80-adfd-74365ee0313f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731100553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2731100553
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.296591900
Short name T494
Test name
Test status
Simulation time 199300062055 ps
CPU time 744.51 seconds
Started Aug 10 06:09:26 PM PDT 24
Finished Aug 10 06:21:51 PM PDT 24
Peak memory 199884 kb
Host smart-0537b904-d0d9-414b-b046-6cc52dbd1f48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296591900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.296591900
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.421722775
Short name T795
Test name
Test status
Simulation time 54804204217 ps
CPU time 551.15 seconds
Started Aug 10 06:09:29 PM PDT 24
Finished Aug 10 06:18:40 PM PDT 24
Peak memory 216500 kb
Host smart-a5a156e1-cb18-4281-9e07-8255e2966e35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421722775 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.421722775
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1868356626
Short name T881
Test name
Test status
Simulation time 1214626956 ps
CPU time 5.41 seconds
Started Aug 10 06:09:29 PM PDT 24
Finished Aug 10 06:09:34 PM PDT 24
Peak memory 199664 kb
Host smart-92b56209-fbf3-48f3-a484-3644294e6637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868356626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1868356626
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1237068216
Short name T707
Test name
Test status
Simulation time 74808576784 ps
CPU time 127.46 seconds
Started Aug 10 06:09:17 PM PDT 24
Finished Aug 10 06:11:25 PM PDT 24
Peak memory 199920 kb
Host smart-be8edfad-8f97-4973-a574-8ce821d10df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237068216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1237068216
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.3247297893
Short name T1011
Test name
Test status
Simulation time 110503704887 ps
CPU time 42.81 seconds
Started Aug 10 06:14:29 PM PDT 24
Finished Aug 10 06:15:12 PM PDT 24
Peak memory 199972 kb
Host smart-ff83fd4c-4175-4acc-ab68-401ff6838e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247297893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.3247297893
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.201067725
Short name T339
Test name
Test status
Simulation time 219048337503 ps
CPU time 1260.53 seconds
Started Aug 10 06:14:31 PM PDT 24
Finished Aug 10 06:35:32 PM PDT 24
Peak memory 224688 kb
Host smart-a8a043d9-336a-4eb4-a2ea-7fa7eeb5f04e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201067725 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.201067725
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.3480784279
Short name T444
Test name
Test status
Simulation time 72747223308 ps
CPU time 54.87 seconds
Started Aug 10 06:14:31 PM PDT 24
Finished Aug 10 06:15:26 PM PDT 24
Peak memory 199512 kb
Host smart-2afb1b5c-2d90-4b56-9484-d3feb32ec741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480784279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3480784279
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1566518725
Short name T546
Test name
Test status
Simulation time 48301247359 ps
CPU time 160.56 seconds
Started Aug 10 06:14:31 PM PDT 24
Finished Aug 10 06:17:12 PM PDT 24
Peak memory 208284 kb
Host smart-9edf078e-a2c0-42e5-b618-e89ab114310a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566518725 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1566518725
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.3646469998
Short name T1057
Test name
Test status
Simulation time 221671101863 ps
CPU time 785.08 seconds
Started Aug 10 06:14:30 PM PDT 24
Finished Aug 10 06:27:35 PM PDT 24
Peak memory 225212 kb
Host smart-90486086-810b-4913-97d0-d1080a7ce7a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646469998 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.3646469998
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3204863444
Short name T986
Test name
Test status
Simulation time 84326527338 ps
CPU time 70.41 seconds
Started Aug 10 06:14:28 PM PDT 24
Finished Aug 10 06:15:39 PM PDT 24
Peak memory 200000 kb
Host smart-3e98bad0-7dfa-404b-99eb-0567bcb6c24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204863444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3204863444
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.2925299832
Short name T17
Test name
Test status
Simulation time 25468573573 ps
CPU time 477.12 seconds
Started Aug 10 06:14:27 PM PDT 24
Finished Aug 10 06:22:25 PM PDT 24
Peak memory 216408 kb
Host smart-c02e4142-11e0-4944-8204-4c2e4933a29b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925299832 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2925299832
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.4179536460
Short name T632
Test name
Test status
Simulation time 25975866774 ps
CPU time 18.07 seconds
Started Aug 10 06:14:29 PM PDT 24
Finished Aug 10 06:14:47 PM PDT 24
Peak memory 199964 kb
Host smart-3281072f-51c6-43a4-b130-9cc64126a3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179536460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.4179536460
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1427606078
Short name T718
Test name
Test status
Simulation time 137282952112 ps
CPU time 24.54 seconds
Started Aug 10 06:14:38 PM PDT 24
Finished Aug 10 06:15:02 PM PDT 24
Peak memory 199964 kb
Host smart-4a14df08-a64d-479f-9932-672f3d5c1d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427606078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1427606078
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2888136101
Short name T700
Test name
Test status
Simulation time 269523351306 ps
CPU time 1163.42 seconds
Started Aug 10 06:14:36 PM PDT 24
Finished Aug 10 06:34:00 PM PDT 24
Peak memory 216428 kb
Host smart-79f7fa03-86c0-474e-9eee-61ed63e4a38a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888136101 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2888136101
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.3141626357
Short name T674
Test name
Test status
Simulation time 6683249631 ps
CPU time 13.88 seconds
Started Aug 10 06:14:38 PM PDT 24
Finished Aug 10 06:14:52 PM PDT 24
Peak memory 199964 kb
Host smart-11c3ba15-91ba-4012-9edc-e8b639a442b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141626357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3141626357
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.322521448
Short name T694
Test name
Test status
Simulation time 123251078093 ps
CPU time 692.35 seconds
Started Aug 10 06:14:39 PM PDT 24
Finished Aug 10 06:26:12 PM PDT 24
Peak memory 216432 kb
Host smart-8ecc5eba-3d26-442a-8d66-bc00bd55cddb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322521448 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.322521448
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.615547455
Short name T1083
Test name
Test status
Simulation time 61956928180 ps
CPU time 101.05 seconds
Started Aug 10 06:14:38 PM PDT 24
Finished Aug 10 06:16:19 PM PDT 24
Peak memory 199960 kb
Host smart-701800a4-a326-4af2-870d-7a49f01dd830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615547455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.615547455
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.881744731
Short name T163
Test name
Test status
Simulation time 96970820920 ps
CPU time 199.63 seconds
Started Aug 10 06:14:35 PM PDT 24
Finished Aug 10 06:17:55 PM PDT 24
Peak memory 216496 kb
Host smart-478794e7-8e9e-49bd-bc16-69969b3bdb1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881744731 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.881744731
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.1794691933
Short name T1099
Test name
Test status
Simulation time 26257231977 ps
CPU time 50.19 seconds
Started Aug 10 06:14:40 PM PDT 24
Finished Aug 10 06:15:31 PM PDT 24
Peak memory 210740 kb
Host smart-498a27fc-b06f-47df-a768-67d156d6986e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794691933 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.1794691933
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.4246924199
Short name T220
Test name
Test status
Simulation time 12146192309 ps
CPU time 18.66 seconds
Started Aug 10 06:14:36 PM PDT 24
Finished Aug 10 06:14:55 PM PDT 24
Peak memory 199864 kb
Host smart-bb06b4fa-021c-4ec2-b72d-3c4977c9ee85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246924199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.4246924199
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.848936027
Short name T968
Test name
Test status
Simulation time 234232808080 ps
CPU time 572.48 seconds
Started Aug 10 06:14:38 PM PDT 24
Finished Aug 10 06:24:10 PM PDT 24
Peak memory 224772 kb
Host smart-358d5e58-2beb-4357-93d5-87feaa1cd300
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848936027 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.848936027
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.2268932819
Short name T1167
Test name
Test status
Simulation time 13090984 ps
CPU time 0.54 seconds
Started Aug 10 06:09:36 PM PDT 24
Finished Aug 10 06:09:37 PM PDT 24
Peak memory 195328 kb
Host smart-b9104d65-520b-4d38-97ff-a932e2384e7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268932819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2268932819
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1068363624
Short name T311
Test name
Test status
Simulation time 39700458669 ps
CPU time 30.45 seconds
Started Aug 10 06:09:37 PM PDT 24
Finished Aug 10 06:10:08 PM PDT 24
Peak memory 199756 kb
Host smart-7ead2da9-f997-47bc-b8e1-85efc44a6326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068363624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1068363624
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.4068817520
Short name T348
Test name
Test status
Simulation time 64495019989 ps
CPU time 127.59 seconds
Started Aug 10 06:09:40 PM PDT 24
Finished Aug 10 06:11:48 PM PDT 24
Peak memory 199896 kb
Host smart-fe98d1b4-429a-4c10-8d04-95936844566f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068817520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.4068817520
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.3085973489
Short name T599
Test name
Test status
Simulation time 49350815399 ps
CPU time 79.37 seconds
Started Aug 10 06:09:37 PM PDT 24
Finished Aug 10 06:10:57 PM PDT 24
Peak memory 199892 kb
Host smart-ccfc5c64-0683-4e95-b589-7b2de5adc721
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085973489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3085973489
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.2873765947
Short name T605
Test name
Test status
Simulation time 145015784402 ps
CPU time 803.1 seconds
Started Aug 10 06:09:38 PM PDT 24
Finished Aug 10 06:23:01 PM PDT 24
Peak memory 199868 kb
Host smart-33cf7b7a-dd09-4027-83c1-e42c9bdb05b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2873765947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2873765947
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.233674001
Short name T1023
Test name
Test status
Simulation time 2973001626 ps
CPU time 3.58 seconds
Started Aug 10 06:09:38 PM PDT 24
Finished Aug 10 06:09:42 PM PDT 24
Peak memory 198728 kb
Host smart-aac386f2-c869-452f-af48-348762063354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233674001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.233674001
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.622714021
Short name T293
Test name
Test status
Simulation time 61569287216 ps
CPU time 25.11 seconds
Started Aug 10 06:09:38 PM PDT 24
Finished Aug 10 06:10:03 PM PDT 24
Peak memory 199960 kb
Host smart-9bc2192b-e93a-4486-ba4d-7c1c4f13a531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622714021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.622714021
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.2591490514
Short name T732
Test name
Test status
Simulation time 13057905130 ps
CPU time 618.79 seconds
Started Aug 10 06:09:38 PM PDT 24
Finished Aug 10 06:19:57 PM PDT 24
Peak memory 199976 kb
Host smart-1051211d-4c62-444d-a077-e8dcbc2a8ea3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2591490514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2591490514
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.2101154005
Short name T602
Test name
Test status
Simulation time 7030183171 ps
CPU time 15.05 seconds
Started Aug 10 06:09:39 PM PDT 24
Finished Aug 10 06:09:54 PM PDT 24
Peak memory 198144 kb
Host smart-70f68a2c-a2a7-48aa-80ac-5d8d0ba21ae0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2101154005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2101154005
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2001863440
Short name T1173
Test name
Test status
Simulation time 288776753325 ps
CPU time 94.33 seconds
Started Aug 10 06:09:42 PM PDT 24
Finished Aug 10 06:11:16 PM PDT 24
Peak memory 199908 kb
Host smart-3e4d3495-81fb-4e1e-961c-8a1fc3b19fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001863440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2001863440
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.3919206883
Short name T338
Test name
Test status
Simulation time 635933740 ps
CPU time 1.07 seconds
Started Aug 10 06:09:36 PM PDT 24
Finished Aug 10 06:09:37 PM PDT 24
Peak memory 195480 kb
Host smart-74d3b2d4-3f6a-4160-9785-a105602488df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919206883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3919206883
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.3224974506
Short name T333
Test name
Test status
Simulation time 312754230 ps
CPU time 1.25 seconds
Started Aug 10 06:09:30 PM PDT 24
Finished Aug 10 06:09:31 PM PDT 24
Peak memory 198864 kb
Host smart-1577f8dc-4511-4866-bd7d-2a3bc4e3bb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224974506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3224974506
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.950284053
Short name T210
Test name
Test status
Simulation time 149421711441 ps
CPU time 254.56 seconds
Started Aug 10 06:09:41 PM PDT 24
Finished Aug 10 06:13:56 PM PDT 24
Peak memory 199796 kb
Host smart-62b6bc39-5d1a-49c0-ab5e-1c47bb2c7658
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950284053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.950284053
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.210256377
Short name T501
Test name
Test status
Simulation time 3527624958 ps
CPU time 2.09 seconds
Started Aug 10 06:09:40 PM PDT 24
Finished Aug 10 06:09:43 PM PDT 24
Peak memory 199868 kb
Host smart-0ca591ef-5012-4747-99dd-7f5d0da729c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210256377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.210256377
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.3334979212
Short name T803
Test name
Test status
Simulation time 46104765139 ps
CPU time 78.69 seconds
Started Aug 10 06:09:29 PM PDT 24
Finished Aug 10 06:10:48 PM PDT 24
Peak memory 199944 kb
Host smart-81fe9fd9-af65-43cd-9eb8-009afea37746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334979212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3334979212
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.86778663
Short name T130
Test name
Test status
Simulation time 58543230228 ps
CPU time 8.52 seconds
Started Aug 10 06:14:36 PM PDT 24
Finished Aug 10 06:14:44 PM PDT 24
Peak memory 199880 kb
Host smart-55b4de7c-6193-41fc-a48b-3345cd9c8c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86778663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.86778663
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.346978404
Short name T178
Test name
Test status
Simulation time 164833435110 ps
CPU time 810.39 seconds
Started Aug 10 06:14:36 PM PDT 24
Finished Aug 10 06:28:07 PM PDT 24
Peak memory 227064 kb
Host smart-7d733fc0-329e-4d78-99e7-ee0c53b32ab4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346978404 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.346978404
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.1847844518
Short name T193
Test name
Test status
Simulation time 30111465434 ps
CPU time 43.72 seconds
Started Aug 10 06:14:35 PM PDT 24
Finished Aug 10 06:15:19 PM PDT 24
Peak memory 199832 kb
Host smart-4163cbb3-4611-4521-af55-aad36e89bbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847844518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1847844518
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.831030806
Short name T802
Test name
Test status
Simulation time 37109388380 ps
CPU time 327.73 seconds
Started Aug 10 06:14:34 PM PDT 24
Finished Aug 10 06:20:02 PM PDT 24
Peak memory 208296 kb
Host smart-93297f88-c5de-4889-b443-996104acc15f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831030806 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.831030806
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1111450873
Short name T337
Test name
Test status
Simulation time 162927331416 ps
CPU time 63.42 seconds
Started Aug 10 06:14:41 PM PDT 24
Finished Aug 10 06:15:45 PM PDT 24
Peak memory 199928 kb
Host smart-232645d3-eaac-4263-8eae-168a2069f14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111450873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1111450873
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.2188977085
Short name T866
Test name
Test status
Simulation time 216362252208 ps
CPU time 519.73 seconds
Started Aug 10 06:14:42 PM PDT 24
Finished Aug 10 06:23:22 PM PDT 24
Peak memory 224840 kb
Host smart-ce1d0da5-68f0-4b62-a715-a9495079df80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188977085 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.2188977085
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.4110326682
Short name T285
Test name
Test status
Simulation time 86295556119 ps
CPU time 73.21 seconds
Started Aug 10 06:14:45 PM PDT 24
Finished Aug 10 06:15:58 PM PDT 24
Peak memory 199900 kb
Host smart-20c0dc7c-50a6-4735-9b39-d17ce48d9e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110326682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.4110326682
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1397889918
Short name T880
Test name
Test status
Simulation time 208647137796 ps
CPU time 1066.03 seconds
Started Aug 10 06:14:41 PM PDT 24
Finished Aug 10 06:32:27 PM PDT 24
Peak memory 224812 kb
Host smart-aa5b9e72-59cf-4996-b87a-8bd00a415d8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397889918 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1397889918
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.204002793
Short name T766
Test name
Test status
Simulation time 262341648218 ps
CPU time 69.11 seconds
Started Aug 10 06:14:46 PM PDT 24
Finished Aug 10 06:15:55 PM PDT 24
Peak memory 199916 kb
Host smart-604330c0-38fd-48aa-9764-3cfdd7561d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204002793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.204002793
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.3078322602
Short name T271
Test name
Test status
Simulation time 18669485181 ps
CPU time 421.69 seconds
Started Aug 10 06:14:46 PM PDT 24
Finished Aug 10 06:21:48 PM PDT 24
Peak memory 208292 kb
Host smart-5f95e1b9-0d30-4e10-a968-61941a3de10e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078322602 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.3078322602
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3032079344
Short name T277
Test name
Test status
Simulation time 19915723518 ps
CPU time 24.23 seconds
Started Aug 10 06:14:42 PM PDT 24
Finished Aug 10 06:15:06 PM PDT 24
Peak memory 200144 kb
Host smart-046d9596-8080-440e-bde7-96e86f1217c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032079344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3032079344
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3686523930
Short name T825
Test name
Test status
Simulation time 30177169056 ps
CPU time 340.35 seconds
Started Aug 10 06:14:47 PM PDT 24
Finished Aug 10 06:20:27 PM PDT 24
Peak memory 207264 kb
Host smart-bb37f650-acbb-4aeb-95ac-d1cb79712749
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686523930 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3686523930
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1514452719
Short name T1061
Test name
Test status
Simulation time 51986575969 ps
CPU time 24.88 seconds
Started Aug 10 06:14:40 PM PDT 24
Finished Aug 10 06:15:05 PM PDT 24
Peak memory 199964 kb
Host smart-56f6103f-0c8e-4190-98df-bd4a023ed37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514452719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1514452719
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.3136885649
Short name T703
Test name
Test status
Simulation time 40517859001 ps
CPU time 367.29 seconds
Started Aug 10 06:14:42 PM PDT 24
Finished Aug 10 06:20:49 PM PDT 24
Peak memory 216440 kb
Host smart-16cb64f9-5f9d-43c1-911a-eaadbe54ba2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136885649 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.3136885649
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.3380381319
Short name T222
Test name
Test status
Simulation time 54529462999 ps
CPU time 78.89 seconds
Started Aug 10 06:14:42 PM PDT 24
Finished Aug 10 06:16:01 PM PDT 24
Peak memory 199948 kb
Host smart-79a9f549-8ff7-4693-8a84-dbb8f5c7d49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380381319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3380381319
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.4168209177
Short name T304
Test name
Test status
Simulation time 10016037045 ps
CPU time 230.22 seconds
Started Aug 10 06:14:43 PM PDT 24
Finished Aug 10 06:18:33 PM PDT 24
Peak memory 208420 kb
Host smart-1eac8c35-2190-46c8-8d6b-cb37e07b0aab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168209177 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.4168209177
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.2361688283
Short name T675
Test name
Test status
Simulation time 30599116734 ps
CPU time 30.26 seconds
Started Aug 10 06:14:41 PM PDT 24
Finished Aug 10 06:15:12 PM PDT 24
Peak memory 199784 kb
Host smart-f16d59f9-cfd4-4af1-8ba9-cf94b722b734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361688283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2361688283
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.3744270656
Short name T800
Test name
Test status
Simulation time 337455360675 ps
CPU time 628.27 seconds
Started Aug 10 06:14:42 PM PDT 24
Finished Aug 10 06:25:11 PM PDT 24
Peak memory 216624 kb
Host smart-0c75ba32-bedb-4794-8272-1c60c7582489
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744270656 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.3744270656
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2267992977
Short name T1085
Test name
Test status
Simulation time 12455173 ps
CPU time 0.56 seconds
Started Aug 10 06:09:46 PM PDT 24
Finished Aug 10 06:09:47 PM PDT 24
Peak memory 195328 kb
Host smart-0141558b-b304-4572-8180-b8eeed328834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267992977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2267992977
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3324231948
Short name T1026
Test name
Test status
Simulation time 100892349428 ps
CPU time 43.55 seconds
Started Aug 10 06:09:37 PM PDT 24
Finished Aug 10 06:10:21 PM PDT 24
Peak memory 199976 kb
Host smart-19e1c786-0797-4146-927a-632d1455a2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324231948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3324231948
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3794388990
Short name T794
Test name
Test status
Simulation time 13150188533 ps
CPU time 7.22 seconds
Started Aug 10 06:09:37 PM PDT 24
Finished Aug 10 06:09:44 PM PDT 24
Peak memory 199316 kb
Host smart-88657787-a27b-47ae-ac9a-120d7547c2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794388990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3794388990
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.3411250185
Short name T847
Test name
Test status
Simulation time 194157051902 ps
CPU time 373.39 seconds
Started Aug 10 06:09:37 PM PDT 24
Finished Aug 10 06:15:51 PM PDT 24
Peak memory 199924 kb
Host smart-e1748b0b-440a-4377-b35d-f4fdb8a96439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411250185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.3411250185
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1747561933
Short name T422
Test name
Test status
Simulation time 9112220607 ps
CPU time 15.82 seconds
Started Aug 10 06:09:40 PM PDT 24
Finished Aug 10 06:09:56 PM PDT 24
Peak memory 199968 kb
Host smart-dca9055b-bf31-47f9-9823-1f42bd5d985c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747561933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1747561933
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3213751282
Short name T267
Test name
Test status
Simulation time 97470428669 ps
CPU time 185.94 seconds
Started Aug 10 06:09:45 PM PDT 24
Finished Aug 10 06:12:51 PM PDT 24
Peak memory 199964 kb
Host smart-44c5818e-ca2d-4502-af2f-83115a7ff63e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3213751282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3213751282
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1146193542
Short name T407
Test name
Test status
Simulation time 2113422985 ps
CPU time 1.18 seconds
Started Aug 10 06:09:49 PM PDT 24
Finished Aug 10 06:09:50 PM PDT 24
Peak memory 196924 kb
Host smart-8da6dc0e-d86b-40a3-aba9-a7ff003df820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146193542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1146193542
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.681372832
Short name T667
Test name
Test status
Simulation time 123345310743 ps
CPU time 116.19 seconds
Started Aug 10 06:09:44 PM PDT 24
Finished Aug 10 06:11:41 PM PDT 24
Peak memory 199960 kb
Host smart-8e88de19-2421-48de-bd29-8b470b1d54ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681372832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.681372832
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.1597108868
Short name T908
Test name
Test status
Simulation time 8224942932 ps
CPU time 44.39 seconds
Started Aug 10 06:09:46 PM PDT 24
Finished Aug 10 06:10:31 PM PDT 24
Peak memory 199836 kb
Host smart-805c7366-1086-48e6-9ac4-b522f7389724
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1597108868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1597108868
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.2938511322
Short name T413
Test name
Test status
Simulation time 6659219683 ps
CPU time 29.11 seconds
Started Aug 10 06:09:42 PM PDT 24
Finished Aug 10 06:10:11 PM PDT 24
Peak memory 198712 kb
Host smart-6c0922c7-4145-4bef-8320-417243916060
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2938511322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2938511322
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.2819322290
Short name T332
Test name
Test status
Simulation time 67364521552 ps
CPU time 56.08 seconds
Started Aug 10 06:09:46 PM PDT 24
Finished Aug 10 06:10:43 PM PDT 24
Peak memory 199884 kb
Host smart-c21d253a-111b-4f6e-bc04-9ab8229129c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819322290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2819322290
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.2895785770
Short name T836
Test name
Test status
Simulation time 39499367127 ps
CPU time 60.29 seconds
Started Aug 10 06:09:45 PM PDT 24
Finished Aug 10 06:10:46 PM PDT 24
Peak memory 196820 kb
Host smart-2335551e-fc67-4f98-8854-cd219cd9ec13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895785770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2895785770
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1416384263
Short name T578
Test name
Test status
Simulation time 5542908936 ps
CPU time 7.67 seconds
Started Aug 10 06:09:38 PM PDT 24
Finished Aug 10 06:09:46 PM PDT 24
Peak memory 199664 kb
Host smart-f9560cfc-e73a-4bf7-b980-429b9d6db360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416384263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1416384263
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.3579268848
Short name T1025
Test name
Test status
Simulation time 113275684830 ps
CPU time 42.57 seconds
Started Aug 10 06:09:46 PM PDT 24
Finished Aug 10 06:10:28 PM PDT 24
Peak memory 199964 kb
Host smart-c4febf95-2efd-4113-a023-68550d5c387a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579268848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3579268848
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3284040250
Short name T155
Test name
Test status
Simulation time 282521018923 ps
CPU time 1464.48 seconds
Started Aug 10 06:09:46 PM PDT 24
Finished Aug 10 06:34:11 PM PDT 24
Peak memory 224832 kb
Host smart-bd9a0abe-0e87-445d-a4f2-4a12bde7878d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284040250 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3284040250
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.1060112014
Short name T316
Test name
Test status
Simulation time 796005054 ps
CPU time 2.16 seconds
Started Aug 10 06:09:46 PM PDT 24
Finished Aug 10 06:09:49 PM PDT 24
Peak memory 198400 kb
Host smart-a35954b6-51ad-43e8-96db-b4b765f0dca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060112014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1060112014
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.3319584101
Short name T746
Test name
Test status
Simulation time 55777397504 ps
CPU time 23.96 seconds
Started Aug 10 06:09:41 PM PDT 24
Finished Aug 10 06:10:05 PM PDT 24
Peak memory 199836 kb
Host smart-9140f851-493d-4ec8-b3c9-f5304be8a9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319584101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3319584101
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2572559252
Short name T830
Test name
Test status
Simulation time 28598886740 ps
CPU time 12.23 seconds
Started Aug 10 06:14:45 PM PDT 24
Finished Aug 10 06:14:57 PM PDT 24
Peak memory 199904 kb
Host smart-9f611d4f-2eab-4e4e-abc6-e09392cc3f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572559252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2572559252
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1909208076
Short name T628
Test name
Test status
Simulation time 131294981728 ps
CPU time 218.62 seconds
Started Aug 10 06:14:47 PM PDT 24
Finished Aug 10 06:18:26 PM PDT 24
Peak memory 198672 kb
Host smart-ddb58b23-4580-4223-8482-465258ca94a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909208076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1909208076
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.992942704
Short name T103
Test name
Test status
Simulation time 48603292751 ps
CPU time 118.79 seconds
Started Aug 10 06:14:47 PM PDT 24
Finished Aug 10 06:16:46 PM PDT 24
Peak memory 214868 kb
Host smart-107fdc05-c706-47cc-ae4f-5eee9426003f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992942704 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.992942704
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.2231380951
Short name T221
Test name
Test status
Simulation time 55474449238 ps
CPU time 24.3 seconds
Started Aug 10 06:14:42 PM PDT 24
Finished Aug 10 06:15:06 PM PDT 24
Peak memory 199964 kb
Host smart-36f33ef4-9e42-46c8-9b86-97fa060e3fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231380951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2231380951
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3595697626
Short name T997
Test name
Test status
Simulation time 31583532137 ps
CPU time 157.71 seconds
Started Aug 10 06:14:45 PM PDT 24
Finished Aug 10 06:17:23 PM PDT 24
Peak memory 216628 kb
Host smart-6bba4c82-d0d8-4917-8fac-597696536b02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595697626 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3595697626
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.4122174969
Short name T816
Test name
Test status
Simulation time 65696464904 ps
CPU time 37.99 seconds
Started Aug 10 06:14:46 PM PDT 24
Finished Aug 10 06:15:24 PM PDT 24
Peak memory 199984 kb
Host smart-3797ce5d-d437-4f7d-ac54-abe879b3ec76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122174969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.4122174969
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3643255498
Short name T1017
Test name
Test status
Simulation time 45369496006 ps
CPU time 560.95 seconds
Started Aug 10 06:14:50 PM PDT 24
Finished Aug 10 06:24:11 PM PDT 24
Peak memory 215652 kb
Host smart-bf10ffcb-f3ef-4e09-965c-f888a87ed3cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643255498 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3643255498
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.198278128
Short name T228
Test name
Test status
Simulation time 140417135022 ps
CPU time 13.84 seconds
Started Aug 10 06:14:51 PM PDT 24
Finished Aug 10 06:15:05 PM PDT 24
Peak memory 199972 kb
Host smart-e5c84383-caf4-4e69-9421-c3530692b418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198278128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.198278128
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1211864631
Short name T983
Test name
Test status
Simulation time 62742653127 ps
CPU time 561.98 seconds
Started Aug 10 06:14:52 PM PDT 24
Finished Aug 10 06:24:14 PM PDT 24
Peak memory 224836 kb
Host smart-23ce87ed-3dcf-4e4e-aef8-a48d516fe6fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211864631 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1211864631
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3112075598
Short name T907
Test name
Test status
Simulation time 65670465929 ps
CPU time 109.38 seconds
Started Aug 10 06:14:48 PM PDT 24
Finished Aug 10 06:16:38 PM PDT 24
Peak memory 199848 kb
Host smart-49c18f5a-1639-452b-8ac8-3acec0dbc6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112075598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3112075598
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.146454588
Short name T346
Test name
Test status
Simulation time 193136713990 ps
CPU time 117.09 seconds
Started Aug 10 06:14:49 PM PDT 24
Finished Aug 10 06:16:46 PM PDT 24
Peak memory 199952 kb
Host smart-bc36bd7d-dbdb-4d96-aea7-0f90a6b0e568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146454588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.146454588
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.2854054856
Short name T108
Test name
Test status
Simulation time 150430344103 ps
CPU time 229.82 seconds
Started Aug 10 06:14:50 PM PDT 24
Finished Aug 10 06:18:40 PM PDT 24
Peak memory 211456 kb
Host smart-909b9423-8099-46a4-b24b-1aa30ff980d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854054856 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2854054856
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.3589156301
Short name T741
Test name
Test status
Simulation time 32746485837 ps
CPU time 48.45 seconds
Started Aug 10 06:14:50 PM PDT 24
Finished Aug 10 06:15:38 PM PDT 24
Peak memory 199876 kb
Host smart-f5531e6b-9181-4c4d-b40a-222cee68b44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589156301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3589156301
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1593075848
Short name T909
Test name
Test status
Simulation time 94022167819 ps
CPU time 226.37 seconds
Started Aug 10 06:14:51 PM PDT 24
Finished Aug 10 06:18:37 PM PDT 24
Peak memory 216504 kb
Host smart-f9a6e47b-6795-4e34-9a44-2d1f9618c85e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593075848 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1593075848
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.2903649873
Short name T736
Test name
Test status
Simulation time 86457112899 ps
CPU time 149.6 seconds
Started Aug 10 06:14:48 PM PDT 24
Finished Aug 10 06:17:18 PM PDT 24
Peak memory 199928 kb
Host smart-cae489f3-1719-4ca7-aa42-18a2f363db5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903649873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2903649873
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2481711286
Short name T436
Test name
Test status
Simulation time 55592208500 ps
CPU time 363.06 seconds
Started Aug 10 06:14:51 PM PDT 24
Finished Aug 10 06:20:55 PM PDT 24
Peak memory 215252 kb
Host smart-f18e413f-0612-41ab-b592-20d33f3b005d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481711286 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2481711286
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2335098102
Short name T42
Test name
Test status
Simulation time 151976537481 ps
CPU time 299.31 seconds
Started Aug 10 06:14:49 PM PDT 24
Finished Aug 10 06:19:49 PM PDT 24
Peak memory 199988 kb
Host smart-ea2f1ad0-e245-446a-a498-ddf56565f3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335098102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2335098102
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.1746562093
Short name T1179
Test name
Test status
Simulation time 99043779827 ps
CPU time 1331.44 seconds
Started Aug 10 06:14:51 PM PDT 24
Finished Aug 10 06:37:02 PM PDT 24
Peak memory 227348 kb
Host smart-d1413f1e-bd2c-4358-a290-1a8323571b59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746562093 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.1746562093
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2909164601
Short name T403
Test name
Test status
Simulation time 32554359 ps
CPU time 0.53 seconds
Started Aug 10 06:09:53 PM PDT 24
Finished Aug 10 06:09:53 PM PDT 24
Peak memory 194340 kb
Host smart-4c2860a7-9e1f-4e61-9ffc-20924ca46e9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909164601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2909164601
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.2454650679
Short name T328
Test name
Test status
Simulation time 202839492896 ps
CPU time 19.14 seconds
Started Aug 10 06:09:49 PM PDT 24
Finished Aug 10 06:10:08 PM PDT 24
Peak memory 199652 kb
Host smart-1dc4625d-8edf-47e0-be1e-7e7a1f975095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454650679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2454650679
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1736668295
Short name T547
Test name
Test status
Simulation time 89516533363 ps
CPU time 34.06 seconds
Started Aug 10 06:09:56 PM PDT 24
Finished Aug 10 06:10:30 PM PDT 24
Peak memory 199568 kb
Host smart-4ae8c9a3-28eb-46f4-9252-ea39c5e4d2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736668295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1736668295
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.1453163063
Short name T204
Test name
Test status
Simulation time 69528125656 ps
CPU time 146.02 seconds
Started Aug 10 06:09:54 PM PDT 24
Finished Aug 10 06:12:20 PM PDT 24
Peak memory 199860 kb
Host smart-1487d4b9-2181-4722-bc0d-a06ec1edf75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453163063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1453163063
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3013885004
Short name T1010
Test name
Test status
Simulation time 170304712897 ps
CPU time 216.91 seconds
Started Aug 10 06:09:58 PM PDT 24
Finished Aug 10 06:13:35 PM PDT 24
Peak memory 199920 kb
Host smart-742d7ce6-4363-4cb3-b779-bb8d5b10e5e8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013885004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3013885004
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.1548106706
Short name T1086
Test name
Test status
Simulation time 72529753948 ps
CPU time 187.5 seconds
Started Aug 10 06:09:56 PM PDT 24
Finished Aug 10 06:13:03 PM PDT 24
Peak memory 199880 kb
Host smart-ed9f42e2-f4ca-4c64-9d1b-358f4e088394
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1548106706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1548106706
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.375229863
Short name T362
Test name
Test status
Simulation time 6598328757 ps
CPU time 12.76 seconds
Started Aug 10 06:09:58 PM PDT 24
Finished Aug 10 06:10:11 PM PDT 24
Peak memory 199796 kb
Host smart-1330b504-663a-4f17-9498-16dcc1f65cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375229863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.375229863
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.3642313024
Short name T1110
Test name
Test status
Simulation time 155021610413 ps
CPU time 81.37 seconds
Started Aug 10 06:09:58 PM PDT 24
Finished Aug 10 06:11:20 PM PDT 24
Peak memory 199964 kb
Host smart-64806f34-42b0-41c7-af84-4b4b5272e0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642313024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3642313024
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.1511948828
Short name T1134
Test name
Test status
Simulation time 16986329428 ps
CPU time 965.55 seconds
Started Aug 10 06:09:54 PM PDT 24
Finished Aug 10 06:26:00 PM PDT 24
Peak memory 199900 kb
Host smart-c7e1714f-5f19-4cbd-a610-e3e1f60a40d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1511948828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1511948828
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1662826825
Short name T552
Test name
Test status
Simulation time 5578241995 ps
CPU time 11.06 seconds
Started Aug 10 06:09:53 PM PDT 24
Finished Aug 10 06:10:04 PM PDT 24
Peak memory 198084 kb
Host smart-50eb35c4-2cbd-47a6-bdea-bba85d57f135
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1662826825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1662826825
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3115879233
Short name T979
Test name
Test status
Simulation time 16164404378 ps
CPU time 22.89 seconds
Started Aug 10 06:09:55 PM PDT 24
Finished Aug 10 06:10:18 PM PDT 24
Peak memory 199896 kb
Host smart-86314bae-d0e1-4f39-aa6d-3ad2a4f99cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115879233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3115879233
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2131843669
Short name T1159
Test name
Test status
Simulation time 2180754039 ps
CPU time 2.1 seconds
Started Aug 10 06:09:53 PM PDT 24
Finished Aug 10 06:09:55 PM PDT 24
Peak memory 195684 kb
Host smart-bb69b69c-64f7-4418-8529-3b478be17fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131843669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2131843669
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.4288543895
Short name T575
Test name
Test status
Simulation time 272324753 ps
CPU time 1.28 seconds
Started Aug 10 06:09:45 PM PDT 24
Finished Aug 10 06:09:47 PM PDT 24
Peak memory 198804 kb
Host smart-1926b897-596a-4fec-a091-e85e8ab54a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288543895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.4288543895
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.3847969320
Short name T515
Test name
Test status
Simulation time 224758675273 ps
CPU time 577.94 seconds
Started Aug 10 06:09:55 PM PDT 24
Finished Aug 10 06:19:33 PM PDT 24
Peak memory 208260 kb
Host smart-32177207-8251-4b02-b719-88d621895641
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847969320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3847969320
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1566805582
Short name T1030
Test name
Test status
Simulation time 296694956685 ps
CPU time 710.59 seconds
Started Aug 10 06:09:55 PM PDT 24
Finished Aug 10 06:21:45 PM PDT 24
Peak memory 224940 kb
Host smart-148b33b8-ebf9-4718-b8b3-ece57c051c28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566805582 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1566805582
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3674434215
Short name T510
Test name
Test status
Simulation time 441716377 ps
CPU time 1.42 seconds
Started Aug 10 06:09:53 PM PDT 24
Finished Aug 10 06:09:54 PM PDT 24
Peak memory 197176 kb
Host smart-9e1a9352-c6df-49e7-a527-1ab52abb082e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674434215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3674434215
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3060442537
Short name T808
Test name
Test status
Simulation time 45384331475 ps
CPU time 17.03 seconds
Started Aug 10 06:09:46 PM PDT 24
Finished Aug 10 06:10:04 PM PDT 24
Peak memory 199828 kb
Host smart-ce250936-9e25-433a-af7b-cb77d2b8d209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060442537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3060442537
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.51586207
Short name T1033
Test name
Test status
Simulation time 49990105726 ps
CPU time 16.29 seconds
Started Aug 10 06:14:49 PM PDT 24
Finished Aug 10 06:15:06 PM PDT 24
Peak memory 199984 kb
Host smart-75467261-2a0f-4f3f-ba33-fd68a68f9dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51586207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.51586207
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2835318737
Short name T30
Test name
Test status
Simulation time 133059492432 ps
CPU time 748.7 seconds
Started Aug 10 06:14:49 PM PDT 24
Finished Aug 10 06:27:18 PM PDT 24
Peak memory 226632 kb
Host smart-cfca64cb-173a-49de-8a5f-6bd7375f4ff8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835318737 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2835318737
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.890721298
Short name T641
Test name
Test status
Simulation time 90429355213 ps
CPU time 34.73 seconds
Started Aug 10 06:14:52 PM PDT 24
Finished Aug 10 06:15:26 PM PDT 24
Peak memory 199476 kb
Host smart-cb6fac82-1768-4de9-9e6d-e1e6a18be308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890721298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.890721298
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.647388564
Short name T568
Test name
Test status
Simulation time 63168223447 ps
CPU time 832.49 seconds
Started Aug 10 06:14:48 PM PDT 24
Finished Aug 10 06:28:41 PM PDT 24
Peak memory 224936 kb
Host smart-38b86006-fa08-4cd5-9ce6-d935e41e1c55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647388564 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.647388564
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.1442489143
Short name T1022
Test name
Test status
Simulation time 20695884757 ps
CPU time 39.82 seconds
Started Aug 10 06:14:49 PM PDT 24
Finished Aug 10 06:15:29 PM PDT 24
Peak memory 199880 kb
Host smart-25907971-7f23-461e-8c25-c03bcfcecc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442489143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1442489143
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3304074902
Short name T158
Test name
Test status
Simulation time 58331787704 ps
CPU time 578.86 seconds
Started Aug 10 06:14:51 PM PDT 24
Finished Aug 10 06:24:30 PM PDT 24
Peak memory 216608 kb
Host smart-b4d4fd11-bd12-45e5-b521-de8656777954
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304074902 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3304074902
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2023702701
Short name T256
Test name
Test status
Simulation time 16592305928 ps
CPU time 8.62 seconds
Started Aug 10 06:14:50 PM PDT 24
Finished Aug 10 06:14:59 PM PDT 24
Peak memory 199904 kb
Host smart-bc64c0fd-371b-497c-a663-ce65cc6c10e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023702701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2023702701
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.3911165120
Short name T918
Test name
Test status
Simulation time 132261908089 ps
CPU time 286.11 seconds
Started Aug 10 06:14:50 PM PDT 24
Finished Aug 10 06:19:37 PM PDT 24
Peak memory 216472 kb
Host smart-e21bb27a-ba95-4d5a-8fbe-e555f6a12fbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911165120 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.3911165120
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3187071198
Short name T894
Test name
Test status
Simulation time 106538755437 ps
CPU time 74.3 seconds
Started Aug 10 06:14:48 PM PDT 24
Finished Aug 10 06:16:03 PM PDT 24
Peak memory 199772 kb
Host smart-06c0a7c0-fcbd-48b1-a7bd-d7eefa469404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187071198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3187071198
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.3896021899
Short name T972
Test name
Test status
Simulation time 104858305752 ps
CPU time 431.48 seconds
Started Aug 10 06:14:51 PM PDT 24
Finished Aug 10 06:22:02 PM PDT 24
Peak memory 216440 kb
Host smart-ceec191a-5fd1-4d89-a2ec-414ce71a9a6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896021899 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3896021899
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2467639701
Short name T200
Test name
Test status
Simulation time 149521554177 ps
CPU time 33.4 seconds
Started Aug 10 06:14:51 PM PDT 24
Finished Aug 10 06:15:25 PM PDT 24
Peak memory 199940 kb
Host smart-483ee6b1-cbfb-409c-8459-6cdea0083865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467639701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2467639701
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.526629504
Short name T577
Test name
Test status
Simulation time 83125143734 ps
CPU time 1387.52 seconds
Started Aug 10 06:14:50 PM PDT 24
Finished Aug 10 06:37:58 PM PDT 24
Peak memory 224952 kb
Host smart-6e468405-2e9a-45f8-bb22-a74264ad23ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526629504 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.526629504
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.179063663
Short name T1165
Test name
Test status
Simulation time 77573220756 ps
CPU time 28.91 seconds
Started Aug 10 06:14:52 PM PDT 24
Finished Aug 10 06:15:21 PM PDT 24
Peak memory 199468 kb
Host smart-1efe396f-5bfa-4cf7-89bf-04966040f159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179063663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.179063663
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3488094297
Short name T897
Test name
Test status
Simulation time 59579046416 ps
CPU time 268.93 seconds
Started Aug 10 06:14:58 PM PDT 24
Finished Aug 10 06:19:27 PM PDT 24
Peak memory 216236 kb
Host smart-798c4888-5143-414a-a64c-1b14a906784a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488094297 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3488094297
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3763897874
Short name T865
Test name
Test status
Simulation time 30160669426 ps
CPU time 12.39 seconds
Started Aug 10 06:14:58 PM PDT 24
Finished Aug 10 06:15:10 PM PDT 24
Peak memory 199912 kb
Host smart-b3a4e799-08ad-49e2-b719-3908be6d6cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763897874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3763897874
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.4120412173
Short name T686
Test name
Test status
Simulation time 82956176356 ps
CPU time 224.97 seconds
Started Aug 10 06:14:55 PM PDT 24
Finished Aug 10 06:18:41 PM PDT 24
Peak memory 213348 kb
Host smart-a9ef63f1-caa3-4586-966a-463894088333
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120412173 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.4120412173
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1198093093
Short name T842
Test name
Test status
Simulation time 36674849648 ps
CPU time 55.15 seconds
Started Aug 10 06:14:57 PM PDT 24
Finished Aug 10 06:15:52 PM PDT 24
Peak memory 199904 kb
Host smart-057fd554-225d-4840-8ddb-6778e7741e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198093093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1198093093
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3696078656
Short name T146
Test name
Test status
Simulation time 165358297852 ps
CPU time 460.12 seconds
Started Aug 10 06:14:56 PM PDT 24
Finished Aug 10 06:22:36 PM PDT 24
Peak memory 224744 kb
Host smart-57b0df68-ca0a-40d0-a41f-a145bab85104
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696078656 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3696078656
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2361053008
Short name T760
Test name
Test status
Simulation time 298125094436 ps
CPU time 502.57 seconds
Started Aug 10 06:14:58 PM PDT 24
Finished Aug 10 06:23:21 PM PDT 24
Peak memory 212076 kb
Host smart-cc3cdf5f-084a-474d-aecd-02b7fe51ce99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361053008 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2361053008
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.80742824
Short name T884
Test name
Test status
Simulation time 30660453 ps
CPU time 0.57 seconds
Started Aug 10 06:10:03 PM PDT 24
Finished Aug 10 06:10:04 PM PDT 24
Peak memory 195004 kb
Host smart-705c0be0-d38c-4c4e-bc2b-b1b7bb56bb44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80742824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.80742824
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.2811264956
Short name T507
Test name
Test status
Simulation time 75887391598 ps
CPU time 114.49 seconds
Started Aug 10 06:09:53 PM PDT 24
Finished Aug 10 06:11:48 PM PDT 24
Peak memory 199840 kb
Host smart-a62edc40-74b0-42bc-a4f6-2c1f36e6026d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811264956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2811264956
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.3583219993
Short name T1113
Test name
Test status
Simulation time 124065730375 ps
CPU time 87.39 seconds
Started Aug 10 06:10:03 PM PDT 24
Finished Aug 10 06:11:30 PM PDT 24
Peak memory 199856 kb
Host smart-ff85e547-a5d6-4c8d-b696-837f0e9eed3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583219993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3583219993
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1960078521
Short name T266
Test name
Test status
Simulation time 35879991156 ps
CPU time 74.97 seconds
Started Aug 10 06:10:02 PM PDT 24
Finished Aug 10 06:11:17 PM PDT 24
Peak memory 199960 kb
Host smart-2c106d02-2e13-474d-be92-33c9beaa42c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960078521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1960078521
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.1330476995
Short name T944
Test name
Test status
Simulation time 13597614496 ps
CPU time 12.02 seconds
Started Aug 10 06:10:02 PM PDT 24
Finished Aug 10 06:10:14 PM PDT 24
Peak memory 200152 kb
Host smart-eee8a654-4f30-4bc7-bf3f-3b14d9c517d5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330476995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1330476995
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.3917149609
Short name T926
Test name
Test status
Simulation time 214804249722 ps
CPU time 177.44 seconds
Started Aug 10 06:10:09 PM PDT 24
Finished Aug 10 06:13:06 PM PDT 24
Peak memory 199844 kb
Host smart-8114e223-c644-41a8-bdbd-1cd02bbed5f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3917149609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3917149609
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1325894813
Short name T373
Test name
Test status
Simulation time 1178449403 ps
CPU time 1.66 seconds
Started Aug 10 06:10:02 PM PDT 24
Finished Aug 10 06:10:04 PM PDT 24
Peak memory 198488 kb
Host smart-520895a9-ca42-4e1b-8b46-557cc46d338e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325894813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1325894813
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1233108277
Short name T334
Test name
Test status
Simulation time 23024651664 ps
CPU time 35.96 seconds
Started Aug 10 06:10:00 PM PDT 24
Finished Aug 10 06:10:36 PM PDT 24
Peak memory 198572 kb
Host smart-b7757469-ccef-4054-9c81-1e954bb49c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233108277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1233108277
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.3663569463
Short name T523
Test name
Test status
Simulation time 12901859466 ps
CPU time 310.29 seconds
Started Aug 10 06:10:03 PM PDT 24
Finished Aug 10 06:15:14 PM PDT 24
Peak memory 199836 kb
Host smart-20b09635-cb29-470b-a662-6288997b42cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3663569463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3663569463
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1747231400
Short name T645
Test name
Test status
Simulation time 5890982522 ps
CPU time 47.3 seconds
Started Aug 10 06:10:03 PM PDT 24
Finished Aug 10 06:10:50 PM PDT 24
Peak memory 198304 kb
Host smart-bfb2f772-27e1-4cc9-9f00-262fb8b9836f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1747231400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1747231400
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2479469286
Short name T393
Test name
Test status
Simulation time 23691886980 ps
CPU time 54.18 seconds
Started Aug 10 06:10:01 PM PDT 24
Finished Aug 10 06:10:55 PM PDT 24
Peak memory 199864 kb
Host smart-89f67640-3ab9-4519-9418-0696436a3115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479469286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2479469286
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1624283376
Short name T443
Test name
Test status
Simulation time 47141813833 ps
CPU time 75.27 seconds
Started Aug 10 06:10:02 PM PDT 24
Finished Aug 10 06:11:17 PM PDT 24
Peak memory 195828 kb
Host smart-ff41d685-eb59-4036-adc3-bf6f30b898d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624283376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1624283376
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.425338872
Short name T875
Test name
Test status
Simulation time 5440585501 ps
CPU time 15.53 seconds
Started Aug 10 06:09:57 PM PDT 24
Finished Aug 10 06:10:13 PM PDT 24
Peak memory 199736 kb
Host smart-be50b392-47a8-4ca3-8625-81ed3a818923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425338872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.425338872
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3253846156
Short name T636
Test name
Test status
Simulation time 168579992191 ps
CPU time 293.44 seconds
Started Aug 10 06:10:02 PM PDT 24
Finished Aug 10 06:14:55 PM PDT 24
Peak memory 199992 kb
Host smart-be427f40-dd41-405a-873d-8ad8b4274b51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253846156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3253846156
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.4015894579
Short name T727
Test name
Test status
Simulation time 80663605851 ps
CPU time 726.5 seconds
Started Aug 10 06:10:08 PM PDT 24
Finished Aug 10 06:22:15 PM PDT 24
Peak memory 224828 kb
Host smart-91787dfd-7cbe-457d-8b22-10df9f7e4217
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015894579 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.4015894579
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.4222727054
Short name T440
Test name
Test status
Simulation time 806920263 ps
CPU time 1.81 seconds
Started Aug 10 06:10:01 PM PDT 24
Finished Aug 10 06:10:03 PM PDT 24
Peak memory 198324 kb
Host smart-f1eae105-5135-4735-aa5f-01cbd04d3253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222727054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.4222727054
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.997642551
Short name T1070
Test name
Test status
Simulation time 5311059479 ps
CPU time 5.59 seconds
Started Aug 10 06:09:54 PM PDT 24
Finished Aug 10 06:09:59 PM PDT 24
Peak memory 199808 kb
Host smart-8295db06-83ce-4b07-b578-3b992c644861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997642551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.997642551
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.1190671458
Short name T1143
Test name
Test status
Simulation time 159521487469 ps
CPU time 96.63 seconds
Started Aug 10 06:14:58 PM PDT 24
Finished Aug 10 06:16:35 PM PDT 24
Peak memory 199904 kb
Host smart-9e0f87cd-e7bb-416d-973b-73beaa391de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190671458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1190671458
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.1558929472
Short name T191
Test name
Test status
Simulation time 67478395976 ps
CPU time 58.92 seconds
Started Aug 10 06:14:57 PM PDT 24
Finished Aug 10 06:15:56 PM PDT 24
Peak memory 199884 kb
Host smart-cb315388-8e98-42d9-a01c-106393c38297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558929472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1558929472
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.1972510346
Short name T106
Test name
Test status
Simulation time 38583070175 ps
CPU time 444.6 seconds
Started Aug 10 06:14:57 PM PDT 24
Finished Aug 10 06:22:21 PM PDT 24
Peak memory 208400 kb
Host smart-19658fc7-6204-4aa2-afdc-5739af6d6a8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972510346 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1972510346
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3745383527
Short name T815
Test name
Test status
Simulation time 106175666755 ps
CPU time 153.33 seconds
Started Aug 10 06:14:56 PM PDT 24
Finished Aug 10 06:17:29 PM PDT 24
Peak memory 199864 kb
Host smart-7017516d-ee8b-402f-8f10-e8caecebdaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745383527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3745383527
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3267983915
Short name T737
Test name
Test status
Simulation time 80748466385 ps
CPU time 176.39 seconds
Started Aug 10 06:14:56 PM PDT 24
Finished Aug 10 06:17:53 PM PDT 24
Peak memory 213232 kb
Host smart-547c29da-29d8-42c2-a517-c7e6146432c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267983915 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3267983915
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.795246625
Short name T1177
Test name
Test status
Simulation time 31449491867 ps
CPU time 12.41 seconds
Started Aug 10 06:14:57 PM PDT 24
Finished Aug 10 06:15:09 PM PDT 24
Peak memory 199984 kb
Host smart-2af6c41d-d298-41d7-b14a-70f2cc683b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795246625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.795246625
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.258757022
Short name T31
Test name
Test status
Simulation time 47647040421 ps
CPU time 796.26 seconds
Started Aug 10 06:14:57 PM PDT 24
Finished Aug 10 06:28:13 PM PDT 24
Peak memory 224964 kb
Host smart-6423afe7-c528-4688-8808-e89edcc03542
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258757022 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.258757022
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.1799772891
Short name T395
Test name
Test status
Simulation time 29379372619 ps
CPU time 41.49 seconds
Started Aug 10 06:14:57 PM PDT 24
Finished Aug 10 06:15:39 PM PDT 24
Peak memory 199692 kb
Host smart-2f8f5991-e97e-4c21-b49a-4c9ce0fc1186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799772891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1799772891
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.2703520810
Short name T540
Test name
Test status
Simulation time 82968873797 ps
CPU time 1304.34 seconds
Started Aug 10 06:14:58 PM PDT 24
Finished Aug 10 06:36:42 PM PDT 24
Peak memory 225152 kb
Host smart-aab1e0bc-e9f7-4193-8b62-3e5bfa73c539
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703520810 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.2703520810
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.925873516
Short name T768
Test name
Test status
Simulation time 64719789264 ps
CPU time 27.97 seconds
Started Aug 10 06:14:56 PM PDT 24
Finished Aug 10 06:15:24 PM PDT 24
Peak memory 199976 kb
Host smart-78200494-e8fd-4392-aba7-93f1ee5420a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925873516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.925873516
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.3684375040
Short name T292
Test name
Test status
Simulation time 19916723597 ps
CPU time 229.74 seconds
Started Aug 10 06:14:57 PM PDT 24
Finished Aug 10 06:18:47 PM PDT 24
Peak memory 216604 kb
Host smart-b4d1b69b-3bd4-44cf-b0f8-19b87901f765
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684375040 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3684375040
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3882500736
Short name T887
Test name
Test status
Simulation time 131578102731 ps
CPU time 109.57 seconds
Started Aug 10 06:15:00 PM PDT 24
Finished Aug 10 06:16:49 PM PDT 24
Peak memory 199692 kb
Host smart-93cd3616-1854-4079-8323-23e101cbc5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882500736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3882500736
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.1535379236
Short name T536
Test name
Test status
Simulation time 235477590389 ps
CPU time 877.11 seconds
Started Aug 10 06:14:55 PM PDT 24
Finished Aug 10 06:29:32 PM PDT 24
Peak memory 220888 kb
Host smart-18022eee-796b-48b8-a347-5b49bf377903
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535379236 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.1535379236
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.1891608492
Short name T186
Test name
Test status
Simulation time 20291073648 ps
CPU time 32.88 seconds
Started Aug 10 06:14:55 PM PDT 24
Finished Aug 10 06:15:28 PM PDT 24
Peak memory 199972 kb
Host smart-d3d17c56-14be-4733-9c74-36dec035579f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891608492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1891608492
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3311074318
Short name T1114
Test name
Test status
Simulation time 27301497709 ps
CPU time 296.87 seconds
Started Aug 10 06:14:57 PM PDT 24
Finished Aug 10 06:19:54 PM PDT 24
Peak memory 216496 kb
Host smart-b1249658-fe16-43f0-88bf-786c94877342
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311074318 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3311074318
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1054510456
Short name T538
Test name
Test status
Simulation time 78064577653 ps
CPU time 109.37 seconds
Started Aug 10 06:14:58 PM PDT 24
Finished Aug 10 06:16:47 PM PDT 24
Peak memory 199984 kb
Host smart-28d63ff8-af27-4b3c-b4fd-bedadb4867af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054510456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1054510456
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1314650613
Short name T665
Test name
Test status
Simulation time 76998676866 ps
CPU time 2106.49 seconds
Started Aug 10 06:14:57 PM PDT 24
Finished Aug 10 06:50:04 PM PDT 24
Peak memory 224832 kb
Host smart-2b1ea2b8-500c-4a1f-9b4e-e66ef7b7a396
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314650613 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1314650613
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.4114019353
Short name T1002
Test name
Test status
Simulation time 34085177369 ps
CPU time 33.97 seconds
Started Aug 10 06:14:59 PM PDT 24
Finished Aug 10 06:15:33 PM PDT 24
Peak memory 198256 kb
Host smart-a53e638d-f764-43da-9009-618dd3dd734c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114019353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.4114019353
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.3312530160
Short name T817
Test name
Test status
Simulation time 443535664176 ps
CPU time 408.14 seconds
Started Aug 10 06:14:58 PM PDT 24
Finished Aug 10 06:21:47 PM PDT 24
Peak memory 225544 kb
Host smart-0c455435-f415-4edd-b93c-da4d605a2e57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312530160 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3312530160
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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