Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	116708	1			T1	1		T2	15		T3	14
all_values[1]	116708	1			T1	1		T2	15		T3	14
all_values[2]	116708	1			T1	1		T2	15		T3	14
all_values[3]	116708	1			T1	1		T2	15		T3	14
all_values[4]	116708	1			T1	1		T2	15		T3	14
all_values[5]	116708	1			T1	1		T2	15		T3	14
all_values[6]	116708	1			T1	1		T2	15		T3	14
all_values[7]	116708	1			T1	1		T2	15		T3	14
all_values[8]	116708	1			T1	1		T2	15		T3	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

529851

1

T1

3

T2

65

T3

44

auto[1]

520521

1

T1

6

T2

70

T3

82

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

954966

1

T1

7

T2

107

T3

113

auto[1]

95406

1

T1

2

T2

28

T3

13

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	36582	1			T2	3		T5	3		T6	106
all_values[0]	auto[0]	auto[1]	24233	1			T1	1		T2	4		T3	2
all_values[0]	auto[1]	auto[0]	33177	1			T2	3		T3	10		T5	17
all_values[0]	auto[1]	auto[1]	22716	1			T2	5		T3	2		T6	73
all_values[1]	auto[0]	auto[0]	55811	1			T1	1		T2	5		T4	2
all_values[1]	auto[0]	auto[1]	1709	1			T5	1		T7	2		T12	7
all_values[1]	auto[1]	auto[0]	57464	1			T2	6		T3	14		T5	8
all_values[1]	auto[1]	auto[1]	1724	1			T2	4		T5	7		T9	11
all_values[2]	auto[0]	auto[0]	54968	1			T1	1		T2	3		T3	9
all_values[2]	auto[0]	auto[1]	2946	1			T2	2		T3	5		T4	1
all_values[2]	auto[1]	auto[0]	56266	1			T2	6		T5	1		T6	170
all_values[2]	auto[1]	auto[1]	2528	1			T2	4		T5	1		T6	6
all_values[3]	auto[0]	auto[0]	59250	1			T2	4		T3	2		T4	2
all_values[3]	auto[0]	auto[1]	316	1			T7	1		T9	2		T11	1
all_values[3]	auto[1]	auto[0]	56839	1			T1	1		T2	11		T3	12
all_values[3]	auto[1]	auto[1]	303	1			T14	7		T20	3		T130	1
all_values[4]	auto[0]	auto[0]	58829	1			T2	4		T4	2		T5	8
all_values[4]	auto[0]	auto[1]	467	1			T9	1		T14	17		T20	3
all_values[4]	auto[1]	auto[0]	56889	1			T1	1		T2	11		T3	14
all_values[4]	auto[1]	auto[1]	523	1			T9	2		T12	1		T14	9
all_values[5]	auto[0]	auto[0]	54241	1			T2	9		T3	2		T4	2
all_values[5]	auto[0]	auto[1]	179	1			T9	2		T15	2		T20	1
all_values[5]	auto[1]	auto[0]	62102	1			T1	1		T2	6		T3	12
all_values[5]	auto[1]	auto[1]	186	1			T9	2		T33	2		T112	5
all_values[6]	auto[0]	auto[0]	54797	1			T2	11		T3	4		T4	2
all_values[6]	auto[0]	auto[1]	188	1			T14	2		T15	4		T20	1
all_values[6]	auto[1]	auto[0]	61533	1			T1	1		T2	4		T3	10
all_values[6]	auto[1]	auto[1]	190	1			T14	3		T33	3		T35	4
all_values[7]	auto[0]	auto[0]	61571	1			T2	11		T3	10		T4	2
all_values[7]	auto[0]	auto[1]	411	1			T14	3		T33	1		T34	3
all_values[7]	auto[1]	auto[0]	54379	1			T1	1		T2	4		T3	4
all_values[7]	auto[1]	auto[1]	347	1			T9	3		T14	16		T43	4
all_values[8]	auto[0]	auto[0]	43801	1			T2	3		T3	10		T6	120
all_values[8]	auto[0]	auto[1]	19552	1			T2	6		T4	2		T5	2
all_values[8]	auto[1]	auto[0]	36467	1			T2	3		T5	21		T6	82
all_values[8]	auto[1]	auto[1]	16888	1			T1	1		T2	3		T3	4