Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2567

1

T1

1

T2

1

T3

1

auto[UartRx]

2567

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4538	1			T1	2		T2	2		T3	2
values[1]	48	1			T12	1		T32	1		T133	2
values[2]	66	1			T9	1		T20	2		T32	1
values[3]	50	1			T20	1		T31	2		T32	2
values[4]	63	1			T9	1		T14	2		T32	1
values[5]	65	1			T9	2		T12	1		T14	1
values[6]	57	1			T14	1		T31	2		T32	2
values[7]	38	1			T34	1		T35	1		T53	1
values[8]	62	1			T9	1		T14	2		T32	1
values[9]	49	1			T14	1		T34	1		T306	4
values[10]	72	1			T12	3		T14	2		T33	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2352	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	15	1			T32	1		T133	1		T114	1
auto[UartTx]	values[2]	22	1			T32	1		T35	1		T133	1
auto[UartTx]	values[3]	22	1			T20	1		T32	1		T53	1
auto[UartTx]	values[4]	22	1			T14	1		T32	1		T34	1
auto[UartTx]	values[5]	23	1			T9	1		T14	1		T34	1
auto[UartTx]	values[6]	21	1			T31	1		T36	1		T336	1
auto[UartTx]	values[7]	10	1			T34	1		T35	1		T337	1
auto[UartTx]	values[8]	20	1			T36	1		T53	1		T149	2
auto[UartTx]	values[9]	17	1			T14	1		T306	2		T338	1
auto[UartTx]	values[10]	30	1			T12	1		T34	3		T113	1
auto[UartRx]	values[0]	2186	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	33	1			T12	1		T133	1		T339	1
auto[UartRx]	values[2]	44	1			T9	1		T20	2		T36	1
auto[UartRx]	values[3]	28	1			T31	2		T32	1		T36	1
auto[UartRx]	values[4]	41	1			T9	1		T14	1		T112	2
auto[UartRx]	values[5]	42	1			T9	1		T12	1		T20	1
auto[UartRx]	values[6]	36	1			T14	1		T31	1		T32	2
auto[UartRx]	values[7]	28	1			T53	1		T340	1		T115	1
auto[UartRx]	values[8]	42	1			T9	1		T14	2		T32	1
auto[UartRx]	values[9]	32	1			T34	1		T306	2		T114	1
auto[UartRx]	values[10]	42	1			T12	2		T14	2		T33	1