Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2262	1			T1	3		T2	1		T3	1
auto[BaudRate115200]	2079	1			T2	3		T5	3		T6	2
auto[BaudRate230400]	1937	1			T4	1		T5	3		T6	2
auto[BaudRate128Kbps]	2103	1			T2	1		T3	2		T4	1
auto[BaudRate256Kbps]	2211	1			T3	4		T6	1		T7	1
auto[BaudRate1Mbps]	1902	1			T2	1		T6	1		T7	1
auto[BaudRate1p5Mbps]	1340	1			T2	3		T6	2		T7	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1473	1			T14	78		T136	7		T15	3
freqs[25]	1468	1			T6	8		T269	7		T305	3
freqs[48]	616	1			T2	9		T341	57		T135	6
freqs[50]	607	1			T195	7		T314	10		T166	10
freqs[100]	1100	1			T12	12		T38	10		T40	7

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	240	1			T14	4		T136	1		T15	3
auto[BaudRate9600]	freqs[25]	213	1			T305	1		T48	1		T190	2
auto[BaudRate9600]	freqs[48]	76	1			T2	1		T341	15		T294	1
auto[BaudRate9600]	freqs[50]	91	1			T195	2		T314	2		T166	1
auto[BaudRate9600]	freqs[100]	155	1			T12	5		T38	2		T342	3
auto[BaudRate115200]	freqs[24]	207	1			T14	12		T290	6		T130	2
auto[BaudRate115200]	freqs[25]	235	1			T6	2		T48	3		T190	3
auto[BaudRate115200]	freqs[48]	91	1			T2	3		T341	6		T135	2
auto[BaudRate115200]	freqs[50]	92	1			T195	3		T314	2		T71	1
auto[BaudRate115200]	freqs[100]	132	1			T12	2		T40	1		T143	1
auto[BaudRate230400]	freqs[24]	191	1			T14	14		T136	2		T140	1
auto[BaudRate230400]	freqs[25]	211	1			T6	2		T48	5		T190	1
auto[BaudRate230400]	freqs[48]	60	1			T135	1		T47	2		T158	3
auto[BaudRate230400]	freqs[50]	86	1			T314	2		T166	2		T71	6
auto[BaudRate230400]	freqs[100]	154	1			T12	2		T40	2		T143	1
auto[BaudRate128Kbps]	freqs[24]	249	1			T14	11		T136	1		T140	2
auto[BaudRate128Kbps]	freqs[25]	247	1			T305	1		T48	2		T190	1
auto[BaudRate128Kbps]	freqs[48]	93	1			T2	1		T341	12		T135	1
auto[BaudRate128Kbps]	freqs[50]	89	1			T314	1		T166	2		T71	4
auto[BaudRate128Kbps]	freqs[100]	167	1			T12	1		T38	1		T291	1
auto[BaudRate256Kbps]	freqs[24]	232	1			T14	16		T136	1		T290	1
auto[BaudRate256Kbps]	freqs[25]	200	1			T6	1		T269	2		T48	3
auto[BaudRate256Kbps]	freqs[48]	70	1			T47	2		T158	2		T270	1
auto[BaudRate256Kbps]	freqs[50]	79	1			T195	1		T314	1		T166	2
auto[BaudRate256Kbps]	freqs[100]	182	1			T38	2		T40	1		T291	1
auto[BaudRate1Mbps]	freqs[24]	243	1			T14	17		T136	1		T290	1
auto[BaudRate1Mbps]	freqs[25]	247	1			T6	1		T269	4		T48	4
auto[BaudRate1Mbps]	freqs[48]	112	1			T2	1		T341	18		T135	1
auto[BaudRate1Mbps]	freqs[50]	73	1			T314	2		T166	1		T71	2
auto[BaudRate1Mbps]	freqs[100]	144	1			T12	2		T38	4		T40	2
auto[BaudRate1p5Mbps]	freqs[25]	115	1			T6	2		T269	1		T305	1
auto[BaudRate1p5Mbps]	freqs[48]	114	1			T2	3		T341	6		T135	1
auto[BaudRate1p5Mbps]	freqs[50]	97	1			T195	1		T166	2		T71	2
auto[BaudRate1p5Mbps]	freqs[100]	166	1			T38	1		T40	1		T143	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded