Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.40	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	13	117	90.00

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	13	117	90.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	32748351	1			T2	45		T3	22		T5	37
all_levels[1]	181200	1			T5	2		T6	147		T8	1
all_levels[2]	2565	1			T5	3		T7	1		T9	3
all_levels[3]	1244	1			T5	5		T9	6		T12	4
all_levels[4]	748	1			T5	3		T7	1		T9	1
all_levels[5]	606	1			T5	2		T7	1		T8	2
all_levels[6]	479	1			T5	2		T12	3		T14	1
all_levels[7]	337	1			T5	2		T7	1		T8	2
all_levels[8]	300	1			T2	1		T5	1		T7	2
all_levels[9]	276	1			T12	1		T14	1		T135	2
all_levels[10]	219	1			T5	2		T12	1		T20	1
all_levels[11]	228	1			T5	2		T12	1		T136	1
all_levels[12]	184	1			T12	1		T11	1		T38	1
all_levels[13]	161	1			T5	1		T41	1		T136	1
all_levels[14]	150	1			T5	2		T43	2		T20	1
all_levels[15]	170	1			T5	1		T43	1		T137	3
all_levels[16]	129	1			T5	1		T9	1		T12	1
all_levels[17]	90	1			T2	1		T5	1		T9	1
all_levels[18]	101	1			T138	1		T43	1		T139	1
all_levels[19]	100	1			T14	1		T136	1		T140	1
all_levels[20]	75	1			T141	1		T142	2		T36	1
all_levels[21]	74	1			T9	1		T119	1		T141	1
all_levels[22]	71	1			T12	1		T126	1		T143	1
all_levels[23]	71	1			T9	1		T41	1		T43	1
all_levels[24]	71	1			T135	1		T138	1		T144	3
all_levels[25]	54	1			T145	1		T146	1		T147	1
all_levels[26]	56	1			T5	1		T126	1		T146	1
all_levels[27]	73	1			T12	1		T138	1		T148	2
all_levels[28]	41	1			T130	1		T35	1		T149	3
all_levels[29]	50	1			T9	1		T150	2		T143	1
all_levels[30]	49	1			T38	1		T136	1		T146	1
all_levels[31]	48	1			T38	2		T142	1		T146	1
all_levels[32]	37	1			T136	1		T35	1		T149	1
all_levels[33]	27	1			T39	1		T139	1		T133	1
all_levels[34]	33	1			T151	1		T152	1		T153	1
all_levels[35]	29	1			T5	1		T14	1		T138	2
all_levels[36]	30	1			T5	1		T138	1		T154	1
all_levels[37]	20	1			T39	1		T151	1		T155	1
all_levels[38]	15	1			T141	1		T143	2		T76	1
all_levels[39]	30	1			T5	1		T150	1		T141	1
all_levels[40]	16	1			T38	1		T150	1		T145	1
all_levels[41]	16	1			T38	1		T136	1		T143	1
all_levels[42]	14	1			T38	1		T76	1		T152	1
all_levels[43]	16	1			T136	1		T140	1		T47	1
all_levels[44]	15	1			T144	1		T141	1		T156	1
all_levels[45]	21	1			T144	2		T143	1		T157	1
all_levels[46]	12	1			T46	1		T158	1		T54	1
all_levels[47]	11	1			T143	1		T146	1		T159	1
all_levels[48]	17	1			T154	1		T155	1		T160	2
all_levels[49]	21	1			T138	1		T158	1		T161	5
all_levels[50]	11	1			T162	3		T163	1		T164	1
all_levels[51]	8	1			T165	1		T166	1		T167	1
all_levels[52]	15	1			T158	1		T168	3		T169	1
all_levels[53]	9	1			T170	1		T171	1		T172	2
all_levels[54]	10	1			T166	1		T163	1		T173	1
all_levels[55]	9	1			T156	1		T76	1		T174	1
all_levels[56]	11	1			T7	1		T158	1		T175	1
all_levels[57]	15	1			T31	1		T176	1		T177	1
all_levels[58]	10	1			T158	1		T178	1		T146	1
all_levels[59]	6	1			T117	1		T179	1		T180	1
all_levels[60]	3	1			T178	1		T181	1		T182	1
all_levels[61]	5	1			T130	1		T142	2		T183	1
all_levels[62]	11	1			T184	1		T185	2		T186	1
all_levels[63]	16	1			T51	4		T113	2		T187	1
all_levels[64]	99	1			T7	1		T11	1		T119	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32933948

1

T2

47

T3

16

T5

71

auto[1]

5041

1

T3

6

T7

4

T8

9

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	13	117	90.00	13

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[38]]	[auto[1]]	0	1	1
[all_levels[41] , all_levels[42]]	[auto[1]]	--	--	2
[all_levels[46] , all_levels[47]]	[auto[1]]	--	--	2
[all_levels[51]]	[auto[1]]	0	1	1
[all_levels[54] , all_levels[55] , all_levels[56]]	[auto[1]]	--	--	3
[all_levels[58] , all_levels[59] , all_levels[60]]	[auto[1]]	--	--	3
[all_levels[62]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	32743819	1			T2	45		T3	16		T5	37
all_levels[0]	auto[1]	4532	1			T3	6		T7	3		T8	8
all_levels[1]	auto[0]	181142	1			T5	2		T6	147		T8	1
all_levels[1]	auto[1]	58	1			T138	1		T188	2		T147	2
all_levels[2]	auto[0]	2534	1			T5	3		T7	1		T9	3
all_levels[2]	auto[1]	31	1			T165	1		T137	1		T189	2
all_levels[3]	auto[0]	1218	1			T5	5		T9	6		T12	4
all_levels[3]	auto[1]	26	1			T190	1		T191	1		T192	1
all_levels[4]	auto[0]	725	1			T5	3		T7	1		T9	1
all_levels[4]	auto[1]	23	1			T11	3		T193	2		T194	3
all_levels[5]	auto[0]	591	1			T5	2		T7	1		T8	1
all_levels[5]	auto[1]	15	1			T8	1		T195	1		T192	1
all_levels[6]	auto[0]	450	1			T5	2		T12	3		T14	1
all_levels[6]	auto[1]	29	1			T138	1		T178	2		T196	2
all_levels[7]	auto[0]	334	1			T5	2		T7	1		T8	2
all_levels[7]	auto[1]	3	1			T197	1		T198	1		T199	1
all_levels[8]	auto[0]	292	1			T2	1		T5	1		T7	1
all_levels[8]	auto[1]	8	1			T7	1		T200	1		T201	2
all_levels[9]	auto[0]	263	1			T12	1		T14	1		T135	1
all_levels[9]	auto[1]	13	1			T135	1		T74	1		T202	1
all_levels[10]	auto[0]	207	1			T5	2		T12	1		T20	1
all_levels[10]	auto[1]	12	1			T119	1		T203	1		T204	2
all_levels[11]	auto[0]	182	1			T5	2		T12	1		T136	1
all_levels[11]	auto[1]	46	1			T196	1		T205	1		T206	1
all_levels[12]	auto[0]	176	1			T12	1		T11	1		T38	1
all_levels[12]	auto[1]	8	1			T119	1		T207	1		T208	1
all_levels[13]	auto[0]	143	1			T5	1		T41	1		T136	1
all_levels[13]	auto[1]	18	1			T141	5		T162	4		T209	2
all_levels[14]	auto[0]	134	1			T5	2		T43	2		T20	1
all_levels[14]	auto[1]	16	1			T46	1		T210	1		T180	1
all_levels[15]	auto[0]	161	1			T5	1		T43	1		T137	2
all_levels[15]	auto[1]	9	1			T137	1		T120	1		T190	1
all_levels[16]	auto[0]	117	1			T5	1		T9	1		T12	1
all_levels[16]	auto[1]	12	1			T36	1		T211	1		T212	3
all_levels[17]	auto[0]	83	1			T2	1		T5	1		T9	1
all_levels[17]	auto[1]	7	1			T147	1		T213	1		T214	1
all_levels[18]	auto[0]	95	1			T138	1		T43	1		T139	1
all_levels[18]	auto[1]	6	1			T178	1		T215	1		T216	2
all_levels[19]	auto[0]	90	1			T14	1		T136	1		T140	1
all_levels[19]	auto[1]	10	1			T46	4		T217	1		T218	2
all_levels[20]	auto[0]	67	1			T141	1		T142	1		T36	1
all_levels[20]	auto[1]	8	1			T142	1		T211	2		T219	1
all_levels[21]	auto[0]	69	1			T9	1		T119	1		T141	1
all_levels[21]	auto[1]	5	1			T220	1		T74	1		T221	1
all_levels[22]	auto[0]	67	1			T12	1		T126	1		T143	1
all_levels[22]	auto[1]	4	1			T222	1		T223	2		T224	1
all_levels[23]	auto[0]	63	1			T9	1		T41	1		T43	1
all_levels[23]	auto[1]	8	1			T225	1		T226	2		T227	3
all_levels[24]	auto[0]	54	1			T135	1		T138	1		T144	1
all_levels[24]	auto[1]	17	1			T144	2		T228	2		T204	1
all_levels[25]	auto[0]	51	1			T145	1		T146	1		T147	1
all_levels[25]	auto[1]	3	1			T229	1		T230	1		T231	1
all_levels[26]	auto[0]	53	1			T5	1		T126	1		T146	1
all_levels[26]	auto[1]	3	1			T232	1		T233	1		T234	1
all_levels[27]	auto[0]	61	1			T12	1		T138	1		T148	1
all_levels[27]	auto[1]	12	1			T148	1		T235	1		T236	2
all_levels[28]	auto[0]	36	1			T130	1		T35	1		T149	1
all_levels[28]	auto[1]	5	1			T149	2		T237	2		T238	1
all_levels[29]	auto[0]	44	1			T9	1		T150	1		T143	1
all_levels[29]	auto[1]	6	1			T150	1		T239	1		T240	1
all_levels[30]	auto[0]	46	1			T38	1		T136	1		T146	1
all_levels[30]	auto[1]	3	1			T241	1		T242	1		T229	1
all_levels[31]	auto[0]	44	1			T38	2		T142	1		T146	1
all_levels[31]	auto[1]	4	1			T241	1		T243	1		T244	1
all_levels[32]	auto[0]	33	1			T136	1		T35	1		T149	1
all_levels[32]	auto[1]	4	1			T245	1		T246	1		T247	2
all_levels[33]	auto[0]	23	1			T39	1		T139	1		T133	1
all_levels[33]	auto[1]	4	1			T245	3		T248	1		-	-
all_levels[34]	auto[0]	26	1			T151	1		T152	1		T153	1
all_levels[34]	auto[1]	7	1			T249	1		T250	2		T251	1
all_levels[35]	auto[0]	27	1			T5	1		T14	1		T138	2
all_levels[35]	auto[1]	2	1			T156	1		T252	1		-	-
all_levels[36]	auto[0]	23	1			T5	1		T138	1		T154	1
all_levels[36]	auto[1]	7	1			T253	4		T254	1		T255	1
all_levels[37]	auto[0]	18	1			T39	1		T151	1		T155	1
all_levels[37]	auto[1]	2	1			T213	1		T256	1		-	-
all_levels[38]	auto[0]	15	1			T141	1		T143	2		T76	1
all_levels[39]	auto[0]	28	1			T5	1		T150	1		T141	1
all_levels[39]	auto[1]	2	1			T257	1		T252	1		-	-
all_levels[40]	auto[0]	14	1			T38	1		T150	1		T145	1
all_levels[40]	auto[1]	2	1			T258	2		-	-		-	-
all_levels[41]	auto[0]	16	1			T38	1		T136	1		T143	1
all_levels[42]	auto[0]	14	1			T38	1		T76	1		T152	1
all_levels[43]	auto[0]	14	1			T136	1		T140	1		T47	1
all_levels[43]	auto[1]	2	1			T259	2		-	-		-	-
all_levels[44]	auto[0]	13	1			T144	1		T141	1		T156	1
all_levels[44]	auto[1]	2	1			T168	2		-	-		-	-
all_levels[45]	auto[0]	15	1			T144	1		T143	1		T157	1
all_levels[45]	auto[1]	6	1			T144	1		T215	2		T260	1
all_levels[46]	auto[0]	12	1			T46	1		T158	1		T54	1
all_levels[47]	auto[0]	11	1			T143	1		T146	1		T159	1
all_levels[48]	auto[0]	11	1			T154	1		T155	1		T160	1
all_levels[48]	auto[1]	6	1			T160	1		T55	2		T261	1
all_levels[49]	auto[0]	13	1			T138	1		T158	1		T161	1
all_levels[49]	auto[1]	8	1			T161	4		T225	3		T262	1
all_levels[50]	auto[0]	9	1			T162	1		T163	1		T164	1
all_levels[50]	auto[1]	2	1			T162	2		-	-		-	-
all_levels[51]	auto[0]	8	1			T165	1		T166	1		T167	1
all_levels[52]	auto[0]	13	1			T158	1		T168	1		T169	1
all_levels[52]	auto[1]	2	1			T168	2		-	-		-	-
all_levels[53]	auto[0]	8	1			T170	1		T171	1		T172	1
all_levels[53]	auto[1]	1	1			T172	1		-	-		-	-
all_levels[54]	auto[0]	10	1			T166	1		T163	1		T173	1
all_levels[55]	auto[0]	9	1			T156	1		T76	1		T174	1
all_levels[56]	auto[0]	11	1			T7	1		T158	1		T175	1
all_levels[57]	auto[0]	14	1			T31	1		T176	1		T177	1
all_levels[57]	auto[1]	1	1			T58	1		-	-		-	-
all_levels[58]	auto[0]	10	1			T158	1		T178	1		T146	1
all_levels[59]	auto[0]	6	1			T117	1		T179	1		T180	1
all_levels[60]	auto[0]	3	1			T178	1		T181	1		T182	1
all_levels[61]	auto[0]	4	1			T130	1		T142	1		T183	1
all_levels[61]	auto[1]	1	1			T142	1		-	-		-	-
all_levels[62]	auto[0]	11	1			T184	1		T185	2		T186	1
all_levels[63]	auto[0]	10	1			T51	1		T113	1		T187	1
all_levels[63]	auto[1]	6	1			T51	3		T113	1		T263	2
all_levels[64]	auto[0]	85	1			T7	1		T11	1		T119	1
all_levels[64]	auto[1]	14	1			T264	3		T212	1		T210	2