Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	116708	1			T1	1		T2	15		T3	14
all_pins[1]	116708	1			T1	1		T2	15		T3	14
all_pins[2]	116708	1			T1	1		T2	15		T3	14
all_pins[3]	116708	1			T1	1		T2	15		T3	14
all_pins[4]	116708	1			T1	1		T2	15		T3	14
all_pins[5]	116708	1			T1	1		T2	15		T3	14
all_pins[6]	116708	1			T1	1		T2	15		T3	14
all_pins[7]	116708	1			T1	1		T2	15		T3	14
all_pins[8]	116708	1			T1	1		T2	15		T3	14

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1003983	1			T1	8		T2	119		T3	120
values[0x1]	46389	1			T1	1		T2	16		T3	6
transitions[0x0=>0x1]	35806	1			T2	14		T3	4		T5	8
transitions[0x1=>0x0]	35630	1			T1	1		T2	14		T3	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	93910	1			T1	1		T2	10		T3	12
all_pins[0]	values[0x1]	22798	1			T2	5		T3	2		T6	73
all_pins[0]	transitions[0x0=>0x1]	22172	1			T2	4		T3	2		T6	73
all_pins[0]	transitions[0x1=>0x0]	1091	1			T2	3		T5	7		T9	2
all_pins[1]	values[0x0]	114991	1			T1	1		T2	11		T3	14
all_pins[1]	values[0x1]	1717	1			T2	4		T5	7		T9	11
all_pins[1]	transitions[0x0=>0x1]	1599	1			T2	3		T5	7		T9	10
all_pins[1]	transitions[0x1=>0x0]	2486	1			T2	3		T5	1		T6	6
all_pins[2]	values[0x0]	114104	1			T1	1		T2	11		T3	14
all_pins[2]	values[0x1]	2604	1			T2	4		T5	1		T6	6
all_pins[2]	transitions[0x0=>0x1]	2530	1			T2	4		T5	1		T6	6
all_pins[2]	transitions[0x1=>0x0]	229	1			T14	7		T20	3		T220	2
all_pins[3]	values[0x0]	116405	1			T1	1		T2	15		T3	14
all_pins[3]	values[0x1]	303	1			T14	7		T20	3		T130	1
all_pins[3]	transitions[0x0=>0x1]	253	1			T14	7		T20	3		T130	1
all_pins[3]	transitions[0x1=>0x0]	473	1			T9	2		T12	1		T14	9
all_pins[4]	values[0x0]	116185	1			T1	1		T2	15		T3	14
all_pins[4]	values[0x1]	523	1			T9	2		T12	1		T14	9
all_pins[4]	transitions[0x0=>0x1]	434	1			T9	2		T12	1		T14	8
all_pins[4]	transitions[0x1=>0x0]	151	1			T9	2		T14	3		T33	2
all_pins[5]	values[0x0]	116468	1			T1	1		T2	15		T3	14
all_pins[5]	values[0x1]	240	1			T9	2		T14	4		T33	2
all_pins[5]	transitions[0x0=>0x1]	189	1			T9	2		T14	4		T112	4
all_pins[5]	transitions[0x1=>0x0]	856	1			T9	1		T29	1		T11	1
all_pins[6]	values[0x0]	115801	1			T1	1		T2	15		T3	14
all_pins[6]	values[0x1]	907	1			T9	1		T29	1		T11	1
all_pins[6]	transitions[0x0=>0x1]	854	1			T9	1		T29	1		T11	1
all_pins[6]	transitions[0x1=>0x0]	294	1			T9	3		T14	16		T43	4
all_pins[7]	values[0x0]	116361	1			T1	1		T2	15		T3	14
all_pins[7]	values[0x1]	347	1			T9	3		T14	16		T43	4
all_pins[7]	transitions[0x0=>0x1]	197	1			T9	1		T14	14		T43	4
all_pins[7]	transitions[0x1=>0x0]	16800	1			T1	1		T2	3		T3	4
all_pins[8]	values[0x0]	99758	1			T2	12		T3	10		T4	2
all_pins[8]	values[0x1]	16950	1			T1	1		T2	3		T3	4
all_pins[8]	transitions[0x0=>0x1]	7578	1			T2	3		T3	2		T6	1
all_pins[8]	transitions[0x1=>0x0]	13250	1			T2	5		T3	1		T6	33