Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7828363	1			T2	17		T3	14		T5	7
all_levels[1]	1876501	1			T2	1		T6	1629		T7	1
all_levels[2]	291887	1			T6	1618		T9	19		T29	2
all_levels[3]	309446	1			T2	1		T6	1615		T9	21
all_levels[4]	799386	1			T2	1		T6	1601		T9	13
all_levels[5]	218865	1			T2	13		T5	1		T6	1617
all_levels[6]	211281	1			T5	1		T6	1621		T8	2
all_levels[7]	353794	1			T2	2		T5	2		T6	1591
all_levels[8]	333678	1			T2	1		T6	1617		T8	4
all_levels[9]	199015	1			T6	1621		T9	13		T12	1
all_levels[10]	359213	1			T5	21		T6	1618		T7	1
all_levels[11]	216324	1			T6	1526		T7	1		T9	13
all_levels[12]	212691	1			T6	477		T9	13		T12	4
all_levels[13]	197901	1			T5	2		T6	476		T9	14
all_levels[14]	193806	1			T5	4		T6	475		T9	9
all_levels[15]	216814	1			T5	3		T6	477		T9	24
all_levels[16]	383406	1			T5	4		T6	487		T7	1
all_levels[17]	193159	1			T5	3		T6	493		T7	1
all_levels[18]	198567	1			T2	9		T5	5		T6	483
all_levels[19]	182682	1			T6	479		T7	3		T9	15
all_levels[20]	270932	1			T6	479		T8	1		T9	12
all_levels[21]	186248	1			T5	4		T6	477		T8	2
all_levels[22]	225093	1			T2	2		T6	474		T9	15
all_levels[23]	237291	1			T6	466		T9	9		T30	62
all_levels[24]	254166	1			T6	433		T9	11		T12	1
all_levels[25]	273625	1			T6	394		T8	1		T9	9
all_levels[26]	224635	1			T6	393		T8	1		T9	14
all_levels[27]	558805	1			T5	7		T6	393		T9	7
all_levels[28]	235135	1			T6	333		T7	1		T9	12
all_levels[29]	165691	1			T6	294		T9	6		T269	22
all_levels[30]	269853	1			T5	1		T6	300		T9	9
all_levels[31]	526300	1			T6	341		T8	2		T9	458
all_levels[32]	14733943	1			T3	9		T5	6		T6	25421

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32933948

1

T2

47

T3

16

T5

71

auto[1]

4548

1

T3

7

T7

3

T8

7

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7825717	1			T2	17		T3	8		T5	7
all_levels[0]	auto[1]	2646	1			T3	6		T7	2		T8	5
all_levels[1]	auto[0]	1876146	1			T2	1		T6	1629		T7	1
all_levels[1]	auto[1]	355	1			T9	1		T38	1		T195	1
all_levels[2]	auto[0]	291862	1			T6	1618		T9	19		T29	2
all_levels[2]	auto[1]	25	1			T14	1		T148	1		T49	1
all_levels[3]	auto[0]	309300	1			T2	1		T6	1615		T9	21
all_levels[3]	auto[1]	146	1			T41	1		T137	1		T20	5
all_levels[4]	auto[0]	799354	1			T2	1		T6	1601		T9	13
all_levels[4]	auto[1]	32	1			T203	1		T220	1		T217	1
all_levels[5]	auto[0]	218839	1			T2	13		T5	1		T6	1617
all_levels[5]	auto[1]	26	1			T51	1		T36	1		T334	1
all_levels[6]	auto[0]	211257	1			T5	1		T6	1621		T8	2
all_levels[6]	auto[1]	24	1			T112	2		T74	1		T246	1
all_levels[7]	auto[0]	353654	1			T2	2		T5	2		T6	1591
all_levels[7]	auto[1]	140	1			T130	6		T220	1		T317	3
all_levels[8]	auto[0]	333653	1			T2	1		T6	1617		T8	2
all_levels[8]	auto[1]	25	1			T8	2		T140	2		T203	2
all_levels[9]	auto[0]	198981	1			T6	1621		T9	13		T12	1
all_levels[9]	auto[1]	34	1			T211	2		T329	1		T297	1
all_levels[10]	auto[0]	359191	1			T5	21		T6	1618		T7	1
all_levels[10]	auto[1]	22	1			T276	2		T264	3		T286	1
all_levels[11]	auto[0]	216303	1			T6	1526		T7	1		T9	13
all_levels[11]	auto[1]	21	1			T188	1		T284	1		T344	1
all_levels[12]	auto[0]	212672	1			T6	477		T9	13		T12	4
all_levels[12]	auto[1]	19	1			T334	2		T152	1		T117	2
all_levels[13]	auto[0]	197882	1			T5	2		T6	476		T9	14
all_levels[13]	auto[1]	19	1			T345	1		T328	1		T212	1
all_levels[14]	auto[0]	193786	1			T5	4		T6	475		T9	9
all_levels[14]	auto[1]	20	1			T289	2		T322	1		T226	2
all_levels[15]	auto[0]	216622	1			T5	3		T6	477		T9	10
all_levels[15]	auto[1]	192	1			T9	14		T32	1		T289	1
all_levels[16]	auto[0]	383388	1			T5	4		T6	487		T7	1
all_levels[16]	auto[1]	18	1			T271	1		T188	2		T346	1
all_levels[17]	auto[0]	193143	1			T5	3		T6	493		T7	1
all_levels[17]	auto[1]	16	1			T144	1		T130	1		T142	2
all_levels[18]	auto[0]	198541	1			T2	9		T5	5		T6	483
all_levels[18]	auto[1]	26	1			T11	1		T195	1		T138	1
all_levels[19]	auto[0]	182667	1			T6	479		T7	2		T9	15
all_levels[19]	auto[1]	15	1			T7	1		T34	1		T212	1
all_levels[20]	auto[0]	270903	1			T6	479		T8	1		T9	12
all_levels[20]	auto[1]	29	1			T130	1		T178	1		T161	4
all_levels[21]	auto[0]	186222	1			T5	4		T6	477		T8	2
all_levels[21]	auto[1]	26	1			T190	6		T178	2		T228	1
all_levels[22]	auto[0]	225061	1			T2	2		T6	474		T9	15
all_levels[22]	auto[1]	32	1			T41	1		T144	1		T276	1
all_levels[23]	auto[0]	237267	1			T6	466		T9	9		T30	61
all_levels[23]	auto[1]	24	1			T30	1		T140	1		T141	1
all_levels[24]	auto[0]	254148	1			T6	433		T9	11		T12	1
all_levels[24]	auto[1]	18	1			T347	2		T348	1		T323	1
all_levels[25]	auto[0]	273610	1			T6	394		T8	1		T9	9
all_levels[25]	auto[1]	15	1			T156	1		T204	1		T337	1
all_levels[26]	auto[0]	224622	1			T6	393		T8	1		T9	14
all_levels[26]	auto[1]	13	1			T203	2		T190	1		T147	1
all_levels[27]	auto[0]	558784	1			T5	7		T6	393		T9	7
all_levels[27]	auto[1]	21	1			T292	3		T214	2		T349	3
all_levels[28]	auto[0]	235116	1			T6	333		T7	1		T9	12
all_levels[28]	auto[1]	19	1			T265	1		T289	1		T350	2
all_levels[29]	auto[0]	165681	1			T6	294		T9	6		T269	22
all_levels[29]	auto[1]	10	1			T108	1		T351	1		T192	1
all_levels[30]	auto[0]	269840	1			T5	1		T6	300		T9	9
all_levels[30]	auto[1]	13	1			T302	1		T347	1		T214	2
all_levels[31]	auto[0]	526288	1			T6	341		T8	2		T9	458
all_levels[31]	auto[1]	12	1			T140	1		T289	1		T196	2
all_levels[32]	auto[0]	14733448	1			T3	8		T5	6		T6	25421
all_levels[32]	auto[1]	495	1			T3	1		T9	1		T29	1