Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	789	1			T9	4		T14	11		T15	8
all_values[1]	789	1			T9	4		T14	11		T15	8
all_values[2]	789	1			T9	4		T14	11		T15	8
all_values[3]	789	1			T9	4		T14	11		T15	8
all_values[4]	789	1			T9	4		T14	11		T15	8
all_values[5]	789	1			T9	4		T14	11		T15	8
all_values[6]	789	1			T9	4		T14	11		T15	8
all_values[7]	789	1			T9	4		T14	11		T15	8
all_values[8]	789	1			T9	4		T14	11		T15	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3778

1

T9

17

T14

65

T15

45

auto[1]

3323

1

T9

19

T14

34

T15

27

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2295

1

T9

13

T14

35

T15

31

auto[1]

4806

1

T9

23

T14

64

T15

41

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4169

1

T9

23

T14

56

T15

51

auto[1]

2932

1

T9

13

T14

43

T15

21

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	231	1			T14	3		T15	6		T20	3
all_values[0]	auto[0]	auto[1]	auto[1]	223	1			T9	1		T15	1		T35	4
all_values[0]	auto[1]	auto[0]	auto[1]	189	1			T9	3		T14	5		T15	1
all_values[0]	auto[1]	auto[1]	auto[1]	146	1			T14	3		T20	2		T33	1
all_values[1]	auto[0]	auto[0]	auto[0]	233	1			T14	3		T15	4		T20	1
all_values[1]	auto[0]	auto[1]	auto[0]	223	1			T9	2		T14	2		T15	2
all_values[1]	auto[1]	auto[0]	auto[1]	175	1			T9	1		T14	4		T15	2
all_values[1]	auto[1]	auto[1]	auto[1]	158	1			T9	1		T14	2		T20	2
all_values[2]	auto[0]	auto[0]	auto[0]	174	1			T9	1		T14	4		T15	1
all_values[2]	auto[0]	auto[0]	auto[1]	72	1			T9	1		T15	1		T20	1
all_values[2]	auto[0]	auto[1]	auto[0]	148	1			T14	2		T15	3		T33	1
all_values[2]	auto[0]	auto[1]	auto[1]	78	1			T9	1		T14	1		T20	2
all_values[2]	auto[1]	auto[0]	auto[1]	180	1			T14	4		T15	1		T20	1
all_values[2]	auto[1]	auto[1]	auto[1]	137	1			T9	1		T15	2		T20	2
all_values[3]	auto[0]	auto[0]	auto[0]	169	1			T9	1		T14	3		T15	3
all_values[3]	auto[0]	auto[0]	auto[1]	84	1			T14	3		T15	1		T20	1
all_values[3]	auto[0]	auto[1]	auto[0]	147	1			T9	3		T14	1		T15	1
all_values[3]	auto[0]	auto[1]	auto[1]	80	1			T14	1		T20	1		T112	1
all_values[3]	auto[1]	auto[0]	auto[1]	170	1			T14	3		T15	3		T20	4
all_values[3]	auto[1]	auto[1]	auto[1]	139	1			T35	3		T112	4		T133	1
all_values[4]	auto[0]	auto[0]	auto[0]	156	1			T14	1		T15	1		T35	3
all_values[4]	auto[0]	auto[0]	auto[1]	88	1			T14	3		T20	1		T35	3
all_values[4]	auto[0]	auto[1]	auto[0]	129	1			T9	2		T14	2		T15	1
all_values[4]	auto[0]	auto[1]	auto[1]	77	1			T9	1		T14	2		T112	1
all_values[4]	auto[1]	auto[0]	auto[1]	181	1			T9	1		T14	2		T15	2
all_values[4]	auto[1]	auto[1]	auto[1]	158	1			T14	1		T15	4		T20	3
all_values[5]	auto[0]	auto[0]	auto[0]	172	1			T14	5		T15	5		T20	1
all_values[5]	auto[0]	auto[0]	auto[1]	83	1			T9	1		T15	1		T20	1
all_values[5]	auto[0]	auto[1]	auto[0]	138	1			T14	3		T15	1		T20	2
all_values[5]	auto[0]	auto[1]	auto[1]	87	1			T33	2		T112	1		T106	2
all_values[5]	auto[1]	auto[0]	auto[1]	164	1			T9	1		T14	1		T20	1
all_values[5]	auto[1]	auto[1]	auto[1]	145	1			T9	2		T14	2		T15	1
all_values[6]	auto[0]	auto[0]	auto[0]	141	1			T9	1		T14	2		T15	1
all_values[6]	auto[0]	auto[0]	auto[1]	80	1			T15	3		T20	1		T35	2
all_values[6]	auto[0]	auto[1]	auto[0]	150	1			T9	3		T14	1		T15	1
all_values[6]	auto[0]	auto[1]	auto[1]	85	1			T14	1		T33	2		T35	1
all_values[6]	auto[1]	auto[0]	auto[1]	174	1			T14	6		T15	3		T20	1
all_values[6]	auto[1]	auto[1]	auto[1]	159	1			T14	1		T20	1		T33	1
all_values[7]	auto[0]	auto[0]	auto[0]	182	1			T14	5		T15	2		T20	2
all_values[7]	auto[0]	auto[0]	auto[1]	83	1			T9	1		T35	1		T133	1
all_values[7]	auto[0]	auto[1]	auto[0]	133	1			T14	1		T15	5		T20	3
all_values[7]	auto[0]	auto[1]	auto[1]	73	1			T9	1		T14	1		T33	1
all_values[7]	auto[1]	auto[0]	auto[1]	177	1			T9	2		T14	1		T33	1
all_values[7]	auto[1]	auto[1]	auto[1]	141	1			T14	3		T15	1		T20	2
all_values[8]	auto[0]	auto[0]	auto[1]	218	1			T9	2		T14	2		T15	4
all_values[8]	auto[0]	auto[1]	auto[1]	232	1			T9	1		T14	4		T15	3
all_values[8]	auto[1]	auto[0]	auto[1]	202	1			T9	1		T14	5		T20	1
all_values[8]	auto[1]	auto[1]	auto[1]	137	1			T15	1		T20	3		T33	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal