Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.10 99.10 97.65 100.00 98.38 100.00 99.48


Total test records in report: 1314
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T1257 /workspace/coverage/cover_reg_top/2.uart_tl_errors.4109768820 Aug 11 04:52:18 PM PDT 24 Aug 11 04:52:19 PM PDT 24 341349166 ps
T1258 /workspace/coverage/cover_reg_top/21.uart_intr_test.3671079146 Aug 11 04:52:44 PM PDT 24 Aug 11 04:52:45 PM PDT 24 15275237 ps
T1259 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2249631940 Aug 11 04:52:21 PM PDT 24 Aug 11 04:52:22 PM PDT 24 67090048 ps
T1260 /workspace/coverage/cover_reg_top/0.uart_tl_errors.41502393 Aug 11 04:52:14 PM PDT 24 Aug 11 04:52:16 PM PDT 24 118059247 ps
T1261 /workspace/coverage/cover_reg_top/5.uart_csr_rw.512559178 Aug 11 04:52:20 PM PDT 24 Aug 11 04:52:21 PM PDT 24 12881668 ps
T94 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2641956875 Aug 11 04:52:23 PM PDT 24 Aug 11 04:52:25 PM PDT 24 88498953 ps
T1262 /workspace/coverage/cover_reg_top/8.uart_intr_test.2848093438 Aug 11 04:52:19 PM PDT 24 Aug 11 04:52:20 PM PDT 24 20463263 ps
T1263 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3786433178 Aug 11 04:52:21 PM PDT 24 Aug 11 04:52:22 PM PDT 24 109057390 ps
T1264 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1026353616 Aug 11 04:52:38 PM PDT 24 Aug 11 04:52:39 PM PDT 24 69611119 ps
T1265 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.454309268 Aug 11 04:52:14 PM PDT 24 Aug 11 04:52:16 PM PDT 24 352309756 ps
T65 /workspace/coverage/cover_reg_top/10.uart_csr_rw.3249956821 Aug 11 04:52:29 PM PDT 24 Aug 11 04:52:29 PM PDT 24 76623329 ps
T1266 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1143138860 Aug 11 04:52:25 PM PDT 24 Aug 11 04:52:26 PM PDT 24 19894868 ps
T66 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.4150905447 Aug 11 04:52:17 PM PDT 24 Aug 11 04:52:18 PM PDT 24 40313716 ps
T1267 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.891621435 Aug 11 04:52:24 PM PDT 24 Aug 11 04:52:25 PM PDT 24 73444519 ps
T1268 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3361727186 Aug 11 04:52:20 PM PDT 24 Aug 11 04:52:20 PM PDT 24 15884606 ps
T1269 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.439040788 Aug 11 04:52:36 PM PDT 24 Aug 11 04:52:36 PM PDT 24 17970233 ps
T1270 /workspace/coverage/cover_reg_top/20.uart_intr_test.710035250 Aug 11 04:52:35 PM PDT 24 Aug 11 04:52:35 PM PDT 24 11311649 ps
T1271 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3238481407 Aug 11 04:52:14 PM PDT 24 Aug 11 04:52:14 PM PDT 24 72412621 ps
T1272 /workspace/coverage/cover_reg_top/27.uart_intr_test.212118960 Aug 11 04:52:44 PM PDT 24 Aug 11 04:52:44 PM PDT 24 57920039 ps
T1273 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.797295049 Aug 11 04:52:20 PM PDT 24 Aug 11 04:52:21 PM PDT 24 59286554 ps
T1274 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3603128949 Aug 11 04:52:25 PM PDT 24 Aug 11 04:52:26 PM PDT 24 176032479 ps
T1275 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2930137381 Aug 11 04:52:36 PM PDT 24 Aug 11 04:52:37 PM PDT 24 52840501 ps
T1276 /workspace/coverage/cover_reg_top/26.uart_intr_test.2281296234 Aug 11 04:52:38 PM PDT 24 Aug 11 04:52:39 PM PDT 24 76359187 ps
T1277 /workspace/coverage/cover_reg_top/33.uart_intr_test.3323064067 Aug 11 04:52:38 PM PDT 24 Aug 11 04:52:38 PM PDT 24 84602222 ps
T67 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2008853970 Aug 11 04:52:18 PM PDT 24 Aug 11 04:52:19 PM PDT 24 16233551 ps
T1278 /workspace/coverage/cover_reg_top/38.uart_intr_test.25482320 Aug 11 04:52:44 PM PDT 24 Aug 11 04:52:44 PM PDT 24 26959910 ps
T1279 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1695225965 Aug 11 04:52:15 PM PDT 24 Aug 11 04:52:16 PM PDT 24 40800058 ps
T1280 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3354079548 Aug 11 04:52:14 PM PDT 24 Aug 11 04:52:15 PM PDT 24 140387853 ps
T1281 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1955938028 Aug 11 04:52:21 PM PDT 24 Aug 11 04:52:22 PM PDT 24 92021641 ps
T1282 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1588458022 Aug 11 04:52:15 PM PDT 24 Aug 11 04:52:16 PM PDT 24 12900959 ps
T1283 /workspace/coverage/cover_reg_top/14.uart_intr_test.2947176267 Aug 11 04:52:26 PM PDT 24 Aug 11 04:52:26 PM PDT 24 23628194 ps
T1284 /workspace/coverage/cover_reg_top/2.uart_intr_test.1838136452 Aug 11 04:52:15 PM PDT 24 Aug 11 04:52:16 PM PDT 24 16764801 ps
T1285 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1676245379 Aug 11 04:52:29 PM PDT 24 Aug 11 04:52:31 PM PDT 24 28569472 ps
T1286 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.231449111 Aug 11 04:52:29 PM PDT 24 Aug 11 04:52:29 PM PDT 24 135619916 ps
T1287 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2004559389 Aug 11 04:52:30 PM PDT 24 Aug 11 04:52:31 PM PDT 24 29660754 ps
T1288 /workspace/coverage/cover_reg_top/42.uart_intr_test.4267608204 Aug 11 04:52:39 PM PDT 24 Aug 11 04:52:39 PM PDT 24 13287413 ps
T1289 /workspace/coverage/cover_reg_top/6.uart_tl_errors.3248846262 Aug 11 04:52:22 PM PDT 24 Aug 11 04:52:24 PM PDT 24 62819955 ps
T1290 /workspace/coverage/cover_reg_top/16.uart_tl_errors.3495154703 Aug 11 04:52:38 PM PDT 24 Aug 11 04:52:41 PM PDT 24 253088525 ps
T1291 /workspace/coverage/cover_reg_top/46.uart_intr_test.2253460679 Aug 11 04:52:39 PM PDT 24 Aug 11 04:52:40 PM PDT 24 13926551 ps
T1292 /workspace/coverage/cover_reg_top/8.uart_tl_errors.735979335 Aug 11 04:52:20 PM PDT 24 Aug 11 04:52:22 PM PDT 24 82219104 ps
T1293 /workspace/coverage/cover_reg_top/17.uart_tl_errors.1673970323 Aug 11 04:52:31 PM PDT 24 Aug 11 04:52:34 PM PDT 24 39489325 ps
T1294 /workspace/coverage/cover_reg_top/16.uart_csr_rw.3060558850 Aug 11 04:52:31 PM PDT 24 Aug 11 04:52:32 PM PDT 24 27667319 ps
T1295 /workspace/coverage/cover_reg_top/3.uart_tl_errors.4097069573 Aug 11 04:52:19 PM PDT 24 Aug 11 04:52:21 PM PDT 24 144890066 ps
T1296 /workspace/coverage/cover_reg_top/1.uart_csr_rw.3579187890 Aug 11 04:52:19 PM PDT 24 Aug 11 04:52:20 PM PDT 24 17705783 ps
T1297 /workspace/coverage/cover_reg_top/7.uart_tl_errors.3805133180 Aug 11 04:52:20 PM PDT 24 Aug 11 04:52:23 PM PDT 24 40424406 ps
T1298 /workspace/coverage/cover_reg_top/22.uart_intr_test.2993012787 Aug 11 04:52:33 PM PDT 24 Aug 11 04:52:34 PM PDT 24 16120892 ps
T68 /workspace/coverage/cover_reg_top/19.uart_csr_rw.7084799 Aug 11 04:52:36 PM PDT 24 Aug 11 04:52:37 PM PDT 24 47112736 ps
T1299 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2967174423 Aug 11 04:52:25 PM PDT 24 Aug 11 04:52:26 PM PDT 24 34999288 ps
T1300 /workspace/coverage/cover_reg_top/41.uart_intr_test.2631815792 Aug 11 04:52:44 PM PDT 24 Aug 11 04:52:45 PM PDT 24 113648146 ps
T1301 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1902216074 Aug 11 04:52:14 PM PDT 24 Aug 11 04:52:17 PM PDT 24 59347780 ps
T1302 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3820761992 Aug 11 04:52:20 PM PDT 24 Aug 11 04:52:22 PM PDT 24 40580367 ps
T69 /workspace/coverage/cover_reg_top/8.uart_csr_rw.3315999874 Aug 11 04:52:20 PM PDT 24 Aug 11 04:52:21 PM PDT 24 23707415 ps
T1303 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2136296154 Aug 11 04:52:29 PM PDT 24 Aug 11 04:52:31 PM PDT 24 21077990 ps
T1304 /workspace/coverage/cover_reg_top/24.uart_intr_test.1818160780 Aug 11 04:52:38 PM PDT 24 Aug 11 04:52:39 PM PDT 24 20408659 ps
T1305 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.587668481 Aug 11 04:52:14 PM PDT 24 Aug 11 04:52:15 PM PDT 24 119842389 ps
T1306 /workspace/coverage/cover_reg_top/14.uart_csr_rw.1565803284 Aug 11 04:52:22 PM PDT 24 Aug 11 04:52:23 PM PDT 24 23358057 ps
T1307 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1631120720 Aug 11 04:52:21 PM PDT 24 Aug 11 04:52:22 PM PDT 24 94037584 ps
T1308 /workspace/coverage/cover_reg_top/29.uart_intr_test.17545166 Aug 11 04:52:32 PM PDT 24 Aug 11 04:52:33 PM PDT 24 29608985 ps
T1309 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2452099127 Aug 11 04:52:25 PM PDT 24 Aug 11 04:52:26 PM PDT 24 85612939 ps
T1310 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2070727394 Aug 11 04:52:17 PM PDT 24 Aug 11 04:52:20 PM PDT 24 639073375 ps
T1311 /workspace/coverage/cover_reg_top/4.uart_tl_errors.1234551084 Aug 11 04:52:20 PM PDT 24 Aug 11 04:52:23 PM PDT 24 137353500 ps
T1312 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2272446780 Aug 11 04:52:19 PM PDT 24 Aug 11 04:52:20 PM PDT 24 114855029 ps
T1313 /workspace/coverage/cover_reg_top/6.uart_csr_rw.3595670677 Aug 11 04:52:21 PM PDT 24 Aug 11 04:52:22 PM PDT 24 22708812 ps
T1314 /workspace/coverage/cover_reg_top/4.uart_csr_rw.727465346 Aug 11 04:52:20 PM PDT 24 Aug 11 04:52:21 PM PDT 24 120461826 ps

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.3146275737
Short name T9
Test name
Test status
Simulation time 290311927852 ps
CPU time 790.01 seconds
Started Aug 11 04:26:47 PM PDT 24
Finished Aug 11 04:39:57 PM PDT 24
Peak memory 216248 kb
Host smart-45cdf0e8-a179-4e0f-814c-95d75515e840
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146275737 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3146275737
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.3328019172
Short name T14
Test name
Test status
Simulation time 166782699415 ps
CPU time 856.53 seconds
Started Aug 11 04:26:58 PM PDT 24
Finished Aug 11 04:41:15 PM PDT 24
Peak memory 224640 kb
Host smart-79876175-b77a-4e4f-84b1-1903f0216164
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328019172 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.3328019172
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.1980927819
Short name T35
Test name
Test status
Simulation time 161553609393 ps
CPU time 658.52 seconds
Started Aug 11 04:27:59 PM PDT 24
Finished Aug 11 04:38:58 PM PDT 24
Peak memory 216432 kb
Host smart-7e97f576-b036-489b-94e6-05ec781093cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980927819 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.1980927819
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.1506753960
Short name T31
Test name
Test status
Simulation time 125983309580 ps
CPU time 300.26 seconds
Started Aug 11 04:27:41 PM PDT 24
Finished Aug 11 04:32:42 PM PDT 24
Peak memory 216340 kb
Host smart-b8226f69-9838-409e-ae06-186efdaa9ba7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506753960 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.1506753960
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.3310229361
Short name T113
Test name
Test status
Simulation time 260350972353 ps
CPU time 620.74 seconds
Started Aug 11 04:28:12 PM PDT 24
Finished Aug 11 04:38:33 PM PDT 24
Peak memory 228868 kb
Host smart-7179e9be-a423-4d68-b37e-9b470f64a94f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310229361 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3310229361
Directory /workspace/99.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1548500212
Short name T53
Test name
Test status
Simulation time 213265115194 ps
CPU time 811.87 seconds
Started Aug 11 04:26:57 PM PDT 24
Finished Aug 11 04:40:29 PM PDT 24
Peak memory 230160 kb
Host smart-b11bb390-5895-40d4-9ac0-b8f3d7cf1690
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548500212 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1548500212
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_sec_cm.343858885
Short name T26
Test name
Test status
Simulation time 1264047703 ps
CPU time 0.83 seconds
Started Aug 11 04:26:15 PM PDT 24
Finished Aug 11 04:26:16 PM PDT 24
Peak memory 218372 kb
Host smart-62bd076a-c0fc-462b-9483-0f2f1014829a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343858885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.343858885
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/37.uart_stress_all.647788468
Short name T146
Test name
Test status
Simulation time 110180782060 ps
CPU time 99.53 seconds
Started Aug 11 04:27:26 PM PDT 24
Finished Aug 11 04:29:05 PM PDT 24
Peak memory 215608 kb
Host smart-723f1658-7ab3-41a9-93fb-df350e9e5f0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647788468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.647788468
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1695227451
Short name T269
Test name
Test status
Simulation time 82896499290 ps
CPU time 159.46 seconds
Started Aug 11 04:27:10 PM PDT 24
Finished Aug 11 04:29:50 PM PDT 24
Peak memory 199724 kb
Host smart-18f015d2-b69a-436d-a898-0f562f8be304
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1695227451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1695227451
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_stress_all.1796571850
Short name T388
Test name
Test status
Simulation time 129748673370 ps
CPU time 403.42 seconds
Started Aug 11 04:27:04 PM PDT 24
Finished Aug 11 04:33:47 PM PDT 24
Peak memory 199724 kb
Host smart-c8e67f36-0150-443d-a5e7-d671e628784d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796571850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1796571850
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3486120446
Short name T133
Test name
Test status
Simulation time 349646720693 ps
CPU time 651.45 seconds
Started Aug 11 04:27:12 PM PDT 24
Finished Aug 11 04:38:03 PM PDT 24
Peak memory 227072 kb
Host smart-c4bf1394-3cc8-4405-a34b-91569cbf1cef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486120446 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3486120446
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.1211447611
Short name T5
Test name
Test status
Simulation time 27533312290 ps
CPU time 50.21 seconds
Started Aug 11 04:26:40 PM PDT 24
Finished Aug 11 04:27:30 PM PDT 24
Peak memory 200084 kb
Host smart-bfeda9cf-d231-4d43-995f-9e2292abd6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211447611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1211447611
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.2386336212
Short name T36
Test name
Test status
Simulation time 528514257655 ps
CPU time 745.55 seconds
Started Aug 11 04:27:42 PM PDT 24
Finished Aug 11 04:40:08 PM PDT 24
Peak memory 216232 kb
Host smart-d113aad7-6263-405c-911e-cc1a26295069
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386336212 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.2386336212
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.183917127
Short name T43
Test name
Test status
Simulation time 137781882010 ps
CPU time 124.88 seconds
Started Aug 11 04:27:28 PM PDT 24
Finished Aug 11 04:29:33 PM PDT 24
Peak memory 199772 kb
Host smart-0b79e703-68d0-4743-93df-f76549ec0785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183917127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.183917127
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.476418866
Short name T443
Test name
Test status
Simulation time 216936418843 ps
CPU time 515.58 seconds
Started Aug 11 04:28:42 PM PDT 24
Finished Aug 11 04:37:18 PM PDT 24
Peak memory 199660 kb
Host smart-049683b1-d5b3-4627-9b54-6fdf74782719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476418866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.476418866
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1326077390
Short name T93
Test name
Test status
Simulation time 69775002 ps
CPU time 1.36 seconds
Started Aug 11 04:52:17 PM PDT 24
Finished Aug 11 04:52:19 PM PDT 24
Peak memory 199608 kb
Host smart-fd79148d-ecf2-4c01-8cb4-6d07cb52a112
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326077390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1326077390
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/19.uart_fifo_full.3985591010
Short name T296
Test name
Test status
Simulation time 192263392460 ps
CPU time 270.32 seconds
Started Aug 11 04:26:42 PM PDT 24
Finished Aug 11 04:31:12 PM PDT 24
Peak memory 199720 kb
Host smart-84b62361-6def-4e61-aa7e-83c4490dbe20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985591010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3985591010
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3315569931
Short name T149
Test name
Test status
Simulation time 39296612430 ps
CPU time 957.95 seconds
Started Aug 11 04:23:34 PM PDT 24
Finished Aug 11 04:39:32 PM PDT 24
Peak memory 216064 kb
Host smart-df098fad-7da3-49de-b0fc-2b411e7dab90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315569931 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3315569931
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_alert_test.3384999449
Short name T70
Test name
Test status
Simulation time 15614102 ps
CPU time 0.59 seconds
Started Aug 11 04:23:00 PM PDT 24
Finished Aug 11 04:23:00 PM PDT 24
Peak memory 195224 kb
Host smart-95b0989d-9c79-4d52-b9e8-45e454756f3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384999449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.3384999449
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_stress_all.1691235281
Short name T413
Test name
Test status
Simulation time 310714061136 ps
CPU time 595.16 seconds
Started Aug 11 04:27:22 PM PDT 24
Finished Aug 11 04:37:17 PM PDT 24
Peak memory 199752 kb
Host smart-8dcff2f9-88b1-4fe2-b584-909124e1250d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691235281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1691235281
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all.3815829642
Short name T130
Test name
Test status
Simulation time 384406835162 ps
CPU time 171.49 seconds
Started Aug 11 04:27:44 PM PDT 24
Finished Aug 11 04:30:36 PM PDT 24
Peak memory 208096 kb
Host smart-a6d37ee5-5ad2-4ab1-802e-b7a3c14f1801
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815829642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3815829642
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.2031129598
Short name T39
Test name
Test status
Simulation time 135265631433 ps
CPU time 52.29 seconds
Started Aug 11 04:28:39 PM PDT 24
Finished Aug 11 04:29:32 PM PDT 24
Peak memory 199808 kb
Host smart-74d7cfc4-b540-4543-a28d-be1fac18db6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031129598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2031129598
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2698252721
Short name T286
Test name
Test status
Simulation time 143597760558 ps
CPU time 299.96 seconds
Started Aug 11 04:28:41 PM PDT 24
Finished Aug 11 04:33:41 PM PDT 24
Peak memory 199668 kb
Host smart-51e58cb7-1350-438e-82a5-cd9b14094f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698252721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2698252721
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.2745352308
Short name T758
Test name
Test status
Simulation time 15079957982 ps
CPU time 23.81 seconds
Started Aug 11 04:27:08 PM PDT 24
Finished Aug 11 04:27:32 PM PDT 24
Peak memory 199872 kb
Host smart-15eb5f0d-302d-4f2b-b829-098e46f1e25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745352308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2745352308
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_tx_rx.3095650414
Short name T48
Test name
Test status
Simulation time 110586836674 ps
CPU time 45.4 seconds
Started Aug 11 04:27:36 PM PDT 24
Finished Aug 11 04:28:21 PM PDT 24
Peak memory 199660 kb
Host smart-38d9398d-995a-454c-9c29-8546cbc77a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095650414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3095650414
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.781506352
Short name T84
Test name
Test status
Simulation time 13292281 ps
CPU time 0.64 seconds
Started Aug 11 04:52:15 PM PDT 24
Finished Aug 11 04:52:16 PM PDT 24
Peak memory 195624 kb
Host smart-57f36c77-ade8-46e2-8c21-bf76d05baa84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781506352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.781506352
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3249956821
Short name T65
Test name
Test status
Simulation time 76623329 ps
CPU time 0.63 seconds
Started Aug 11 04:52:29 PM PDT 24
Finished Aug 11 04:52:29 PM PDT 24
Peak memory 195768 kb
Host smart-deb869be-ebdd-4e72-b0c3-faf396cb6c3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249956821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3249956821
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/default/37.uart_noise_filter.3395074682
Short name T71
Test name
Test status
Simulation time 52102226335 ps
CPU time 58.55 seconds
Started Aug 11 04:27:36 PM PDT 24
Finished Aug 11 04:28:35 PM PDT 24
Peak memory 199964 kb
Host smart-dc7fbfb5-cfa5-46a1-a4b7-043116fc23e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395074682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3395074682
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1427131364
Short name T228
Test name
Test status
Simulation time 61192202142 ps
CPU time 110.41 seconds
Started Aug 11 04:28:40 PM PDT 24
Finished Aug 11 04:30:31 PM PDT 24
Peak memory 199776 kb
Host smart-623cb000-b015-4bec-a59d-5fc371752e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427131364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1427131364
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3447721156
Short name T144
Test name
Test status
Simulation time 20878484722 ps
CPU time 11.7 seconds
Started Aug 11 04:27:55 PM PDT 24
Finished Aug 11 04:28:07 PM PDT 24
Peak memory 199684 kb
Host smart-e1dc0fdd-9863-431a-a1f7-df71110e151b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447721156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3447721156
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_full.3039857238
Short name T76
Test name
Test status
Simulation time 177032221158 ps
CPU time 42.55 seconds
Started Aug 11 04:26:36 PM PDT 24
Finished Aug 11 04:27:19 PM PDT 24
Peak memory 199624 kb
Host smart-cce8bff9-0a3f-48bf-94a1-09cb7b1ca12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039857238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3039857238
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.446480780
Short name T134
Test name
Test status
Simulation time 213024554 ps
CPU time 1.42 seconds
Started Aug 11 04:52:12 PM PDT 24
Finished Aug 11 04:52:13 PM PDT 24
Peak memory 199552 kb
Host smart-8e396431-1a7a-483f-aa9f-64c7f4908ab4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446480780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.446480780
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/default/20.uart_stress_all.1366339973
Short name T182
Test name
Test status
Simulation time 127346870865 ps
CPU time 217.14 seconds
Started Aug 11 04:26:50 PM PDT 24
Finished Aug 11 04:30:28 PM PDT 24
Peak memory 199664 kb
Host smart-ecd23d71-bf02-479d-86a0-1381f34b9307
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366339973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1366339973
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2283690004
Short name T191
Test name
Test status
Simulation time 104325686103 ps
CPU time 33.87 seconds
Started Aug 11 04:28:26 PM PDT 24
Finished Aug 11 04:29:00 PM PDT 24
Peak memory 199700 kb
Host smart-b4476ae9-83ea-4c72-8c9d-0c1c4597d92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283690004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2283690004
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_stress_all.1869209888
Short name T212
Test name
Test status
Simulation time 336969529178 ps
CPU time 214.4 seconds
Started Aug 11 04:26:55 PM PDT 24
Finished Aug 11 04:30:30 PM PDT 24
Peak memory 199740 kb
Host smart-5d2378fd-0366-402d-ae1f-c83644078958
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869209888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1869209888
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2994059635
Short name T242
Test name
Test status
Simulation time 205635751604 ps
CPU time 114.49 seconds
Started Aug 11 04:28:39 PM PDT 24
Finished Aug 11 04:30:34 PM PDT 24
Peak memory 199828 kb
Host smart-28797e3e-bce4-4f9c-a351-bfdb6e6b2b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994059635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2994059635
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_perf.4008458902
Short name T6
Test name
Test status
Simulation time 12582519640 ps
CPU time 149 seconds
Started Aug 11 04:26:53 PM PDT 24
Finished Aug 11 04:29:23 PM PDT 24
Peak memory 199740 kb
Host smart-13c847c0-51e5-4588-8962-167dbca23e65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4008458902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.4008458902
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.3237105660
Short name T74
Test name
Test status
Simulation time 142092786139 ps
CPU time 132.92 seconds
Started Aug 11 04:28:34 PM PDT 24
Finished Aug 11 04:30:47 PM PDT 24
Peak memory 199824 kb
Host smart-f8553634-795e-47a2-9b34-e426cdbc4351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237105660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3237105660
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2990167944
Short name T168
Test name
Test status
Simulation time 101301754703 ps
CPU time 41.63 seconds
Started Aug 11 04:26:52 PM PDT 24
Finished Aug 11 04:27:34 PM PDT 24
Peak memory 199748 kb
Host smart-a5042388-3739-4a5c-9871-035bc9df6443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990167944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2990167944
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.920274499
Short name T180
Test name
Test status
Simulation time 87828664947 ps
CPU time 11.88 seconds
Started Aug 11 04:28:39 PM PDT 24
Finished Aug 11 04:28:52 PM PDT 24
Peak memory 199756 kb
Host smart-2387ced8-9acf-4e85-93d9-52b76b26922c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920274499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.920274499
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.4079409714
Short name T347
Test name
Test status
Simulation time 70714606256 ps
CPU time 152.38 seconds
Started Aug 11 04:28:26 PM PDT 24
Finished Aug 11 04:30:58 PM PDT 24
Peak memory 199744 kb
Host smart-5d06adde-8560-4322-9b70-0f01fe962792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079409714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.4079409714
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.668284061
Short name T159
Test name
Test status
Simulation time 234211386010 ps
CPU time 691.48 seconds
Started Aug 11 04:28:27 PM PDT 24
Finished Aug 11 04:39:59 PM PDT 24
Peak memory 199776 kb
Host smart-d5a02d95-ce21-4c82-997a-d9b1d78544d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668284061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.668284061
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.981192688
Short name T225
Test name
Test status
Simulation time 80116871956 ps
CPU time 31.06 seconds
Started Aug 11 04:28:45 PM PDT 24
Finished Aug 11 04:29:16 PM PDT 24
Peak memory 199816 kb
Host smart-cbd644df-8c34-456f-a8c6-91d220e759bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981192688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.981192688
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_stress_all.1909092252
Short name T265
Test name
Test status
Simulation time 130454174058 ps
CPU time 209.57 seconds
Started Aug 11 04:21:38 PM PDT 24
Finished Aug 11 04:25:07 PM PDT 24
Peak memory 215424 kb
Host smart-95a32361-6114-4b64-9f7e-770064d3e8e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909092252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1909092252
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2307908015
Short name T163
Test name
Test status
Simulation time 127396124149 ps
CPU time 42.79 seconds
Started Aug 11 04:26:26 PM PDT 24
Finished Aug 11 04:27:09 PM PDT 24
Peak memory 199700 kb
Host smart-18ca7c86-2570-45c0-b4d8-396b21de2004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307908015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2307908015
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.3268527734
Short name T223
Test name
Test status
Simulation time 33183119426 ps
CPU time 26.88 seconds
Started Aug 11 04:28:09 PM PDT 24
Finished Aug 11 04:28:36 PM PDT 24
Peak memory 199744 kb
Host smart-32d809ce-4e6b-4d41-8bd3-66da0d17ebb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268527734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3268527734
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3456874294
Short name T38
Test name
Test status
Simulation time 23902679490 ps
CPU time 37.58 seconds
Started Aug 11 04:26:49 PM PDT 24
Finished Aug 11 04:27:27 PM PDT 24
Peak memory 199640 kb
Host smart-9bc71776-118f-4934-b787-a4506828ff31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456874294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3456874294
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.3427249140
Short name T156
Test name
Test status
Simulation time 29753844608 ps
CPU time 15.83 seconds
Started Aug 11 04:28:30 PM PDT 24
Finished Aug 11 04:28:46 PM PDT 24
Peak memory 199696 kb
Host smart-3fc9a6a5-b24e-48e7-a280-21eb67e5f3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427249140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.3427249140
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1871284905
Short name T338
Test name
Test status
Simulation time 75927168565 ps
CPU time 876.22 seconds
Started Aug 11 04:26:33 PM PDT 24
Finished Aug 11 04:41:10 PM PDT 24
Peak memory 224572 kb
Host smart-ee6ec521-3299-4811-9dc3-946d9d42e8b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871284905 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1871284905
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.1641605797
Short name T254
Test name
Test status
Simulation time 278642025887 ps
CPU time 127.28 seconds
Started Aug 11 04:28:13 PM PDT 24
Finished Aug 11 04:30:20 PM PDT 24
Peak memory 199812 kb
Host smart-98cb4de5-5981-42e5-922d-6509372a48eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641605797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1641605797
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2850725785
Short name T229
Test name
Test status
Simulation time 15806796404 ps
CPU time 25.96 seconds
Started Aug 11 04:26:35 PM PDT 24
Finished Aug 11 04:27:01 PM PDT 24
Peak memory 199424 kb
Host smart-90882eb6-d87b-424a-ac41-11bc0111ecad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850725785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2850725785
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.1885594326
Short name T203
Test name
Test status
Simulation time 96744710859 ps
CPU time 24.55 seconds
Started Aug 11 04:28:25 PM PDT 24
Finished Aug 11 04:28:50 PM PDT 24
Peak memory 199760 kb
Host smart-067d3750-f07d-459a-947b-cc750662999f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885594326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1885594326
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2273525183
Short name T998
Test name
Test status
Simulation time 85614288730 ps
CPU time 34.34 seconds
Started Aug 11 04:28:15 PM PDT 24
Finished Aug 11 04:28:49 PM PDT 24
Peak memory 199708 kb
Host smart-640f6d79-f160-42ef-b430-5596ad5a8f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273525183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2273525183
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1588361151
Short name T506
Test name
Test status
Simulation time 177336825681 ps
CPU time 75.77 seconds
Started Aug 11 04:26:49 PM PDT 24
Finished Aug 11 04:28:04 PM PDT 24
Peak memory 199736 kb
Host smart-ba71d4e7-6979-4c30-a5b3-ce412bb589c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588361151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1588361151
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2519325093
Short name T241
Test name
Test status
Simulation time 58521568289 ps
CPU time 87.78 seconds
Started Aug 11 04:28:46 PM PDT 24
Finished Aug 11 04:30:14 PM PDT 24
Peak memory 199360 kb
Host smart-483c75e2-aaee-492f-9298-e7166eb8460a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519325093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2519325093
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.1221803378
Short name T239
Test name
Test status
Simulation time 149729413192 ps
CPU time 366.66 seconds
Started Aug 11 04:28:39 PM PDT 24
Finished Aug 11 04:34:46 PM PDT 24
Peak memory 199824 kb
Host smart-4ba118bc-a9cf-488d-9efc-6502bfbda2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221803378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1221803378
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.1023392431
Short name T245
Test name
Test status
Simulation time 49550090554 ps
CPU time 22.35 seconds
Started Aug 11 04:28:51 PM PDT 24
Finished Aug 11 04:29:14 PM PDT 24
Peak memory 199700 kb
Host smart-39b906d6-e585-4259-8b39-069bb2679288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023392431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1023392431
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.391543782
Short name T142
Test name
Test status
Simulation time 27505153354 ps
CPU time 21.01 seconds
Started Aug 11 04:28:49 PM PDT 24
Finished Aug 11 04:29:10 PM PDT 24
Peak memory 200116 kb
Host smart-0f3d5b95-f0d1-426e-ac8b-b8bd6a834522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391543782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.391543782
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.144665039
Short name T127
Test name
Test status
Simulation time 30736785259 ps
CPU time 15.94 seconds
Started Aug 11 04:21:17 PM PDT 24
Finished Aug 11 04:21:33 PM PDT 24
Peak memory 199772 kb
Host smart-545722f3-a2ae-4d41-94ec-7d7b0dfb8874
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144665039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.144665039
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2234992443
Short name T365
Test name
Test status
Simulation time 155314764083 ps
CPU time 323.61 seconds
Started Aug 11 04:23:00 PM PDT 24
Finished Aug 11 04:28:23 PM PDT 24
Peak memory 199552 kb
Host smart-5dcf4e0d-d315-4c15-b3a3-558c2d9ca1da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2234992443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2234992443
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1546731215
Short name T256
Test name
Test status
Simulation time 55370642080 ps
CPU time 20.47 seconds
Started Aug 11 04:28:08 PM PDT 24
Finished Aug 11 04:28:29 PM PDT 24
Peak memory 199736 kb
Host smart-3a2c7612-5356-42cc-b477-b3c3725928ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546731215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1546731215
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.3012193214
Short name T208
Test name
Test status
Simulation time 77095099959 ps
CPU time 28.52 seconds
Started Aug 11 04:28:10 PM PDT 24
Finished Aug 11 04:28:38 PM PDT 24
Peak memory 199776 kb
Host smart-e52da6d6-53b1-4cb5-a8bd-56b83c055671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012193214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3012193214
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.865681130
Short name T373
Test name
Test status
Simulation time 47830600372 ps
CPU time 37.88 seconds
Started Aug 11 04:28:12 PM PDT 24
Finished Aug 11 04:28:50 PM PDT 24
Peak memory 199836 kb
Host smart-a7aaa59e-c5cb-4a3d-ad75-bec1cf25cadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865681130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.865681130
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.10613533
Short name T257
Test name
Test status
Simulation time 15882949727 ps
CPU time 25.49 seconds
Started Aug 11 04:28:08 PM PDT 24
Finished Aug 11 04:28:34 PM PDT 24
Peak memory 199628 kb
Host smart-d84de6a8-dd94-4b30-b5f2-6890e0e74571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10613533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.10613533
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3096809244
Short name T1167
Test name
Test status
Simulation time 58467897764 ps
CPU time 46.94 seconds
Started Aug 11 04:28:11 PM PDT 24
Finished Aug 11 04:28:58 PM PDT 24
Peak memory 199560 kb
Host smart-4fa8e035-fae8-4a77-92b3-751c14edd6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096809244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3096809244
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1247520716
Short name T198
Test name
Test status
Simulation time 133765460480 ps
CPU time 338.82 seconds
Started Aug 11 04:26:34 PM PDT 24
Finished Aug 11 04:32:13 PM PDT 24
Peak memory 216256 kb
Host smart-325afef3-5c76-4609-8067-ca2749945065
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247520716 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1247520716
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.882750655
Short name T1152
Test name
Test status
Simulation time 87288786127 ps
CPU time 179.67 seconds
Started Aug 11 04:26:37 PM PDT 24
Finished Aug 11 04:29:36 PM PDT 24
Peak memory 199724 kb
Host smart-60bba3d6-5d53-4f4e-a0b0-b3d91f6539fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882750655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.882750655
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.3398646529
Short name T162
Test name
Test status
Simulation time 27820822895 ps
CPU time 20.21 seconds
Started Aug 11 04:28:46 PM PDT 24
Finished Aug 11 04:29:07 PM PDT 24
Peak memory 199268 kb
Host smart-7a79c060-fd85-4d44-b929-dfc494899d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398646529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3398646529
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1965281361
Short name T172
Test name
Test status
Simulation time 25805098904 ps
CPU time 13.7 seconds
Started Aug 11 04:28:52 PM PDT 24
Finished Aug 11 04:29:05 PM PDT 24
Peak memory 199764 kb
Host smart-5e4d3d46-4f6e-4c2e-8d70-e69612df4508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965281361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1965281361
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.2207149305
Short name T233
Test name
Test status
Simulation time 115660539300 ps
CPU time 154.63 seconds
Started Aug 11 04:28:42 PM PDT 24
Finished Aug 11 04:31:17 PM PDT 24
Peak memory 199752 kb
Host smart-cd2bc647-7db4-4e12-9b95-de00f5dfaec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207149305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2207149305
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.2230703852
Short name T58
Test name
Test status
Simulation time 506011520959 ps
CPU time 1535.36 seconds
Started Aug 11 04:27:56 PM PDT 24
Finished Aug 11 04:53:31 PM PDT 24
Peak memory 232728 kb
Host smart-b8fdf174-a069-45b1-a796-95347cc29661
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230703852 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.2230703852
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3230825938
Short name T258
Test name
Test status
Simulation time 63710056890 ps
CPU time 178.82 seconds
Started Aug 11 04:26:11 PM PDT 24
Finished Aug 11 04:29:10 PM PDT 24
Peak memory 216364 kb
Host smart-1220dc22-160f-4c97-8663-fbb097090a51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230825938 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3230825938
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2168975630
Short name T259
Test name
Test status
Simulation time 160841934904 ps
CPU time 17.04 seconds
Started Aug 11 04:27:58 PM PDT 24
Finished Aug 11 04:28:15 PM PDT 24
Peak memory 199768 kb
Host smart-e2164529-9d66-4c39-8052-d354df124ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168975630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2168975630
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3354079548
Short name T1280
Test name
Test status
Simulation time 140387853 ps
CPU time 0.79 seconds
Started Aug 11 04:52:14 PM PDT 24
Finished Aug 11 04:52:15 PM PDT 24
Peak memory 196656 kb
Host smart-c6639933-9a36-45a7-97f4-234c850aa606
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354079548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3354079548
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1067179448
Short name T1235
Test name
Test status
Simulation time 519975302 ps
CPU time 1.55 seconds
Started Aug 11 04:52:12 PM PDT 24
Finished Aug 11 04:52:14 PM PDT 24
Peak memory 198196 kb
Host smart-3e0edd4e-587f-470a-92e3-91730d9cab99
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067179448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1067179448
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4042500902
Short name T81
Test name
Test status
Simulation time 23958006 ps
CPU time 0.61 seconds
Started Aug 11 04:52:13 PM PDT 24
Finished Aug 11 04:52:13 PM PDT 24
Peak memory 195688 kb
Host smart-7d7232ff-aec9-41db-b843-a3e29cacdb32
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042500902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.4042500902
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1159063086
Short name T1245
Test name
Test status
Simulation time 30924392 ps
CPU time 0.87 seconds
Started Aug 11 04:52:15 PM PDT 24
Finished Aug 11 04:52:15 PM PDT 24
Peak memory 200040 kb
Host smart-ac96b53e-6779-4c87-8e09-1205c6270594
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159063086 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1159063086
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.467795940
Short name T1191
Test name
Test status
Simulation time 10644308 ps
CPU time 0.57 seconds
Started Aug 11 04:52:15 PM PDT 24
Finished Aug 11 04:52:15 PM PDT 24
Peak memory 194616 kb
Host smart-647df1a8-d1c9-418c-b76f-be97e291a262
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467795940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.467795940
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2646371279
Short name T87
Test name
Test status
Simulation time 26901477 ps
CPU time 0.68 seconds
Started Aug 11 04:52:15 PM PDT 24
Finished Aug 11 04:52:16 PM PDT 24
Peak memory 195132 kb
Host smart-0f71b7f6-d163-4459-a00e-f36a51cb7d77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646371279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.2646371279
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.41502393
Short name T1260
Test name
Test status
Simulation time 118059247 ps
CPU time 2.56 seconds
Started Aug 11 04:52:14 PM PDT 24
Finished Aug 11 04:52:16 PM PDT 24
Peak memory 200256 kb
Host smart-677f4fd5-aa0b-4e30-afda-a2ec680b55c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41502393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.41502393
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.4069515442
Short name T92
Test name
Test status
Simulation time 362420353 ps
CPU time 1.32 seconds
Started Aug 11 04:52:18 PM PDT 24
Finished Aug 11 04:52:20 PM PDT 24
Peak memory 199560 kb
Host smart-f0f66b5d-829b-4c7d-b8f0-676071139338
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069515442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.4069515442
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3238481407
Short name T1271
Test name
Test status
Simulation time 72412621 ps
CPU time 0.7 seconds
Started Aug 11 04:52:14 PM PDT 24
Finished Aug 11 04:52:14 PM PDT 24
Peak memory 195024 kb
Host smart-528c9a78-2dcb-4547-9c90-b4fbfb54ee1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238481407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3238481407
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1902216074
Short name T1301
Test name
Test status
Simulation time 59347780 ps
CPU time 2.29 seconds
Started Aug 11 04:52:14 PM PDT 24
Finished Aug 11 04:52:17 PM PDT 24
Peak memory 198136 kb
Host smart-ddd6e56d-4b20-4dfa-b60d-9a2170819c41
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902216074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1902216074
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3363392741
Short name T1225
Test name
Test status
Simulation time 18042421 ps
CPU time 0.61 seconds
Started Aug 11 04:52:14 PM PDT 24
Finished Aug 11 04:52:15 PM PDT 24
Peak memory 195576 kb
Host smart-b7449f6c-b30c-48eb-87f5-2240c55423b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363392741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3363392741
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2656104732
Short name T1248
Test name
Test status
Simulation time 58878117 ps
CPU time 0.72 seconds
Started Aug 11 04:52:14 PM PDT 24
Finished Aug 11 04:52:14 PM PDT 24
Peak memory 198384 kb
Host smart-2ff53152-4f26-42b7-8935-26d53f012fae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656104732 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2656104732
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3579187890
Short name T1296
Test name
Test status
Simulation time 17705783 ps
CPU time 0.61 seconds
Started Aug 11 04:52:19 PM PDT 24
Finished Aug 11 04:52:20 PM PDT 24
Peak memory 196000 kb
Host smart-b87e2ac5-0652-473c-80db-3e3975b41db7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579187890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3579187890
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3316668900
Short name T1199
Test name
Test status
Simulation time 12505541 ps
CPU time 0.59 seconds
Started Aug 11 04:52:13 PM PDT 24
Finished Aug 11 04:52:14 PM PDT 24
Peak memory 194648 kb
Host smart-dd6815ac-a970-416d-a5d8-974c2bbcda2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316668900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3316668900
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1695225965
Short name T1279
Test name
Test status
Simulation time 40800058 ps
CPU time 0.63 seconds
Started Aug 11 04:52:15 PM PDT 24
Finished Aug 11 04:52:16 PM PDT 24
Peak memory 194788 kb
Host smart-f67ad7d5-90d9-460c-94d6-8a69a9e255fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695225965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1695225965
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3362186881
Short name T1206
Test name
Test status
Simulation time 73402248 ps
CPU time 1.2 seconds
Started Aug 11 04:52:14 PM PDT 24
Finished Aug 11 04:52:15 PM PDT 24
Peak memory 200076 kb
Host smart-1dd4487f-106a-449f-9066-7d97c851accb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362186881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3362186881
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.569853351
Short name T1232
Test name
Test status
Simulation time 51941842 ps
CPU time 0.79 seconds
Started Aug 11 04:52:31 PM PDT 24
Finished Aug 11 04:52:32 PM PDT 24
Peak memory 198812 kb
Host smart-f9322b70-6d0d-4b2e-a001-662c109ff829
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569853351 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.569853351
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3190124303
Short name T1211
Test name
Test status
Simulation time 95193472 ps
CPU time 0.55 seconds
Started Aug 11 04:52:41 PM PDT 24
Finished Aug 11 04:52:42 PM PDT 24
Peak memory 194628 kb
Host smart-cd82564f-6a0e-477a-85b3-1621baaa64cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190124303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3190124303
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.231449111
Short name T1286
Test name
Test status
Simulation time 135619916 ps
CPU time 0.64 seconds
Started Aug 11 04:52:29 PM PDT 24
Finished Aug 11 04:52:29 PM PDT 24
Peak memory 195712 kb
Host smart-3ed82f4b-3398-4d7e-b9fc-cce39aff4d4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231449111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.231449111
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2940310727
Short name T1256
Test name
Test status
Simulation time 60313587 ps
CPU time 1.46 seconds
Started Aug 11 04:52:25 PM PDT 24
Finished Aug 11 04:52:26 PM PDT 24
Peak memory 200236 kb
Host smart-45658996-676d-4ffc-821e-c88864c6531b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940310727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2940310727
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.881553021
Short name T97
Test name
Test status
Simulation time 51659194 ps
CPU time 1 seconds
Started Aug 11 04:52:25 PM PDT 24
Finished Aug 11 04:52:26 PM PDT 24
Peak memory 199284 kb
Host smart-88e8fd14-5da3-4222-a89f-4d0d8ee81808
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881553021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.881553021
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.891621435
Short name T1267
Test name
Test status
Simulation time 73444519 ps
CPU time 0.86 seconds
Started Aug 11 04:52:24 PM PDT 24
Finished Aug 11 04:52:25 PM PDT 24
Peak memory 200112 kb
Host smart-b12d753f-3f9e-4dca-bbc8-7cc7ddbf0ebc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891621435 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.891621435
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.1648116632
Short name T1181
Test name
Test status
Simulation time 167057795 ps
CPU time 0.58 seconds
Started Aug 11 04:52:41 PM PDT 24
Finished Aug 11 04:52:42 PM PDT 24
Peak memory 195660 kb
Host smart-d611dc95-98a3-4d87-a6a4-36d854e1642e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648116632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1648116632
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.3004837789
Short name T1212
Test name
Test status
Simulation time 21001100 ps
CPU time 0.6 seconds
Started Aug 11 04:52:25 PM PDT 24
Finished Aug 11 04:52:26 PM PDT 24
Peak memory 194696 kb
Host smart-7144ec83-c649-4cdc-844a-59f1e77d5ba0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004837789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3004837789
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1143138860
Short name T1266
Test name
Test status
Simulation time 19894868 ps
CPU time 0.77 seconds
Started Aug 11 04:52:25 PM PDT 24
Finished Aug 11 04:52:26 PM PDT 24
Peak memory 197396 kb
Host smart-1d5f24e7-141f-456c-8484-5d600e6c81ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143138860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1143138860
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.2425231188
Short name T1240
Test name
Test status
Simulation time 424016608 ps
CPU time 1.19 seconds
Started Aug 11 04:52:25 PM PDT 24
Finished Aug 11 04:52:27 PM PDT 24
Peak memory 200324 kb
Host smart-7a3f8af8-d5b6-417b-89bc-28af098445b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425231188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2425231188
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2614500184
Short name T90
Test name
Test status
Simulation time 139916550 ps
CPU time 0.98 seconds
Started Aug 11 04:52:29 PM PDT 24
Finished Aug 11 04:52:30 PM PDT 24
Peak memory 199068 kb
Host smart-efd69f3a-164c-498d-ac7b-e5d18f972fc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614500184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2614500184
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1676245379
Short name T1285
Test name
Test status
Simulation time 28569472 ps
CPU time 1.37 seconds
Started Aug 11 04:52:29 PM PDT 24
Finished Aug 11 04:52:31 PM PDT 24
Peak memory 200336 kb
Host smart-07dad9a5-7411-408b-aedc-8f67bf9bf50a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676245379 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1676245379
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.1667952126
Short name T1251
Test name
Test status
Simulation time 14479250 ps
CPU time 0.6 seconds
Started Aug 11 04:52:27 PM PDT 24
Finished Aug 11 04:52:28 PM PDT 24
Peak memory 195664 kb
Host smart-683e5f52-0f15-4aa0-83a7-386d4e91a4d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667952126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1667952126
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2280886918
Short name T1207
Test name
Test status
Simulation time 21239490 ps
CPU time 0.58 seconds
Started Aug 11 04:52:25 PM PDT 24
Finished Aug 11 04:52:26 PM PDT 24
Peak memory 194672 kb
Host smart-082ceb8b-5e58-4844-bae1-df76d0ac2559
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280886918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2280886918
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1052310798
Short name T1255
Test name
Test status
Simulation time 21665559 ps
CPU time 0.65 seconds
Started Aug 11 04:52:28 PM PDT 24
Finished Aug 11 04:52:29 PM PDT 24
Peak memory 195896 kb
Host smart-b2b9cc13-07e5-441d-8ec1-aaad1c6314fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052310798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1052310798
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.453543790
Short name T1220
Test name
Test status
Simulation time 205613744 ps
CPU time 2.11 seconds
Started Aug 11 04:52:25 PM PDT 24
Finished Aug 11 04:52:27 PM PDT 24
Peak memory 200280 kb
Host smart-1bdf22d0-ce1f-4847-bbb7-892bc716126d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453543790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.453543790
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2641956875
Short name T94
Test name
Test status
Simulation time 88498953 ps
CPU time 1.38 seconds
Started Aug 11 04:52:23 PM PDT 24
Finished Aug 11 04:52:25 PM PDT 24
Peak memory 199676 kb
Host smart-ab50e6b0-e5f6-4d4b-b6d6-511f7097962b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641956875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2641956875
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2136296154
Short name T1303
Test name
Test status
Simulation time 21077990 ps
CPU time 1.12 seconds
Started Aug 11 04:52:29 PM PDT 24
Finished Aug 11 04:52:31 PM PDT 24
Peak memory 200084 kb
Host smart-609d315c-022a-4961-9edf-2d205b8dab85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136296154 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2136296154
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.2927142060
Short name T89
Test name
Test status
Simulation time 13501259 ps
CPU time 0.6 seconds
Started Aug 11 04:52:42 PM PDT 24
Finished Aug 11 04:52:42 PM PDT 24
Peak memory 195660 kb
Host smart-01448dfb-86ec-4515-9ee5-d6debb31317f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927142060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2927142060
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3259282005
Short name T1195
Test name
Test status
Simulation time 12536146 ps
CPU time 0.61 seconds
Started Aug 11 04:52:25 PM PDT 24
Finished Aug 11 04:52:26 PM PDT 24
Peak memory 194584 kb
Host smart-acf5820f-ab52-4d7c-966d-06dfe936f5ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259282005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3259282005
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.778469681
Short name T85
Test name
Test status
Simulation time 102193448 ps
CPU time 0.76 seconds
Started Aug 11 04:52:28 PM PDT 24
Finished Aug 11 04:52:29 PM PDT 24
Peak memory 197768 kb
Host smart-725a73a0-c5fc-4c0f-ab43-c3598b6842a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778469681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.778469681
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.4172997282
Short name T1204
Test name
Test status
Simulation time 122666005 ps
CPU time 2.38 seconds
Started Aug 11 04:52:22 PM PDT 24
Finished Aug 11 04:52:25 PM PDT 24
Peak memory 200336 kb
Host smart-7b1a3a6c-3e5f-4c1e-9f74-df26bc22ccab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172997282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.4172997282
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.495233391
Short name T1223
Test name
Test status
Simulation time 92096654 ps
CPU time 1.33 seconds
Started Aug 11 04:52:24 PM PDT 24
Finished Aug 11 04:52:26 PM PDT 24
Peak memory 199600 kb
Host smart-ed5f0136-2407-4963-a388-79c02b246e3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495233391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.495233391
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.4205665873
Short name T1190
Test name
Test status
Simulation time 189666223 ps
CPU time 0.89 seconds
Started Aug 11 04:52:31 PM PDT 24
Finished Aug 11 04:52:32 PM PDT 24
Peak memory 200016 kb
Host smart-e590abb5-0798-4428-8568-87f280c66212
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205665873 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.4205665873
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1565803284
Short name T1306
Test name
Test status
Simulation time 23358057 ps
CPU time 0.59 seconds
Started Aug 11 04:52:22 PM PDT 24
Finished Aug 11 04:52:23 PM PDT 24
Peak memory 195712 kb
Host smart-33a544f2-eeeb-45dc-8f63-8213120c398c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565803284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1565803284
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.2947176267
Short name T1283
Test name
Test status
Simulation time 23628194 ps
CPU time 0.6 seconds
Started Aug 11 04:52:26 PM PDT 24
Finished Aug 11 04:52:26 PM PDT 24
Peak memory 194672 kb
Host smart-b47bb9cf-220f-47a8-9f87-56802ea291bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947176267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2947176267
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2148844461
Short name T82
Test name
Test status
Simulation time 74678122 ps
CPU time 0.64 seconds
Started Aug 11 04:52:28 PM PDT 24
Finished Aug 11 04:52:29 PM PDT 24
Peak memory 194908 kb
Host smart-f873598d-223d-4e44-a44a-49c70ddb29c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148844461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2148844461
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.3148723744
Short name T1218
Test name
Test status
Simulation time 52995733 ps
CPU time 1.35 seconds
Started Aug 11 04:52:29 PM PDT 24
Finished Aug 11 04:52:31 PM PDT 24
Peak memory 200264 kb
Host smart-7a7b3f88-c243-4a33-861c-2134acebf28e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148723744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3148723744
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3603128949
Short name T1274
Test name
Test status
Simulation time 176032479 ps
CPU time 1 seconds
Started Aug 11 04:52:25 PM PDT 24
Finished Aug 11 04:52:26 PM PDT 24
Peak memory 199132 kb
Host smart-0242b6da-28db-42fe-96a8-f812e3a17092
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603128949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3603128949
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4097357240
Short name T1201
Test name
Test status
Simulation time 84523133 ps
CPU time 1.14 seconds
Started Aug 11 04:52:32 PM PDT 24
Finished Aug 11 04:52:33 PM PDT 24
Peak memory 200216 kb
Host smart-9c2da6ef-ef68-4c04-803e-c777a880c675
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097357240 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.4097357240
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.4053742547
Short name T80
Test name
Test status
Simulation time 35978474 ps
CPU time 0.61 seconds
Started Aug 11 04:52:31 PM PDT 24
Finished Aug 11 04:52:31 PM PDT 24
Peak memory 195648 kb
Host smart-336ad9f0-6ea9-4d36-a073-a9ed53b97469
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053742547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.4053742547
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3679324396
Short name T1214
Test name
Test status
Simulation time 11228590 ps
CPU time 0.57 seconds
Started Aug 11 04:52:41 PM PDT 24
Finished Aug 11 04:52:42 PM PDT 24
Peak memory 194632 kb
Host smart-d36e4052-f9fe-469d-93f6-b2e5e0a3a8fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679324396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3679324396
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2005679323
Short name T1231
Test name
Test status
Simulation time 19082030 ps
CPU time 0.72 seconds
Started Aug 11 04:52:37 PM PDT 24
Finished Aug 11 04:52:37 PM PDT 24
Peak memory 197332 kb
Host smart-39e6c915-9db3-49b9-bff6-7c0ceaaa9c22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005679323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.2005679323
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3323545667
Short name T1217
Test name
Test status
Simulation time 238807625 ps
CPU time 1.38 seconds
Started Aug 11 04:52:41 PM PDT 24
Finished Aug 11 04:52:43 PM PDT 24
Peak memory 200304 kb
Host smart-1c97348f-e5c5-46e1-89e0-0669e3ae4a3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323545667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3323545667
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2452099127
Short name T1309
Test name
Test status
Simulation time 85612939 ps
CPU time 0.97 seconds
Started Aug 11 04:52:25 PM PDT 24
Finished Aug 11 04:52:26 PM PDT 24
Peak memory 199144 kb
Host smart-f0e61183-4d63-49a5-80a5-ccf63b1865e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452099127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2452099127
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2004559389
Short name T1287
Test name
Test status
Simulation time 29660754 ps
CPU time 1.04 seconds
Started Aug 11 04:52:30 PM PDT 24
Finished Aug 11 04:52:31 PM PDT 24
Peak memory 200076 kb
Host smart-41692a35-c8b2-4f94-9cc2-35341a9a771a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004559389 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2004559389
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.3060558850
Short name T1294
Test name
Test status
Simulation time 27667319 ps
CPU time 0.67 seconds
Started Aug 11 04:52:31 PM PDT 24
Finished Aug 11 04:52:32 PM PDT 24
Peak memory 195876 kb
Host smart-9d1aaf84-57b5-4d06-bf02-8a41d731157b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060558850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3060558850
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.696441365
Short name T1226
Test name
Test status
Simulation time 33580363 ps
CPU time 0.55 seconds
Started Aug 11 04:53:08 PM PDT 24
Finished Aug 11 04:53:09 PM PDT 24
Peak memory 194624 kb
Host smart-15afd0c4-9d52-4eec-b19a-110446b910fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696441365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.696441365
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2532484894
Short name T1236
Test name
Test status
Simulation time 16082632 ps
CPU time 0.7 seconds
Started Aug 11 04:52:43 PM PDT 24
Finished Aug 11 04:52:44 PM PDT 24
Peak memory 195228 kb
Host smart-55bc1811-2a6b-49be-8595-f7d6f6a8945c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532484894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.2532484894
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3495154703
Short name T1290
Test name
Test status
Simulation time 253088525 ps
CPU time 2.21 seconds
Started Aug 11 04:52:38 PM PDT 24
Finished Aug 11 04:52:41 PM PDT 24
Peak memory 200316 kb
Host smart-74efb8d6-3b7c-4392-bde4-3292ea3cf0ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495154703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3495154703
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3856066096
Short name T100
Test name
Test status
Simulation time 195231877 ps
CPU time 0.97 seconds
Started Aug 11 04:52:42 PM PDT 24
Finished Aug 11 04:52:43 PM PDT 24
Peak memory 198844 kb
Host smart-4e1a36c1-39c1-459d-bfb1-29bc2311e30b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856066096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3856066096
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2930137381
Short name T1275
Test name
Test status
Simulation time 52840501 ps
CPU time 0.91 seconds
Started Aug 11 04:52:36 PM PDT 24
Finished Aug 11 04:52:37 PM PDT 24
Peak memory 200100 kb
Host smart-2449db41-6c78-44d5-a6ec-f542257698ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930137381 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2930137381
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3619845538
Short name T79
Test name
Test status
Simulation time 24488137 ps
CPU time 0.61 seconds
Started Aug 11 04:52:34 PM PDT 24
Finished Aug 11 04:52:35 PM PDT 24
Peak memory 195712 kb
Host smart-aac09821-d9f4-4aa8-876d-116cfd519ab7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619845538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3619845538
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2741816539
Short name T1233
Test name
Test status
Simulation time 13480191 ps
CPU time 0.6 seconds
Started Aug 11 04:52:41 PM PDT 24
Finished Aug 11 04:52:42 PM PDT 24
Peak memory 194632 kb
Host smart-0b0388cb-0aff-4923-8e25-cdf8d82330c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741816539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2741816539
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.439040788
Short name T1269
Test name
Test status
Simulation time 17970233 ps
CPU time 0.76 seconds
Started Aug 11 04:52:36 PM PDT 24
Finished Aug 11 04:52:36 PM PDT 24
Peak memory 197560 kb
Host smart-3c089a9c-bc94-4bbd-98b8-3365d0c1673a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439040788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.439040788
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.1673970323
Short name T1293
Test name
Test status
Simulation time 39489325 ps
CPU time 2.22 seconds
Started Aug 11 04:52:31 PM PDT 24
Finished Aug 11 04:52:34 PM PDT 24
Peak memory 200304 kb
Host smart-55319844-bcc0-4dab-93b5-8706904c52bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673970323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1673970323
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3569633433
Short name T1230
Test name
Test status
Simulation time 121713179 ps
CPU time 0.96 seconds
Started Aug 11 04:52:43 PM PDT 24
Finished Aug 11 04:52:44 PM PDT 24
Peak memory 199268 kb
Host smart-09af3635-61b4-4d76-82ee-495a4ad45946
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569633433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3569633433
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1026353616
Short name T1264
Test name
Test status
Simulation time 69611119 ps
CPU time 0.69 seconds
Started Aug 11 04:52:38 PM PDT 24
Finished Aug 11 04:52:39 PM PDT 24
Peak memory 198592 kb
Host smart-175f4070-15ec-497d-8cf8-1a18c475dd93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026353616 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1026353616
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.454184597
Short name T1252
Test name
Test status
Simulation time 40092831 ps
CPU time 0.66 seconds
Started Aug 11 04:52:32 PM PDT 24
Finished Aug 11 04:52:33 PM PDT 24
Peak memory 195740 kb
Host smart-d23eb60d-b869-4f65-977b-87f30dc472d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454184597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.454184597
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.2629589900
Short name T1180
Test name
Test status
Simulation time 11356161 ps
CPU time 0.6 seconds
Started Aug 11 04:52:33 PM PDT 24
Finished Aug 11 04:52:34 PM PDT 24
Peak memory 194676 kb
Host smart-f442cbbb-da40-4155-886d-1082904265bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629589900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2629589900
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2723852400
Short name T83
Test name
Test status
Simulation time 81879044 ps
CPU time 0.71 seconds
Started Aug 11 04:52:45 PM PDT 24
Finished Aug 11 04:52:47 PM PDT 24
Peak memory 197300 kb
Host smart-3247b3e0-dbb1-4568-ba65-f27221b4684f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723852400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2723852400
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2980476749
Short name T1224
Test name
Test status
Simulation time 126405510 ps
CPU time 2.18 seconds
Started Aug 11 04:52:48 PM PDT 24
Finished Aug 11 04:52:51 PM PDT 24
Peak memory 200340 kb
Host smart-8d83713f-af9a-4b4a-9643-0406ba09fb0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980476749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2980476749
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.543348819
Short name T98
Test name
Test status
Simulation time 313554622 ps
CPU time 1.22 seconds
Started Aug 11 04:53:08 PM PDT 24
Finished Aug 11 04:53:10 PM PDT 24
Peak memory 199464 kb
Host smart-f50b13e5-5e5b-42db-8330-89a42ed6fbb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543348819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.543348819
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3462622804
Short name T1200
Test name
Test status
Simulation time 121144042 ps
CPU time 0.84 seconds
Started Aug 11 04:52:45 PM PDT 24
Finished Aug 11 04:52:46 PM PDT 24
Peak memory 200096 kb
Host smart-61439abb-33e7-47ff-9a53-8e581c93a79b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462622804 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3462622804
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.7084799
Short name T68
Test name
Test status
Simulation time 47112736 ps
CPU time 0.6 seconds
Started Aug 11 04:52:36 PM PDT 24
Finished Aug 11 04:52:37 PM PDT 24
Peak memory 195692 kb
Host smart-c8f3255f-4c87-400b-ad50-067342618d81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7084799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.7084799
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.2303651569
Short name T1202
Test name
Test status
Simulation time 16074141 ps
CPU time 0.76 seconds
Started Aug 11 04:52:36 PM PDT 24
Finished Aug 11 04:52:38 PM PDT 24
Peak memory 193784 kb
Host smart-b70e9947-3779-40d0-8524-2bed3d76ef72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303651569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2303651569
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3215220276
Short name T86
Test name
Test status
Simulation time 17839148 ps
CPU time 0.71 seconds
Started Aug 11 04:52:31 PM PDT 24
Finished Aug 11 04:52:32 PM PDT 24
Peak memory 196024 kb
Host smart-56964989-a78e-4f1b-a920-dd043c546bd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215220276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.3215220276
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.4102391327
Short name T1250
Test name
Test status
Simulation time 240796749 ps
CPU time 1.63 seconds
Started Aug 11 04:52:30 PM PDT 24
Finished Aug 11 04:52:32 PM PDT 24
Peak memory 200240 kb
Host smart-e55e5ba6-3e0c-433b-9304-3a2084858de6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102391327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.4102391327
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1683238441
Short name T1238
Test name
Test status
Simulation time 96496395 ps
CPU time 1.4 seconds
Started Aug 11 04:52:42 PM PDT 24
Finished Aug 11 04:52:43 PM PDT 24
Peak memory 199668 kb
Host smart-a1311e45-90fb-47a8-a302-de6a1db2f587
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683238441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1683238441
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1588458022
Short name T1282
Test name
Test status
Simulation time 12900959 ps
CPU time 0.65 seconds
Started Aug 11 04:52:15 PM PDT 24
Finished Aug 11 04:52:16 PM PDT 24
Peak memory 195664 kb
Host smart-d7b7caf8-fdff-483f-93c7-6d899c878df9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588458022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1588458022
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.454309268
Short name T1265
Test name
Test status
Simulation time 352309756 ps
CPU time 1.61 seconds
Started Aug 11 04:52:14 PM PDT 24
Finished Aug 11 04:52:16 PM PDT 24
Peak memory 198156 kb
Host smart-9b432806-b395-499d-af49-f78eaca95a40
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454309268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.454309268
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.4150905447
Short name T66
Test name
Test status
Simulation time 40313716 ps
CPU time 0.57 seconds
Started Aug 11 04:52:17 PM PDT 24
Finished Aug 11 04:52:18 PM PDT 24
Peak memory 195620 kb
Host smart-27eaedfb-7136-453d-ab42-b66d6497d0b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150905447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.4150905447
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.4215985907
Short name T1184
Test name
Test status
Simulation time 55909248 ps
CPU time 0.82 seconds
Started Aug 11 04:52:16 PM PDT 24
Finished Aug 11 04:52:16 PM PDT 24
Peak memory 200080 kb
Host smart-382fc869-98c2-42f1-aa46-0caab01b79b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215985907 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.4215985907
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.4201060309
Short name T1189
Test name
Test status
Simulation time 13058703 ps
CPU time 0.6 seconds
Started Aug 11 04:52:13 PM PDT 24
Finished Aug 11 04:52:14 PM PDT 24
Peak memory 195660 kb
Host smart-b9d78b08-196a-4b15-aee6-a972ecd0bf05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201060309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.4201060309
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.1838136452
Short name T1284
Test name
Test status
Simulation time 16764801 ps
CPU time 0.58 seconds
Started Aug 11 04:52:15 PM PDT 24
Finished Aug 11 04:52:16 PM PDT 24
Peak memory 194972 kb
Host smart-9c760325-68e6-4997-a252-65de6594fc7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838136452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1838136452
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3915708322
Short name T1222
Test name
Test status
Simulation time 111422187 ps
CPU time 0.75 seconds
Started Aug 11 04:52:14 PM PDT 24
Finished Aug 11 04:52:15 PM PDT 24
Peak memory 198036 kb
Host smart-4ebabf27-b980-432f-a8e6-a105144b0ecd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915708322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3915708322
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.4109768820
Short name T1257
Test name
Test status
Simulation time 341349166 ps
CPU time 1.48 seconds
Started Aug 11 04:52:18 PM PDT 24
Finished Aug 11 04:52:19 PM PDT 24
Peak memory 200264 kb
Host smart-a36bb57c-05cf-4b1d-8b82-d5946d3a23ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109768820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.4109768820
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.710035250
Short name T1270
Test name
Test status
Simulation time 11311649 ps
CPU time 0.57 seconds
Started Aug 11 04:52:35 PM PDT 24
Finished Aug 11 04:52:35 PM PDT 24
Peak memory 194684 kb
Host smart-68370097-7a62-47b2-8cc0-206820737f92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710035250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.710035250
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.3671079146
Short name T1258
Test name
Test status
Simulation time 15275237 ps
CPU time 0.59 seconds
Started Aug 11 04:52:44 PM PDT 24
Finished Aug 11 04:52:45 PM PDT 24
Peak memory 194676 kb
Host smart-c312c07a-5159-4343-9cfd-d6c37a92ba68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671079146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3671079146
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2993012787
Short name T1298
Test name
Test status
Simulation time 16120892 ps
CPU time 0.61 seconds
Started Aug 11 04:52:33 PM PDT 24
Finished Aug 11 04:52:34 PM PDT 24
Peak memory 194624 kb
Host smart-3c3de777-6187-4eab-a314-0377dc2cc886
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993012787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2993012787
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.1226761715
Short name T1213
Test name
Test status
Simulation time 52652787 ps
CPU time 0.61 seconds
Started Aug 11 04:52:32 PM PDT 24
Finished Aug 11 04:52:32 PM PDT 24
Peak memory 194636 kb
Host smart-c8bf7b6f-e370-41d1-8338-9c96d3fe7955
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226761715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1226761715
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1818160780
Short name T1304
Test name
Test status
Simulation time 20408659 ps
CPU time 0.62 seconds
Started Aug 11 04:52:38 PM PDT 24
Finished Aug 11 04:52:39 PM PDT 24
Peak memory 194580 kb
Host smart-626e5f08-915b-42a9-831a-9a0b66fd1b74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818160780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1818160780
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2566489514
Short name T1209
Test name
Test status
Simulation time 13562137 ps
CPU time 0.56 seconds
Started Aug 11 04:52:47 PM PDT 24
Finished Aug 11 04:52:48 PM PDT 24
Peak memory 194676 kb
Host smart-9a6061c8-2acd-47bb-a9a4-1d02b6d0388c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566489514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2566489514
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.2281296234
Short name T1276
Test name
Test status
Simulation time 76359187 ps
CPU time 0.59 seconds
Started Aug 11 04:52:38 PM PDT 24
Finished Aug 11 04:52:39 PM PDT 24
Peak memory 194588 kb
Host smart-120b86e3-8163-42a2-bab3-da9117941847
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281296234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2281296234
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.212118960
Short name T1272
Test name
Test status
Simulation time 57920039 ps
CPU time 0.59 seconds
Started Aug 11 04:52:44 PM PDT 24
Finished Aug 11 04:52:44 PM PDT 24
Peak memory 194692 kb
Host smart-c159b3fb-4fe5-4575-b414-46ce6bb1e71c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212118960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.212118960
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.829204534
Short name T1241
Test name
Test status
Simulation time 27979928 ps
CPU time 0.62 seconds
Started Aug 11 04:52:32 PM PDT 24
Finished Aug 11 04:52:33 PM PDT 24
Peak memory 194616 kb
Host smart-99d74b70-afd5-4d95-af99-d9de63fe7c9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829204534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.829204534
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.17545166
Short name T1308
Test name
Test status
Simulation time 29608985 ps
CPU time 0.61 seconds
Started Aug 11 04:52:32 PM PDT 24
Finished Aug 11 04:52:33 PM PDT 24
Peak memory 194632 kb
Host smart-01462398-dada-455d-b68b-e4fe880edc42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17545166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.17545166
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2008853970
Short name T67
Test name
Test status
Simulation time 16233551 ps
CPU time 0.8 seconds
Started Aug 11 04:52:18 PM PDT 24
Finished Aug 11 04:52:19 PM PDT 24
Peak memory 196608 kb
Host smart-881005c5-0dc0-40be-a3c0-133b6ad1f357
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008853970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2008853970
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2070727394
Short name T1310
Test name
Test status
Simulation time 639073375 ps
CPU time 2.59 seconds
Started Aug 11 04:52:17 PM PDT 24
Finished Aug 11 04:52:20 PM PDT 24
Peak memory 197840 kb
Host smart-7c4a8ec8-51b2-45dd-ac20-85f36f7139fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070727394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2070727394
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1421690619
Short name T1188
Test name
Test status
Simulation time 21949076 ps
CPU time 0.6 seconds
Started Aug 11 04:52:15 PM PDT 24
Finished Aug 11 04:52:15 PM PDT 24
Peak memory 195684 kb
Host smart-75192275-8565-48c6-b9bc-2afd36ca685f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421690619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1421690619
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3820761992
Short name T1302
Test name
Test status
Simulation time 40580367 ps
CPU time 1.21 seconds
Started Aug 11 04:52:20 PM PDT 24
Finished Aug 11 04:52:22 PM PDT 24
Peak memory 200344 kb
Host smart-8b992c57-4f7f-4297-8fcd-b18c73fd9740
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820761992 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3820761992
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2038689356
Short name T1228
Test name
Test status
Simulation time 43504922 ps
CPU time 0.64 seconds
Started Aug 11 04:52:15 PM PDT 24
Finished Aug 11 04:52:15 PM PDT 24
Peak memory 195764 kb
Host smart-b02a6b87-510e-4f0f-8091-ea8e03081095
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038689356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2038689356
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3246326298
Short name T1205
Test name
Test status
Simulation time 13796365 ps
CPU time 0.64 seconds
Started Aug 11 04:52:13 PM PDT 24
Finished Aug 11 04:52:14 PM PDT 24
Peak memory 194636 kb
Host smart-1c506fc6-d3af-4882-b8f8-ae5c2a3c9100
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246326298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3246326298
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1955938028
Short name T1281
Test name
Test status
Simulation time 92021641 ps
CPU time 0.74 seconds
Started Aug 11 04:52:21 PM PDT 24
Finished Aug 11 04:52:22 PM PDT 24
Peak memory 197256 kb
Host smart-63c6211c-0c08-4ef6-b062-f5eb8957ad2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955938028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1955938028
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.4097069573
Short name T1295
Test name
Test status
Simulation time 144890066 ps
CPU time 1.9 seconds
Started Aug 11 04:52:19 PM PDT 24
Finished Aug 11 04:52:21 PM PDT 24
Peak memory 200324 kb
Host smart-bf7d3bda-d3e5-4bae-9b06-56f9e77cf6d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097069573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.4097069573
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.587668481
Short name T1305
Test name
Test status
Simulation time 119842389 ps
CPU time 0.93 seconds
Started Aug 11 04:52:14 PM PDT 24
Finished Aug 11 04:52:15 PM PDT 24
Peak memory 199308 kb
Host smart-c1eb96b6-9a4b-4a23-a5c8-44296c883805
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587668481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.587668481
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.191144434
Short name T1198
Test name
Test status
Simulation time 16629585 ps
CPU time 0.59 seconds
Started Aug 11 04:52:43 PM PDT 24
Finished Aug 11 04:52:44 PM PDT 24
Peak memory 194672 kb
Host smart-8e53575b-866e-4226-94a8-95dda4a41272
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191144434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.191144434
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2065507717
Short name T1216
Test name
Test status
Simulation time 53946864 ps
CPU time 0.59 seconds
Started Aug 11 04:52:44 PM PDT 24
Finished Aug 11 04:52:45 PM PDT 24
Peak memory 194620 kb
Host smart-364441b6-1677-4a83-8c78-46bfbdd17c8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065507717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2065507717
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1899974427
Short name T1185
Test name
Test status
Simulation time 22799430 ps
CPU time 0.61 seconds
Started Aug 11 04:52:46 PM PDT 24
Finished Aug 11 04:52:47 PM PDT 24
Peak memory 194624 kb
Host smart-3cf402c4-083a-429d-8678-2371d7113515
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899974427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1899974427
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.3323064067
Short name T1277
Test name
Test status
Simulation time 84602222 ps
CPU time 0.59 seconds
Started Aug 11 04:52:38 PM PDT 24
Finished Aug 11 04:52:38 PM PDT 24
Peak memory 194652 kb
Host smart-8cf41feb-11a3-475f-84cb-e940130fa1ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323064067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3323064067
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.3261137207
Short name T1186
Test name
Test status
Simulation time 47200496 ps
CPU time 0.58 seconds
Started Aug 11 04:52:36 PM PDT 24
Finished Aug 11 04:52:37 PM PDT 24
Peak memory 194696 kb
Host smart-c43dc832-ca6a-4b7c-ab9e-07c5157cbe82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261137207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3261137207
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.183536001
Short name T1193
Test name
Test status
Simulation time 16992096 ps
CPU time 0.58 seconds
Started Aug 11 04:52:44 PM PDT 24
Finished Aug 11 04:52:45 PM PDT 24
Peak memory 194668 kb
Host smart-fc03c59b-b894-4723-91c5-1716de42ae72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183536001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.183536001
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1339060239
Short name T1187
Test name
Test status
Simulation time 22995573 ps
CPU time 0.58 seconds
Started Aug 11 04:52:44 PM PDT 24
Finished Aug 11 04:52:45 PM PDT 24
Peak memory 194676 kb
Host smart-e367c575-34b3-4a45-82c4-403411f3a7c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339060239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1339060239
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.3975351848
Short name T1229
Test name
Test status
Simulation time 36766468 ps
CPU time 0.59 seconds
Started Aug 11 04:52:44 PM PDT 24
Finished Aug 11 04:52:45 PM PDT 24
Peak memory 194668 kb
Host smart-82a548f3-2e07-4ec4-8017-0b41f9a0b5c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975351848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.3975351848
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.25482320
Short name T1278
Test name
Test status
Simulation time 26959910 ps
CPU time 0.61 seconds
Started Aug 11 04:52:44 PM PDT 24
Finished Aug 11 04:52:44 PM PDT 24
Peak memory 194696 kb
Host smart-019af02c-83c4-4ca3-b075-b6ea611aeada
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25482320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.25482320
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.2018721711
Short name T1242
Test name
Test status
Simulation time 13950571 ps
CPU time 0.59 seconds
Started Aug 11 04:52:46 PM PDT 24
Finished Aug 11 04:52:47 PM PDT 24
Peak memory 194676 kb
Host smart-b71a18ab-7ef8-47df-a5e6-a044f2532712
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018721711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2018721711
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1800267498
Short name T63
Test name
Test status
Simulation time 57385827 ps
CPU time 0.76 seconds
Started Aug 11 04:52:20 PM PDT 24
Finished Aug 11 04:52:21 PM PDT 24
Peak memory 196536 kb
Host smart-5cccc603-39bd-4329-b57f-9536ad90fa09
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800267498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1800267498
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2595545012
Short name T1196
Test name
Test status
Simulation time 63092866 ps
CPU time 1.38 seconds
Started Aug 11 04:52:21 PM PDT 24
Finished Aug 11 04:52:23 PM PDT 24
Peak memory 197952 kb
Host smart-6210d635-daca-4b51-868c-d2a7c6918b78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595545012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2595545012
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3039453321
Short name T64
Test name
Test status
Simulation time 47308732 ps
CPU time 0.62 seconds
Started Aug 11 04:52:20 PM PDT 24
Finished Aug 11 04:52:21 PM PDT 24
Peak memory 195684 kb
Host smart-729e5c83-4f1a-477a-bc5c-1deb1dbc8ea9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039453321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3039453321
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2272446780
Short name T1312
Test name
Test status
Simulation time 114855029 ps
CPU time 0.63 seconds
Started Aug 11 04:52:19 PM PDT 24
Finished Aug 11 04:52:20 PM PDT 24
Peak memory 197480 kb
Host smart-6e7d7129-64eb-4fc3-acfc-7b84e6dbb055
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272446780 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2272446780
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.727465346
Short name T1314
Test name
Test status
Simulation time 120461826 ps
CPU time 0.63 seconds
Started Aug 11 04:52:20 PM PDT 24
Finished Aug 11 04:52:21 PM PDT 24
Peak memory 195652 kb
Host smart-a80fa5db-2ee1-418d-988b-dcdeb8917466
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727465346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.727465346
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.329716497
Short name T1197
Test name
Test status
Simulation time 10911621 ps
CPU time 0.56 seconds
Started Aug 11 04:52:21 PM PDT 24
Finished Aug 11 04:52:22 PM PDT 24
Peak memory 194640 kb
Host smart-ba215d2f-3571-43f6-92bf-1db9a581d384
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329716497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.329716497
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3361727186
Short name T1268
Test name
Test status
Simulation time 15884606 ps
CPU time 0.69 seconds
Started Aug 11 04:52:20 PM PDT 24
Finished Aug 11 04:52:20 PM PDT 24
Peak memory 195788 kb
Host smart-52bb9446-067c-422d-abc9-5c1bf112d982
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361727186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.3361727186
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1234551084
Short name T1311
Test name
Test status
Simulation time 137353500 ps
CPU time 2.27 seconds
Started Aug 11 04:52:20 PM PDT 24
Finished Aug 11 04:52:23 PM PDT 24
Peak memory 200348 kb
Host smart-ff208386-6ada-4daf-8845-b78515756f63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234551084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1234551084
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3601789286
Short name T91
Test name
Test status
Simulation time 80485415 ps
CPU time 0.95 seconds
Started Aug 11 04:52:19 PM PDT 24
Finished Aug 11 04:52:20 PM PDT 24
Peak memory 199064 kb
Host smart-b135034b-0ad3-4e8c-b0b9-c6d1b8a85d78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601789286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3601789286
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2748504136
Short name T1239
Test name
Test status
Simulation time 79202869 ps
CPU time 0.59 seconds
Started Aug 11 04:52:53 PM PDT 24
Finished Aug 11 04:52:54 PM PDT 24
Peak memory 194700 kb
Host smart-50d2eb5a-d79d-4100-b3cb-aae80744b326
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748504136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2748504136
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2631815792
Short name T1300
Test name
Test status
Simulation time 113648146 ps
CPU time 0.59 seconds
Started Aug 11 04:52:44 PM PDT 24
Finished Aug 11 04:52:45 PM PDT 24
Peak memory 194676 kb
Host smart-f642565f-c747-496a-8570-5205a01f1013
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631815792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2631815792
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.4267608204
Short name T1288
Test name
Test status
Simulation time 13287413 ps
CPU time 0.61 seconds
Started Aug 11 04:52:39 PM PDT 24
Finished Aug 11 04:52:39 PM PDT 24
Peak memory 194720 kb
Host smart-8f287b99-ac6a-46a5-b73e-adc7fa0f3512
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267608204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.4267608204
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1870554946
Short name T1210
Test name
Test status
Simulation time 123062012 ps
CPU time 0.6 seconds
Started Aug 11 04:52:48 PM PDT 24
Finished Aug 11 04:52:49 PM PDT 24
Peak memory 194692 kb
Host smart-9b1d84e3-7418-45c0-a3f3-b9ac5a77eb10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870554946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1870554946
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.440833591
Short name T1183
Test name
Test status
Simulation time 63686578 ps
CPU time 0.63 seconds
Started Aug 11 04:52:41 PM PDT 24
Finished Aug 11 04:52:42 PM PDT 24
Peak memory 194684 kb
Host smart-d47ea444-62e5-4642-9be0-6e1f083f1883
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440833591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.440833591
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3757741380
Short name T1203
Test name
Test status
Simulation time 12194370 ps
CPU time 0.59 seconds
Started Aug 11 04:52:42 PM PDT 24
Finished Aug 11 04:52:43 PM PDT 24
Peak memory 194660 kb
Host smart-9e945aaa-e064-4e0b-b909-79d8cba7dca1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757741380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3757741380
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2253460679
Short name T1291
Test name
Test status
Simulation time 13926551 ps
CPU time 0.59 seconds
Started Aug 11 04:52:39 PM PDT 24
Finished Aug 11 04:52:40 PM PDT 24
Peak memory 194676 kb
Host smart-805c3b76-7746-43e3-955b-d1149077ea13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253460679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2253460679
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.605454881
Short name T1219
Test name
Test status
Simulation time 101436873 ps
CPU time 0.62 seconds
Started Aug 11 04:52:41 PM PDT 24
Finished Aug 11 04:52:42 PM PDT 24
Peak memory 194616 kb
Host smart-45a9e696-389f-4497-bd55-e789f66b0d0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605454881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.605454881
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.3219963339
Short name T1182
Test name
Test status
Simulation time 23671153 ps
CPU time 0.57 seconds
Started Aug 11 04:52:42 PM PDT 24
Finished Aug 11 04:52:43 PM PDT 24
Peak memory 194644 kb
Host smart-deaa581f-4e31-47d1-a820-f493238b8cc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219963339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3219963339
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2251010651
Short name T1234
Test name
Test status
Simulation time 54717470 ps
CPU time 0.6 seconds
Started Aug 11 04:52:37 PM PDT 24
Finished Aug 11 04:52:38 PM PDT 24
Peak memory 194668 kb
Host smart-11e1e90d-2ec4-4e14-bab8-72abbbb0c21f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251010651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2251010651
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.134358238
Short name T1208
Test name
Test status
Simulation time 42331285 ps
CPU time 0.89 seconds
Started Aug 11 04:52:22 PM PDT 24
Finished Aug 11 04:52:23 PM PDT 24
Peak memory 200032 kb
Host smart-2b33c716-23e0-4210-84a6-464e782d2fce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134358238 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.134358238
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.512559178
Short name T1261
Test name
Test status
Simulation time 12881668 ps
CPU time 0.65 seconds
Started Aug 11 04:52:20 PM PDT 24
Finished Aug 11 04:52:21 PM PDT 24
Peak memory 195684 kb
Host smart-07379491-92ef-4982-87e5-4d615f647653
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512559178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.512559178
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.2969352854
Short name T1246
Test name
Test status
Simulation time 21780455 ps
CPU time 0.6 seconds
Started Aug 11 04:52:19 PM PDT 24
Finished Aug 11 04:52:20 PM PDT 24
Peak memory 194692 kb
Host smart-8cdd85dd-d56c-43f7-a477-cc76fc70292b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969352854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2969352854
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2249631940
Short name T1259
Test name
Test status
Simulation time 67090048 ps
CPU time 0.67 seconds
Started Aug 11 04:52:21 PM PDT 24
Finished Aug 11 04:52:22 PM PDT 24
Peak memory 195264 kb
Host smart-31514838-e576-432d-bfab-e5c0db508eb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249631940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2249631940
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.2369380640
Short name T1244
Test name
Test status
Simulation time 34357016 ps
CPU time 1.58 seconds
Started Aug 11 04:52:20 PM PDT 24
Finished Aug 11 04:52:22 PM PDT 24
Peak memory 200280 kb
Host smart-21e614bf-dce2-40ba-bc2e-d417997224fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369380640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2369380640
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.4170520634
Short name T95
Test name
Test status
Simulation time 177435040 ps
CPU time 1.07 seconds
Started Aug 11 04:52:20 PM PDT 24
Finished Aug 11 04:52:21 PM PDT 24
Peak memory 199284 kb
Host smart-c83ff6d0-cfed-4957-9aa1-f2b73598c7b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170520634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.4170520634
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1509138037
Short name T1192
Test name
Test status
Simulation time 39665609 ps
CPU time 1.2 seconds
Started Aug 11 04:52:17 PM PDT 24
Finished Aug 11 04:52:19 PM PDT 24
Peak memory 200328 kb
Host smart-b7b47aae-0ea4-4f71-928e-b66f6900510b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509138037 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1509138037
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3595670677
Short name T1313
Test name
Test status
Simulation time 22708812 ps
CPU time 0.59 seconds
Started Aug 11 04:52:21 PM PDT 24
Finished Aug 11 04:52:22 PM PDT 24
Peak memory 195676 kb
Host smart-2d1f6a86-a590-47ee-a6be-61f1ee8721be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595670677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3595670677
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.428433717
Short name T1194
Test name
Test status
Simulation time 16943185 ps
CPU time 0.56 seconds
Started Aug 11 04:52:20 PM PDT 24
Finished Aug 11 04:52:20 PM PDT 24
Peak memory 194680 kb
Host smart-7b5b6b44-1f92-43cd-8863-7dd9eb6b5d14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428433717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.428433717
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.797295049
Short name T1273
Test name
Test status
Simulation time 59286554 ps
CPU time 0.73 seconds
Started Aug 11 04:52:20 PM PDT 24
Finished Aug 11 04:52:21 PM PDT 24
Peak memory 197276 kb
Host smart-acc770b3-6081-4b45-8fb8-1795465a57ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797295049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.797295049
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3248846262
Short name T1289
Test name
Test status
Simulation time 62819955 ps
CPU time 1.6 seconds
Started Aug 11 04:52:22 PM PDT 24
Finished Aug 11 04:52:24 PM PDT 24
Peak memory 200276 kb
Host smart-d5a61ec9-b7db-4a41-a590-0858ac33f0bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248846262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3248846262
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.4165691774
Short name T99
Test name
Test status
Simulation time 597738765 ps
CPU time 0.93 seconds
Started Aug 11 04:52:20 PM PDT 24
Finished Aug 11 04:52:21 PM PDT 24
Peak memory 199064 kb
Host smart-6ed10c0d-54b6-401f-a35e-d0e26b75ab2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165691774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.4165691774
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2939745966
Short name T1247
Test name
Test status
Simulation time 20817694 ps
CPU time 0.97 seconds
Started Aug 11 04:52:22 PM PDT 24
Finished Aug 11 04:52:23 PM PDT 24
Peak memory 200096 kb
Host smart-5e2b997c-cb36-4f8b-9785-cb95a4df523b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939745966 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2939745966
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.262885832
Short name T1237
Test name
Test status
Simulation time 13240414 ps
CPU time 0.55 seconds
Started Aug 11 04:52:19 PM PDT 24
Finished Aug 11 04:52:20 PM PDT 24
Peak memory 195692 kb
Host smart-ddcb2816-92d1-497a-9eb0-91b046260103
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262885832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.262885832
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2887571683
Short name T1249
Test name
Test status
Simulation time 23070618 ps
CPU time 0.58 seconds
Started Aug 11 04:52:20 PM PDT 24
Finished Aug 11 04:52:21 PM PDT 24
Peak memory 194588 kb
Host smart-c9a0d957-0fca-40d2-be36-26f50a41773e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887571683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2887571683
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2393827395
Short name T1253
Test name
Test status
Simulation time 49224595 ps
CPU time 0.62 seconds
Started Aug 11 04:52:19 PM PDT 24
Finished Aug 11 04:52:19 PM PDT 24
Peak memory 196080 kb
Host smart-36e08f06-afe3-47a2-8197-5c14d9ca35a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393827395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2393827395
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.3805133180
Short name T1297
Test name
Test status
Simulation time 40424406 ps
CPU time 1.96 seconds
Started Aug 11 04:52:20 PM PDT 24
Finished Aug 11 04:52:23 PM PDT 24
Peak memory 200300 kb
Host smart-5f095c61-ff98-4588-b073-880f2fe89193
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805133180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.3805133180
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2924783501
Short name T96
Test name
Test status
Simulation time 74410639 ps
CPU time 1.35 seconds
Started Aug 11 04:52:21 PM PDT 24
Finished Aug 11 04:52:22 PM PDT 24
Peak memory 199676 kb
Host smart-b15438e7-645c-4ada-bd2d-2b49819ea36b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924783501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2924783501
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1859690230
Short name T1243
Test name
Test status
Simulation time 21664710 ps
CPU time 0.78 seconds
Started Aug 11 04:52:21 PM PDT 24
Finished Aug 11 04:52:22 PM PDT 24
Peak memory 199312 kb
Host smart-c83c540d-ee31-430f-9ff2-48417be58348
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859690230 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1859690230
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3315999874
Short name T69
Test name
Test status
Simulation time 23707415 ps
CPU time 0.62 seconds
Started Aug 11 04:52:20 PM PDT 24
Finished Aug 11 04:52:21 PM PDT 24
Peak memory 195740 kb
Host smart-563424ff-bef0-4ae7-8258-f98868ad3639
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315999874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3315999874
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2848093438
Short name T1262
Test name
Test status
Simulation time 20463263 ps
CPU time 0.6 seconds
Started Aug 11 04:52:19 PM PDT 24
Finished Aug 11 04:52:20 PM PDT 24
Peak memory 194600 kb
Host smart-7563e904-1521-4d1c-abe1-b8a75ce5e76b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848093438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2848093438
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.999309396
Short name T1221
Test name
Test status
Simulation time 29768388 ps
CPU time 0.67 seconds
Started Aug 11 04:52:20 PM PDT 24
Finished Aug 11 04:52:21 PM PDT 24
Peak memory 196104 kb
Host smart-42481433-e696-463b-aa66-399edd2f718e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999309396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_
outstanding.999309396
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.735979335
Short name T1292
Test name
Test status
Simulation time 82219104 ps
CPU time 1.84 seconds
Started Aug 11 04:52:20 PM PDT 24
Finished Aug 11 04:52:22 PM PDT 24
Peak memory 200324 kb
Host smart-0d19a0fd-8ce1-4233-9c01-45da572079db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735979335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.735979335
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3786433178
Short name T1263
Test name
Test status
Simulation time 109057390 ps
CPU time 0.98 seconds
Started Aug 11 04:52:21 PM PDT 24
Finished Aug 11 04:52:22 PM PDT 24
Peak memory 199168 kb
Host smart-e065ea63-fbf7-43fe-b264-7a93a80b0f11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786433178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3786433178
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2967174423
Short name T1299
Test name
Test status
Simulation time 34999288 ps
CPU time 0.94 seconds
Started Aug 11 04:52:25 PM PDT 24
Finished Aug 11 04:52:26 PM PDT 24
Peak memory 200044 kb
Host smart-0c6beb45-93ab-4676-8dc4-90f5de6175b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967174423 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2967174423
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1695008451
Short name T1215
Test name
Test status
Simulation time 40147317 ps
CPU time 0.67 seconds
Started Aug 11 04:52:31 PM PDT 24
Finished Aug 11 04:52:32 PM PDT 24
Peak memory 195780 kb
Host smart-a2aa9389-9f22-4bc6-afd5-8a072df1403f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695008451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1695008451
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1058738213
Short name T1227
Test name
Test status
Simulation time 46646137 ps
CPU time 0.63 seconds
Started Aug 11 04:52:19 PM PDT 24
Finished Aug 11 04:52:20 PM PDT 24
Peak memory 194968 kb
Host smart-96687aef-d3ca-44ac-a7d3-66a50b611737
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058738213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1058738213
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.13848301
Short name T88
Test name
Test status
Simulation time 99357115 ps
CPU time 0.76 seconds
Started Aug 11 04:52:31 PM PDT 24
Finished Aug 11 04:52:32 PM PDT 24
Peak memory 197140 kb
Host smart-6fe2f3e1-3ae8-4688-b857-cc1ad42b03bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13848301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_o
utstanding.13848301
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.564701672
Short name T1254
Test name
Test status
Simulation time 141297700 ps
CPU time 2.42 seconds
Started Aug 11 04:52:22 PM PDT 24
Finished Aug 11 04:52:24 PM PDT 24
Peak memory 200264 kb
Host smart-58b9ac76-d7c6-4bad-b523-0114dd5b4324
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564701672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.564701672
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1631120720
Short name T1307
Test name
Test status
Simulation time 94037584 ps
CPU time 1.39 seconds
Started Aug 11 04:52:21 PM PDT 24
Finished Aug 11 04:52:22 PM PDT 24
Peak memory 199600 kb
Host smart-716cb114-8f85-4d41-bb44-f4fd6ff4dc95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631120720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1631120720
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3328729444
Short name T1013
Test name
Test status
Simulation time 41916456320 ps
CPU time 29.29 seconds
Started Aug 11 04:24:00 PM PDT 24
Finished Aug 11 04:24:29 PM PDT 24
Peak memory 199448 kb
Host smart-811638fd-38a5-4d88-964f-dc79e92f0dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328729444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3328729444
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.2855251972
Short name T1074
Test name
Test status
Simulation time 95319282371 ps
CPU time 43.03 seconds
Started Aug 11 04:24:32 PM PDT 24
Finished Aug 11 04:25:15 PM PDT 24
Peak memory 199408 kb
Host smart-4232095d-a456-4d9d-8384-abc97efd1118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855251972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.2855251972
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.389439337
Short name T195
Test name
Test status
Simulation time 46219832846 ps
CPU time 54.13 seconds
Started Aug 11 04:20:48 PM PDT 24
Finished Aug 11 04:21:42 PM PDT 24
Peak memory 200112 kb
Host smart-f970c249-bed9-4696-a186-d48b726365f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389439337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.389439337
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_loopback.3919452533
Short name T583
Test name
Test status
Simulation time 1747692973 ps
CPU time 1.41 seconds
Started Aug 11 04:19:40 PM PDT 24
Finished Aug 11 04:19:42 PM PDT 24
Peak memory 195936 kb
Host smart-6fbfd8ba-ec17-4f53-9137-ec0b2e9fe9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919452533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.3919452533
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.2291920596
Short name T589
Test name
Test status
Simulation time 73895870811 ps
CPU time 91.5 seconds
Started Aug 11 04:22:18 PM PDT 24
Finished Aug 11 04:23:49 PM PDT 24
Peak memory 200176 kb
Host smart-99e6e053-2900-4b6d-8185-a0546f219ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291920596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.2291920596
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.993476617
Short name T268
Test name
Test status
Simulation time 12933448998 ps
CPU time 81.74 seconds
Started Aug 11 04:23:54 PM PDT 24
Finished Aug 11 04:25:16 PM PDT 24
Peak memory 199352 kb
Host smart-82826f29-fcea-4036-8d1e-e113c65ad9f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=993476617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.993476617
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.188871407
Short name T552
Test name
Test status
Simulation time 3588020798 ps
CPU time 12.85 seconds
Started Aug 11 04:24:32 PM PDT 24
Finished Aug 11 04:24:45 PM PDT 24
Peak memory 198376 kb
Host smart-28d9bf51-bd58-4acd-ba3b-c9cbc4db5402
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=188871407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.188871407
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2118301
Short name T544
Test name
Test status
Simulation time 25957724147 ps
CPU time 40.23 seconds
Started Aug 11 04:23:57 PM PDT 24
Finished Aug 11 04:24:37 PM PDT 24
Peak memory 198952 kb
Host smart-d14b95f3-bc07-4244-a5c1-4c5f5a71248b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2118301
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.2478347881
Short name T479
Test name
Test status
Simulation time 3164475269 ps
CPU time 1.78 seconds
Started Aug 11 04:23:56 PM PDT 24
Finished Aug 11 04:23:58 PM PDT 24
Peak memory 196000 kb
Host smart-5f663b0e-ef74-4f42-b914-c88b7a75d15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478347881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2478347881
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3103422863
Short name T102
Test name
Test status
Simulation time 296765006 ps
CPU time 0.92 seconds
Started Aug 11 04:19:14 PM PDT 24
Finished Aug 11 04:19:15 PM PDT 24
Peak memory 218000 kb
Host smart-7db2dd4a-d336-4f38-9421-f69636e580b0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103422863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3103422863
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.2597195819
Short name T444
Test name
Test status
Simulation time 308126026 ps
CPU time 1.11 seconds
Started Aug 11 04:19:40 PM PDT 24
Finished Aug 11 04:19:41 PM PDT 24
Peak memory 198308 kb
Host smart-e5ef1614-3096-41a6-a220-b4670b21b01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597195819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2597195819
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.3262725729
Short name T1019
Test name
Test status
Simulation time 1063699988 ps
CPU time 2.4 seconds
Started Aug 11 04:23:54 PM PDT 24
Finished Aug 11 04:23:57 PM PDT 24
Peak memory 198088 kb
Host smart-83ee7e8d-ef9b-4af3-8552-f096f9d0f85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262725729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3262725729
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.223619109
Short name T104
Test name
Test status
Simulation time 42868079215 ps
CPU time 16.6 seconds
Started Aug 11 04:20:23 PM PDT 24
Finished Aug 11 04:20:39 PM PDT 24
Peak memory 199700 kb
Host smart-12981f6c-4808-49b5-ac38-f15c727ed622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223619109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.223619109
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.2435164702
Short name T445
Test name
Test status
Simulation time 11689587 ps
CPU time 0.58 seconds
Started Aug 11 04:23:55 PM PDT 24
Finished Aug 11 04:23:56 PM PDT 24
Peak memory 193100 kb
Host smart-5dabb660-15bf-46d9-adbb-2f034c7abf4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435164702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2435164702
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3076279751
Short name T892
Test name
Test status
Simulation time 38866718750 ps
CPU time 14.61 seconds
Started Aug 11 04:23:07 PM PDT 24
Finished Aug 11 04:23:22 PM PDT 24
Peak memory 199076 kb
Host smart-1bf13ca9-bd31-49c4-b9ac-371c43fa86ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076279751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3076279751
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.3256553084
Short name T274
Test name
Test status
Simulation time 35598449985 ps
CPU time 60.34 seconds
Started Aug 11 04:23:07 PM PDT 24
Finished Aug 11 04:24:07 PM PDT 24
Peak memory 199500 kb
Host smart-a8a60057-0669-455b-90cd-0b0049283187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256553084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3256553084
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2123890196
Short name T1079
Test name
Test status
Simulation time 288188003189 ps
CPU time 22.38 seconds
Started Aug 11 04:19:17 PM PDT 24
Finished Aug 11 04:19:39 PM PDT 24
Peak memory 199440 kb
Host smart-6f1e44ea-4a54-4058-ab7c-33f2ad5f9e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123890196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2123890196
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.834563926
Short name T569
Test name
Test status
Simulation time 49306761551 ps
CPU time 40.32 seconds
Started Aug 11 04:21:07 PM PDT 24
Finished Aug 11 04:21:48 PM PDT 24
Peak memory 199820 kb
Host smart-64595d48-0ee8-4d68-96ae-98722ae0ca6c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834563926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.834563926
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.4210416124
Short name T805
Test name
Test status
Simulation time 77698101444 ps
CPU time 183.44 seconds
Started Aug 11 04:23:40 PM PDT 24
Finished Aug 11 04:26:44 PM PDT 24
Peak memory 199736 kb
Host smart-b7d080d0-ca68-4453-af29-3c523a0a0518
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4210416124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.4210416124
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.967447020
Short name T1
Test name
Test status
Simulation time 1255313308 ps
CPU time 1.71 seconds
Started Aug 11 04:23:38 PM PDT 24
Finished Aug 11 04:23:40 PM PDT 24
Peak memory 197576 kb
Host smart-5867c52a-09a0-4b73-ae6f-c2354a2ead3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967447020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.967447020
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.237005350
Short name T401
Test name
Test status
Simulation time 34768440824 ps
CPU time 49.86 seconds
Started Aug 11 04:23:25 PM PDT 24
Finished Aug 11 04:24:15 PM PDT 24
Peak memory 198788 kb
Host smart-49371cf9-d48c-483a-975d-41ac09c0cbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237005350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.237005350
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.1028764960
Short name T918
Test name
Test status
Simulation time 10610022824 ps
CPU time 147.14 seconds
Started Aug 11 04:23:39 PM PDT 24
Finished Aug 11 04:26:06 PM PDT 24
Peak memory 199340 kb
Host smart-103eb8f0-b05e-468f-bb92-96fdb0d2fbff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1028764960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1028764960
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.67798080
Short name T1099
Test name
Test status
Simulation time 3396578342 ps
CPU time 20.74 seconds
Started Aug 11 04:21:09 PM PDT 24
Finished Aug 11 04:21:30 PM PDT 24
Peak memory 197752 kb
Host smart-6be4d932-8d7a-4da9-8c30-50a261439f60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=67798080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.67798080
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.3180122221
Short name T842
Test name
Test status
Simulation time 11162547427 ps
CPU time 18.74 seconds
Started Aug 11 04:24:01 PM PDT 24
Finished Aug 11 04:24:20 PM PDT 24
Peak memory 198736 kb
Host smart-7a48e68a-40ff-4581-bbd5-c60a147859ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180122221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3180122221
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.4165633233
Short name T490
Test name
Test status
Simulation time 1786802220 ps
CPU time 1.35 seconds
Started Aug 11 04:23:25 PM PDT 24
Finished Aug 11 04:23:26 PM PDT 24
Peak memory 194048 kb
Host smart-ece6c597-d415-4a91-9e5a-78bb26b38cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165633233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.4165633233
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.2080422577
Short name T28
Test name
Test status
Simulation time 1782829247 ps
CPU time 1.3 seconds
Started Aug 11 04:23:57 PM PDT 24
Finished Aug 11 04:23:59 PM PDT 24
Peak memory 217416 kb
Host smart-f8813f77-a5a1-41b5-803d-052ef5f2d8a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080422577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2080422577
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.1774963161
Short name T914
Test name
Test status
Simulation time 5806519542 ps
CPU time 14.02 seconds
Started Aug 11 04:22:53 PM PDT 24
Finished Aug 11 04:23:07 PM PDT 24
Peak memory 198532 kb
Host smart-af35b030-ed07-4769-bc66-5cf5623c4b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774963161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1774963161
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.351804161
Short name T1107
Test name
Test status
Simulation time 534648346408 ps
CPU time 1497.6 seconds
Started Aug 11 04:21:02 PM PDT 24
Finished Aug 11 04:45:59 PM PDT 24
Peak memory 208184 kb
Host smart-3efcb72a-0c68-434f-90e4-62106659dac5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351804161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.351804161
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.731535910
Short name T56
Test name
Test status
Simulation time 27484887547 ps
CPU time 548.96 seconds
Started Aug 11 04:24:02 PM PDT 24
Finished Aug 11 04:33:11 PM PDT 24
Peak memory 216044 kb
Host smart-223dc753-4d40-494d-8e30-aca9db438748
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731535910 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.731535910
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.1174045360
Short name T1062
Test name
Test status
Simulation time 5810379851 ps
CPU time 2.51 seconds
Started Aug 11 04:24:01 PM PDT 24
Finished Aug 11 04:24:04 PM PDT 24
Peak memory 198376 kb
Host smart-9ce25171-91ae-4138-8bf2-313826ac6027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174045360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1174045360
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.2164221414
Short name T953
Test name
Test status
Simulation time 109939981698 ps
CPU time 100.17 seconds
Started Aug 11 04:19:57 PM PDT 24
Finished Aug 11 04:21:37 PM PDT 24
Peak memory 199808 kb
Host smart-d20b9296-cee0-4c4a-825e-ec7153545068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164221414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2164221414
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.4278349295
Short name T650
Test name
Test status
Simulation time 14108654 ps
CPU time 0.59 seconds
Started Aug 11 04:26:30 PM PDT 24
Finished Aug 11 04:26:36 PM PDT 24
Peak memory 195168 kb
Host smart-2e004a10-fe35-4100-999f-0ded0fb274b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278349295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.4278349295
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.269007517
Short name T494
Test name
Test status
Simulation time 51305092029 ps
CPU time 23.65 seconds
Started Aug 11 04:26:29 PM PDT 24
Finished Aug 11 04:26:53 PM PDT 24
Peak memory 199692 kb
Host smart-e8a9d579-06e3-41cd-8b9b-cb11d1722d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269007517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.269007517
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2763323680
Short name T533
Test name
Test status
Simulation time 251802339908 ps
CPU time 89.02 seconds
Started Aug 11 04:26:31 PM PDT 24
Finished Aug 11 04:28:00 PM PDT 24
Peak memory 199728 kb
Host smart-969db1e9-6ae6-4c97-b4c8-04a5a9a048cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763323680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2763323680
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.1332475685
Short name T868
Test name
Test status
Simulation time 30610289490 ps
CPU time 27.24 seconds
Started Aug 11 04:26:24 PM PDT 24
Finished Aug 11 04:26:51 PM PDT 24
Peak memory 199584 kb
Host smart-fc7d76e1-18be-4af9-9e87-2d1287da238e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332475685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1332475685
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2587570677
Short name T727
Test name
Test status
Simulation time 107105202370 ps
CPU time 446.9 seconds
Started Aug 11 04:26:23 PM PDT 24
Finished Aug 11 04:33:50 PM PDT 24
Peak memory 199704 kb
Host smart-4e3c6260-ca47-4b19-ba19-6456316bc8cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2587570677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2587570677
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3149436378
Short name T974
Test name
Test status
Simulation time 1145665839 ps
CPU time 3.44 seconds
Started Aug 11 04:26:20 PM PDT 24
Finished Aug 11 04:26:23 PM PDT 24
Peak memory 198596 kb
Host smart-f722d3b3-caea-497c-a440-1d4658cf330d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149436378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3149436378
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.869544643
Short name T303
Test name
Test status
Simulation time 42642020601 ps
CPU time 67.65 seconds
Started Aug 11 04:26:44 PM PDT 24
Finished Aug 11 04:27:52 PM PDT 24
Peak memory 199296 kb
Host smart-bf5814b3-17a7-4be4-8398-e1505ab91329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869544643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.869544643
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.3825298330
Short name T664
Test name
Test status
Simulation time 6577046986 ps
CPU time 82.75 seconds
Started Aug 11 04:26:38 PM PDT 24
Finished Aug 11 04:28:01 PM PDT 24
Peak memory 199720 kb
Host smart-81a1cf37-c8b2-4b95-9af3-f38db1a608d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3825298330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.3825298330
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.280484889
Short name T848
Test name
Test status
Simulation time 1186878917 ps
CPU time 1.01 seconds
Started Aug 11 04:26:38 PM PDT 24
Finished Aug 11 04:26:40 PM PDT 24
Peak memory 195408 kb
Host smart-948e7d32-84a5-41bd-9f1a-75f2d099977a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=280484889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.280484889
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1623608251
Short name T412
Test name
Test status
Simulation time 63257294251 ps
CPU time 37.62 seconds
Started Aug 11 04:26:22 PM PDT 24
Finished Aug 11 04:27:00 PM PDT 24
Peak memory 199744 kb
Host smart-19c20fcc-d152-470b-b5b5-404cd4a435fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623608251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1623608251
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3039898504
Short name T571
Test name
Test status
Simulation time 36963499727 ps
CPU time 30.64 seconds
Started Aug 11 04:26:36 PM PDT 24
Finished Aug 11 04:27:07 PM PDT 24
Peak memory 195944 kb
Host smart-d96c3735-dc18-487b-bc48-af91d76b0d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039898504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3039898504
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.4225298950
Short name T670
Test name
Test status
Simulation time 507237400 ps
CPU time 2.05 seconds
Started Aug 11 04:26:46 PM PDT 24
Finished Aug 11 04:26:48 PM PDT 24
Peak memory 198492 kb
Host smart-9e21bb1b-1ebf-4a5d-b290-5728c4575f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225298950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.4225298950
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.3264417122
Short name T428
Test name
Test status
Simulation time 26040606584 ps
CPU time 286.67 seconds
Started Aug 11 04:26:35 PM PDT 24
Finished Aug 11 04:31:22 PM PDT 24
Peak memory 199684 kb
Host smart-37e92345-49a9-46da-8ded-e40678c05945
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264417122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3264417122
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.2012823512
Short name T19
Test name
Test status
Simulation time 12563368272 ps
CPU time 55.06 seconds
Started Aug 11 04:26:23 PM PDT 24
Finished Aug 11 04:27:19 PM PDT 24
Peak memory 199880 kb
Host smart-db86b805-a879-430f-bc21-3412b3b661c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012823512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.2012823512
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2235762447
Short name T37
Test name
Test status
Simulation time 11306676829 ps
CPU time 5.3 seconds
Started Aug 11 04:26:44 PM PDT 24
Finished Aug 11 04:26:49 PM PDT 24
Peak memory 199644 kb
Host smart-1f8e8352-fb1d-477c-b856-ecae91a17650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235762447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2235762447
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.4286524061
Short name T237
Test name
Test status
Simulation time 60749714922 ps
CPU time 99.65 seconds
Started Aug 11 04:28:16 PM PDT 24
Finished Aug 11 04:29:56 PM PDT 24
Peak memory 199672 kb
Host smart-83f2ce91-98a9-4bc8-b0e1-38f5fa5e8081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286524061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.4286524061
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2473688877
Short name T1113
Test name
Test status
Simulation time 4101328086 ps
CPU time 7.09 seconds
Started Aug 11 04:28:13 PM PDT 24
Finished Aug 11 04:28:20 PM PDT 24
Peak memory 199332 kb
Host smart-d6ed20f3-3b74-4199-9dfc-e9230ef9b9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473688877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2473688877
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1065541435
Short name T453
Test name
Test status
Simulation time 23457955265 ps
CPU time 39.97 seconds
Started Aug 11 04:28:12 PM PDT 24
Finished Aug 11 04:28:52 PM PDT 24
Peak memory 199712 kb
Host smart-862b0ed8-ed31-4be3-9c66-808f024f33de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065541435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1065541435
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.27563469
Short name T865
Test name
Test status
Simulation time 23820509161 ps
CPU time 36.51 seconds
Started Aug 11 04:28:25 PM PDT 24
Finished Aug 11 04:29:02 PM PDT 24
Peak memory 199736 kb
Host smart-8160df4a-f774-46d7-9446-921169cd1918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27563469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.27563469
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1026168517
Short name T1115
Test name
Test status
Simulation time 19260934136 ps
CPU time 39.02 seconds
Started Aug 11 04:28:15 PM PDT 24
Finished Aug 11 04:28:54 PM PDT 24
Peak memory 199892 kb
Host smart-ef84b813-1c2c-405d-b5ed-8be7a346f60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026168517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1026168517
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.433871108
Short name T1033
Test name
Test status
Simulation time 39148211157 ps
CPU time 16.9 seconds
Started Aug 11 04:28:11 PM PDT 24
Finished Aug 11 04:28:28 PM PDT 24
Peak memory 199800 kb
Host smart-d80b7765-4072-4224-b7b1-6c1d56677c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433871108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.433871108
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1967799267
Short name T260
Test name
Test status
Simulation time 180401329681 ps
CPU time 61.99 seconds
Started Aug 11 04:28:10 PM PDT 24
Finished Aug 11 04:29:12 PM PDT 24
Peak memory 199768 kb
Host smart-37ba7dfe-3ac0-4f98-bde1-c3a9d1c7265b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967799267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1967799267
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.4277583409
Short name T25
Test name
Test status
Simulation time 12456843 ps
CPU time 0.54 seconds
Started Aug 11 04:26:15 PM PDT 24
Finished Aug 11 04:26:16 PM PDT 24
Peak memory 195268 kb
Host smart-a71213a1-8a34-425e-808b-90df374402c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277583409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.4277583409
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.72413892
Short name T1140
Test name
Test status
Simulation time 137632523645 ps
CPU time 54.44 seconds
Started Aug 11 04:26:22 PM PDT 24
Finished Aug 11 04:27:16 PM PDT 24
Peak memory 199692 kb
Host smart-4d5337a2-6b4b-443f-b2a0-714cfd9e897e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72413892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.72413892
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3725138362
Short name T519
Test name
Test status
Simulation time 100996091061 ps
CPU time 82.93 seconds
Started Aug 11 04:26:23 PM PDT 24
Finished Aug 11 04:27:46 PM PDT 24
Peak memory 199800 kb
Host smart-c246b9b9-40e1-497d-ac88-ecd2f283bf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725138362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3725138362
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2957692560
Short name T909
Test name
Test status
Simulation time 26663865109 ps
CPU time 21.25 seconds
Started Aug 11 04:26:27 PM PDT 24
Finished Aug 11 04:26:48 PM PDT 24
Peak memory 199744 kb
Host smart-78115ad3-be24-4e4a-9086-86af9be1e0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957692560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2957692560
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.3225733009
Short name T1064
Test name
Test status
Simulation time 41484814150 ps
CPU time 15.66 seconds
Started Aug 11 04:26:32 PM PDT 24
Finished Aug 11 04:26:48 PM PDT 24
Peak memory 199676 kb
Host smart-cf45e49e-92db-4e14-b5b8-c642be06124f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225733009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.3225733009
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.129871171
Short name T945
Test name
Test status
Simulation time 114477825137 ps
CPU time 755.83 seconds
Started Aug 11 04:26:27 PM PDT 24
Finished Aug 11 04:39:03 PM PDT 24
Peak memory 199660 kb
Host smart-6d74f14a-f7e2-41fd-b524-c68fdabac24d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=129871171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.129871171
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.3406070363
Short name T1035
Test name
Test status
Simulation time 4887976567 ps
CPU time 3.72 seconds
Started Aug 11 04:26:24 PM PDT 24
Finished Aug 11 04:26:28 PM PDT 24
Peak memory 198840 kb
Host smart-949f304d-44a3-4d14-b6bd-34832fda9120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406070363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.3406070363
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1135888179
Short name T824
Test name
Test status
Simulation time 16361351029 ps
CPU time 13.87 seconds
Started Aug 11 04:26:23 PM PDT 24
Finished Aug 11 04:26:37 PM PDT 24
Peak memory 199800 kb
Host smart-9058463f-04ab-4b3f-8c93-4e52e23939ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135888179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1135888179
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.1729153726
Short name T1130
Test name
Test status
Simulation time 27301773560 ps
CPU time 553.27 seconds
Started Aug 11 04:26:33 PM PDT 24
Finished Aug 11 04:35:46 PM PDT 24
Peak memory 199728 kb
Host smart-fd9d0dd9-2936-4e98-ab2d-37244ee7c578
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1729153726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1729153726
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1478422984
Short name T45
Test name
Test status
Simulation time 4696854106 ps
CPU time 4.22 seconds
Started Aug 11 04:26:23 PM PDT 24
Finished Aug 11 04:26:27 PM PDT 24
Peak memory 198996 kb
Host smart-baa2cdc7-6c7d-46bb-a5e4-e881193bc3d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1478422984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1478422984
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1336672859
Short name T902
Test name
Test status
Simulation time 151100868296 ps
CPU time 120.85 seconds
Started Aug 11 04:26:40 PM PDT 24
Finished Aug 11 04:28:41 PM PDT 24
Peak memory 199764 kb
Host smart-7c31f64c-f984-450e-b343-d3c70657eb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336672859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1336672859
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.19013960
Short name T576
Test name
Test status
Simulation time 1783614156 ps
CPU time 3.34 seconds
Started Aug 11 04:26:29 PM PDT 24
Finished Aug 11 04:26:33 PM PDT 24
Peak memory 195220 kb
Host smart-996297a6-1b22-4228-a1ed-6c76be2e3f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19013960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.19013960
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3894879258
Short name T414
Test name
Test status
Simulation time 852751216 ps
CPU time 2.47 seconds
Started Aug 11 04:26:17 PM PDT 24
Finished Aug 11 04:26:20 PM PDT 24
Peak memory 199396 kb
Host smart-bc44f0bf-4317-4fad-8a3a-934fbc5861f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894879258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3894879258
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.1342296572
Short name T952
Test name
Test status
Simulation time 91193743281 ps
CPU time 110.08 seconds
Started Aug 11 04:26:51 PM PDT 24
Finished Aug 11 04:28:42 PM PDT 24
Peak memory 199764 kb
Host smart-c3e8bad5-018b-4360-8390-750e22e09b89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342296572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1342296572
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3488630830
Short name T947
Test name
Test status
Simulation time 101250176857 ps
CPU time 772.4 seconds
Started Aug 11 04:26:25 PM PDT 24
Finished Aug 11 04:39:18 PM PDT 24
Peak memory 230184 kb
Host smart-2d7acada-a04a-4792-bd62-dfbae3d93b83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488630830 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3488630830
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2135448442
Short name T18
Test name
Test status
Simulation time 345629525 ps
CPU time 1.58 seconds
Started Aug 11 04:26:26 PM PDT 24
Finished Aug 11 04:26:28 PM PDT 24
Peak memory 197528 kb
Host smart-cb744ef0-a6a6-447b-847e-5c3c632e19c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135448442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2135448442
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.1597469591
Short name T440
Test name
Test status
Simulation time 132412227536 ps
CPU time 133.44 seconds
Started Aug 11 04:26:14 PM PDT 24
Finished Aug 11 04:28:28 PM PDT 24
Peak memory 199808 kb
Host smart-d8da3254-bb9a-41a2-a27a-d17d29d74ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597469591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1597469591
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1724253311
Short name T500
Test name
Test status
Simulation time 17939141090 ps
CPU time 48.05 seconds
Started Aug 11 04:28:28 PM PDT 24
Finished Aug 11 04:29:16 PM PDT 24
Peak memory 199788 kb
Host smart-1b5d8172-8929-4b31-90ab-fdea130a6376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724253311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1724253311
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.4267836845
Short name T742
Test name
Test status
Simulation time 244510179913 ps
CPU time 45.06 seconds
Started Aug 11 04:28:12 PM PDT 24
Finished Aug 11 04:28:58 PM PDT 24
Peak memory 199812 kb
Host smart-ebc4756b-421b-47c6-9b96-f776fbae4630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267836845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.4267836845
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.3366566361
Short name T236
Test name
Test status
Simulation time 43046260196 ps
CPU time 15.72 seconds
Started Aug 11 04:28:12 PM PDT 24
Finished Aug 11 04:28:28 PM PDT 24
Peak memory 199756 kb
Host smart-4d864948-49ad-4a5d-a36a-a64122fb9671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366566361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3366566361
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.773837306
Short name T548
Test name
Test status
Simulation time 18077009212 ps
CPU time 21.41 seconds
Started Aug 11 04:28:15 PM PDT 24
Finished Aug 11 04:28:36 PM PDT 24
Peak memory 199644 kb
Host smart-cfdcd704-b099-4d54-9f19-fb731abd5403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773837306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.773837306
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.244496264
Short name T714
Test name
Test status
Simulation time 78464853861 ps
CPU time 49.14 seconds
Started Aug 11 04:28:10 PM PDT 24
Finished Aug 11 04:28:59 PM PDT 24
Peak memory 199724 kb
Host smart-6a4ce22f-9766-4c6e-a23a-bd92bd97e836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244496264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.244496264
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2206076100
Short name T787
Test name
Test status
Simulation time 7089818625 ps
CPU time 12.18 seconds
Started Aug 11 04:28:12 PM PDT 24
Finished Aug 11 04:28:24 PM PDT 24
Peak memory 199792 kb
Host smart-79df3cae-d3b6-4d13-87ca-c58083c8dd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206076100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2206076100
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2820735508
Short name T213
Test name
Test status
Simulation time 109401574666 ps
CPU time 56.77 seconds
Started Aug 11 04:28:12 PM PDT 24
Finished Aug 11 04:29:09 PM PDT 24
Peak memory 199688 kb
Host smart-d09235c6-5535-41d7-99b4-1abcd5c9d3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820735508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2820735508
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2707504374
Short name T1163
Test name
Test status
Simulation time 116718070679 ps
CPU time 81.83 seconds
Started Aug 11 04:28:31 PM PDT 24
Finished Aug 11 04:29:53 PM PDT 24
Peak memory 199788 kb
Host smart-53474a3b-ca6e-4098-854a-9530516fd845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707504374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2707504374
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3481285928
Short name T799
Test name
Test status
Simulation time 13859748 ps
CPU time 0.59 seconds
Started Aug 11 04:26:18 PM PDT 24
Finished Aug 11 04:26:19 PM PDT 24
Peak memory 195460 kb
Host smart-fc84c0fc-b46d-431d-a934-78947a319f6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481285928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3481285928
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.606874018
Short name T1006
Test name
Test status
Simulation time 56785721462 ps
CPU time 88.46 seconds
Started Aug 11 04:26:24 PM PDT 24
Finished Aug 11 04:27:52 PM PDT 24
Peak memory 199704 kb
Host smart-5f0ba619-708e-496b-bac9-bfa0c20cb79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606874018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.606874018
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2586388408
Short name T1036
Test name
Test status
Simulation time 107928074433 ps
CPU time 153.06 seconds
Started Aug 11 04:26:33 PM PDT 24
Finished Aug 11 04:29:11 PM PDT 24
Peak memory 200084 kb
Host smart-e518e1da-75d8-4dc0-a4d5-f1bbfa38d3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586388408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2586388408
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.3401413628
Short name T912
Test name
Test status
Simulation time 56805598900 ps
CPU time 148.76 seconds
Started Aug 11 04:26:28 PM PDT 24
Finished Aug 11 04:28:57 PM PDT 24
Peak memory 199808 kb
Host smart-38a81496-1724-457c-bf16-144a6c494dee
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401413628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3401413628
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1739611423
Short name T307
Test name
Test status
Simulation time 333662296073 ps
CPU time 597.33 seconds
Started Aug 11 04:26:45 PM PDT 24
Finished Aug 11 04:36:42 PM PDT 24
Peak memory 199712 kb
Host smart-0b5561dd-1700-446e-ae15-3df3fddb4029
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1739611423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1739611423
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.3226294642
Short name T342
Test name
Test status
Simulation time 3322343518 ps
CPU time 5.61 seconds
Started Aug 11 04:26:32 PM PDT 24
Finished Aug 11 04:26:37 PM PDT 24
Peak memory 198416 kb
Host smart-bdf3aff0-97cd-418f-a70f-806107d6fed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226294642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3226294642
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2849519297
Short name T460
Test name
Test status
Simulation time 115207340316 ps
CPU time 247.72 seconds
Started Aug 11 04:26:29 PM PDT 24
Finished Aug 11 04:30:37 PM PDT 24
Peak memory 199840 kb
Host smart-96178e43-b6cb-4dc2-a398-7b2815ddad94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849519297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2849519297
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.943235472
Short name T982
Test name
Test status
Simulation time 19294864938 ps
CPU time 985.15 seconds
Started Aug 11 04:26:37 PM PDT 24
Finished Aug 11 04:43:03 PM PDT 24
Peak memory 199716 kb
Host smart-f9a66fd4-c3c7-4ebe-a066-74077c3822fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=943235472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.943235472
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1031695946
Short name T869
Test name
Test status
Simulation time 7046762363 ps
CPU time 28.57 seconds
Started Aug 11 04:26:22 PM PDT 24
Finished Aug 11 04:26:50 PM PDT 24
Peak memory 197868 kb
Host smart-3186dc45-c3e2-4ebe-9e42-ec89679b0b2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1031695946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1031695946
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2594990844
Short name T688
Test name
Test status
Simulation time 22351708663 ps
CPU time 62.75 seconds
Started Aug 11 04:26:47 PM PDT 24
Finished Aug 11 04:27:51 PM PDT 24
Peak memory 199636 kb
Host smart-69f4278a-6aa3-4d83-aee4-d4a13703f34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594990844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2594990844
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.2800361884
Short name T1129
Test name
Test status
Simulation time 5631232578 ps
CPU time 4.73 seconds
Started Aug 11 04:26:33 PM PDT 24
Finished Aug 11 04:26:37 PM PDT 24
Peak memory 195856 kb
Host smart-57e5e6d4-8c00-4861-92fd-835ce7421e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800361884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2800361884
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3654525079
Short name T773
Test name
Test status
Simulation time 925686795 ps
CPU time 1.39 seconds
Started Aug 11 04:26:20 PM PDT 24
Finished Aug 11 04:26:22 PM PDT 24
Peak memory 199328 kb
Host smart-4adcd872-f33e-40bc-ac02-c4324af73b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654525079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3654525079
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.3895962337
Short name T907
Test name
Test status
Simulation time 304197101438 ps
CPU time 649.58 seconds
Started Aug 11 04:26:48 PM PDT 24
Finished Aug 11 04:37:38 PM PDT 24
Peak memory 199720 kb
Host smart-74ea50c3-23f9-43f8-b2fe-6bcc46179331
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895962337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3895962337
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.3670680290
Short name T633
Test name
Test status
Simulation time 18435964557 ps
CPU time 567.27 seconds
Started Aug 11 04:26:40 PM PDT 24
Finished Aug 11 04:36:08 PM PDT 24
Peak memory 215464 kb
Host smart-a16634f5-5508-44dd-89f5-ef776d643b36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670680290 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.3670680290
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1988636909
Short name T330
Test name
Test status
Simulation time 7189909019 ps
CPU time 14.13 seconds
Started Aug 11 04:26:39 PM PDT 24
Finished Aug 11 04:26:53 PM PDT 24
Peak memory 199740 kb
Host smart-df13aadd-f993-40da-9d68-53dda67b583a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988636909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1988636909
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1097084430
Short name T721
Test name
Test status
Simulation time 69056489157 ps
CPU time 32.2 seconds
Started Aug 11 04:26:39 PM PDT 24
Finished Aug 11 04:27:11 PM PDT 24
Peak memory 200084 kb
Host smart-c90bffd5-4bda-4f51-ac69-21275f232e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097084430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1097084430
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.4004772130
Short name T1162
Test name
Test status
Simulation time 175932696805 ps
CPU time 115.85 seconds
Started Aug 11 04:28:11 PM PDT 24
Finished Aug 11 04:30:07 PM PDT 24
Peak memory 199768 kb
Host smart-76ad1e46-db05-4e0b-a23a-08ea39c27b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004772130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.4004772130
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.3309612378
Short name T255
Test name
Test status
Simulation time 109031171609 ps
CPU time 172.76 seconds
Started Aug 11 04:28:12 PM PDT 24
Finished Aug 11 04:31:05 PM PDT 24
Peak memory 199720 kb
Host smart-3e14b6a4-ba9a-486d-b1ae-28c76b1ce662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309612378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3309612378
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.945337010
Short name T916
Test name
Test status
Simulation time 109794020069 ps
CPU time 20.49 seconds
Started Aug 11 04:28:10 PM PDT 24
Finished Aug 11 04:28:30 PM PDT 24
Peak memory 199692 kb
Host smart-180fc743-b017-471e-afe1-7fd6ab62264c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945337010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.945337010
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1532997193
Short name T739
Test name
Test status
Simulation time 32591038692 ps
CPU time 48.92 seconds
Started Aug 11 04:28:30 PM PDT 24
Finished Aug 11 04:29:19 PM PDT 24
Peak memory 200076 kb
Host smart-efacf1d8-6705-471d-9ac1-e8ab2b8fe98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532997193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1532997193
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3981466136
Short name T1133
Test name
Test status
Simulation time 59313756638 ps
CPU time 21.34 seconds
Started Aug 11 04:28:12 PM PDT 24
Finished Aug 11 04:28:34 PM PDT 24
Peak memory 199712 kb
Host smart-0d173951-77e3-42b2-85c6-8ef5c486401d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981466136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3981466136
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.3038980153
Short name T193
Test name
Test status
Simulation time 7612934109 ps
CPU time 10.24 seconds
Started Aug 11 04:28:13 PM PDT 24
Finished Aug 11 04:28:23 PM PDT 24
Peak memory 199580 kb
Host smart-72820722-a7a6-464b-bf92-ad435b3a59bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038980153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3038980153
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.375593717
Short name T886
Test name
Test status
Simulation time 35807975454 ps
CPU time 29.46 seconds
Started Aug 11 04:28:09 PM PDT 24
Finished Aug 11 04:28:39 PM PDT 24
Peak memory 199716 kb
Host smart-f787fbb2-d1dc-4594-8521-261fdc45f209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375593717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.375593717
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2493815690
Short name T790
Test name
Test status
Simulation time 14968319174 ps
CPU time 21.34 seconds
Started Aug 11 04:28:21 PM PDT 24
Finished Aug 11 04:28:42 PM PDT 24
Peak memory 199764 kb
Host smart-b2ffca75-4195-4852-880a-c57825ca29f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493815690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2493815690
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.4289603216
Short name T1040
Test name
Test status
Simulation time 83352685132 ps
CPU time 34.76 seconds
Started Aug 11 04:28:11 PM PDT 24
Finished Aug 11 04:28:46 PM PDT 24
Peak memory 199764 kb
Host smart-903f6b65-b10d-4b67-b990-bf197fcc115a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289603216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.4289603216
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.3005532739
Short name T1093
Test name
Test status
Simulation time 146155799 ps
CPU time 0.55 seconds
Started Aug 11 04:26:46 PM PDT 24
Finished Aug 11 04:26:47 PM PDT 24
Peak memory 195156 kb
Host smart-6c9b7fe3-5af1-4d1a-8000-9cc451e78215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005532739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.3005532739
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.818886604
Short name T1118
Test name
Test status
Simulation time 206069941864 ps
CPU time 255.47 seconds
Started Aug 11 04:26:37 PM PDT 24
Finished Aug 11 04:30:52 PM PDT 24
Peak memory 199728 kb
Host smart-617e10e2-e802-421e-95ee-a8df2cb3845d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818886604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.818886604
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2963020430
Short name T696
Test name
Test status
Simulation time 48115805184 ps
CPU time 75.6 seconds
Started Aug 11 04:26:30 PM PDT 24
Finished Aug 11 04:27:46 PM PDT 24
Peak memory 199740 kb
Host smart-e3b0d556-8c03-4124-a29e-bccd8c7fa502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963020430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2963020430
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_intr.226102068
Short name T469
Test name
Test status
Simulation time 547223382833 ps
CPU time 493.67 seconds
Started Aug 11 04:26:42 PM PDT 24
Finished Aug 11 04:34:56 PM PDT 24
Peak memory 199484 kb
Host smart-9551afbf-ac62-49a1-bbf0-174f182bd953
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226102068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.226102068
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.1885656840
Short name T736
Test name
Test status
Simulation time 322089278179 ps
CPU time 424.2 seconds
Started Aug 11 04:26:29 PM PDT 24
Finished Aug 11 04:33:33 PM PDT 24
Peak memory 199664 kb
Host smart-0605d672-eb1f-4e7e-a54f-3859ca66f9c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1885656840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1885656840
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.2404884622
Short name T603
Test name
Test status
Simulation time 6554867901 ps
CPU time 2.98 seconds
Started Aug 11 04:26:23 PM PDT 24
Finished Aug 11 04:26:26 PM PDT 24
Peak memory 198476 kb
Host smart-9a85b8d6-245e-4c19-899f-a375e573dea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404884622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.2404884622
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.496676844
Short name T1034
Test name
Test status
Simulation time 304056091778 ps
CPU time 131.39 seconds
Started Aug 11 04:26:30 PM PDT 24
Finished Aug 11 04:28:41 PM PDT 24
Peak memory 207904 kb
Host smart-0c88c45d-de60-494a-a6e3-0a89dba62410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496676844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.496676844
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.1002074773
Short name T351
Test name
Test status
Simulation time 25311051531 ps
CPU time 1174.25 seconds
Started Aug 11 04:26:28 PM PDT 24
Finished Aug 11 04:46:02 PM PDT 24
Peak memory 199704 kb
Host smart-bd9aaf7d-39a8-425f-b3de-8a17d35cfd9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1002074773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1002074773
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.33754884
Short name T719
Test name
Test status
Simulation time 5893499322 ps
CPU time 44.14 seconds
Started Aug 11 04:26:37 PM PDT 24
Finished Aug 11 04:27:21 PM PDT 24
Peak memory 198932 kb
Host smart-1ef4bda3-0bc5-478d-b25a-867530aa065e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=33754884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.33754884
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.74154548
Short name T792
Test name
Test status
Simulation time 133023518364 ps
CPU time 51.39 seconds
Started Aug 11 04:26:32 PM PDT 24
Finished Aug 11 04:27:24 PM PDT 24
Peak memory 199748 kb
Host smart-3c2b45e1-59c2-4c6b-b942-35de2eb41b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74154548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.74154548
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.1081320573
Short name T899
Test name
Test status
Simulation time 34481190408 ps
CPU time 52.64 seconds
Started Aug 11 04:26:29 PM PDT 24
Finished Aug 11 04:27:21 PM PDT 24
Peak memory 196644 kb
Host smart-db13bf5a-53c5-42a5-b296-644e17275805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081320573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1081320573
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3907843430
Short name T863
Test name
Test status
Simulation time 6063332648 ps
CPU time 8.89 seconds
Started Aug 11 04:26:30 PM PDT 24
Finished Aug 11 04:26:39 PM PDT 24
Peak memory 199748 kb
Host smart-dbd0f569-77b8-4199-bd27-64a050a62778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907843430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3907843430
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.3769749292
Short name T610
Test name
Test status
Simulation time 34323721528 ps
CPU time 13.07 seconds
Started Aug 11 04:26:26 PM PDT 24
Finished Aug 11 04:26:39 PM PDT 24
Peak memory 199728 kb
Host smart-a963f952-80f3-4776-8a8b-f5dc32646dcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769749292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3769749292
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.713571147
Short name T1090
Test name
Test status
Simulation time 321807016627 ps
CPU time 714.37 seconds
Started Aug 11 04:26:45 PM PDT 24
Finished Aug 11 04:38:40 PM PDT 24
Peak memory 216424 kb
Host smart-6b070231-22c1-4b54-9dbc-f0b76444ee17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713571147 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.713571147
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.1928469707
Short name T999
Test name
Test status
Simulation time 623236611 ps
CPU time 1.95 seconds
Started Aug 11 04:26:30 PM PDT 24
Finished Aug 11 04:26:32 PM PDT 24
Peak memory 197956 kb
Host smart-1411ba5d-49f1-45fc-88b7-92ce4cbff081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928469707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.1928469707
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3057369555
Short name T111
Test name
Test status
Simulation time 12694793198 ps
CPU time 6 seconds
Started Aug 11 04:26:21 PM PDT 24
Finished Aug 11 04:26:27 PM PDT 24
Peak memory 199612 kb
Host smart-80ca6bbd-c079-4613-8eea-64dc548f4dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057369555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3057369555
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.3600489769
Short name T41
Test name
Test status
Simulation time 178286869385 ps
CPU time 510.83 seconds
Started Aug 11 04:28:31 PM PDT 24
Finished Aug 11 04:37:02 PM PDT 24
Peak memory 199800 kb
Host smart-5d60d0fa-1ea3-44d9-87be-4f610f817e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600489769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3600489769
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3355579342
Short name T693
Test name
Test status
Simulation time 51979802066 ps
CPU time 20.56 seconds
Started Aug 11 04:28:10 PM PDT 24
Finished Aug 11 04:28:30 PM PDT 24
Peak memory 199672 kb
Host smart-d54782e0-4ef9-4eb1-a8c3-7ae76af25bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355579342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3355579342
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3763850203
Short name T802
Test name
Test status
Simulation time 28025886199 ps
CPU time 42.53 seconds
Started Aug 11 04:28:28 PM PDT 24
Finished Aug 11 04:29:11 PM PDT 24
Peak memory 199768 kb
Host smart-8405dbb2-a391-4fbc-b072-32322466386b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763850203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3763850203
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1477754959
Short name T247
Test name
Test status
Simulation time 24408454170 ps
CPU time 29.98 seconds
Started Aug 11 04:28:14 PM PDT 24
Finished Aug 11 04:28:44 PM PDT 24
Peak memory 199660 kb
Host smart-102049d7-8821-4425-ad1f-c6468fb0db7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477754959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1477754959
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.461784183
Short name T297
Test name
Test status
Simulation time 85506769666 ps
CPU time 63.41 seconds
Started Aug 11 04:28:25 PM PDT 24
Finished Aug 11 04:29:29 PM PDT 24
Peak memory 199732 kb
Host smart-e0e472fa-844e-4e9a-8338-bae98e45e72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461784183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.461784183
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1628871945
Short name T738
Test name
Test status
Simulation time 194633916886 ps
CPU time 23.84 seconds
Started Aug 11 04:28:43 PM PDT 24
Finished Aug 11 04:29:06 PM PDT 24
Peak memory 199780 kb
Host smart-636ca960-5fc1-4caf-963a-784d1aee87d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628871945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1628871945
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2804874280
Short name T1170
Test name
Test status
Simulation time 58541781376 ps
CPU time 42.78 seconds
Started Aug 11 04:28:25 PM PDT 24
Finished Aug 11 04:29:07 PM PDT 24
Peak memory 199712 kb
Host smart-220a821b-f6b4-4d5a-ae3f-b835af1be4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804874280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2804874280
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2243534769
Short name T997
Test name
Test status
Simulation time 75483715117 ps
CPU time 9.57 seconds
Started Aug 11 04:28:24 PM PDT 24
Finished Aug 11 04:28:34 PM PDT 24
Peak memory 199664 kb
Host smart-c14398ff-be97-4952-a473-375069c6fb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243534769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2243534769
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.1680452925
Short name T840
Test name
Test status
Simulation time 113786609009 ps
CPU time 211.27 seconds
Started Aug 11 04:28:13 PM PDT 24
Finished Aug 11 04:31:45 PM PDT 24
Peak memory 199636 kb
Host smart-1400020f-c981-4870-844e-f29481c471e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680452925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1680452925
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.4289883722
Short name T23
Test name
Test status
Simulation time 26167869 ps
CPU time 0.56 seconds
Started Aug 11 04:26:16 PM PDT 24
Finished Aug 11 04:26:17 PM PDT 24
Peak memory 195168 kb
Host smart-2a57a833-a9c3-4b72-9edb-df7309461f97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289883722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.4289883722
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.4073711854
Short name T157
Test name
Test status
Simulation time 254672632547 ps
CPU time 57.51 seconds
Started Aug 11 04:26:41 PM PDT 24
Finished Aug 11 04:27:39 PM PDT 24
Peak memory 199720 kb
Host smart-eccdb18e-dc8a-4bac-be09-c4b73e5c1d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073711854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.4073711854
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.2650599935
Short name T181
Test name
Test status
Simulation time 32653007893 ps
CPU time 22.88 seconds
Started Aug 11 04:26:28 PM PDT 24
Finished Aug 11 04:26:51 PM PDT 24
Peak memory 199784 kb
Host smart-7ca99637-43c9-4d2a-be66-94b1a80b62a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650599935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2650599935
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.654951958
Short name T870
Test name
Test status
Simulation time 45147453450 ps
CPU time 20.48 seconds
Started Aug 11 04:26:42 PM PDT 24
Finished Aug 11 04:27:03 PM PDT 24
Peak memory 199644 kb
Host smart-9583f11f-049f-4910-abef-ddde6cde68d6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654951958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.654951958
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.3854329539
Short name T789
Test name
Test status
Simulation time 152755178514 ps
CPU time 304.55 seconds
Started Aug 11 04:26:27 PM PDT 24
Finished Aug 11 04:31:32 PM PDT 24
Peak memory 199680 kb
Host smart-04988ce2-091a-483f-89f9-70d550fc9f69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3854329539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3854329539
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2588358003
Short name T682
Test name
Test status
Simulation time 5114418776 ps
CPU time 9.24 seconds
Started Aug 11 04:26:35 PM PDT 24
Finished Aug 11 04:26:44 PM PDT 24
Peak memory 198160 kb
Host smart-752705fe-cd3f-4172-8ef2-2676241b7523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588358003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2588358003
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.1018431997
Short name T328
Test name
Test status
Simulation time 81724001829 ps
CPU time 151.44 seconds
Started Aug 11 04:26:34 PM PDT 24
Finished Aug 11 04:29:06 PM PDT 24
Peak memory 199648 kb
Host smart-b157c973-e4a3-427a-b0e1-4329dcf1490f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018431997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1018431997
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.834801157
Short name T1041
Test name
Test status
Simulation time 25789989992 ps
CPU time 1507.53 seconds
Started Aug 11 04:26:41 PM PDT 24
Finished Aug 11 04:51:49 PM PDT 24
Peak memory 199608 kb
Host smart-f9598abf-f2ac-4d15-af3d-72277c684d35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=834801157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.834801157
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1887352347
Short name T16
Test name
Test status
Simulation time 3311811792 ps
CPU time 3.18 seconds
Started Aug 11 04:26:40 PM PDT 24
Finished Aug 11 04:26:44 PM PDT 24
Peak memory 197800 kb
Host smart-47834795-0da9-468e-a495-a73d516c3fb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1887352347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1887352347
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2520392401
Short name T503
Test name
Test status
Simulation time 8914005504 ps
CPU time 8.39 seconds
Started Aug 11 04:26:51 PM PDT 24
Finished Aug 11 04:27:00 PM PDT 24
Peak memory 198672 kb
Host smart-0aee6c68-1eb0-4bf2-ab71-ea7b677dae57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520392401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2520392401
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3722506117
Short name T804
Test name
Test status
Simulation time 3623731762 ps
CPU time 1.99 seconds
Started Aug 11 04:26:30 PM PDT 24
Finished Aug 11 04:26:33 PM PDT 24
Peak memory 195996 kb
Host smart-57cdfe02-f359-4ad0-abb2-d1f4ecbdb3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722506117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3722506117
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.1094853390
Short name T424
Test name
Test status
Simulation time 284973811 ps
CPU time 1.46 seconds
Started Aug 11 04:26:30 PM PDT 24
Finished Aug 11 04:26:31 PM PDT 24
Peak memory 199520 kb
Host smart-437e7b43-dc6f-4c20-80bf-3bebabb3256d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094853390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1094853390
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.811262317
Short name T169
Test name
Test status
Simulation time 254608138481 ps
CPU time 353.04 seconds
Started Aug 11 04:26:47 PM PDT 24
Finished Aug 11 04:32:40 PM PDT 24
Peak memory 208340 kb
Host smart-a370e3ee-2849-4514-bff5-f99fa38a1d22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811262317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.811262317
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.506071067
Short name T625
Test name
Test status
Simulation time 1084200053 ps
CPU time 3.89 seconds
Started Aug 11 04:26:47 PM PDT 24
Finished Aug 11 04:26:52 PM PDT 24
Peak memory 198124 kb
Host smart-3b755a90-e18b-42eb-996d-816b10df5792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506071067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.506071067
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.452525585
Short name T1142
Test name
Test status
Simulation time 94540915432 ps
CPU time 121.87 seconds
Started Aug 11 04:26:42 PM PDT 24
Finished Aug 11 04:28:44 PM PDT 24
Peak memory 199704 kb
Host smart-f9f4ad1e-2619-40cb-aad1-ad6c6e9f88f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452525585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.452525585
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3767986912
Short name T987
Test name
Test status
Simulation time 63088007837 ps
CPU time 151.64 seconds
Started Aug 11 04:28:14 PM PDT 24
Finished Aug 11 04:30:45 PM PDT 24
Peak memory 199716 kb
Host smart-be9b8906-0eeb-4f9d-bca7-0d715889c8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767986912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3767986912
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2392134148
Short name T1097
Test name
Test status
Simulation time 32089052048 ps
CPU time 46.37 seconds
Started Aug 11 04:28:15 PM PDT 24
Finished Aug 11 04:29:01 PM PDT 24
Peak memory 199692 kb
Host smart-f6f420cd-1c13-4090-bc26-1809c6fe59aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392134148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2392134148
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3395222180
Short name T651
Test name
Test status
Simulation time 49727889416 ps
CPU time 40.97 seconds
Started Aug 11 04:28:39 PM PDT 24
Finished Aug 11 04:29:20 PM PDT 24
Peak memory 199708 kb
Host smart-e92d4e5d-b6de-4a19-8788-197ae96fabd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395222180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3395222180
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.484460255
Short name T7
Test name
Test status
Simulation time 16096752523 ps
CPU time 24.27 seconds
Started Aug 11 04:28:49 PM PDT 24
Finished Aug 11 04:29:13 PM PDT 24
Peak memory 199812 kb
Host smart-f9fb42fd-a5d2-42d2-8573-aea362d51292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484460255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.484460255
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.344793374
Short name T230
Test name
Test status
Simulation time 201224050439 ps
CPU time 159.57 seconds
Started Aug 11 04:28:22 PM PDT 24
Finished Aug 11 04:31:01 PM PDT 24
Peak memory 199692 kb
Host smart-12cd44b0-e028-4ca9-9624-df728fbd774f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344793374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.344793374
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3932252938
Short name T220
Test name
Test status
Simulation time 67625984845 ps
CPU time 30.38 seconds
Started Aug 11 04:28:36 PM PDT 24
Finished Aug 11 04:29:06 PM PDT 24
Peak memory 199676 kb
Host smart-fe5e80fa-29fd-42ac-aa0a-4ef1752953aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932252938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3932252938
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.4157765583
Short name T161
Test name
Test status
Simulation time 32091419336 ps
CPU time 14.16 seconds
Started Aug 11 04:28:15 PM PDT 24
Finished Aug 11 04:28:29 PM PDT 24
Peak memory 199720 kb
Host smart-cb922c90-971f-40b1-abfd-0dd93277f7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157765583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.4157765583
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2790946258
Short name T165
Test name
Test status
Simulation time 15873169746 ps
CPU time 36.55 seconds
Started Aug 11 04:28:23 PM PDT 24
Finished Aug 11 04:29:00 PM PDT 24
Peak memory 200140 kb
Host smart-8f7cf0a8-9d2b-4ecf-bf7c-d2e0eb3e0097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790946258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2790946258
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3259659426
Short name T606
Test name
Test status
Simulation time 18994598 ps
CPU time 0.54 seconds
Started Aug 11 04:26:39 PM PDT 24
Finished Aug 11 04:26:40 PM PDT 24
Peak memory 195132 kb
Host smart-20ca15a7-105b-4c7e-89e3-b9c6d0b248c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259659426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3259659426
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2736914617
Short name T175
Test name
Test status
Simulation time 30008740366 ps
CPU time 19.55 seconds
Started Aug 11 04:26:39 PM PDT 24
Finished Aug 11 04:26:59 PM PDT 24
Peak memory 199592 kb
Host smart-a28354b2-c09f-4445-9204-abaa586d27da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736914617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2736914617
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3898783966
Short name T109
Test name
Test status
Simulation time 26854298122 ps
CPU time 23.81 seconds
Started Aug 11 04:26:25 PM PDT 24
Finished Aug 11 04:26:49 PM PDT 24
Peak memory 199748 kb
Host smart-5f9203c7-e235-4b60-8ca3-22c6872cac91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898783966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3898783966
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.1959823557
Short name T666
Test name
Test status
Simulation time 40862682633 ps
CPU time 59.93 seconds
Started Aug 11 04:26:45 PM PDT 24
Finished Aug 11 04:27:45 PM PDT 24
Peak memory 199792 kb
Host smart-0cdaae5a-0ada-4537-9fa2-a8cc3f08d970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959823557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1959823557
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.3582270365
Short name T601
Test name
Test status
Simulation time 79032960018 ps
CPU time 28.54 seconds
Started Aug 11 04:26:50 PM PDT 24
Finished Aug 11 04:27:19 PM PDT 24
Peak memory 199176 kb
Host smart-6a20b7c4-5117-436b-bdca-3e2066ecdf63
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582270365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3582270365
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2971718377
Short name T881
Test name
Test status
Simulation time 109577113727 ps
CPU time 501.05 seconds
Started Aug 11 04:26:45 PM PDT 24
Finished Aug 11 04:35:06 PM PDT 24
Peak memory 199664 kb
Host smart-37bdf6ee-ba1c-493b-8f7e-e83226781a67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2971718377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2971718377
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.777918348
Short name T588
Test name
Test status
Simulation time 4772606898 ps
CPU time 2.75 seconds
Started Aug 11 04:26:31 PM PDT 24
Finished Aug 11 04:26:34 PM PDT 24
Peak memory 198936 kb
Host smart-3dbf8810-939a-4495-8d55-a223205a6e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777918348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.777918348
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.438368067
Short name T434
Test name
Test status
Simulation time 103821367278 ps
CPU time 136.09 seconds
Started Aug 11 04:26:30 PM PDT 24
Finished Aug 11 04:28:47 PM PDT 24
Peak memory 198380 kb
Host smart-70cc04d5-14f3-4ec4-8bc1-6bdc1518ae3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438368067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.438368067
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2671573293
Short name T695
Test name
Test status
Simulation time 9721747252 ps
CPU time 442.56 seconds
Started Aug 11 04:26:36 PM PDT 24
Finished Aug 11 04:33:59 PM PDT 24
Peak memory 199640 kb
Host smart-6cd91478-fb05-4bd9-9f3b-3163affa2d15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2671573293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2671573293
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.722176996
Short name T1141
Test name
Test status
Simulation time 5511124356 ps
CPU time 9.25 seconds
Started Aug 11 04:26:34 PM PDT 24
Finished Aug 11 04:26:44 PM PDT 24
Peak memory 199208 kb
Host smart-df398396-c061-48b9-856f-07c200ac13d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=722176996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.722176996
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.3357357503
Short name T1056
Test name
Test status
Simulation time 203352913099 ps
CPU time 76.5 seconds
Started Aug 11 04:26:48 PM PDT 24
Finished Aug 11 04:28:05 PM PDT 24
Peak memory 199740 kb
Host smart-711b8245-79c0-4669-b3b4-0d45caafdc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357357503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3357357503
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.766655724
Short name T1059
Test name
Test status
Simulation time 3590522083 ps
CPU time 3.27 seconds
Started Aug 11 04:26:32 PM PDT 24
Finished Aug 11 04:26:36 PM PDT 24
Peak memory 196224 kb
Host smart-4d475bd2-8883-4c3a-9fe8-90fad43df638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766655724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.766655724
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1747447031
Short name T546
Test name
Test status
Simulation time 697522290 ps
CPU time 1.96 seconds
Started Aug 11 04:26:30 PM PDT 24
Finished Aug 11 04:26:32 PM PDT 24
Peak memory 199188 kb
Host smart-cf6deafe-a3ac-498a-8221-c79f244b5b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747447031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1747447031
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.3075998786
Short name T913
Test name
Test status
Simulation time 639217857164 ps
CPU time 246.25 seconds
Started Aug 11 04:26:37 PM PDT 24
Finished Aug 11 04:30:44 PM PDT 24
Peak memory 199624 kb
Host smart-fd6fe590-3858-4021-b564-f39bf1a16e70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075998786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3075998786
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.1866867007
Short name T944
Test name
Test status
Simulation time 54918510199 ps
CPU time 330.1 seconds
Started Aug 11 04:26:31 PM PDT 24
Finished Aug 11 04:32:01 PM PDT 24
Peak memory 216388 kb
Host smart-15726a9f-2f5e-4ed0-855a-653e10973cf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866867007 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.1866867007
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1319371070
Short name T435
Test name
Test status
Simulation time 6625298352 ps
CPU time 38.71 seconds
Started Aug 11 04:26:32 PM PDT 24
Finished Aug 11 04:27:11 PM PDT 24
Peak memory 199688 kb
Host smart-e08b6e41-f5ad-4309-975b-9bc85d5c26e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319371070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1319371070
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2083680264
Short name T441
Test name
Test status
Simulation time 126019653757 ps
CPU time 45.21 seconds
Started Aug 11 04:26:34 PM PDT 24
Finished Aug 11 04:27:20 PM PDT 24
Peak memory 199704 kb
Host smart-0d74c647-adb6-4412-b86f-456074df25dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083680264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2083680264
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.2870303537
Short name T246
Test name
Test status
Simulation time 20755172881 ps
CPU time 34.27 seconds
Started Aug 11 04:28:42 PM PDT 24
Finished Aug 11 04:29:17 PM PDT 24
Peak memory 199760 kb
Host smart-6c36ab97-ae0b-4ed7-a2af-9a99ac2bb425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870303537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2870303537
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1905696319
Short name T323
Test name
Test status
Simulation time 211673211624 ps
CPU time 130.62 seconds
Started Aug 11 04:28:19 PM PDT 24
Finished Aug 11 04:30:30 PM PDT 24
Peak memory 199716 kb
Host smart-bec7cc54-6786-4785-addd-3f81234ab522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905696319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1905696319
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1672090787
Short name T653
Test name
Test status
Simulation time 126126880266 ps
CPU time 50.17 seconds
Started Aug 11 04:28:24 PM PDT 24
Finished Aug 11 04:29:15 PM PDT 24
Peak memory 199700 kb
Host smart-b84abb88-7f41-49dc-88b9-746f50e60b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672090787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1672090787
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3582879958
Short name T663
Test name
Test status
Simulation time 5240780321 ps
CPU time 8.97 seconds
Started Aug 11 04:28:23 PM PDT 24
Finished Aug 11 04:28:32 PM PDT 24
Peak memory 199688 kb
Host smart-7bd499f2-cec5-40b0-afdc-35c56464c5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582879958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3582879958
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.1597306249
Short name T190
Test name
Test status
Simulation time 102657893274 ps
CPU time 48.03 seconds
Started Aug 11 04:28:24 PM PDT 24
Finished Aug 11 04:29:12 PM PDT 24
Peak memory 199768 kb
Host smart-8d710cce-6b8b-449b-86d0-11b117566beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597306249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1597306249
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.4167232073
Short name T1147
Test name
Test status
Simulation time 109221644128 ps
CPU time 35.36 seconds
Started Aug 11 04:28:25 PM PDT 24
Finished Aug 11 04:29:00 PM PDT 24
Peak memory 199824 kb
Host smart-d36e33d8-c3be-42de-b4f6-0634d742daf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167232073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.4167232073
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.429937795
Short name T51
Test name
Test status
Simulation time 15296042934 ps
CPU time 24.67 seconds
Started Aug 11 04:28:14 PM PDT 24
Finished Aug 11 04:28:39 PM PDT 24
Peak memory 199804 kb
Host smart-cec3a5ef-6f88-4018-a9f2-f2ea18318d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429937795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.429937795
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.3682185197
Short name T222
Test name
Test status
Simulation time 126063413745 ps
CPU time 209.31 seconds
Started Aug 11 04:28:39 PM PDT 24
Finished Aug 11 04:32:08 PM PDT 24
Peak memory 199720 kb
Host smart-17402c49-9a9b-4057-8590-432884973f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682185197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.3682185197
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1174968302
Short name T166
Test name
Test status
Simulation time 17435956130 ps
CPU time 14.6 seconds
Started Aug 11 04:28:16 PM PDT 24
Finished Aug 11 04:28:30 PM PDT 24
Peak memory 199676 kb
Host smart-79a4d517-91be-47d1-b988-11f5d2fcc32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174968302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1174968302
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.1290014799
Short name T1114
Test name
Test status
Simulation time 28138810581 ps
CPU time 17.41 seconds
Started Aug 11 04:28:31 PM PDT 24
Finished Aug 11 04:28:49 PM PDT 24
Peak memory 199520 kb
Host smart-d378ad88-20b0-41a2-877b-bf4b23a40040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290014799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1290014799
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.750671528
Short name T830
Test name
Test status
Simulation time 43577311 ps
CPU time 0.58 seconds
Started Aug 11 04:26:38 PM PDT 24
Finished Aug 11 04:26:39 PM PDT 24
Peak memory 195096 kb
Host smart-a6534293-8c8e-4197-a885-f9efd526f9cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750671528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.750671528
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.1753852453
Short name T431
Test name
Test status
Simulation time 195871065484 ps
CPU time 350.09 seconds
Started Aug 11 04:26:38 PM PDT 24
Finished Aug 11 04:32:28 PM PDT 24
Peak memory 199740 kb
Host smart-89e0b3d1-b645-4a62-8334-525f72a4c7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753852453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1753852453
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1919737750
Short name T158
Test name
Test status
Simulation time 37416165205 ps
CPU time 40.64 seconds
Started Aug 11 04:26:44 PM PDT 24
Finished Aug 11 04:27:25 PM PDT 24
Peak memory 199820 kb
Host smart-9430a14a-e80c-4a57-ad35-89a252adc9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919737750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1919737750
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1207957328
Short name T140
Test name
Test status
Simulation time 61411668221 ps
CPU time 26.14 seconds
Started Aug 11 04:26:45 PM PDT 24
Finished Aug 11 04:27:11 PM PDT 24
Peak memory 199524 kb
Host smart-5344a34f-db7a-4c06-b4a0-ff428414c0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207957328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1207957328
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.165118867
Short name T959
Test name
Test status
Simulation time 31859508769 ps
CPU time 35.95 seconds
Started Aug 11 04:26:38 PM PDT 24
Finished Aug 11 04:27:14 PM PDT 24
Peak memory 199556 kb
Host smart-7f31487f-6c8e-42d2-a7f0-5252a77e44d7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165118867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.165118867
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1971311876
Short name T321
Test name
Test status
Simulation time 105216840932 ps
CPU time 374.39 seconds
Started Aug 11 04:26:38 PM PDT 24
Finished Aug 11 04:32:53 PM PDT 24
Peak memory 199696 kb
Host smart-f30c5309-a0e9-4e5f-a7e8-a16709a1a8ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1971311876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1971311876
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.59347255
Short name T341
Test name
Test status
Simulation time 10286224698 ps
CPU time 12.96 seconds
Started Aug 11 04:26:56 PM PDT 24
Finished Aug 11 04:27:09 PM PDT 24
Peak memory 199784 kb
Host smart-59472019-0ea4-4a69-b9e9-90b4afd776b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59347255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.59347255
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.2944161525
Short name T708
Test name
Test status
Simulation time 23116117347 ps
CPU time 43.87 seconds
Started Aug 11 04:26:49 PM PDT 24
Finished Aug 11 04:27:33 PM PDT 24
Peak memory 199916 kb
Host smart-c758a25d-d4d8-43d1-ad8a-4632671258fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944161525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2944161525
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2163951817
Short name T313
Test name
Test status
Simulation time 18278132252 ps
CPU time 1047.05 seconds
Started Aug 11 04:26:48 PM PDT 24
Finished Aug 11 04:44:16 PM PDT 24
Peak memory 199784 kb
Host smart-4e2c03e1-d7ea-4608-b57f-362c62243d42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2163951817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2163951817
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.1235818316
Short name T383
Test name
Test status
Simulation time 6241592996 ps
CPU time 58.87 seconds
Started Aug 11 04:26:38 PM PDT 24
Finished Aug 11 04:27:37 PM PDT 24
Peak memory 199160 kb
Host smart-ab043a37-bb97-46d5-99f0-46ae1ed29c81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1235818316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1235818316
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.4076505195
Short name T461
Test name
Test status
Simulation time 48338641191 ps
CPU time 38.25 seconds
Started Aug 11 04:26:32 PM PDT 24
Finished Aug 11 04:27:11 PM PDT 24
Peak memory 199620 kb
Host smart-9de0bb23-e8fb-47dd-8c0c-2875bd02c363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076505195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.4076505195
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.179382635
Short name T983
Test name
Test status
Simulation time 40156646653 ps
CPU time 14.24 seconds
Started Aug 11 04:26:33 PM PDT 24
Finished Aug 11 04:26:48 PM PDT 24
Peak memory 196536 kb
Host smart-92c8ae8b-904c-498b-9706-2efa9474d7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179382635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.179382635
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.658294827
Short name T783
Test name
Test status
Simulation time 517948799 ps
CPU time 1.67 seconds
Started Aug 11 04:26:43 PM PDT 24
Finished Aug 11 04:26:44 PM PDT 24
Peak memory 198748 kb
Host smart-6bd1c822-8fbe-4844-83f6-e179d046c852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658294827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.658294827
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.137410355
Short name T808
Test name
Test status
Simulation time 415171184570 ps
CPU time 478.52 seconds
Started Aug 11 04:26:47 PM PDT 24
Finished Aug 11 04:34:46 PM PDT 24
Peak memory 199716 kb
Host smart-601aa43c-3669-4650-b34b-aac7bcac9e93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137410355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.137410355
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.798241786
Short name T322
Test name
Test status
Simulation time 61746703630 ps
CPU time 415.44 seconds
Started Aug 11 04:26:36 PM PDT 24
Finished Aug 11 04:33:32 PM PDT 24
Peak memory 215104 kb
Host smart-eaa14311-2c07-4daa-85ee-d691c9d9b581
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798241786 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.798241786
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1554787357
Short name T472
Test name
Test status
Simulation time 1347738242 ps
CPU time 2.27 seconds
Started Aug 11 04:26:48 PM PDT 24
Finished Aug 11 04:26:51 PM PDT 24
Peak memory 198636 kb
Host smart-9935e970-5247-4d98-9ab8-b22cdf005230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554787357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1554787357
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1113137186
Short name T597
Test name
Test status
Simulation time 31249656049 ps
CPU time 49.71 seconds
Started Aug 11 04:26:35 PM PDT 24
Finished Aug 11 04:27:24 PM PDT 24
Peak memory 199620 kb
Host smart-27f9d798-0678-4350-a186-0b0eeecd8e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113137186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1113137186
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.2574064877
Short name T209
Test name
Test status
Simulation time 126215944782 ps
CPU time 188.02 seconds
Started Aug 11 04:28:38 PM PDT 24
Finished Aug 11 04:31:46 PM PDT 24
Peak memory 199728 kb
Host smart-9d11f7a1-d4e7-4ba7-b4f6-56eee3428d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574064877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2574064877
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.3027710248
Short name T818
Test name
Test status
Simulation time 22672436066 ps
CPU time 52.27 seconds
Started Aug 11 04:28:24 PM PDT 24
Finished Aug 11 04:29:17 PM PDT 24
Peak memory 199764 kb
Host smart-d1fb4dbf-bc0c-4d6b-9680-89232a4a8ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027710248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3027710248
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2421587334
Short name T210
Test name
Test status
Simulation time 81641024571 ps
CPU time 15.99 seconds
Started Aug 11 04:28:15 PM PDT 24
Finished Aug 11 04:28:31 PM PDT 24
Peak memory 199748 kb
Host smart-9838f380-498f-46c2-bf07-246b85eb79b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421587334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2421587334
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.461572361
Short name T329
Test name
Test status
Simulation time 114907772446 ps
CPU time 53.3 seconds
Started Aug 11 04:28:17 PM PDT 24
Finished Aug 11 04:29:10 PM PDT 24
Peak memory 199752 kb
Host smart-0023eae5-24e8-4dc9-a52e-785af45dff91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461572361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.461572361
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3688619843
Short name T680
Test name
Test status
Simulation time 19462214579 ps
CPU time 60.1 seconds
Started Aug 11 04:28:25 PM PDT 24
Finished Aug 11 04:29:26 PM PDT 24
Peak memory 199764 kb
Host smart-edf7bf87-5596-4d9e-8f6f-01c8d9a02531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688619843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3688619843
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.3815862399
Short name T527
Test name
Test status
Simulation time 221187077042 ps
CPU time 65.08 seconds
Started Aug 11 04:28:16 PM PDT 24
Finished Aug 11 04:29:21 PM PDT 24
Peak memory 199808 kb
Host smart-7bad6608-b983-4315-84c8-b9c189c80403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815862399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3815862399
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.4245373928
Short name T669
Test name
Test status
Simulation time 91960085430 ps
CPU time 72.66 seconds
Started Aug 11 04:28:17 PM PDT 24
Finished Aug 11 04:29:29 PM PDT 24
Peak memory 199820 kb
Host smart-dd2003ea-b80e-42e5-9d7e-562418cc03c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245373928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.4245373928
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.3376126002
Short name T641
Test name
Test status
Simulation time 57450710711 ps
CPU time 82.53 seconds
Started Aug 11 04:28:15 PM PDT 24
Finished Aug 11 04:29:38 PM PDT 24
Peak memory 199688 kb
Host smart-98356c02-717a-40f4-91b4-72226712bde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376126002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.3376126002
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2464360950
Short name T480
Test name
Test status
Simulation time 10066173036 ps
CPU time 16.06 seconds
Started Aug 11 04:28:20 PM PDT 24
Finished Aug 11 04:28:36 PM PDT 24
Peak memory 199768 kb
Host smart-0d6f999c-9264-49d1-9574-c7c57a9f0c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464360950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2464360950
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1030869130
Short name T859
Test name
Test status
Simulation time 21816957 ps
CPU time 0.56 seconds
Started Aug 11 04:26:46 PM PDT 24
Finished Aug 11 04:26:47 PM PDT 24
Peak memory 195052 kb
Host smart-f1f9998a-178b-4587-be96-53b51c2fc1f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030869130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1030869130
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.532268811
Short name T275
Test name
Test status
Simulation time 107276273356 ps
CPU time 149.5 seconds
Started Aug 11 04:26:38 PM PDT 24
Finished Aug 11 04:29:07 PM PDT 24
Peak memory 199732 kb
Host smart-6ee16b08-54d7-40de-aabe-f014f4bca441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532268811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.532268811
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_intr.3514205045
Short name T516
Test name
Test status
Simulation time 1335370312 ps
CPU time 1.16 seconds
Started Aug 11 04:26:41 PM PDT 24
Finished Aug 11 04:26:43 PM PDT 24
Peak memory 195412 kb
Host smart-af19943b-6420-49ce-b989-8c17af170a03
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514205045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3514205045
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.1642254389
Short name T538
Test name
Test status
Simulation time 205495314833 ps
CPU time 2247.8 seconds
Started Aug 11 04:26:57 PM PDT 24
Finished Aug 11 05:04:25 PM PDT 24
Peak memory 199736 kb
Host smart-176725a6-33e0-4b87-ab8a-74fdd1c34ad9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1642254389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1642254389
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2962976480
Short name T910
Test name
Test status
Simulation time 8740005286 ps
CPU time 13.69 seconds
Started Aug 11 04:26:46 PM PDT 24
Finished Aug 11 04:27:00 PM PDT 24
Peak memory 198168 kb
Host smart-a0ca6ab3-dbab-47de-bc8f-acab85c8ae81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962976480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2962976480
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.1200784692
Short name T1082
Test name
Test status
Simulation time 27912728357 ps
CPU time 39.69 seconds
Started Aug 11 04:26:35 PM PDT 24
Finished Aug 11 04:27:14 PM PDT 24
Peak memory 199828 kb
Host smart-98a7e055-01de-45e4-ac5d-ad00e66ea799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200784692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1200784692
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.1783379189
Short name T40
Test name
Test status
Simulation time 18161276255 ps
CPU time 745.36 seconds
Started Aug 11 04:26:37 PM PDT 24
Finished Aug 11 04:39:03 PM PDT 24
Peak memory 199688 kb
Host smart-ad30e333-ae07-4859-9f04-3d27e59435a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1783379189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1783379189
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.3148920954
Short name T1007
Test name
Test status
Simulation time 4293704735 ps
CPU time 33.23 seconds
Started Aug 11 04:26:48 PM PDT 24
Finished Aug 11 04:27:22 PM PDT 24
Peak memory 197872 kb
Host smart-34a1076f-ad54-4733-a4b0-6309ba7871ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3148920954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3148920954
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.4175240659
Short name T723
Test name
Test status
Simulation time 29673428458 ps
CPU time 16.18 seconds
Started Aug 11 04:26:41 PM PDT 24
Finished Aug 11 04:26:58 PM PDT 24
Peak memory 199328 kb
Host smart-fb365ce9-b595-4f59-8af5-c89a8c4c1ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175240659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.4175240659
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.4079351228
Short name T536
Test name
Test status
Simulation time 3884591439 ps
CPU time 1.99 seconds
Started Aug 11 04:26:49 PM PDT 24
Finished Aug 11 04:26:51 PM PDT 24
Peak memory 195876 kb
Host smart-5cef3836-a8c7-425d-b938-5bc89adcc5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079351228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.4079351228
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.344120415
Short name T1031
Test name
Test status
Simulation time 5506644774 ps
CPU time 17.41 seconds
Started Aug 11 04:26:44 PM PDT 24
Finished Aug 11 04:27:02 PM PDT 24
Peak memory 199428 kb
Host smart-32d50dda-b526-420b-9640-946b9a4a146e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344120415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.344120415
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.2230847342
Short name T534
Test name
Test status
Simulation time 104037972573 ps
CPU time 78 seconds
Started Aug 11 04:26:34 PM PDT 24
Finished Aug 11 04:27:52 PM PDT 24
Peak memory 208024 kb
Host smart-b41ef402-87a2-474e-bcfc-27c8b2051a38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230847342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2230847342
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.828562469
Short name T573
Test name
Test status
Simulation time 120128224433 ps
CPU time 632.69 seconds
Started Aug 11 04:26:40 PM PDT 24
Finished Aug 11 04:37:12 PM PDT 24
Peak memory 216476 kb
Host smart-b3604749-55c0-4b71-b669-a2140543da9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828562469 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.828562469
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1159088720
Short name T484
Test name
Test status
Simulation time 7065711119 ps
CPU time 26.92 seconds
Started Aug 11 04:26:29 PM PDT 24
Finished Aug 11 04:26:56 PM PDT 24
Peak memory 199544 kb
Host smart-6d0cf02f-b649-444f-853f-509e55249b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159088720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1159088720
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.221943605
Short name T44
Test name
Test status
Simulation time 239083226557 ps
CPU time 84.88 seconds
Started Aug 11 04:26:48 PM PDT 24
Finished Aug 11 04:28:13 PM PDT 24
Peak memory 199664 kb
Host smart-280a9c40-fc38-495c-b72a-2a23a32bcc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221943605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.221943605
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.2973395966
Short name T897
Test name
Test status
Simulation time 210276485223 ps
CPU time 753.93 seconds
Started Aug 11 04:28:29 PM PDT 24
Finished Aug 11 04:41:03 PM PDT 24
Peak memory 199712 kb
Host smart-de53082b-34cc-4fd8-875b-4398e6690f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973395966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2973395966
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.1627332844
Short name T3
Test name
Test status
Simulation time 149900930843 ps
CPU time 21.02 seconds
Started Aug 11 04:28:34 PM PDT 24
Finished Aug 11 04:28:55 PM PDT 24
Peak memory 199792 kb
Host smart-20e70def-7865-41c5-9848-8274d9c0b2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627332844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1627332844
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.30902616
Short name T1050
Test name
Test status
Simulation time 105927609484 ps
CPU time 75.63 seconds
Started Aug 11 04:28:28 PM PDT 24
Finished Aug 11 04:29:44 PM PDT 24
Peak memory 199748 kb
Host smart-27209403-092a-4328-be37-79f0eb672287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30902616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.30902616
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2755319063
Short name T403
Test name
Test status
Simulation time 49990711768 ps
CPU time 23.59 seconds
Started Aug 11 04:28:27 PM PDT 24
Finished Aug 11 04:28:51 PM PDT 24
Peak memory 199716 kb
Host smart-5b1dad77-de6a-40ac-9303-8f3953e0d496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755319063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2755319063
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3636962417
Short name T476
Test name
Test status
Simulation time 16363694773 ps
CPU time 27.94 seconds
Started Aug 11 04:28:26 PM PDT 24
Finished Aug 11 04:28:55 PM PDT 24
Peak memory 199756 kb
Host smart-3da658fa-a073-4c69-b3f9-de30e51929df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636962417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3636962417
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.3287425614
Short name T975
Test name
Test status
Simulation time 117014201522 ps
CPU time 160.51 seconds
Started Aug 11 04:28:34 PM PDT 24
Finished Aug 11 04:31:15 PM PDT 24
Peak memory 199704 kb
Host smart-e62dc670-efe6-4dbd-bb1a-69731aaf2075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287425614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3287425614
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.278203486
Short name T8
Test name
Test status
Simulation time 16364055450 ps
CPU time 25.11 seconds
Started Aug 11 04:28:37 PM PDT 24
Finished Aug 11 04:29:02 PM PDT 24
Peak memory 199760 kb
Host smart-dcb1c413-2499-43ba-b221-b937994d659e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278203486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.278203486
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.4161809624
Short name T141
Test name
Test status
Simulation time 22380378902 ps
CPU time 27.32 seconds
Started Aug 11 04:28:21 PM PDT 24
Finished Aug 11 04:28:49 PM PDT 24
Peak memory 199696 kb
Host smart-3aebe134-8de9-4dea-bf49-c9e987bbf60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161809624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.4161809624
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3821188276
Short name T207
Test name
Test status
Simulation time 80565751930 ps
CPU time 28.49 seconds
Started Aug 11 04:28:27 PM PDT 24
Finished Aug 11 04:28:56 PM PDT 24
Peak memory 199652 kb
Host smart-1fd08ca2-51b5-4985-b6cd-fb6e88dd8e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821188276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3821188276
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.4068081840
Short name T762
Test name
Test status
Simulation time 14550495 ps
CPU time 0.53 seconds
Started Aug 11 04:26:50 PM PDT 24
Finished Aug 11 04:26:51 PM PDT 24
Peak memory 194320 kb
Host smart-5a07b448-a611-4d33-8f05-dfbd07836cd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068081840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.4068081840
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3857839249
Short name T72
Test name
Test status
Simulation time 246555126118 ps
CPU time 51.32 seconds
Started Aug 11 04:26:27 PM PDT 24
Finished Aug 11 04:27:18 PM PDT 24
Peak memory 199680 kb
Host smart-43e887bb-56cb-4399-99f5-750235de853d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857839249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3857839249
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.1226423812
Short name T1134
Test name
Test status
Simulation time 18753386671 ps
CPU time 15.51 seconds
Started Aug 11 04:26:53 PM PDT 24
Finished Aug 11 04:27:09 PM PDT 24
Peak memory 199728 kb
Host smart-6d9df546-eb09-4197-9d6a-129c4bbe9457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226423812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1226423812
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.1023671590
Short name T765
Test name
Test status
Simulation time 43507898257 ps
CPU time 71.46 seconds
Started Aug 11 04:26:51 PM PDT 24
Finished Aug 11 04:28:03 PM PDT 24
Peak memory 199772 kb
Host smart-f792d03e-214d-46cd-b9a5-696fbad8dc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023671590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1023671590
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.1633807911
Short name T419
Test name
Test status
Simulation time 33272076187 ps
CPU time 29.06 seconds
Started Aug 11 04:26:40 PM PDT 24
Finished Aug 11 04:27:09 PM PDT 24
Peak memory 198232 kb
Host smart-37f46a3c-6a81-478a-b802-07f1cb277d60
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633807911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1633807911
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.3656964100
Short name T819
Test name
Test status
Simulation time 118631642997 ps
CPU time 770.93 seconds
Started Aug 11 04:26:55 PM PDT 24
Finished Aug 11 04:39:47 PM PDT 24
Peak memory 199712 kb
Host smart-3eaeaec9-7330-4a66-8683-ca619c05c722
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3656964100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3656964100
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.3315615726
Short name T1054
Test name
Test status
Simulation time 13807915478 ps
CPU time 7.51 seconds
Started Aug 11 04:26:50 PM PDT 24
Finished Aug 11 04:26:58 PM PDT 24
Peak memory 198696 kb
Host smart-cb3c94da-5d9f-4cc7-8e75-aac76079434c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315615726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.3315615726
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.3720641131
Short name T284
Test name
Test status
Simulation time 167368601830 ps
CPU time 130.98 seconds
Started Aug 11 04:26:50 PM PDT 24
Finished Aug 11 04:29:01 PM PDT 24
Peak memory 199928 kb
Host smart-b8f325c6-f649-4ff3-a9ab-9c82a230fa2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720641131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3720641131
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.706145648
Short name T283
Test name
Test status
Simulation time 21360787253 ps
CPU time 1127.85 seconds
Started Aug 11 04:26:47 PM PDT 24
Finished Aug 11 04:45:36 PM PDT 24
Peak memory 199716 kb
Host smart-42fd442e-d2fa-4094-8fc0-f742fa9d6cd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=706145648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.706145648
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2436620376
Short name T760
Test name
Test status
Simulation time 6107872110 ps
CPU time 12.88 seconds
Started Aug 11 04:26:53 PM PDT 24
Finished Aug 11 04:27:06 PM PDT 24
Peak memory 198000 kb
Host smart-98208bf6-282a-484a-9d70-2779bcfc0e8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2436620376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2436620376
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2127866371
Short name T312
Test name
Test status
Simulation time 109162886711 ps
CPU time 77.95 seconds
Started Aug 11 04:26:39 PM PDT 24
Finished Aug 11 04:27:57 PM PDT 24
Peak memory 199784 kb
Host smart-889e16c5-5371-4a9d-a8c2-08e1e7b269a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127866371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2127866371
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.3395554745
Short name T489
Test name
Test status
Simulation time 39955905282 ps
CPU time 26.12 seconds
Started Aug 11 04:26:50 PM PDT 24
Finished Aug 11 04:27:16 PM PDT 24
Peak memory 196252 kb
Host smart-6391bbf4-3f9a-4c0b-999f-90b16269990b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395554745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3395554745
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2100853573
Short name T933
Test name
Test status
Simulation time 927659037 ps
CPU time 3.62 seconds
Started Aug 11 04:26:38 PM PDT 24
Finished Aug 11 04:26:42 PM PDT 24
Peak memory 198076 kb
Host smart-81eff7fc-a1f0-47f7-a732-6a9823924ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100853573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2100853573
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.932787929
Short name T679
Test name
Test status
Simulation time 5544520136 ps
CPU time 5.29 seconds
Started Aug 11 04:26:48 PM PDT 24
Finished Aug 11 04:26:53 PM PDT 24
Peak memory 199652 kb
Host smart-5cfb5eec-a20c-41c7-a916-aa9a3b035ff7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932787929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.932787929
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3622520960
Short name T1135
Test name
Test status
Simulation time 2399265854 ps
CPU time 2.33 seconds
Started Aug 11 04:26:48 PM PDT 24
Finished Aug 11 04:26:51 PM PDT 24
Peak memory 198884 kb
Host smart-964c1b32-6e5d-48ca-817d-70eeb90d67bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622520960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3622520960
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.105182446
Short name T815
Test name
Test status
Simulation time 32729457982 ps
CPU time 72.55 seconds
Started Aug 11 04:26:38 PM PDT 24
Finished Aug 11 04:27:50 PM PDT 24
Peak memory 199732 kb
Host smart-64d017ed-ab27-494b-94f2-39339cb40e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105182446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.105182446
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.941379600
Short name T1017
Test name
Test status
Simulation time 30796821043 ps
CPU time 41.85 seconds
Started Aug 11 04:28:39 PM PDT 24
Finished Aug 11 04:29:21 PM PDT 24
Peak memory 199708 kb
Host smart-4cb089d2-180e-4931-9a8f-10bbbd57211d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941379600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.941379600
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.195229564
Short name T501
Test name
Test status
Simulation time 56420167720 ps
CPU time 23.75 seconds
Started Aug 11 04:28:38 PM PDT 24
Finished Aug 11 04:29:02 PM PDT 24
Peak memory 199756 kb
Host smart-c7716034-c066-48ac-a2e9-455986828b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195229564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.195229564
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.2982923792
Short name T553
Test name
Test status
Simulation time 197402485862 ps
CPU time 272.41 seconds
Started Aug 11 04:28:38 PM PDT 24
Finished Aug 11 04:33:10 PM PDT 24
Peak memory 199728 kb
Host smart-f8ad81a2-769c-46ca-b836-97a8831d7a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982923792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.2982923792
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2684986413
Short name T698
Test name
Test status
Simulation time 16005532907 ps
CPU time 21.92 seconds
Started Aug 11 04:28:26 PM PDT 24
Finished Aug 11 04:28:48 PM PDT 24
Peak memory 199804 kb
Host smart-57e60bb1-ae28-423a-b276-99e5eaf4799e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684986413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2684986413
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.1138025407
Short name T11
Test name
Test status
Simulation time 79197619996 ps
CPU time 35.1 seconds
Started Aug 11 04:28:39 PM PDT 24
Finished Aug 11 04:29:14 PM PDT 24
Peak memory 199652 kb
Host smart-934c3fda-f467-48c7-a73e-52f1e93a59ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138025407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1138025407
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1249201395
Short name T561
Test name
Test status
Simulation time 110183735703 ps
CPU time 14.42 seconds
Started Aug 11 04:28:37 PM PDT 24
Finished Aug 11 04:28:52 PM PDT 24
Peak memory 199624 kb
Host smart-34232615-69b6-40dc-896a-45170e610a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249201395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1249201395
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3613585704
Short name T942
Test name
Test status
Simulation time 16465390532 ps
CPU time 30.42 seconds
Started Aug 11 04:28:41 PM PDT 24
Finished Aug 11 04:29:11 PM PDT 24
Peak memory 199668 kb
Host smart-52bbc88c-fd13-46a2-9238-b3139cb5fb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613585704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3613585704
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.2789813987
Short name T1014
Test name
Test status
Simulation time 11552892830 ps
CPU time 10.65 seconds
Started Aug 11 04:28:37 PM PDT 24
Finished Aug 11 04:28:48 PM PDT 24
Peak memory 199800 kb
Host smart-06ee5584-f163-4ad9-9501-6a088b1c2e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789813987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2789813987
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1567695117
Short name T317
Test name
Test status
Simulation time 97480023243 ps
CPU time 157.08 seconds
Started Aug 11 04:28:34 PM PDT 24
Finished Aug 11 04:31:11 PM PDT 24
Peak memory 199820 kb
Host smart-398b1ef3-3390-4d3e-ac6d-fcb5ec7272b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567695117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1567695117
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2278002252
Short name T360
Test name
Test status
Simulation time 11728816 ps
CPU time 0.53 seconds
Started Aug 11 04:26:51 PM PDT 24
Finished Aug 11 04:26:52 PM PDT 24
Peak memory 195420 kb
Host smart-6439c776-9787-417e-88d5-12b39dbdf0c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278002252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2278002252
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.1090818863
Short name T417
Test name
Test status
Simulation time 228388857535 ps
CPU time 23.04 seconds
Started Aug 11 04:26:52 PM PDT 24
Finished Aug 11 04:27:15 PM PDT 24
Peak memory 199304 kb
Host smart-fc277efa-5760-4590-8dda-56bbe63436fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090818863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1090818863
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.3286097944
Short name T436
Test name
Test status
Simulation time 30615046366 ps
CPU time 22.23 seconds
Started Aug 11 04:26:45 PM PDT 24
Finished Aug 11 04:27:07 PM PDT 24
Peak memory 199772 kb
Host smart-c009f028-4302-4264-8b89-aa564cbed697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286097944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3286097944
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.1364258676
Short name T817
Test name
Test status
Simulation time 45923641786 ps
CPU time 40.83 seconds
Started Aug 11 04:26:53 PM PDT 24
Finished Aug 11 04:27:34 PM PDT 24
Peak memory 199712 kb
Host smart-560e7cea-25ca-48cc-94f2-270da8d791d0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364258676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1364258676
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.1913085146
Short name T882
Test name
Test status
Simulation time 96003749484 ps
CPU time 754.47 seconds
Started Aug 11 04:26:54 PM PDT 24
Finished Aug 11 04:39:29 PM PDT 24
Peak memory 199664 kb
Host smart-8b7575f0-2e6c-418d-8b45-2de333300c0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1913085146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1913085146
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.600211646
Short name T1003
Test name
Test status
Simulation time 1576244764 ps
CPU time 1.18 seconds
Started Aug 11 04:26:49 PM PDT 24
Finished Aug 11 04:26:50 PM PDT 24
Peak memory 195464 kb
Host smart-11145e5c-f3bb-4730-9607-ec8c9e9d51b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600211646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.600211646
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.640539595
Short name T904
Test name
Test status
Simulation time 211297012305 ps
CPU time 176.45 seconds
Started Aug 11 04:26:56 PM PDT 24
Finished Aug 11 04:29:53 PM PDT 24
Peak memory 200236 kb
Host smart-8a1cb52d-1211-4f69-944a-70eb99cf73b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640539595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.640539595
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.379318918
Short name T798
Test name
Test status
Simulation time 18464271025 ps
CPU time 627.07 seconds
Started Aug 11 04:26:52 PM PDT 24
Finished Aug 11 04:37:19 PM PDT 24
Peak memory 199588 kb
Host smart-ada71c71-4d62-41f5-a59a-1b280d296a92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=379318918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.379318918
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.575231860
Short name T847
Test name
Test status
Simulation time 7311483154 ps
CPU time 62.01 seconds
Started Aug 11 04:26:52 PM PDT 24
Finished Aug 11 04:27:54 PM PDT 24
Peak memory 197560 kb
Host smart-f40506d6-e37e-4bc7-85f7-f8b138f8f488
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=575231860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.575231860
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.616344292
Short name T1025
Test name
Test status
Simulation time 188975065143 ps
CPU time 56.97 seconds
Started Aug 11 04:26:31 PM PDT 24
Finished Aug 11 04:27:28 PM PDT 24
Peak memory 199720 kb
Host smart-148873d6-1e52-47bb-b19a-7714873cf817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616344292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.616344292
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.824747845
Short name T282
Test name
Test status
Simulation time 77911817563 ps
CPU time 109.73 seconds
Started Aug 11 04:26:50 PM PDT 24
Finished Aug 11 04:28:40 PM PDT 24
Peak memory 195764 kb
Host smart-55fb283f-458d-4846-899a-7651eab7c0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824747845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.824747845
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2774074561
Short name T512
Test name
Test status
Simulation time 456941797 ps
CPU time 1.62 seconds
Started Aug 11 04:26:55 PM PDT 24
Finished Aug 11 04:26:57 PM PDT 24
Peak memory 197976 kb
Host smart-b470a396-8a24-419b-a26e-399da19960de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774074561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2774074561
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.4008073495
Short name T832
Test name
Test status
Simulation time 244180490576 ps
CPU time 286.67 seconds
Started Aug 11 04:26:50 PM PDT 24
Finished Aug 11 04:31:37 PM PDT 24
Peak memory 199752 kb
Host smart-37622b9c-9293-45d5-8a9a-0fdbc234e14d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008073495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.4008073495
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.4243519974
Short name T900
Test name
Test status
Simulation time 807591349 ps
CPU time 1.15 seconds
Started Aug 11 04:26:58 PM PDT 24
Finished Aug 11 04:26:59 PM PDT 24
Peak memory 198304 kb
Host smart-b05180da-2874-48a4-ab55-86d32c6a1485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243519974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.4243519974
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2151721212
Short name T267
Test name
Test status
Simulation time 10033810481 ps
CPU time 19.18 seconds
Started Aug 11 04:26:55 PM PDT 24
Finished Aug 11 04:27:14 PM PDT 24
Peak memory 199692 kb
Host smart-d737c1dd-9724-42d5-83a3-5ae80d29fb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151721212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2151721212
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3770938518
Short name T137
Test name
Test status
Simulation time 65354007673 ps
CPU time 83.58 seconds
Started Aug 11 04:28:34 PM PDT 24
Finished Aug 11 04:29:58 PM PDT 24
Peak memory 199768 kb
Host smart-3bf24134-635e-42df-90bd-ed160591e620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770938518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3770938518
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.92177619
Short name T718
Test name
Test status
Simulation time 67206962401 ps
CPU time 33.97 seconds
Started Aug 11 04:28:37 PM PDT 24
Finished Aug 11 04:29:11 PM PDT 24
Peak memory 199796 kb
Host smart-6f293ac9-5666-4187-8e03-74c804a0a37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92177619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.92177619
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.607156711
Short name T555
Test name
Test status
Simulation time 45910033445 ps
CPU time 15.76 seconds
Started Aug 11 04:28:27 PM PDT 24
Finished Aug 11 04:28:44 PM PDT 24
Peak memory 199728 kb
Host smart-75fd17e4-7757-4ac2-9926-95dcc7fc76d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607156711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.607156711
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1932106951
Short name T707
Test name
Test status
Simulation time 35822810576 ps
CPU time 32.04 seconds
Started Aug 11 04:28:22 PM PDT 24
Finished Aug 11 04:28:54 PM PDT 24
Peak memory 199644 kb
Host smart-7e5d96d4-845c-49fa-96a8-3d82be1bd315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932106951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1932106951
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.725525392
Short name T1173
Test name
Test status
Simulation time 44550084047 ps
CPU time 18.96 seconds
Started Aug 11 04:28:23 PM PDT 24
Finished Aug 11 04:28:42 PM PDT 24
Peak memory 199312 kb
Host smart-2e4a3274-e7f3-423a-8606-5ec91f25a8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725525392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.725525392
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3429849814
Short name T276
Test name
Test status
Simulation time 21208279513 ps
CPU time 41.99 seconds
Started Aug 11 04:28:23 PM PDT 24
Finished Aug 11 04:29:05 PM PDT 24
Peak memory 199632 kb
Host smart-17f07ef4-46cb-4898-a812-bb8797be786c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429849814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3429849814
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2945251370
Short name T189
Test name
Test status
Simulation time 18185640193 ps
CPU time 31.45 seconds
Started Aug 11 04:28:24 PM PDT 24
Finished Aug 11 04:28:56 PM PDT 24
Peak memory 199788 kb
Host smart-e66e482b-6725-4126-afcc-8a5babebc850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945251370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2945251370
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2294581405
Short name T201
Test name
Test status
Simulation time 34406141098 ps
CPU time 18.73 seconds
Started Aug 11 04:28:36 PM PDT 24
Finished Aug 11 04:28:55 PM PDT 24
Peak memory 199684 kb
Host smart-e43b1c31-9130-4340-af96-f337dd6b5f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294581405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2294581405
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3285913912
Short name T1143
Test name
Test status
Simulation time 30785074693 ps
CPU time 17.84 seconds
Started Aug 11 04:28:27 PM PDT 24
Finished Aug 11 04:28:46 PM PDT 24
Peak memory 199700 kb
Host smart-31694eac-a31a-4ac7-837a-eda6e84fc883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285913912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3285913912
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.3400538282
Short name T1136
Test name
Test status
Simulation time 245369651735 ps
CPU time 28.86 seconds
Started Aug 11 04:28:36 PM PDT 24
Finished Aug 11 04:29:05 PM PDT 24
Peak memory 199748 kb
Host smart-cd2d0e11-5bb0-43d2-a504-772457b00f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400538282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3400538282
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.789919452
Short name T103
Test name
Test status
Simulation time 13263392 ps
CPU time 0.59 seconds
Started Aug 11 04:22:08 PM PDT 24
Finished Aug 11 04:22:09 PM PDT 24
Peak memory 195148 kb
Host smart-492fd947-c17a-4a53-8628-c41fccea0b9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789919452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.789919452
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1983707671
Short name T672
Test name
Test status
Simulation time 54012273851 ps
CPU time 83.72 seconds
Started Aug 11 04:20:07 PM PDT 24
Finished Aug 11 04:21:31 PM PDT 24
Peak memory 199728 kb
Host smart-d82549a6-6043-4dd4-bf5f-4954a706c233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983707671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1983707671
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1696253039
Short name T285
Test name
Test status
Simulation time 111132368001 ps
CPU time 313.74 seconds
Started Aug 11 04:19:49 PM PDT 24
Finished Aug 11 04:25:03 PM PDT 24
Peak memory 199724 kb
Host smart-8be9237b-0b3e-4d66-9145-585871f1fda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696253039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1696253039
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.3480926783
Short name T526
Test name
Test status
Simulation time 81124687657 ps
CPU time 45.02 seconds
Started Aug 11 04:23:55 PM PDT 24
Finished Aug 11 04:24:41 PM PDT 24
Peak memory 198960 kb
Host smart-870dc7cf-c0f3-4f8b-b441-dd6a893f43bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480926783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3480926783
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.4110542667
Short name T356
Test name
Test status
Simulation time 18315250677 ps
CPU time 28.27 seconds
Started Aug 11 04:22:05 PM PDT 24
Finished Aug 11 04:22:34 PM PDT 24
Peak memory 196804 kb
Host smart-38dbc578-ab58-45eb-b4fd-e56f987f2d86
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110542667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.4110542667
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.155963042
Short name T820
Test name
Test status
Simulation time 113786774229 ps
CPU time 826.51 seconds
Started Aug 11 04:24:01 PM PDT 24
Finished Aug 11 04:37:47 PM PDT 24
Peak memory 199428 kb
Host smart-1dd75569-134d-4e83-ac6d-af66a247425e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=155963042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.155963042
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.40062847
Short name T410
Test name
Test status
Simulation time 9903119850 ps
CPU time 8.83 seconds
Started Aug 11 04:24:00 PM PDT 24
Finished Aug 11 04:24:09 PM PDT 24
Peak memory 199096 kb
Host smart-e4bc8144-bb0e-40a8-a317-b710f150280c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40062847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.40062847
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.1140310679
Short name T879
Test name
Test status
Simulation time 187136192163 ps
CPU time 217.51 seconds
Started Aug 11 04:22:08 PM PDT 24
Finished Aug 11 04:25:46 PM PDT 24
Peak memory 199824 kb
Host smart-6883360d-b3f6-48a9-a3ab-2cf357004755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140310679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1140310679
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3186868385
Short name T266
Test name
Test status
Simulation time 11621040692 ps
CPU time 134.2 seconds
Started Aug 11 04:24:24 PM PDT 24
Finished Aug 11 04:26:39 PM PDT 24
Peak memory 198860 kb
Host smart-661fe41f-b55d-44e2-8b48-9af3bc182e8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3186868385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3186868385
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.3056817914
Short name T962
Test name
Test status
Simulation time 4802458682 ps
CPU time 19.32 seconds
Started Aug 11 04:24:04 PM PDT 24
Finished Aug 11 04:24:24 PM PDT 24
Peak memory 197700 kb
Host smart-7501a91f-ffee-44a3-b7ac-845e22411bb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3056817914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3056817914
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.2766401416
Short name T966
Test name
Test status
Simulation time 114193737548 ps
CPU time 49.18 seconds
Started Aug 11 04:24:17 PM PDT 24
Finished Aug 11 04:25:06 PM PDT 24
Peak memory 199128 kb
Host smart-d0fa0c4e-7609-4832-ab96-8193b67f559e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766401416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.2766401416
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2842420123
Short name T299
Test name
Test status
Simulation time 4050973468 ps
CPU time 1.94 seconds
Started Aug 11 04:24:29 PM PDT 24
Finished Aug 11 04:24:31 PM PDT 24
Peak memory 196348 kb
Host smart-bb590312-4d97-449a-94a6-485a642c18ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842420123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2842420123
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2076905953
Short name T101
Test name
Test status
Simulation time 131699199 ps
CPU time 0.79 seconds
Started Aug 11 04:21:13 PM PDT 24
Finished Aug 11 04:21:14 PM PDT 24
Peak memory 218156 kb
Host smart-cbb6770e-582c-4440-907c-43fe47800932
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076905953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2076905953
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.4224791903
Short name T355
Test name
Test status
Simulation time 662032408 ps
CPU time 2.46 seconds
Started Aug 11 04:19:42 PM PDT 24
Finished Aug 11 04:19:44 PM PDT 24
Peak memory 198576 kb
Host smart-d6418cfc-366f-4e34-9b98-0aae0291cd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224791903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.4224791903
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.2978359268
Short name T515
Test name
Test status
Simulation time 182466856803 ps
CPU time 99.73 seconds
Started Aug 11 04:24:06 PM PDT 24
Finished Aug 11 04:25:46 PM PDT 24
Peak memory 199536 kb
Host smart-a60077bf-1279-47bc-9b67-17b280560cc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978359268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2978359268
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3294450447
Short name T114
Test name
Test status
Simulation time 51025124457 ps
CPU time 216.52 seconds
Started Aug 11 04:24:02 PM PDT 24
Finished Aug 11 04:27:38 PM PDT 24
Peak memory 216028 kb
Host smart-54fe4f44-f65c-407c-9ddd-f1fb5c7a8686
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294450447 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3294450447
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.218702058
Short name T911
Test name
Test status
Simulation time 7388686832 ps
CPU time 14.3 seconds
Started Aug 11 04:21:07 PM PDT 24
Finished Aug 11 04:21:22 PM PDT 24
Peak memory 199420 kb
Host smart-a4551d83-203f-447c-b67f-014c08fef43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218702058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.218702058
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1480134683
Short name T473
Test name
Test status
Simulation time 36851956958 ps
CPU time 28.21 seconds
Started Aug 11 04:24:13 PM PDT 24
Finished Aug 11 04:24:41 PM PDT 24
Peak memory 199684 kb
Host smart-803b7dca-5527-4535-8017-c7014d56990c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480134683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1480134683
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.2364913392
Short name T378
Test name
Test status
Simulation time 43376345 ps
CPU time 0.54 seconds
Started Aug 11 04:26:52 PM PDT 24
Finished Aug 11 04:26:53 PM PDT 24
Peak memory 195116 kb
Host smart-d6da0170-9b91-4237-84a7-9e4f6442be50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364913392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2364913392
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3679308509
Short name T854
Test name
Test status
Simulation time 110376572870 ps
CPU time 55.96 seconds
Started Aug 11 04:26:35 PM PDT 24
Finished Aug 11 04:27:31 PM PDT 24
Peak memory 199800 kb
Host smart-d18cfab8-5887-47e4-ba0a-d3af1079372a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679308509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3679308509
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.4123001072
Short name T139
Test name
Test status
Simulation time 62909587194 ps
CPU time 20.76 seconds
Started Aug 11 04:26:46 PM PDT 24
Finished Aug 11 04:27:07 PM PDT 24
Peak memory 199640 kb
Host smart-05a0db10-858f-4057-b9f1-5adfdc545772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123001072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.4123001072
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_intr.3697710567
Short name T829
Test name
Test status
Simulation time 47591287747 ps
CPU time 35.83 seconds
Started Aug 11 04:26:52 PM PDT 24
Finished Aug 11 04:27:28 PM PDT 24
Peak memory 199748 kb
Host smart-4ddad90f-1b45-4940-8fb9-0866099df5e9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697710567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3697710567
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1933191317
Short name T1111
Test name
Test status
Simulation time 88941787027 ps
CPU time 407.71 seconds
Started Aug 11 04:26:53 PM PDT 24
Finished Aug 11 04:33:41 PM PDT 24
Peak memory 199712 kb
Host smart-7297751d-603d-4906-bda7-f5ec7c95bd52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1933191317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1933191317
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.3424542172
Short name T806
Test name
Test status
Simulation time 6824553419 ps
CPU time 3.23 seconds
Started Aug 11 04:26:47 PM PDT 24
Finished Aug 11 04:26:50 PM PDT 24
Peak memory 199016 kb
Host smart-5c0fe8cb-00b9-4088-b443-f760446f186a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424542172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3424542172
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.2954010460
Short name T293
Test name
Test status
Simulation time 202881077050 ps
CPU time 111.77 seconds
Started Aug 11 04:26:47 PM PDT 24
Finished Aug 11 04:28:40 PM PDT 24
Peak memory 198788 kb
Host smart-8df48f05-2619-4fb9-aa46-baca2e4c77a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954010460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2954010460
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.645729679
Short name T780
Test name
Test status
Simulation time 18568143592 ps
CPU time 436.4 seconds
Started Aug 11 04:26:51 PM PDT 24
Finished Aug 11 04:34:07 PM PDT 24
Peak memory 199776 kb
Host smart-2a3b1214-06d1-4176-b479-ef20cdac37cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=645729679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.645729679
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.328788240
Short name T839
Test name
Test status
Simulation time 6330274687 ps
CPU time 53.41 seconds
Started Aug 11 04:26:52 PM PDT 24
Finished Aug 11 04:27:46 PM PDT 24
Peak memory 198828 kb
Host smart-f14c437d-5bdf-4fcc-86f3-ffcfa550a2ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=328788240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.328788240
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.4100912552
Short name T1102
Test name
Test status
Simulation time 80433651119 ps
CPU time 10.63 seconds
Started Aug 11 04:26:52 PM PDT 24
Finished Aug 11 04:27:03 PM PDT 24
Peak memory 199592 kb
Host smart-6da3d3ec-0195-478e-81bd-187d8d02a24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100912552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.4100912552
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3808037293
Short name T327
Test name
Test status
Simulation time 5082022779 ps
CPU time 2.64 seconds
Started Aug 11 04:26:53 PM PDT 24
Finished Aug 11 04:26:56 PM PDT 24
Peak memory 196120 kb
Host smart-40eb856e-50d0-4ca3-a573-18124739735e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808037293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3808037293
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.2583491315
Short name T943
Test name
Test status
Simulation time 721892457 ps
CPU time 1.28 seconds
Started Aug 11 04:26:45 PM PDT 24
Finished Aug 11 04:26:46 PM PDT 24
Peak memory 198052 kb
Host smart-949349e3-28ab-4f06-86ed-4eddb2172ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583491315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2583491315
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.816180360
Short name T979
Test name
Test status
Simulation time 51270601216 ps
CPU time 293.62 seconds
Started Aug 11 04:26:55 PM PDT 24
Finished Aug 11 04:31:49 PM PDT 24
Peak memory 213728 kb
Host smart-9d0872ce-818b-4946-bfc8-149dcd802f13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816180360 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.816180360
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.1748886047
Short name T584
Test name
Test status
Simulation time 6477636570 ps
CPU time 1.78 seconds
Started Aug 11 04:26:50 PM PDT 24
Finished Aug 11 04:26:51 PM PDT 24
Peak memory 199036 kb
Host smart-6573f13a-e07f-40af-a532-9e0e5ef03031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748886047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1748886047
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.1925022178
Short name T488
Test name
Test status
Simulation time 101450005982 ps
CPU time 102.03 seconds
Started Aug 11 04:26:53 PM PDT 24
Finished Aug 11 04:28:35 PM PDT 24
Peak memory 199648 kb
Host smart-80609aab-3167-4ddd-945c-b479a5ea9ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925022178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1925022178
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3422083485
Short name T214
Test name
Test status
Simulation time 10506573654 ps
CPU time 12.89 seconds
Started Aug 11 04:28:33 PM PDT 24
Finished Aug 11 04:28:46 PM PDT 24
Peak memory 199724 kb
Host smart-9a2afbfb-c7ae-4ea1-9c8d-108759b49b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422083485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3422083485
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.875009259
Short name T586
Test name
Test status
Simulation time 144879367909 ps
CPU time 55.19 seconds
Started Aug 11 04:28:26 PM PDT 24
Finished Aug 11 04:29:22 PM PDT 24
Peak memory 199744 kb
Host smart-86504b2b-8b95-4e12-89a8-a9d5a05fd808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875009259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.875009259
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2404449137
Short name T971
Test name
Test status
Simulation time 24291807738 ps
CPU time 21.3 seconds
Started Aug 11 04:28:37 PM PDT 24
Finished Aug 11 04:28:59 PM PDT 24
Peak memory 199764 kb
Host smart-ae27ddfb-d695-4694-be2f-18c88ea74a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404449137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2404449137
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3181121428
Short name T199
Test name
Test status
Simulation time 280939340367 ps
CPU time 72.33 seconds
Started Aug 11 04:28:26 PM PDT 24
Finished Aug 11 04:29:39 PM PDT 24
Peak memory 199888 kb
Host smart-fb05592b-01c9-4aa5-ad08-971a53116566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181121428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3181121428
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2886337413
Short name T202
Test name
Test status
Simulation time 90220198025 ps
CPU time 125.03 seconds
Started Aug 11 04:28:28 PM PDT 24
Finished Aug 11 04:30:33 PM PDT 24
Peak memory 199680 kb
Host smart-9d2ef003-3ab5-47c3-a310-007fc9d86f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886337413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2886337413
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1555364876
Short name T991
Test name
Test status
Simulation time 20782866820 ps
CPU time 31.73 seconds
Started Aug 11 04:28:38 PM PDT 24
Finished Aug 11 04:29:10 PM PDT 24
Peak memory 199708 kb
Host smart-2c7c03bc-ffe6-48d1-8a9b-7994fd4a1901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555364876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1555364876
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.4282898402
Short name T251
Test name
Test status
Simulation time 120493141953 ps
CPU time 198.68 seconds
Started Aug 11 04:28:26 PM PDT 24
Finished Aug 11 04:31:45 PM PDT 24
Peak memory 199764 kb
Host smart-9334fa43-5f51-45ca-b370-bb9456f6377d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282898402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.4282898402
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1247447672
Short name T147
Test name
Test status
Simulation time 176564276633 ps
CPU time 409.15 seconds
Started Aug 11 04:28:29 PM PDT 24
Finished Aug 11 04:35:18 PM PDT 24
Peak memory 199688 kb
Host smart-b292eab4-fdd8-4d38-b2c6-9ed1858d8d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247447672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1247447672
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.1095400267
Short name T767
Test name
Test status
Simulation time 56846622205 ps
CPU time 28.79 seconds
Started Aug 11 04:28:27 PM PDT 24
Finished Aug 11 04:28:57 PM PDT 24
Peak memory 199728 kb
Host smart-6a1c02a0-9cee-4b1b-b024-dff4a5bb1b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095400267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1095400267
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1663674343
Short name T511
Test name
Test status
Simulation time 15043363 ps
CPU time 0.56 seconds
Started Aug 11 04:27:00 PM PDT 24
Finished Aug 11 04:27:01 PM PDT 24
Peak memory 195404 kb
Host smart-31c93156-84a6-444d-b7b6-73c3b06762a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663674343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1663674343
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.1212075453
Short name T713
Test name
Test status
Simulation time 42942506229 ps
CPU time 68.67 seconds
Started Aug 11 04:26:50 PM PDT 24
Finished Aug 11 04:27:59 PM PDT 24
Peak memory 199708 kb
Host smart-79039d4f-a4d3-4b0f-8d0a-5577924dcc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212075453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.1212075453
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.1049519253
Short name T457
Test name
Test status
Simulation time 62587823565 ps
CPU time 25.04 seconds
Started Aug 11 04:26:45 PM PDT 24
Finished Aug 11 04:27:25 PM PDT 24
Peak memory 199348 kb
Host smart-22fea09f-276d-484f-9117-14b74a5a77de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049519253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1049519253
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.3846355541
Short name T1055
Test name
Test status
Simulation time 214016252482 ps
CPU time 222.77 seconds
Started Aug 11 04:26:35 PM PDT 24
Finished Aug 11 04:30:18 PM PDT 24
Peak memory 199696 kb
Host smart-03043793-9fc6-486f-a459-4b0f85b60c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846355541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3846355541
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.2594502885
Short name T677
Test name
Test status
Simulation time 156276150641 ps
CPU time 355.07 seconds
Started Aug 11 04:26:52 PM PDT 24
Finished Aug 11 04:32:48 PM PDT 24
Peak memory 199724 kb
Host smart-d510d031-9f71-40dc-8772-cbf7f4282acb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594502885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2594502885
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3916209637
Short name T908
Test name
Test status
Simulation time 149382065964 ps
CPU time 276.08 seconds
Started Aug 11 04:26:52 PM PDT 24
Finished Aug 11 04:31:29 PM PDT 24
Peak memory 199652 kb
Host smart-a840fa33-ead7-42f9-b153-a4dc2aadb291
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3916209637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3916209637
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1912559273
Short name T418
Test name
Test status
Simulation time 2816649138 ps
CPU time 6.08 seconds
Started Aug 11 04:27:20 PM PDT 24
Finished Aug 11 04:27:26 PM PDT 24
Peak memory 199644 kb
Host smart-6468e86d-269b-4455-92f4-5f0b81fb9e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912559273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1912559273
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.900933466
Short name T1048
Test name
Test status
Simulation time 41450077543 ps
CPU time 60.74 seconds
Started Aug 11 04:26:50 PM PDT 24
Finished Aug 11 04:27:52 PM PDT 24
Peak memory 199808 kb
Host smart-82563c2f-1f8f-4831-9959-b4dba2e4ef02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900933466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.900933466
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.2081901244
Short name T279
Test name
Test status
Simulation time 5855049999 ps
CPU time 131.22 seconds
Started Aug 11 04:27:01 PM PDT 24
Finished Aug 11 04:29:13 PM PDT 24
Peak memory 199648 kb
Host smart-6508f4ea-d9a6-40e9-bb37-a6cb9ba017b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2081901244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2081901244
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.1338615930
Short name T724
Test name
Test status
Simulation time 2861136249 ps
CPU time 5.79 seconds
Started Aug 11 04:26:51 PM PDT 24
Finished Aug 11 04:26:57 PM PDT 24
Peak memory 197916 kb
Host smart-6b44b0de-a05a-4a28-be03-04f03f946ca2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1338615930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1338615930
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.3696371368
Short name T152
Test name
Test status
Simulation time 53031389377 ps
CPU time 82.19 seconds
Started Aug 11 04:26:55 PM PDT 24
Finished Aug 11 04:28:17 PM PDT 24
Peak memory 199680 kb
Host smart-6467a254-04be-416b-939f-7c09532d6c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696371368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3696371368
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2570189996
Short name T609
Test name
Test status
Simulation time 3944087854 ps
CPU time 2.24 seconds
Started Aug 11 04:26:51 PM PDT 24
Finished Aug 11 04:26:53 PM PDT 24
Peak memory 196596 kb
Host smart-81068182-7e14-457b-82cc-a4706fcb88c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570189996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2570189996
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.2094113485
Short name T700
Test name
Test status
Simulation time 445801600 ps
CPU time 2.23 seconds
Started Aug 11 04:26:51 PM PDT 24
Finished Aug 11 04:26:53 PM PDT 24
Peak memory 198664 kb
Host smart-55305c8f-3da6-4c2e-82ba-8758c4f5dc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094113485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2094113485
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.3049122807
Short name T938
Test name
Test status
Simulation time 297940672394 ps
CPU time 129.92 seconds
Started Aug 11 04:27:23 PM PDT 24
Finished Aug 11 04:29:34 PM PDT 24
Peak memory 199804 kb
Host smart-b2ec419b-4410-4a11-adc5-ca4ae86655da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049122807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.3049122807
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.2759959641
Short name T809
Test name
Test status
Simulation time 84855068031 ps
CPU time 1138.74 seconds
Started Aug 11 04:27:00 PM PDT 24
Finished Aug 11 04:46:00 PM PDT 24
Peak memory 216308 kb
Host smart-56f0d806-f54a-4e04-8162-e942e2fe023a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759959641 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.2759959641
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.120163145
Short name T887
Test name
Test status
Simulation time 1079619475 ps
CPU time 3.17 seconds
Started Aug 11 04:27:18 PM PDT 24
Finished Aug 11 04:27:21 PM PDT 24
Peak memory 198604 kb
Host smart-6cace3a8-7fdd-4c17-962d-1dc04f84ecc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120163145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.120163145
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1078638089
Short name T524
Test name
Test status
Simulation time 135262433995 ps
CPU time 142.28 seconds
Started Aug 11 04:26:52 PM PDT 24
Finished Aug 11 04:29:14 PM PDT 24
Peak memory 199768 kb
Host smart-50d7e366-e0ac-442b-a6a9-1e11ce8b4b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078638089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1078638089
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3502918973
Short name T636
Test name
Test status
Simulation time 32091082862 ps
CPU time 62.67 seconds
Started Aug 11 04:28:28 PM PDT 24
Finished Aug 11 04:29:31 PM PDT 24
Peak memory 199716 kb
Host smart-9947d973-b94a-47ff-b308-8bb331b57dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502918973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3502918973
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2241370215
Short name T482
Test name
Test status
Simulation time 52382824114 ps
CPU time 115.65 seconds
Started Aug 11 04:28:28 PM PDT 24
Finished Aug 11 04:30:24 PM PDT 24
Peak memory 199752 kb
Host smart-39a484f9-5d4e-4f4d-a119-d04b58fb8552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241370215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2241370215
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.465122218
Short name T211
Test name
Test status
Simulation time 98223660257 ps
CPU time 86.11 seconds
Started Aug 11 04:28:31 PM PDT 24
Finished Aug 11 04:29:57 PM PDT 24
Peak memory 199692 kb
Host smart-209006a5-c994-47d9-a58e-d957a836c903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465122218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.465122218
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2043240685
Short name T594
Test name
Test status
Simulation time 12270845326 ps
CPU time 18.33 seconds
Started Aug 11 04:28:30 PM PDT 24
Finished Aug 11 04:28:49 PM PDT 24
Peak memory 199668 kb
Host smart-8f9bf845-4c15-47e7-bfe6-9896edb56e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043240685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2043240685
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.1674954560
Short name T774
Test name
Test status
Simulation time 89997093772 ps
CPU time 47.22 seconds
Started Aug 11 04:28:40 PM PDT 24
Finished Aug 11 04:29:28 PM PDT 24
Peak memory 199708 kb
Host smart-5ea43893-3019-4f1b-a02e-aa4456f0e6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674954560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1674954560
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2908715091
Short name T1012
Test name
Test status
Simulation time 25569252026 ps
CPU time 38.02 seconds
Started Aug 11 04:28:28 PM PDT 24
Finished Aug 11 04:29:06 PM PDT 24
Peak memory 199808 kb
Host smart-a9f18ab0-fc08-43f7-b55b-f9d916c9ca36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908715091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2908715091
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.832166511
Short name T261
Test name
Test status
Simulation time 48145372782 ps
CPU time 19.3 seconds
Started Aug 11 04:28:27 PM PDT 24
Finished Aug 11 04:28:47 PM PDT 24
Peak memory 199608 kb
Host smart-93bf9a76-d610-4754-b8a2-eaafe5da0d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832166511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.832166511
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1704547744
Short name T249
Test name
Test status
Simulation time 46417913503 ps
CPU time 61.26 seconds
Started Aug 11 04:28:42 PM PDT 24
Finished Aug 11 04:29:43 PM PDT 24
Peak memory 199768 kb
Host smart-637f55f3-0dee-4d06-95ec-8a247f422cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704547744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1704547744
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.610910748
Short name T1103
Test name
Test status
Simulation time 23702624843 ps
CPU time 20.59 seconds
Started Aug 11 04:28:27 PM PDT 24
Finished Aug 11 04:28:48 PM PDT 24
Peak memory 199324 kb
Host smart-60548002-9706-49bb-ba37-76caff1b9ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610910748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.610910748
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1946798563
Short name T831
Test name
Test status
Simulation time 28340063778 ps
CPU time 41.29 seconds
Started Aug 11 04:28:32 PM PDT 24
Finished Aug 11 04:29:14 PM PDT 24
Peak memory 199664 kb
Host smart-4fc41434-b131-4a52-a1b6-ff34d5d59f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946798563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1946798563
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2743849439
Short name T984
Test name
Test status
Simulation time 32422313 ps
CPU time 0.54 seconds
Started Aug 11 04:26:47 PM PDT 24
Finished Aug 11 04:26:47 PM PDT 24
Peak memory 195396 kb
Host smart-218dd9f7-7d08-490e-8720-8b58f9ac55f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743849439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2743849439
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2888371848
Short name T176
Test name
Test status
Simulation time 91815913176 ps
CPU time 30.31 seconds
Started Aug 11 04:26:56 PM PDT 24
Finished Aug 11 04:27:26 PM PDT 24
Peak memory 199800 kb
Host smart-71ea9981-a08b-4585-b224-1708ee253d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888371848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2888371848
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2099177431
Short name T986
Test name
Test status
Simulation time 59359737786 ps
CPU time 48.94 seconds
Started Aug 11 04:26:52 PM PDT 24
Finished Aug 11 04:27:42 PM PDT 24
Peak memory 199772 kb
Host smart-463efe7f-c96a-40c2-9c5e-83ceca0c51f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099177431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2099177431
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.1099286276
Short name T376
Test name
Test status
Simulation time 3135141831 ps
CPU time 3.26 seconds
Started Aug 11 04:26:55 PM PDT 24
Finished Aug 11 04:26:59 PM PDT 24
Peak memory 199508 kb
Host smart-e1787af9-6203-449a-bdf9-96d55d7401b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099286276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1099286276
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.1154594884
Short name T852
Test name
Test status
Simulation time 18611455699 ps
CPU time 13.03 seconds
Started Aug 11 04:27:01 PM PDT 24
Finished Aug 11 04:27:15 PM PDT 24
Peak memory 199720 kb
Host smart-096be325-18ab-4526-960d-dd4198b01e97
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154594884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1154594884
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.2539543637
Short name T390
Test name
Test status
Simulation time 93293579978 ps
CPU time 175.11 seconds
Started Aug 11 04:26:36 PM PDT 24
Finished Aug 11 04:29:31 PM PDT 24
Peak memory 199712 kb
Host smart-caebb122-72dc-479f-8fe9-f99cd5880fc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2539543637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2539543637
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1870524716
Short name T122
Test name
Test status
Simulation time 4941917347 ps
CPU time 11.73 seconds
Started Aug 11 04:26:47 PM PDT 24
Finished Aug 11 04:26:59 PM PDT 24
Peak memory 198944 kb
Host smart-883c1b25-8705-4c55-bd5b-4e1b1fdcea25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870524716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1870524716
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.2962833817
Short name T1020
Test name
Test status
Simulation time 105223778510 ps
CPU time 42.96 seconds
Started Aug 11 04:26:56 PM PDT 24
Finished Aug 11 04:27:39 PM PDT 24
Peak memory 208100 kb
Host smart-ef5c90eb-fd9a-4db6-ba9a-e208ddd0031a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962833817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2962833817
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.324673610
Short name T392
Test name
Test status
Simulation time 4330215991 ps
CPU time 17.72 seconds
Started Aug 11 04:26:52 PM PDT 24
Finished Aug 11 04:27:11 PM PDT 24
Peak memory 199188 kb
Host smart-b76d14c4-253d-421a-b3be-bd2f681460f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=324673610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.324673610
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.725466656
Short name T335
Test name
Test status
Simulation time 84953033586 ps
CPU time 29.03 seconds
Started Aug 11 04:26:47 PM PDT 24
Finished Aug 11 04:27:16 PM PDT 24
Peak memory 199748 kb
Host smart-449469b8-578b-43e0-ada2-245128931775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725466656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.725466656
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.4184434965
Short name T638
Test name
Test status
Simulation time 6120851196 ps
CPU time 4.66 seconds
Started Aug 11 04:27:05 PM PDT 24
Finished Aug 11 04:27:10 PM PDT 24
Peak memory 195832 kb
Host smart-b1ed6860-9b5b-490f-a5c0-8611d10918c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184434965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.4184434965
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.308409900
Short name T309
Test name
Test status
Simulation time 508129731 ps
CPU time 2.07 seconds
Started Aug 11 04:26:54 PM PDT 24
Finished Aug 11 04:26:57 PM PDT 24
Peak memory 198384 kb
Host smart-4122274d-e895-4a78-ab6a-b29aba1ebc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308409900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.308409900
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.2334897017
Short name T50
Test name
Test status
Simulation time 41915123409 ps
CPU time 34.12 seconds
Started Aug 11 04:27:04 PM PDT 24
Finished Aug 11 04:27:39 PM PDT 24
Peak memory 199760 kb
Host smart-5a7bf859-b099-498f-a9ee-d84406aa8322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334897017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2334897017
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.1192055298
Short name T61
Test name
Test status
Simulation time 143360616349 ps
CPU time 1717.53 seconds
Started Aug 11 04:27:06 PM PDT 24
Finished Aug 11 04:55:44 PM PDT 24
Peak memory 229828 kb
Host smart-a41ba063-503d-44cf-9585-289d36eb05a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192055298 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1192055298
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.1498527906
Short name T509
Test name
Test status
Simulation time 1642240079 ps
CPU time 3.12 seconds
Started Aug 11 04:27:07 PM PDT 24
Finished Aug 11 04:27:10 PM PDT 24
Peak memory 198668 kb
Host smart-744f9bf7-6cf7-4dd6-b177-98fc0e5008c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498527906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1498527906
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1732270987
Short name T1137
Test name
Test status
Simulation time 67994339276 ps
CPU time 61.44 seconds
Started Aug 11 04:26:51 PM PDT 24
Finished Aug 11 04:27:52 PM PDT 24
Peak memory 199660 kb
Host smart-bf321571-1feb-488a-9432-b7753d3532af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732270987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1732270987
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.160853805
Short name T197
Test name
Test status
Simulation time 4793256807 ps
CPU time 10.57 seconds
Started Aug 11 04:28:42 PM PDT 24
Finished Aug 11 04:28:53 PM PDT 24
Peak memory 199708 kb
Host smart-5cbc14c4-d7e8-4367-b969-e618f8159fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160853805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.160853805
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.3465504757
Short name T160
Test name
Test status
Simulation time 139925889739 ps
CPU time 216.13 seconds
Started Aug 11 04:28:36 PM PDT 24
Finished Aug 11 04:32:12 PM PDT 24
Peak memory 199796 kb
Host smart-e6f3aa53-9f91-4e49-b09d-d2f44d9444ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465504757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3465504757
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.637755284
Short name T219
Test name
Test status
Simulation time 36496523527 ps
CPU time 59.65 seconds
Started Aug 11 04:28:38 PM PDT 24
Finished Aug 11 04:29:37 PM PDT 24
Peak memory 199752 kb
Host smart-b60a3274-c4a3-4722-b264-86c8667a7409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637755284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.637755284
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2902150229
Short name T532
Test name
Test status
Simulation time 61028408444 ps
CPU time 24.67 seconds
Started Aug 11 04:28:27 PM PDT 24
Finished Aug 11 04:28:52 PM PDT 24
Peak memory 199508 kb
Host smart-3139c52f-1788-4e19-9706-144bfcaffc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902150229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2902150229
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.2818189451
Short name T1177
Test name
Test status
Simulation time 4354159666 ps
CPU time 11.41 seconds
Started Aug 11 04:28:25 PM PDT 24
Finished Aug 11 04:28:37 PM PDT 24
Peak memory 199752 kb
Host smart-547c7146-11c4-4cd8-a03c-4e7ec2ebf438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818189451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2818189451
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2745605384
Short name T937
Test name
Test status
Simulation time 17786854408 ps
CPU time 19.97 seconds
Started Aug 11 04:28:27 PM PDT 24
Finished Aug 11 04:28:48 PM PDT 24
Peak memory 199756 kb
Host smart-b5c3618f-513e-4205-b2f5-2e8398f58d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745605384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2745605384
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.2228604344
Short name T244
Test name
Test status
Simulation time 86976157821 ps
CPU time 124.31 seconds
Started Aug 11 04:28:31 PM PDT 24
Finished Aug 11 04:30:36 PM PDT 24
Peak memory 199764 kb
Host smart-e6c92eb1-e903-43da-8ff5-f567a8e270e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228604344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2228604344
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2033524372
Short name T350
Test name
Test status
Simulation time 174244521393 ps
CPU time 31 seconds
Started Aug 11 04:28:31 PM PDT 24
Finished Aug 11 04:29:02 PM PDT 24
Peak memory 199728 kb
Host smart-b120a00e-7f25-4bde-a2b6-2b0566006673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033524372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2033524372
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.4273836920
Short name T188
Test name
Test status
Simulation time 139191234014 ps
CPU time 55.21 seconds
Started Aug 11 04:28:37 PM PDT 24
Finished Aug 11 04:29:32 PM PDT 24
Peak memory 199748 kb
Host smart-8f301f9a-26d3-4780-ba61-518928086125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273836920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.4273836920
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.206699427
Short name T965
Test name
Test status
Simulation time 26844169 ps
CPU time 0.52 seconds
Started Aug 11 04:26:54 PM PDT 24
Finished Aug 11 04:26:55 PM PDT 24
Peak memory 195112 kb
Host smart-d397abaf-e339-4b8c-8985-77f63ad523d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206699427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.206699427
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1310204521
Short name T154
Test name
Test status
Simulation time 98833399183 ps
CPU time 40.45 seconds
Started Aug 11 04:26:50 PM PDT 24
Finished Aug 11 04:27:30 PM PDT 24
Peak memory 199776 kb
Host smart-41b3be79-1dc9-4802-8005-a3dcabc93a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310204521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1310204521
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.226502028
Short name T179
Test name
Test status
Simulation time 69665144522 ps
CPU time 27.63 seconds
Started Aug 11 04:26:48 PM PDT 24
Finished Aug 11 04:27:16 PM PDT 24
Peak memory 199728 kb
Host smart-99ee99df-a308-4068-ae94-1ff475afdc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226502028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.226502028
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3045699421
Short name T921
Test name
Test status
Simulation time 74392544635 ps
CPU time 91.32 seconds
Started Aug 11 04:26:57 PM PDT 24
Finished Aug 11 04:28:28 PM PDT 24
Peak memory 199712 kb
Host smart-f67804a3-3ff0-4be2-aa26-8765e90e4413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045699421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3045699421
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.3037492563
Short name T110
Test name
Test status
Simulation time 70733549057 ps
CPU time 493.89 seconds
Started Aug 11 04:26:58 PM PDT 24
Finished Aug 11 04:35:12 PM PDT 24
Peak memory 200080 kb
Host smart-108959a7-f076-4ca2-9b36-6a8d49e4c561
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3037492563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3037492563
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1845675640
Short name T568
Test name
Test status
Simulation time 10086698537 ps
CPU time 10.48 seconds
Started Aug 11 04:26:59 PM PDT 24
Finished Aug 11 04:27:09 PM PDT 24
Peak memory 199700 kb
Host smart-ad98f09d-7e9e-4e27-adc1-a9bbbd921465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845675640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1845675640
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.399612402
Short name T838
Test name
Test status
Simulation time 95102404539 ps
CPU time 38.14 seconds
Started Aug 11 04:26:58 PM PDT 24
Finished Aug 11 04:27:36 PM PDT 24
Peak memory 198036 kb
Host smart-e20fd372-6007-4ad0-87f0-ed057c4b782d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399612402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.399612402
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.977177003
Short name T559
Test name
Test status
Simulation time 17085036813 ps
CPU time 728.43 seconds
Started Aug 11 04:26:52 PM PDT 24
Finished Aug 11 04:39:00 PM PDT 24
Peak memory 199640 kb
Host smart-4c0c39cd-c3af-4edf-b292-d2c3f17ba375
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=977177003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.977177003
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.669164565
Short name T872
Test name
Test status
Simulation time 1581725199 ps
CPU time 2.23 seconds
Started Aug 11 04:26:56 PM PDT 24
Finished Aug 11 04:26:58 PM PDT 24
Peak memory 197784 kb
Host smart-c6c72288-627c-48db-82eb-a745186203c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=669164565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.669164565
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2843835409
Short name T704
Test name
Test status
Simulation time 3237037261 ps
CPU time 1.82 seconds
Started Aug 11 04:27:02 PM PDT 24
Finished Aug 11 04:27:04 PM PDT 24
Peak memory 195840 kb
Host smart-d2a1f1a1-2d23-41f3-b366-0e7496c65e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843835409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2843835409
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1843254247
Short name T382
Test name
Test status
Simulation time 709194358 ps
CPU time 1.78 seconds
Started Aug 11 04:27:43 PM PDT 24
Finished Aug 11 04:27:45 PM PDT 24
Peak memory 197980 kb
Host smart-6f98c52e-eb09-4fc9-9742-160cfc0f46e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843254247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1843254247
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.622594446
Short name T1065
Test name
Test status
Simulation time 157892951041 ps
CPU time 1432.68 seconds
Started Aug 11 04:27:34 PM PDT 24
Finished Aug 11 04:51:27 PM PDT 24
Peak memory 216228 kb
Host smart-f395486e-a40f-4ebf-9b65-0cbd79f833cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622594446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.622594446
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3940166135
Short name T32
Test name
Test status
Simulation time 15323341294 ps
CPU time 140.63 seconds
Started Aug 11 04:26:56 PM PDT 24
Finished Aug 11 04:29:17 PM PDT 24
Peak memory 215376 kb
Host smart-398efee1-26e0-4a37-b640-39e0c491f7dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940166135 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3940166135
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.465001042
Short name T1131
Test name
Test status
Simulation time 2418312693 ps
CPU time 2.22 seconds
Started Aug 11 04:26:57 PM PDT 24
Finished Aug 11 04:27:00 PM PDT 24
Peak memory 198548 kb
Host smart-c1728963-2e93-47ba-a8cd-5257acbb8a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465001042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.465001042
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.4051492344
Short name T581
Test name
Test status
Simulation time 77765751639 ps
CPU time 131.45 seconds
Started Aug 11 04:27:29 PM PDT 24
Finished Aug 11 04:29:41 PM PDT 24
Peak memory 199732 kb
Host smart-2b1b98a2-15ad-4051-89cf-43de8ea6bd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051492344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.4051492344
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2561704574
Short name T325
Test name
Test status
Simulation time 47484748412 ps
CPU time 17.47 seconds
Started Aug 11 04:28:29 PM PDT 24
Finished Aug 11 04:28:46 PM PDT 24
Peak memory 199680 kb
Host smart-c0697869-613c-40ab-ad70-e2f2656f7534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561704574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2561704574
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3599870888
Short name T1157
Test name
Test status
Simulation time 97154962769 ps
CPU time 126.71 seconds
Started Aug 11 04:28:28 PM PDT 24
Finished Aug 11 04:30:35 PM PDT 24
Peak memory 199676 kb
Host smart-1f8c57a4-932d-45e5-afef-262a88bace7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599870888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3599870888
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.266868682
Short name T858
Test name
Test status
Simulation time 23598287663 ps
CPU time 11.13 seconds
Started Aug 11 04:28:31 PM PDT 24
Finished Aug 11 04:28:42 PM PDT 24
Peak memory 199816 kb
Host smart-b6174da8-a5c9-426d-8f8c-0705b8cfbd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266868682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.266868682
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1665331393
Short name T1053
Test name
Test status
Simulation time 23133041231 ps
CPU time 17.84 seconds
Started Aug 11 04:28:40 PM PDT 24
Finished Aug 11 04:28:58 PM PDT 24
Peak memory 199216 kb
Host smart-ff938486-d633-418f-b120-3aaa6b40b893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665331393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1665331393
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3910062080
Short name T348
Test name
Test status
Simulation time 106337284587 ps
CPU time 68.38 seconds
Started Aug 11 04:28:27 PM PDT 24
Finished Aug 11 04:29:36 PM PDT 24
Peak memory 199700 kb
Host smart-b64384e4-164e-4d05-a1f4-58349ee66172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910062080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3910062080
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.2352117292
Short name T416
Test name
Test status
Simulation time 164698251302 ps
CPU time 124.16 seconds
Started Aug 11 04:28:26 PM PDT 24
Finished Aug 11 04:30:30 PM PDT 24
Peak memory 199692 kb
Host smart-bdf57e18-075b-4a06-ae7f-7da67646c777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352117292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2352117292
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1959761573
Short name T1000
Test name
Test status
Simulation time 92440812576 ps
CPU time 131.44 seconds
Started Aug 11 04:28:36 PM PDT 24
Finished Aug 11 04:30:48 PM PDT 24
Peak memory 199716 kb
Host smart-970cd135-c6b5-4f61-8ff2-e0cce844765a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959761573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1959761573
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3462643519
Short name T1084
Test name
Test status
Simulation time 35427099868 ps
CPU time 53.11 seconds
Started Aug 11 04:28:30 PM PDT 24
Finished Aug 11 04:29:24 PM PDT 24
Peak memory 199672 kb
Host smart-9b80f029-ce2c-447a-8ac6-85023dd43a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462643519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3462643519
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.573265609
Short name T528
Test name
Test status
Simulation time 42244217677 ps
CPU time 37.83 seconds
Started Aug 11 04:28:35 PM PDT 24
Finished Aug 11 04:29:13 PM PDT 24
Peak memory 199772 kb
Host smart-d2ea1eaa-77c2-4aad-881b-806f8186be21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573265609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.573265609
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2675219052
Short name T334
Test name
Test status
Simulation time 21755702199 ps
CPU time 36.54 seconds
Started Aug 11 04:28:36 PM PDT 24
Finished Aug 11 04:29:12 PM PDT 24
Peak memory 199724 kb
Host smart-4ff80d8b-6838-435a-a933-a289550ab019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675219052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2675219052
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.880359311
Short name T563
Test name
Test status
Simulation time 43823591 ps
CPU time 0.53 seconds
Started Aug 11 04:26:54 PM PDT 24
Finished Aug 11 04:26:54 PM PDT 24
Peak memory 195132 kb
Host smart-aebc41f4-0ba6-4d54-a3a1-3c9dd52d1bbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880359311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.880359311
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.181701306
Short name T898
Test name
Test status
Simulation time 209847180026 ps
CPU time 105.83 seconds
Started Aug 11 04:27:22 PM PDT 24
Finished Aug 11 04:29:08 PM PDT 24
Peak memory 199656 kb
Host smart-a9c9e8ca-d8a6-4c90-9bc1-8971cbb09b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181701306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.181701306
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.1348254919
Short name T535
Test name
Test status
Simulation time 108673548914 ps
CPU time 126.57 seconds
Started Aug 11 04:27:05 PM PDT 24
Finished Aug 11 04:29:12 PM PDT 24
Peak memory 199560 kb
Host smart-3141c07e-3ac9-4520-9cdb-e32763732c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348254919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1348254919
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2361295109
Short name T105
Test name
Test status
Simulation time 9849900056 ps
CPU time 15.75 seconds
Started Aug 11 04:27:35 PM PDT 24
Finished Aug 11 04:27:51 PM PDT 24
Peak memory 199660 kb
Host smart-99eee0c4-0ccf-4db3-b593-618ac4e02f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361295109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2361295109
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3752180501
Short name T131
Test name
Test status
Simulation time 39160131970 ps
CPU time 17.13 seconds
Started Aug 11 04:26:57 PM PDT 24
Finished Aug 11 04:27:14 PM PDT 24
Peak memory 199596 kb
Host smart-f0e300d8-2d97-434c-b48f-8fa1b385ed58
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752180501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3752180501
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.2611818815
Short name T326
Test name
Test status
Simulation time 155815816423 ps
CPU time 495.5 seconds
Started Aug 11 04:26:54 PM PDT 24
Finished Aug 11 04:35:10 PM PDT 24
Peak memory 199708 kb
Host smart-82344c6e-bf41-4b7e-8511-9da59c1a0f59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2611818815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.2611818815
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3811852152
Short name T514
Test name
Test status
Simulation time 13731970119 ps
CPU time 27.39 seconds
Started Aug 11 04:26:58 PM PDT 24
Finished Aug 11 04:27:25 PM PDT 24
Peak memory 199628 kb
Host smart-963ada99-3207-4eb6-b06a-f6ccb71987b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811852152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3811852152
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2440397293
Short name T1008
Test name
Test status
Simulation time 48053188994 ps
CPU time 43.55 seconds
Started Aug 11 04:26:55 PM PDT 24
Finished Aug 11 04:27:39 PM PDT 24
Peak memory 199864 kb
Host smart-4290e61c-a64c-4301-9100-d2150bc53c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440397293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2440397293
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3025477780
Short name T1165
Test name
Test status
Simulation time 4730579463 ps
CPU time 275.43 seconds
Started Aug 11 04:26:57 PM PDT 24
Finished Aug 11 04:31:33 PM PDT 24
Peak memory 199688 kb
Host smart-d78faaf7-5f5b-42fa-95f2-5bd193d17577
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3025477780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3025477780
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1859196760
Short name T42
Test name
Test status
Simulation time 5855955180 ps
CPU time 10.27 seconds
Started Aug 11 04:27:06 PM PDT 24
Finished Aug 11 04:27:17 PM PDT 24
Peak memory 197904 kb
Host smart-ae4c02e1-f8da-466d-8ffd-11e5f190820f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1859196760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1859196760
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.4268897052
Short name T475
Test name
Test status
Simulation time 60424219416 ps
CPU time 26.47 seconds
Started Aug 11 04:27:09 PM PDT 24
Finished Aug 11 04:27:35 PM PDT 24
Peak memory 199748 kb
Host smart-146f56fd-3c59-45a8-99cd-b2b203a9d4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268897052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.4268897052
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.265169862
Short name T454
Test name
Test status
Simulation time 1772859141 ps
CPU time 1.23 seconds
Started Aug 11 04:26:48 PM PDT 24
Finished Aug 11 04:26:49 PM PDT 24
Peak memory 195352 kb
Host smart-bb1f60f7-e27f-4a0c-a767-c3817cf12d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265169862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.265169862
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3600422976
Short name T301
Test name
Test status
Simulation time 6042855225 ps
CPU time 25.87 seconds
Started Aug 11 04:27:24 PM PDT 24
Finished Aug 11 04:27:50 PM PDT 24
Peak memory 199028 kb
Host smart-299353e3-ccf1-4c01-9b76-3e6fd7bad24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600422976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3600422976
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.4086407482
Short name T996
Test name
Test status
Simulation time 67092678538 ps
CPU time 569.17 seconds
Started Aug 11 04:26:59 PM PDT 24
Finished Aug 11 04:36:29 PM PDT 24
Peak memory 224476 kb
Host smart-4fff74b3-2d89-4e27-99ff-fbe0d212917c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086407482 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.4086407482
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3859627068
Short name T992
Test name
Test status
Simulation time 1196394742 ps
CPU time 3.64 seconds
Started Aug 11 04:26:51 PM PDT 24
Finished Aug 11 04:26:55 PM PDT 24
Peak memory 198280 kb
Host smart-4c01dbf5-b93c-435c-a500-8af3808ff6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859627068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3859627068
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.573756045
Short name T558
Test name
Test status
Simulation time 28922627990 ps
CPU time 59.65 seconds
Started Aug 11 04:26:50 PM PDT 24
Finished Aug 11 04:27:50 PM PDT 24
Peak memory 199728 kb
Host smart-fafb75ce-123b-452a-b619-5317bc09a977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573756045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.573756045
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.96405568
Short name T828
Test name
Test status
Simulation time 102582268020 ps
CPU time 200.56 seconds
Started Aug 11 04:28:31 PM PDT 24
Finished Aug 11 04:31:51 PM PDT 24
Peak memory 199732 kb
Host smart-f9449d9f-ae57-48d0-b121-cc9d3d1d86ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96405568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.96405568
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.4129440794
Short name T194
Test name
Test status
Simulation time 42024002921 ps
CPU time 110.14 seconds
Started Aug 11 04:28:47 PM PDT 24
Finished Aug 11 04:30:38 PM PDT 24
Peak memory 199808 kb
Host smart-9add0305-d93d-4d23-a85c-d3115372e1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129440794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.4129440794
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.910220892
Short name T812
Test name
Test status
Simulation time 20456719518 ps
CPU time 38.48 seconds
Started Aug 11 04:28:37 PM PDT 24
Finished Aug 11 04:29:16 PM PDT 24
Peak memory 199704 kb
Host smart-2cf47226-aa0e-4331-9315-210bd0d949ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910220892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.910220892
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.195091975
Short name T1075
Test name
Test status
Simulation time 129572839593 ps
CPU time 230.29 seconds
Started Aug 11 04:28:38 PM PDT 24
Finished Aug 11 04:32:28 PM PDT 24
Peak memory 199600 kb
Host smart-b1422fda-fb02-465c-a624-97c43ff8387f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195091975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.195091975
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.3708614944
Short name T1077
Test name
Test status
Simulation time 129946637968 ps
CPU time 47.82 seconds
Started Aug 11 04:28:52 PM PDT 24
Finished Aug 11 04:29:40 PM PDT 24
Peak memory 199764 kb
Host smart-73d397d3-6aeb-41d3-9f4a-5c6992d173a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708614944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3708614944
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.658789083
Short name T238
Test name
Test status
Simulation time 19846564163 ps
CPU time 30.37 seconds
Started Aug 11 04:28:43 PM PDT 24
Finished Aug 11 04:29:13 PM PDT 24
Peak memory 199768 kb
Host smart-23243e7f-16d2-4dfa-afda-0286cf1389c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658789083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.658789083
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2664914558
Short name T204
Test name
Test status
Simulation time 114942130712 ps
CPU time 57.35 seconds
Started Aug 11 04:28:40 PM PDT 24
Finished Aug 11 04:29:38 PM PDT 24
Peak memory 199788 kb
Host smart-9c33ceba-0558-4d4c-a7f3-289bf8544627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664914558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2664914558
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1914913679
Short name T694
Test name
Test status
Simulation time 123347616858 ps
CPU time 354.64 seconds
Started Aug 11 04:28:52 PM PDT 24
Finished Aug 11 04:34:47 PM PDT 24
Peak memory 199764 kb
Host smart-04c7b427-225e-49e6-9031-9fef3829b983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914913679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1914913679
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1952869407
Short name T697
Test name
Test status
Simulation time 49964469 ps
CPU time 0.58 seconds
Started Aug 11 04:26:53 PM PDT 24
Finished Aug 11 04:26:54 PM PDT 24
Peak memory 195368 kb
Host smart-e5dc59cd-4fa6-4118-b69f-ecf29ea0e4a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952869407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1952869407
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.3881743604
Short name T1016
Test name
Test status
Simulation time 76239066412 ps
CPU time 68.14 seconds
Started Aug 11 04:26:51 PM PDT 24
Finished Aug 11 04:27:59 PM PDT 24
Peak memory 199644 kb
Host smart-ded354b9-00f3-450c-b269-8c38537cd6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881743604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3881743604
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2718826961
Short name T753
Test name
Test status
Simulation time 79655236972 ps
CPU time 194.7 seconds
Started Aug 11 04:27:07 PM PDT 24
Finished Aug 11 04:30:22 PM PDT 24
Peak memory 199512 kb
Host smart-233c77c0-9114-460d-807d-5c06b57d9459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718826961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2718826961
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3306150159
Short name T178
Test name
Test status
Simulation time 24976794806 ps
CPU time 11.59 seconds
Started Aug 11 04:26:52 PM PDT 24
Finished Aug 11 04:27:04 PM PDT 24
Peak memory 199688 kb
Host smart-545ae55b-367d-4638-9b6d-e5a9eb96c14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306150159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3306150159
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.2111884773
Short name T1089
Test name
Test status
Simulation time 267833925171 ps
CPU time 330.37 seconds
Started Aug 11 04:27:09 PM PDT 24
Finished Aug 11 04:32:40 PM PDT 24
Peak memory 198816 kb
Host smart-3695fa20-aa48-4828-b072-b0e3044f74a1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111884773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2111884773
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.3616532052
Short name T628
Test name
Test status
Simulation time 109606441986 ps
CPU time 239.15 seconds
Started Aug 11 04:26:56 PM PDT 24
Finished Aug 11 04:30:55 PM PDT 24
Peak memory 199652 kb
Host smart-5ac55887-9e85-41e4-8f6f-aab9f40821d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3616532052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3616532052
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.3690216912
Short name T642
Test name
Test status
Simulation time 4498131942 ps
CPU time 3.07 seconds
Started Aug 11 04:27:13 PM PDT 24
Finished Aug 11 04:27:16 PM PDT 24
Peak memory 197896 kb
Host smart-c9dd2ec8-2122-4522-810a-53f11a389465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690216912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.3690216912
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.254179196
Short name T396
Test name
Test status
Simulation time 73914524515 ps
CPU time 58.9 seconds
Started Aug 11 04:26:55 PM PDT 24
Finished Aug 11 04:27:54 PM PDT 24
Peak memory 198536 kb
Host smart-cc369116-0d7d-4a4d-a73e-7d7f2499e2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254179196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.254179196
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.2795999175
Short name T895
Test name
Test status
Simulation time 8221317121 ps
CPU time 218.6 seconds
Started Aug 11 04:26:54 PM PDT 24
Finished Aug 11 04:30:33 PM PDT 24
Peak memory 199704 kb
Host smart-e76d763d-d194-444e-87f5-9d56f5cb7515
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2795999175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2795999175
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.3050504470
Short name T359
Test name
Test status
Simulation time 7138645344 ps
CPU time 16.36 seconds
Started Aug 11 04:27:25 PM PDT 24
Finished Aug 11 04:27:41 PM PDT 24
Peak memory 197948 kb
Host smart-608c3d89-c7df-4dc9-a666-0e3e54153b21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3050504470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3050504470
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.4291312624
Short name T969
Test name
Test status
Simulation time 32397499012 ps
CPU time 56.94 seconds
Started Aug 11 04:27:10 PM PDT 24
Finished Aug 11 04:28:07 PM PDT 24
Peak memory 199748 kb
Host smart-4772d5ae-8f5a-4ab2-af29-506823ca672c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291312624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.4291312624
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.490481677
Short name T1127
Test name
Test status
Simulation time 666328874 ps
CPU time 0.89 seconds
Started Aug 11 04:27:07 PM PDT 24
Finished Aug 11 04:27:08 PM PDT 24
Peak memory 195224 kb
Host smart-222e2a95-519d-4ad7-af07-fa408063239f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490481677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.490481677
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.791693615
Short name T1067
Test name
Test status
Simulation time 5758373938 ps
CPU time 9.54 seconds
Started Aug 11 04:27:02 PM PDT 24
Finished Aug 11 04:27:12 PM PDT 24
Peak memory 199604 kb
Host smart-09dd78c4-df80-4b43-858d-e3b540e6aab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791693615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.791693615
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.985986984
Short name T873
Test name
Test status
Simulation time 1223994455 ps
CPU time 1.53 seconds
Started Aug 11 04:26:53 PM PDT 24
Finished Aug 11 04:26:54 PM PDT 24
Peak memory 198380 kb
Host smart-7510f750-2cd2-4175-97a5-af5e033fe1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985986984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.985986984
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.257611318
Short name T596
Test name
Test status
Simulation time 46936043672 ps
CPU time 21.94 seconds
Started Aug 11 04:26:55 PM PDT 24
Finished Aug 11 04:27:18 PM PDT 24
Peak memory 199788 kb
Host smart-5c157239-cf92-4e94-afee-f488417e2ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257611318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.257611318
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2583167435
Short name T973
Test name
Test status
Simulation time 57917296829 ps
CPU time 41.22 seconds
Started Aug 11 04:28:34 PM PDT 24
Finished Aug 11 04:29:15 PM PDT 24
Peak memory 199796 kb
Host smart-80108465-39a6-40b0-8471-1f2790bf990d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583167435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2583167435
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2055151975
Short name T834
Test name
Test status
Simulation time 130948930275 ps
CPU time 95.1 seconds
Started Aug 11 04:28:41 PM PDT 24
Finished Aug 11 04:30:16 PM PDT 24
Peak memory 199768 kb
Host smart-b59bf930-d9a9-40ac-a07a-239fa1701819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055151975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2055151975
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.3346723679
Short name T951
Test name
Test status
Simulation time 49521123452 ps
CPU time 98.58 seconds
Started Aug 11 04:28:46 PM PDT 24
Finished Aug 11 04:30:25 PM PDT 24
Peak memory 199788 kb
Host smart-db658024-cfaf-45e0-8afa-5334b4bb868d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346723679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3346723679
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.229402008
Short name T240
Test name
Test status
Simulation time 95280246769 ps
CPU time 49.25 seconds
Started Aug 11 04:28:54 PM PDT 24
Finished Aug 11 04:29:44 PM PDT 24
Peak memory 199812 kb
Host smart-606f75e0-ab40-47bf-b52c-bca44307ec8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229402008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.229402008
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3075157815
Short name T825
Test name
Test status
Simulation time 49657428732 ps
CPU time 71.43 seconds
Started Aug 11 04:28:38 PM PDT 24
Finished Aug 11 04:29:50 PM PDT 24
Peak memory 199436 kb
Host smart-78a33f80-cacc-4db7-9268-a67b1e11204a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075157815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3075157815
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2826490973
Short name T978
Test name
Test status
Simulation time 53957137041 ps
CPU time 25.82 seconds
Started Aug 11 04:28:50 PM PDT 24
Finished Aug 11 04:29:16 PM PDT 24
Peak memory 199788 kb
Host smart-379d8a11-fdb6-4eda-9d54-7fae6096c197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826490973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2826490973
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1852126355
Short name T363
Test name
Test status
Simulation time 40373088 ps
CPU time 0.56 seconds
Started Aug 11 04:26:47 PM PDT 24
Finished Aug 11 04:26:48 PM PDT 24
Peak memory 195132 kb
Host smart-49e78caa-1569-415c-ae89-3a007509e682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852126355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1852126355
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.2512719591
Short name T1094
Test name
Test status
Simulation time 65917578741 ps
CPU time 28.97 seconds
Started Aug 11 04:27:05 PM PDT 24
Finished Aug 11 04:27:34 PM PDT 24
Peak memory 199712 kb
Host smart-50bacb3a-3fe1-4e5b-bd21-06ef3282f9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512719591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.2512719591
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.2596956797
Short name T891
Test name
Test status
Simulation time 31071170801 ps
CPU time 13.07 seconds
Started Aug 11 04:27:06 PM PDT 24
Finished Aug 11 04:27:19 PM PDT 24
Peak memory 199800 kb
Host smart-a4782308-be92-4e57-bca0-638dd9f3db4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596956797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2596956797
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3704535269
Short name T221
Test name
Test status
Simulation time 76203099863 ps
CPU time 62.03 seconds
Started Aug 11 04:26:53 PM PDT 24
Finished Aug 11 04:27:55 PM PDT 24
Peak memory 199720 kb
Host smart-a0ff5037-2f2d-43c9-888b-14618ea6142c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704535269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3704535269
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1557517104
Short name T579
Test name
Test status
Simulation time 41298712535 ps
CPU time 46.36 seconds
Started Aug 11 04:26:57 PM PDT 24
Finished Aug 11 04:27:44 PM PDT 24
Peak memory 199824 kb
Host smart-b14c5c73-e80a-4cc6-85e6-b1d2413ca6d5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557517104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1557517104
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1287228715
Short name T717
Test name
Test status
Simulation time 89173729616 ps
CPU time 504.26 seconds
Started Aug 11 04:26:56 PM PDT 24
Finished Aug 11 04:35:21 PM PDT 24
Peak memory 199744 kb
Host smart-6f0a3abb-725d-4b53-9190-ef3ed8f9c2b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1287228715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1287228715
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.2439714883
Short name T699
Test name
Test status
Simulation time 8914741519 ps
CPU time 9.37 seconds
Started Aug 11 04:26:57 PM PDT 24
Finished Aug 11 04:27:07 PM PDT 24
Peak memory 199056 kb
Host smart-29489722-b6ea-432f-a438-eb6456248195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439714883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2439714883
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.4284959176
Short name T985
Test name
Test status
Simulation time 183439100031 ps
CPU time 53.2 seconds
Started Aug 11 04:26:51 PM PDT 24
Finished Aug 11 04:27:45 PM PDT 24
Peak memory 208164 kb
Host smart-4c281473-88eb-4b2d-950b-2e6d2e00bac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284959176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.4284959176
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.217950281
Short name T702
Test name
Test status
Simulation time 11508719944 ps
CPU time 102.17 seconds
Started Aug 11 04:26:54 PM PDT 24
Finished Aug 11 04:28:36 PM PDT 24
Peak memory 199700 kb
Host smart-c41c383a-e705-4312-8d3a-ec1dca6ba5f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=217950281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.217950281
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.4249055274
Short name T466
Test name
Test status
Simulation time 1690696421 ps
CPU time 6.19 seconds
Started Aug 11 04:27:06 PM PDT 24
Finished Aug 11 04:27:12 PM PDT 24
Peak memory 197876 kb
Host smart-082d6d86-1082-44d3-91e4-f3d2f711b288
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4249055274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.4249055274
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3030641788
Short name T613
Test name
Test status
Simulation time 153979066915 ps
CPU time 56.41 seconds
Started Aug 11 04:26:51 PM PDT 24
Finished Aug 11 04:27:48 PM PDT 24
Peak memory 199824 kb
Host smart-a8e7cd94-592f-467e-ae0c-df5b6c8b38e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030641788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3030641788
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.3548176344
Short name T776
Test name
Test status
Simulation time 4090815682 ps
CPU time 1.7 seconds
Started Aug 11 04:27:06 PM PDT 24
Finished Aug 11 04:27:08 PM PDT 24
Peak memory 196292 kb
Host smart-89542986-e490-49fb-b3a8-d0b8476af511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548176344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3548176344
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.312345047
Short name T763
Test name
Test status
Simulation time 5630098831 ps
CPU time 11.67 seconds
Started Aug 11 04:27:00 PM PDT 24
Finished Aug 11 04:27:12 PM PDT 24
Peak memory 199720 kb
Host smart-5ef46941-6e85-4d50-affa-16acdd3b1652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312345047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.312345047
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.2757244596
Short name T1122
Test name
Test status
Simulation time 178404747387 ps
CPU time 351.23 seconds
Started Aug 11 04:26:57 PM PDT 24
Finished Aug 11 04:32:49 PM PDT 24
Peak memory 199700 kb
Host smart-ef5337f3-f075-4bfb-a2ab-22911bb7a744
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757244596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2757244596
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.790534842
Short name T463
Test name
Test status
Simulation time 152225537057 ps
CPU time 872.69 seconds
Started Aug 11 04:26:58 PM PDT 24
Finished Aug 11 04:41:31 PM PDT 24
Peak memory 224700 kb
Host smart-104f078c-9c58-429b-8ebe-26bef2aac881
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790534842 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.790534842
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3145402608
Short name T1148
Test name
Test status
Simulation time 1557034428 ps
CPU time 1.58 seconds
Started Aug 11 04:27:27 PM PDT 24
Finished Aug 11 04:27:29 PM PDT 24
Peak memory 198160 kb
Host smart-56e1e81e-7439-4c4b-86b9-7e2abc13e64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145402608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3145402608
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2615083987
Short name T754
Test name
Test status
Simulation time 91891047388 ps
CPU time 165.57 seconds
Started Aug 11 04:26:56 PM PDT 24
Finished Aug 11 04:29:42 PM PDT 24
Peak memory 199088 kb
Host smart-e716d2f0-fc20-4f30-8197-a9594f08eebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615083987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2615083987
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2701798041
Short name T126
Test name
Test status
Simulation time 34696521783 ps
CPU time 52.53 seconds
Started Aug 11 04:28:40 PM PDT 24
Finished Aug 11 04:29:33 PM PDT 24
Peak memory 199644 kb
Host smart-3a46b470-351d-4328-9e11-091fd97d1e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701798041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2701798041
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1772254122
Short name T120
Test name
Test status
Simulation time 70874913990 ps
CPU time 110.79 seconds
Started Aug 11 04:28:34 PM PDT 24
Finished Aug 11 04:30:25 PM PDT 24
Peak memory 198700 kb
Host smart-da458e46-9e69-47f8-abd5-a24224d16e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772254122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1772254122
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2161909891
Short name T939
Test name
Test status
Simulation time 34371849740 ps
CPU time 39.67 seconds
Started Aug 11 04:28:46 PM PDT 24
Finished Aug 11 04:29:26 PM PDT 24
Peak memory 199292 kb
Host smart-5575413b-a693-4c83-8415-d4da40966134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161909891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2161909891
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.1860839777
Short name T631
Test name
Test status
Simulation time 132108031834 ps
CPU time 31.57 seconds
Started Aug 11 04:28:41 PM PDT 24
Finished Aug 11 04:29:13 PM PDT 24
Peak memory 199736 kb
Host smart-7d0cffba-dbcb-4f1b-892a-4b8da571d1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860839777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1860839777
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1889592451
Short name T960
Test name
Test status
Simulation time 28903175100 ps
CPU time 31.29 seconds
Started Aug 11 04:28:37 PM PDT 24
Finished Aug 11 04:29:08 PM PDT 24
Peak memory 199760 kb
Host smart-329b1cb5-5732-4c2e-85cc-673b2edfef89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889592451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1889592451
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3746405202
Short name T1175
Test name
Test status
Simulation time 60345230327 ps
CPU time 130.2 seconds
Started Aug 11 04:28:42 PM PDT 24
Finished Aug 11 04:30:53 PM PDT 24
Peak memory 199816 kb
Host smart-924fb5a1-838f-454c-ac2d-c1345dc77d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746405202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3746405202
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3694364506
Short name T616
Test name
Test status
Simulation time 14262457 ps
CPU time 0.54 seconds
Started Aug 11 04:27:13 PM PDT 24
Finished Aug 11 04:27:14 PM PDT 24
Peak memory 195136 kb
Host smart-1690e404-3fe2-4f0c-a462-e9b6d6170623
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694364506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3694364506
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3128042194
Short name T570
Test name
Test status
Simulation time 99187283303 ps
CPU time 57.91 seconds
Started Aug 11 04:27:05 PM PDT 24
Finished Aug 11 04:28:04 PM PDT 24
Peak memory 199796 kb
Host smart-3bac14dd-8b58-443f-9ade-5df0df48d370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128042194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3128042194
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.200403418
Short name T316
Test name
Test status
Simulation time 104831726897 ps
CPU time 98.61 seconds
Started Aug 11 04:27:02 PM PDT 24
Finished Aug 11 04:28:41 PM PDT 24
Peak memory 199776 kb
Host smart-e4d3fee9-f0d2-471b-8f71-fbf91ace2930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200403418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.200403418
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.2157751061
Short name T691
Test name
Test status
Simulation time 63226332735 ps
CPU time 17.25 seconds
Started Aug 11 04:26:50 PM PDT 24
Finished Aug 11 04:27:08 PM PDT 24
Peak memory 199764 kb
Host smart-9bccbd1b-8a6a-4a61-9cf1-37abf9504c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157751061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2157751061
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.4289877632
Short name T129
Test name
Test status
Simulation time 35920609848 ps
CPU time 32.59 seconds
Started Aug 11 04:27:12 PM PDT 24
Finished Aug 11 04:27:45 PM PDT 24
Peak memory 199612 kb
Host smart-9df25fff-42c5-457a-acda-31c8d09b3e2f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289877632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.4289877632
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.289106920
Short name T530
Test name
Test status
Simulation time 93692908102 ps
CPU time 362.83 seconds
Started Aug 11 04:27:05 PM PDT 24
Finished Aug 11 04:33:08 PM PDT 24
Peak memory 199728 kb
Host smart-a983f9ab-42ce-44d8-9c2f-d857b9de7202
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=289106920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.289106920
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1236631426
Short name T22
Test name
Test status
Simulation time 758221243 ps
CPU time 1.12 seconds
Started Aug 11 04:26:54 PM PDT 24
Finished Aug 11 04:26:55 PM PDT 24
Peak memory 197460 kb
Host smart-245b0ab7-be45-4c48-9097-c233b2aa9fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236631426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1236631426
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.1263050921
Short name T629
Test name
Test status
Simulation time 16142590992 ps
CPU time 30.48 seconds
Started Aug 11 04:27:04 PM PDT 24
Finished Aug 11 04:27:35 PM PDT 24
Peak memory 198908 kb
Host smart-6f696dee-65f6-4b98-b7a4-03c62c913f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263050921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.1263050921
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2782035836
Short name T936
Test name
Test status
Simulation time 16071465002 ps
CPU time 292.05 seconds
Started Aug 11 04:27:06 PM PDT 24
Finished Aug 11 04:31:58 PM PDT 24
Peak memory 199692 kb
Host smart-eda9bdf1-6cc8-4cbf-b248-b2346be46514
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2782035836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2782035836
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.3171593181
Short name T121
Test name
Test status
Simulation time 7318708004 ps
CPU time 17.18 seconds
Started Aug 11 04:26:57 PM PDT 24
Finished Aug 11 04:27:14 PM PDT 24
Peak memory 197876 kb
Host smart-0c0a1c63-e712-4407-a54d-4a4a744345b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3171593181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3171593181
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1724417283
Short name T715
Test name
Test status
Simulation time 13431566203 ps
CPU time 20.22 seconds
Started Aug 11 04:26:51 PM PDT 24
Finished Aug 11 04:27:12 PM PDT 24
Peak memory 199720 kb
Host smart-d43816fa-4ad3-4015-bfdd-0567eda2e650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724417283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1724417283
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1002606006
Short name T1015
Test name
Test status
Simulation time 3514959856 ps
CPU time 2.95 seconds
Started Aug 11 04:27:31 PM PDT 24
Finished Aug 11 04:27:34 PM PDT 24
Peak memory 196116 kb
Host smart-f0ba11e9-f3b9-457a-899a-3578b6860763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002606006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1002606006
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.2877740326
Short name T370
Test name
Test status
Simulation time 735663184 ps
CPU time 3.86 seconds
Started Aug 11 04:26:55 PM PDT 24
Finished Aug 11 04:26:59 PM PDT 24
Peak memory 199336 kb
Host smart-2b9e9fe8-3f9e-4498-9862-f43fc637525b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877740326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2877740326
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1698940401
Short name T826
Test name
Test status
Simulation time 510859298540 ps
CPU time 145.08 seconds
Started Aug 11 04:27:00 PM PDT 24
Finished Aug 11 04:29:25 PM PDT 24
Peak memory 208040 kb
Host smart-fef739c4-8ba1-4503-9726-2866dc8b2491
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698940401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1698940401
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1332630011
Short name T575
Test name
Test status
Simulation time 139280311581 ps
CPU time 698.57 seconds
Started Aug 11 04:26:52 PM PDT 24
Finished Aug 11 04:38:30 PM PDT 24
Peak memory 211868 kb
Host smart-b83610a4-ecf0-4671-abac-7514e10ae835
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332630011 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1332630011
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.4049945119
Short name T1091
Test name
Test status
Simulation time 1086142858 ps
CPU time 2.22 seconds
Started Aug 11 04:26:54 PM PDT 24
Finished Aug 11 04:26:56 PM PDT 24
Peak memory 198964 kb
Host smart-bdcdefb9-3ce3-4c05-92e0-8aea52e39b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049945119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.4049945119
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.4031326244
Short name T640
Test name
Test status
Simulation time 245464069625 ps
CPU time 162.54 seconds
Started Aug 11 04:26:58 PM PDT 24
Finished Aug 11 04:29:41 PM PDT 24
Peak memory 199804 kb
Host smart-692d7f54-0344-4c9f-b838-2295dffd3bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031326244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.4031326244
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.911539563
Short name T961
Test name
Test status
Simulation time 202063305518 ps
CPU time 180.04 seconds
Started Aug 11 04:28:46 PM PDT 24
Finished Aug 11 04:31:47 PM PDT 24
Peak memory 199776 kb
Host smart-ab3f1054-c365-4f2d-82a3-87572215ab62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911539563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.911539563
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.2106779606
Short name T864
Test name
Test status
Simulation time 134053186616 ps
CPU time 104.54 seconds
Started Aug 11 04:28:43 PM PDT 24
Finished Aug 11 04:30:27 PM PDT 24
Peak memory 199680 kb
Host smart-bb67784f-1441-4b97-bca7-d614d787f220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106779606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2106779606
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3393873390
Short name T772
Test name
Test status
Simulation time 11014985271 ps
CPU time 24.31 seconds
Started Aug 11 04:28:46 PM PDT 24
Finished Aug 11 04:29:11 PM PDT 24
Peak memory 199728 kb
Host smart-c2a177a5-c968-433a-a644-2d1563a3cc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393873390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3393873390
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1956480590
Short name T231
Test name
Test status
Simulation time 99817795151 ps
CPU time 142.89 seconds
Started Aug 11 04:28:41 PM PDT 24
Finished Aug 11 04:31:04 PM PDT 24
Peak memory 199708 kb
Host smart-aaa272a0-0d89-4717-9ae8-4733b6b0f4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956480590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1956480590
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.2183194112
Short name T1119
Test name
Test status
Simulation time 50977668421 ps
CPU time 73.74 seconds
Started Aug 11 04:28:37 PM PDT 24
Finished Aug 11 04:29:51 PM PDT 24
Peak memory 199776 kb
Host smart-c6a44d9d-cd31-4cd5-8567-711d160e8259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183194112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2183194112
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.2139152089
Short name T192
Test name
Test status
Simulation time 293176280086 ps
CPU time 55.74 seconds
Started Aug 11 04:28:35 PM PDT 24
Finished Aug 11 04:29:31 PM PDT 24
Peak memory 199840 kb
Host smart-5c4eab94-4ef8-4c38-855b-d50a977a0134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139152089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2139152089
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.2137189851
Short name T471
Test name
Test status
Simulation time 23587166120 ps
CPU time 24.48 seconds
Started Aug 11 04:28:36 PM PDT 24
Finished Aug 11 04:29:01 PM PDT 24
Peak memory 199696 kb
Host smart-c73572f6-84ef-42b4-99f2-520e679630db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137189851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2137189851
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.981101592
Short name T644
Test name
Test status
Simulation time 36428463532 ps
CPU time 14.83 seconds
Started Aug 11 04:28:46 PM PDT 24
Finished Aug 11 04:29:01 PM PDT 24
Peak memory 199780 kb
Host smart-96e2c63e-55a8-4ead-8b8e-0c625095f25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981101592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.981101592
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.4025002204
Short name T1095
Test name
Test status
Simulation time 35214579596 ps
CPU time 8.47 seconds
Started Aug 11 04:28:46 PM PDT 24
Finished Aug 11 04:28:55 PM PDT 24
Peak memory 200144 kb
Host smart-5cde1be6-f7f8-47cc-866e-3c55bdd4cfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025002204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.4025002204
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.3453839396
Short name T648
Test name
Test status
Simulation time 22325930551 ps
CPU time 40.81 seconds
Started Aug 11 04:28:50 PM PDT 24
Finished Aug 11 04:29:31 PM PDT 24
Peak memory 199704 kb
Host smart-655b06ad-ea9c-441e-847e-b886dd54a405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453839396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3453839396
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3409767882
Short name T903
Test name
Test status
Simulation time 17278355 ps
CPU time 0.56 seconds
Started Aug 11 04:27:21 PM PDT 24
Finished Aug 11 04:27:21 PM PDT 24
Peak memory 195160 kb
Host smart-820e9e1d-44be-46c4-a052-173fa88dcdf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409767882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3409767882
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.2092178298
Short name T884
Test name
Test status
Simulation time 28192134877 ps
CPU time 47.89 seconds
Started Aug 11 04:26:53 PM PDT 24
Finished Aug 11 04:27:41 PM PDT 24
Peak memory 199692 kb
Host smart-d69ba340-2e31-4142-b9c1-0af12d2929e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092178298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2092178298
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.911175065
Short name T273
Test name
Test status
Simulation time 258599958178 ps
CPU time 127.6 seconds
Started Aug 11 04:26:53 PM PDT 24
Finished Aug 11 04:29:01 PM PDT 24
Peak memory 199764 kb
Host smart-fdbe60ce-f11d-4224-bc3b-b0cf2afbdf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911175065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.911175065
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_intr.1040659077
Short name T128
Test name
Test status
Simulation time 79988987425 ps
CPU time 61.6 seconds
Started Aug 11 04:27:00 PM PDT 24
Finished Aug 11 04:28:01 PM PDT 24
Peak memory 199616 kb
Host smart-843531ea-cba6-4372-b758-e2b7e6ecfbb3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040659077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1040659077
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.3892981247
Short name T883
Test name
Test status
Simulation time 98520490405 ps
CPU time 801.72 seconds
Started Aug 11 04:27:13 PM PDT 24
Finished Aug 11 04:40:35 PM PDT 24
Peak memory 199752 kb
Host smart-1afde09e-6fbe-4690-854a-7eef647149bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3892981247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3892981247
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2895077954
Short name T1039
Test name
Test status
Simulation time 7430702627 ps
CPU time 7.62 seconds
Started Aug 11 04:27:06 PM PDT 24
Finished Aug 11 04:27:14 PM PDT 24
Peak memory 199700 kb
Host smart-2f0be1bd-d69c-4c26-ba7f-83e9fc22e7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895077954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2895077954
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.1064858077
Short name T906
Test name
Test status
Simulation time 49260748188 ps
CPU time 71.34 seconds
Started Aug 11 04:27:01 PM PDT 24
Finished Aug 11 04:28:13 PM PDT 24
Peak memory 199832 kb
Host smart-c75445aa-281f-4d16-95c3-dcf76c65091a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064858077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1064858077
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.3949504626
Short name T711
Test name
Test status
Simulation time 13129965974 ps
CPU time 671.12 seconds
Started Aug 11 04:26:56 PM PDT 24
Finished Aug 11 04:38:08 PM PDT 24
Peak memory 199112 kb
Host smart-b4ede068-26ea-4d1e-9465-dd982f5373ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3949504626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.3949504626
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2448140990
Short name T409
Test name
Test status
Simulation time 7796416477 ps
CPU time 17.97 seconds
Started Aug 11 04:26:51 PM PDT 24
Finished Aug 11 04:27:09 PM PDT 24
Peak memory 198068 kb
Host smart-b3dc2af0-8c48-4cbb-bf15-c02e0eadb105
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2448140990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2448140990
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.1158607959
Short name T449
Test name
Test status
Simulation time 13129400286 ps
CPU time 20.73 seconds
Started Aug 11 04:27:01 PM PDT 24
Finished Aug 11 04:27:22 PM PDT 24
Peak memory 199148 kb
Host smart-bbb20b2b-4e75-44b6-92bf-33f781e35837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158607959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1158607959
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.4147985229
Short name T822
Test name
Test status
Simulation time 3078611001 ps
CPU time 5.1 seconds
Started Aug 11 04:26:55 PM PDT 24
Finished Aug 11 04:27:00 PM PDT 24
Peak memory 196228 kb
Host smart-a526b9e2-8f9d-4edc-8495-39c6b51e25dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147985229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.4147985229
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3943503715
Short name T507
Test name
Test status
Simulation time 854227141 ps
CPU time 1.14 seconds
Started Aug 11 04:27:06 PM PDT 24
Finished Aug 11 04:27:08 PM PDT 24
Peak memory 198584 kb
Host smart-d8e51c4c-e3ee-4ec4-8c25-2de788a2c8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943503715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3943503715
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.4085414365
Short name T587
Test name
Test status
Simulation time 829380016874 ps
CPU time 191.88 seconds
Started Aug 11 04:27:07 PM PDT 24
Finished Aug 11 04:30:19 PM PDT 24
Peak memory 199604 kb
Host smart-fce1ce9e-133c-41a2-937c-3ec9ff73069a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085414365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.4085414365
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.3698992369
Short name T55
Test name
Test status
Simulation time 99460833200 ps
CPU time 304.38 seconds
Started Aug 11 04:26:58 PM PDT 24
Finished Aug 11 04:32:02 PM PDT 24
Peak memory 209084 kb
Host smart-c60033e1-607c-47e6-9b72-44a586a27435
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698992369 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.3698992369
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1654608832
Short name T407
Test name
Test status
Simulation time 6616826163 ps
CPU time 8.46 seconds
Started Aug 11 04:27:03 PM PDT 24
Finished Aug 11 04:27:12 PM PDT 24
Peak memory 199672 kb
Host smart-53f14c6d-d08d-4c16-bf9b-c6e6e1216b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654608832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1654608832
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.1290521743
Short name T647
Test name
Test status
Simulation time 116810860450 ps
CPU time 216.65 seconds
Started Aug 11 04:27:04 PM PDT 24
Finished Aug 11 04:30:41 PM PDT 24
Peak memory 199732 kb
Host smart-01602319-23c7-4dd5-a4f8-275696d05914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290521743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1290521743
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3911463442
Short name T745
Test name
Test status
Simulation time 94048271365 ps
CPU time 27.27 seconds
Started Aug 11 04:28:41 PM PDT 24
Finished Aug 11 04:29:08 PM PDT 24
Peak memory 199608 kb
Host smart-8cd84aea-d9bf-4b7a-98d7-08cc0e371228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911463442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3911463442
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.905957194
Short name T994
Test name
Test status
Simulation time 138357181258 ps
CPU time 211.09 seconds
Started Aug 11 04:28:41 PM PDT 24
Finished Aug 11 04:32:13 PM PDT 24
Peak memory 199784 kb
Host smart-338e0d0e-a74d-4f7b-8a7f-336d771685a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905957194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.905957194
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2616777602
Short name T123
Test name
Test status
Simulation time 53988453669 ps
CPU time 29.32 seconds
Started Aug 11 04:28:42 PM PDT 24
Finished Aug 11 04:29:11 PM PDT 24
Peak memory 199736 kb
Host smart-bf3ecba4-69a3-4b17-85d7-f3133dfc1f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616777602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2616777602
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1253491337
Short name T1109
Test name
Test status
Simulation time 94717343957 ps
CPU time 225.99 seconds
Started Aug 11 04:28:44 PM PDT 24
Finished Aug 11 04:32:30 PM PDT 24
Peak memory 199784 kb
Host smart-575c2579-c93f-4560-9f62-1841d77dab2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253491337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1253491337
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.1572896376
Short name T345
Test name
Test status
Simulation time 3741222856 ps
CPU time 2.22 seconds
Started Aug 11 04:28:39 PM PDT 24
Finished Aug 11 04:28:41 PM PDT 24
Peak memory 199648 kb
Host smart-2348bb1e-4096-4180-a955-00f411fe2309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572896376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1572896376
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2494923716
Short name T252
Test name
Test status
Simulation time 54955974901 ps
CPU time 73.08 seconds
Started Aug 11 04:28:47 PM PDT 24
Finished Aug 11 04:30:00 PM PDT 24
Peak memory 199712 kb
Host smart-287f5483-bdab-4d6b-beb3-dd176125bdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494923716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2494923716
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.567339347
Short name T592
Test name
Test status
Simulation time 96632698163 ps
CPU time 153.19 seconds
Started Aug 11 04:28:40 PM PDT 24
Finished Aug 11 04:31:13 PM PDT 24
Peak memory 199740 kb
Host smart-34a4d241-eb90-4014-be3c-cd473c7b6d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567339347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.567339347
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1902078800
Short name T941
Test name
Test status
Simulation time 86369112283 ps
CPU time 94.84 seconds
Started Aug 11 04:28:40 PM PDT 24
Finished Aug 11 04:30:15 PM PDT 24
Peak memory 199776 kb
Host smart-41aaed0c-05fa-4eab-bb21-fbe18b5e2576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902078800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1902078800
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.1112029700
Short name T496
Test name
Test status
Simulation time 47614107 ps
CPU time 0.54 seconds
Started Aug 11 04:27:09 PM PDT 24
Finished Aug 11 04:27:10 PM PDT 24
Peak memory 195184 kb
Host smart-dc39064a-3d4c-4d02-af98-4214d8d99ab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112029700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1112029700
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.4045279516
Short name T498
Test name
Test status
Simulation time 23244105848 ps
CPU time 57.28 seconds
Started Aug 11 04:26:56 PM PDT 24
Finished Aug 11 04:27:54 PM PDT 24
Peak memory 199716 kb
Host smart-2747468d-704a-413e-9755-0ce975eb16ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045279516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.4045279516
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.1719033994
Short name T408
Test name
Test status
Simulation time 13321420701 ps
CPU time 13.67 seconds
Started Aug 11 04:27:12 PM PDT 24
Finished Aug 11 04:27:25 PM PDT 24
Peak memory 199848 kb
Host smart-fe6de195-6f49-424a-81fd-17e84376f452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719033994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1719033994
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.2738924274
Short name T577
Test name
Test status
Simulation time 14995733724 ps
CPU time 41.98 seconds
Started Aug 11 04:27:07 PM PDT 24
Finished Aug 11 04:27:49 PM PDT 24
Peak memory 199716 kb
Host smart-5c4956de-c6ce-4cd1-b6e4-4cbd68b567da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738924274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2738924274
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.3815670432
Short name T543
Test name
Test status
Simulation time 49742412820 ps
CPU time 30.92 seconds
Started Aug 11 04:26:58 PM PDT 24
Finished Aug 11 04:27:29 PM PDT 24
Peak memory 200076 kb
Host smart-bb9eac19-65d8-4ece-9c00-5b7611a11355
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815670432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3815670432
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_loopback.3171160915
Short name T737
Test name
Test status
Simulation time 11189157876 ps
CPU time 6.5 seconds
Started Aug 11 04:27:10 PM PDT 24
Finished Aug 11 04:27:17 PM PDT 24
Peak memory 199748 kb
Host smart-a86363f2-1882-47e5-9e21-d19325fde18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171160915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.3171160915
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.2811104721
Short name T686
Test name
Test status
Simulation time 49206287950 ps
CPU time 25.65 seconds
Started Aug 11 04:27:07 PM PDT 24
Finished Aug 11 04:27:33 PM PDT 24
Peak memory 197412 kb
Host smart-011f78b3-2bf8-48c9-9bb0-5013c4ac58a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811104721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2811104721
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.4055210242
Short name T459
Test name
Test status
Simulation time 16955449673 ps
CPU time 993.97 seconds
Started Aug 11 04:26:59 PM PDT 24
Finished Aug 11 04:43:33 PM PDT 24
Peak memory 199836 kb
Host smart-0fd0b1a4-408d-47f5-9ff0-db77e807c41a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4055210242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.4055210242
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2899948340
Short name T1066
Test name
Test status
Simulation time 1174615644 ps
CPU time 1.3 seconds
Started Aug 11 04:27:09 PM PDT 24
Finished Aug 11 04:27:10 PM PDT 24
Peak memory 195516 kb
Host smart-d880b89f-b69b-4d2c-9ac6-9e093a913e18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2899948340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2899948340
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2281788497
Short name T2
Test name
Test status
Simulation time 43311080053 ps
CPU time 35.16 seconds
Started Aug 11 04:26:53 PM PDT 24
Finished Aug 11 04:27:28 PM PDT 24
Peak memory 199792 kb
Host smart-ffd4475d-c57c-4fdf-bc69-da08e5d557e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281788497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2281788497
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.1123703629
Short name T78
Test name
Test status
Simulation time 3192570144 ps
CPU time 1.7 seconds
Started Aug 11 04:26:55 PM PDT 24
Finished Aug 11 04:26:57 PM PDT 24
Peak memory 196136 kb
Host smart-1cd42ccf-0d11-4044-a4b3-5edb1c0dacf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123703629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1123703629
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3344442112
Short name T954
Test name
Test status
Simulation time 5709427180 ps
CPU time 13.11 seconds
Started Aug 11 04:26:59 PM PDT 24
Finished Aug 11 04:27:12 PM PDT 24
Peak memory 199536 kb
Host smart-1557f500-1a07-439e-a525-23fc9cda8d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344442112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3344442112
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.2676078662
Short name T456
Test name
Test status
Simulation time 36338706351 ps
CPU time 30.97 seconds
Started Aug 11 04:26:56 PM PDT 24
Finished Aug 11 04:27:27 PM PDT 24
Peak memory 200144 kb
Host smart-77598d26-b1cc-4119-8ff6-a4dc92af3c8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676078662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2676078662
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.2771415604
Short name T630
Test name
Test status
Simulation time 23019562361 ps
CPU time 251.27 seconds
Started Aug 11 04:27:02 PM PDT 24
Finished Aug 11 04:31:14 PM PDT 24
Peak memory 216432 kb
Host smart-ca282b23-a006-45f4-8de6-cae3e9a49c19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771415604 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.2771415604
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.2622086461
Short name T1081
Test name
Test status
Simulation time 8220241422 ps
CPU time 11.46 seconds
Started Aug 11 04:27:06 PM PDT 24
Finished Aug 11 04:27:17 PM PDT 24
Peak memory 199028 kb
Host smart-f8d3c0ae-2fa3-49ab-9cf1-a9766fd17ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622086461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2622086461
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.260146362
Short name T290
Test name
Test status
Simulation time 38233243677 ps
CPU time 20.41 seconds
Started Aug 11 04:26:54 PM PDT 24
Finished Aug 11 04:27:15 PM PDT 24
Peak memory 199656 kb
Host smart-4e2ea100-05ad-42b4-9bec-18e8b8da4d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260146362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.260146362
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.3974151083
Short name T234
Test name
Test status
Simulation time 114005688312 ps
CPU time 389.69 seconds
Started Aug 11 04:28:40 PM PDT 24
Finished Aug 11 04:35:09 PM PDT 24
Peak memory 199676 kb
Host smart-d152d64f-2f46-44ca-91ba-8c85768ba4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974151083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.3974151083
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1447694618
Short name T135
Test name
Test status
Simulation time 31133412634 ps
CPU time 23.48 seconds
Started Aug 11 04:28:41 PM PDT 24
Finished Aug 11 04:29:05 PM PDT 24
Peak memory 199292 kb
Host smart-f5341f8a-85d7-4a9c-88e9-610c4380ac03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447694618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1447694618
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.4065217899
Short name T224
Test name
Test status
Simulation time 32361007272 ps
CPU time 55.02 seconds
Started Aug 11 04:28:38 PM PDT 24
Finished Aug 11 04:29:33 PM PDT 24
Peak memory 199772 kb
Host smart-3ff77bc5-56f6-4dcd-b24b-f92259b8cf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065217899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.4065217899
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.1456622734
Short name T779
Test name
Test status
Simulation time 38817425792 ps
CPU time 12.29 seconds
Started Aug 11 04:28:41 PM PDT 24
Finished Aug 11 04:28:54 PM PDT 24
Peak memory 198640 kb
Host smart-da2a1765-07ea-4404-b4ed-f72d4d871929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456622734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1456622734
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.729609484
Short name T673
Test name
Test status
Simulation time 276293152556 ps
CPU time 63.3 seconds
Started Aug 11 04:28:41 PM PDT 24
Finished Aug 11 04:29:44 PM PDT 24
Peak memory 199712 kb
Host smart-4cdd6666-4650-4f36-ae41-d18d7b99d8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729609484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.729609484
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.642839008
Short name T599
Test name
Test status
Simulation time 36214492079 ps
CPU time 14.07 seconds
Started Aug 11 04:28:57 PM PDT 24
Finished Aug 11 04:29:11 PM PDT 24
Peak memory 199792 kb
Host smart-7a76dd06-50ce-401f-bdd4-b25f4691ac30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642839008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.642839008
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.4219515451
Short name T980
Test name
Test status
Simulation time 106260353459 ps
CPU time 187.78 seconds
Started Aug 11 04:28:51 PM PDT 24
Finished Aug 11 04:31:59 PM PDT 24
Peak memory 199768 kb
Host smart-3cf841da-b204-4291-a404-d65973a2ff80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219515451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.4219515451
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.1577929281
Short name T399
Test name
Test status
Simulation time 4665827513 ps
CPU time 7.92 seconds
Started Aug 11 04:28:46 PM PDT 24
Finished Aug 11 04:28:54 PM PDT 24
Peak memory 199688 kb
Host smart-c96d2a08-a14a-445f-8135-b0d39e04bd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577929281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1577929281
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.754495066
Short name T450
Test name
Test status
Simulation time 13536371 ps
CPU time 0.55 seconds
Started Aug 11 04:25:59 PM PDT 24
Finished Aug 11 04:25:59 PM PDT 24
Peak memory 195388 kb
Host smart-6a11e385-33d4-4edb-b084-ced067344f02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754495066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.754495066
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.3702759509
Short name T1057
Test name
Test status
Simulation time 17684448658 ps
CPU time 15.32 seconds
Started Aug 11 04:20:43 PM PDT 24
Finished Aug 11 04:20:58 PM PDT 24
Peak memory 199448 kb
Host smart-b06b0fd5-ea3e-427a-87e7-0fd2cab93caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702759509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.3702759509
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.1003408711
Short name T890
Test name
Test status
Simulation time 84291835081 ps
CPU time 33.92 seconds
Started Aug 11 04:20:27 PM PDT 24
Finished Aug 11 04:21:01 PM PDT 24
Peak memory 199444 kb
Host smart-889c376e-f82d-4ef6-87c4-01bc4c49348f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003408711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1003408711
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2826112405
Short name T1023
Test name
Test status
Simulation time 126478605105 ps
CPU time 54.35 seconds
Started Aug 11 04:23:57 PM PDT 24
Finished Aug 11 04:24:51 PM PDT 24
Peak memory 199504 kb
Host smart-6f415ad7-1c92-4722-b616-c78f526cc927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826112405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2826112405
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.2636465289
Short name T1032
Test name
Test status
Simulation time 25259436826 ps
CPU time 42.38 seconds
Started Aug 11 04:23:46 PM PDT 24
Finished Aug 11 04:24:28 PM PDT 24
Peak memory 199624 kb
Host smart-5e8aa33f-921d-441c-8eaf-6df6013d7f00
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636465289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2636465289
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.4257995626
Short name T582
Test name
Test status
Simulation time 97844290555 ps
CPU time 146.17 seconds
Started Aug 11 04:26:00 PM PDT 24
Finished Aug 11 04:28:26 PM PDT 24
Peak memory 199668 kb
Host smart-896d5cd5-4c04-498e-8090-4e0f08fe8c91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4257995626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.4257995626
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3319833320
Short name T523
Test name
Test status
Simulation time 1929335787 ps
CPU time 1.8 seconds
Started Aug 11 04:26:00 PM PDT 24
Finished Aug 11 04:26:02 PM PDT 24
Peak memory 198052 kb
Host smart-78d800f9-10d9-4c14-8592-bcfa831b1acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319833320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3319833320
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.2474938216
Short name T1024
Test name
Test status
Simulation time 68594113248 ps
CPU time 17.84 seconds
Started Aug 11 04:19:40 PM PDT 24
Finished Aug 11 04:19:58 PM PDT 24
Peak memory 198916 kb
Host smart-de961082-be36-43d7-aada-a8df59546739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474938216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2474938216
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.4023957361
Short name T810
Test name
Test status
Simulation time 21908406031 ps
CPU time 115.16 seconds
Started Aug 11 04:26:02 PM PDT 24
Finished Aug 11 04:27:57 PM PDT 24
Peak memory 199596 kb
Host smart-eab977f1-cf6d-4aea-91e1-36b402ce4374
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4023957361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.4023957361
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.78524657
Short name T747
Test name
Test status
Simulation time 2532302847 ps
CPU time 15.13 seconds
Started Aug 11 04:23:07 PM PDT 24
Finished Aug 11 04:23:23 PM PDT 24
Peak memory 197396 kb
Host smart-dad2820d-674c-4dd4-a6e1-7f034233d6b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=78524657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.78524657
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.176326848
Short name T593
Test name
Test status
Simulation time 129381593089 ps
CPU time 99.39 seconds
Started Aug 11 04:22:56 PM PDT 24
Finished Aug 11 04:24:35 PM PDT 24
Peak memory 198752 kb
Host smart-dbf3e5a7-688b-4081-b249-712fd964512f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176326848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.176326848
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.284200237
Short name T287
Test name
Test status
Simulation time 458586861 ps
CPU time 1.28 seconds
Started Aug 11 04:23:07 PM PDT 24
Finished Aug 11 04:23:09 PM PDT 24
Peak memory 195244 kb
Host smart-49a12993-5c4f-4aa8-92d8-3dc77d637dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284200237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.284200237
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_smoke.2218283893
Short name T657
Test name
Test status
Simulation time 6324646546 ps
CPU time 14.28 seconds
Started Aug 11 04:21:57 PM PDT 24
Finished Aug 11 04:22:11 PM PDT 24
Peak memory 199796 kb
Host smart-68c534e2-8665-4a31-9726-5572c3970358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218283893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2218283893
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2466118040
Short name T1088
Test name
Test status
Simulation time 285774085709 ps
CPU time 427.84 seconds
Started Aug 11 04:26:14 PM PDT 24
Finished Aug 11 04:33:22 PM PDT 24
Peak memory 199740 kb
Host smart-7f7dd6fb-bdaa-44c9-a190-2042ced4d95c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466118040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2466118040
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.1259606105
Short name T337
Test name
Test status
Simulation time 520263703588 ps
CPU time 313.51 seconds
Started Aug 11 04:26:11 PM PDT 24
Finished Aug 11 04:31:24 PM PDT 24
Peak memory 216252 kb
Host smart-db82a2c3-05b0-4391-b12f-384369293d38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259606105 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.1259606105
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.3366065220
Short name T107
Test name
Test status
Simulation time 1984291279 ps
CPU time 2.34 seconds
Started Aug 11 04:19:06 PM PDT 24
Finished Aug 11 04:19:08 PM PDT 24
Peak memory 198232 kb
Host smart-89c40a29-71c4-4d62-ac68-8da3ddace2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366065220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.3366065220
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.564650111
Short name T308
Test name
Test status
Simulation time 6685229321 ps
CPU time 4.64 seconds
Started Aug 11 04:24:05 PM PDT 24
Finished Aug 11 04:24:10 PM PDT 24
Peak memory 196700 kb
Host smart-e185f052-aabd-4dc1-9fbc-05538d9b17f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564650111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.564650111
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.2032057950
Short name T925
Test name
Test status
Simulation time 36254657 ps
CPU time 0.55 seconds
Started Aug 11 04:26:53 PM PDT 24
Finished Aug 11 04:26:53 PM PDT 24
Peak memory 195000 kb
Host smart-67b8dd24-6261-408f-bb80-5155376d0b8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032057950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2032057950
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.1961303980
Short name T880
Test name
Test status
Simulation time 35731986839 ps
CPU time 50.32 seconds
Started Aug 11 04:27:09 PM PDT 24
Finished Aug 11 04:28:00 PM PDT 24
Peak memory 199728 kb
Host smart-8cf4f7eb-fbcd-4844-9b2b-f412f17fd43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961303980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1961303980
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3016892407
Short name T554
Test name
Test status
Simulation time 116903997177 ps
CPU time 152.12 seconds
Started Aug 11 04:27:08 PM PDT 24
Finished Aug 11 04:29:40 PM PDT 24
Peak memory 199556 kb
Host smart-195c5909-080a-49b3-bc8c-696f217ffabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016892407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3016892407
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2361856123
Short name T420
Test name
Test status
Simulation time 9805831077 ps
CPU time 16.92 seconds
Started Aug 11 04:27:08 PM PDT 24
Finished Aug 11 04:27:25 PM PDT 24
Peak memory 199708 kb
Host smart-c142f858-b8a3-496e-bd30-eb71c5776e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361856123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2361856123
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.3712628727
Short name T1043
Test name
Test status
Simulation time 68792480684 ps
CPU time 101.97 seconds
Started Aug 11 04:27:07 PM PDT 24
Finished Aug 11 04:28:49 PM PDT 24
Peak memory 199664 kb
Host smart-1cfda511-74b3-4963-a1ac-f95e184bebca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712628727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3712628727
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1913053568
Short name T706
Test name
Test status
Simulation time 72088238069 ps
CPU time 63.47 seconds
Started Aug 11 04:27:20 PM PDT 24
Finished Aug 11 04:28:24 PM PDT 24
Peak memory 199644 kb
Host smart-73e39c87-1e7f-429d-bfff-380324d13b34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1913053568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1913053568
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1768675858
Short name T744
Test name
Test status
Simulation time 2633713546 ps
CPU time 2.14 seconds
Started Aug 11 04:27:01 PM PDT 24
Finished Aug 11 04:27:04 PM PDT 24
Peak memory 198056 kb
Host smart-6ec739e2-f59c-42f3-bd81-0616f6de67df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768675858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1768675858
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.1648563144
Short name T926
Test name
Test status
Simulation time 192277402407 ps
CPU time 79.37 seconds
Started Aug 11 04:27:07 PM PDT 24
Finished Aug 11 04:28:27 PM PDT 24
Peak memory 199884 kb
Host smart-718e45ea-d452-4cd4-96db-24978eaf7f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648563144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1648563144
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2903936663
Short name T782
Test name
Test status
Simulation time 18759129966 ps
CPU time 675.17 seconds
Started Aug 11 04:26:55 PM PDT 24
Finished Aug 11 04:38:10 PM PDT 24
Peak memory 199712 kb
Host smart-873eb661-5e49-484e-9870-b0076af9eff5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2903936663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2903936663
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.1182609092
Short name T458
Test name
Test status
Simulation time 3458287608 ps
CPU time 22.94 seconds
Started Aug 11 04:26:55 PM PDT 24
Finished Aug 11 04:27:18 PM PDT 24
Peak memory 198120 kb
Host smart-0ae97621-433c-4599-912b-4c1e6e89c2e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1182609092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1182609092
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3765712252
Short name T896
Test name
Test status
Simulation time 286308984800 ps
CPU time 268.64 seconds
Started Aug 11 04:26:56 PM PDT 24
Finished Aug 11 04:31:25 PM PDT 24
Peak memory 199732 kb
Host smart-c7c63cd9-f07a-45e8-88c4-62653dae9e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765712252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3765712252
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1809926248
Short name T1174
Test name
Test status
Simulation time 631683291 ps
CPU time 1.05 seconds
Started Aug 11 04:27:09 PM PDT 24
Finished Aug 11 04:27:10 PM PDT 24
Peak memory 195632 kb
Host smart-5f67e799-9dbf-4533-b495-d5c2c45ebac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809926248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1809926248
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2957645670
Short name T671
Test name
Test status
Simulation time 945710974 ps
CPU time 2.18 seconds
Started Aug 11 04:26:53 PM PDT 24
Finished Aug 11 04:26:56 PM PDT 24
Peak memory 199656 kb
Host smart-f493a0ed-81a8-4293-a2fd-b9802cd1fbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957645670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2957645670
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.3418624666
Short name T227
Test name
Test status
Simulation time 145769753150 ps
CPU time 70.62 seconds
Started Aug 11 04:27:14 PM PDT 24
Finished Aug 11 04:28:25 PM PDT 24
Peak memory 199652 kb
Host smart-6a3e489c-43ef-4df5-8579-e5f76faba6c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418624666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3418624666
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1210366448
Short name T956
Test name
Test status
Simulation time 1145524297 ps
CPU time 4 seconds
Started Aug 11 04:27:09 PM PDT 24
Finished Aug 11 04:27:13 PM PDT 24
Peak memory 198136 kb
Host smart-7e08ef94-01c4-48e3-bef0-2e646663433d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210366448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1210366448
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.1781871303
Short name T549
Test name
Test status
Simulation time 34928911713 ps
CPU time 55.96 seconds
Started Aug 11 04:26:55 PM PDT 24
Finished Aug 11 04:27:51 PM PDT 24
Peak memory 199796 kb
Host smart-bc7e98a4-7e15-4650-b8be-2b26e10c30d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781871303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1781871303
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1366797700
Short name T358
Test name
Test status
Simulation time 42804740 ps
CPU time 0.55 seconds
Started Aug 11 04:27:06 PM PDT 24
Finished Aug 11 04:27:07 PM PDT 24
Peak memory 195084 kb
Host smart-2e88d2ca-ac3e-4dde-9788-338bdca7afef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366797700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1366797700
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.112349318
Short name T272
Test name
Test status
Simulation time 83566870363 ps
CPU time 61.7 seconds
Started Aug 11 04:26:58 PM PDT 24
Finished Aug 11 04:28:00 PM PDT 24
Peak memory 200112 kb
Host smart-94700910-e7e1-437b-863e-471ed04aed2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112349318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.112349318
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1165638209
Short name T972
Test name
Test status
Simulation time 21212418126 ps
CPU time 9.97 seconds
Started Aug 11 04:26:53 PM PDT 24
Finished Aug 11 04:27:03 PM PDT 24
Peak memory 199716 kb
Host smart-e8f998e9-e6dc-4f2f-a059-da2d9a9b97eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165638209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1165638209
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.757225248
Short name T369
Test name
Test status
Simulation time 19729324430 ps
CPU time 8.18 seconds
Started Aug 11 04:26:56 PM PDT 24
Finished Aug 11 04:27:04 PM PDT 24
Peak memory 197260 kb
Host smart-3ecfe18c-2273-4c58-81d7-e03d9db5bef3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757225248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.757225248
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.3854056820
Short name T845
Test name
Test status
Simulation time 145083721370 ps
CPU time 319.93 seconds
Started Aug 11 04:27:07 PM PDT 24
Finished Aug 11 04:32:27 PM PDT 24
Peak memory 199692 kb
Host smart-bf87f49d-d0ae-41e1-8e96-2a17e74dcb8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3854056820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3854056820
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.3182159429
Short name T493
Test name
Test status
Simulation time 2436125255 ps
CPU time 4.77 seconds
Started Aug 11 04:26:56 PM PDT 24
Finished Aug 11 04:27:01 PM PDT 24
Peak memory 197088 kb
Host smart-509e29fd-3a7b-49ea-b1ad-0464f83919ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182159429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3182159429
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.981056949
Short name T439
Test name
Test status
Simulation time 99974801235 ps
CPU time 99.72 seconds
Started Aug 11 04:26:57 PM PDT 24
Finished Aug 11 04:28:36 PM PDT 24
Peak memory 199864 kb
Host smart-5c3ba92d-b33b-4907-8c0a-c7541bd9fc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981056949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.981056949
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.3741894136
Short name T333
Test name
Test status
Simulation time 9899350280 ps
CPU time 603.69 seconds
Started Aug 11 04:27:16 PM PDT 24
Finished Aug 11 04:37:19 PM PDT 24
Peak memory 199696 kb
Host smart-d8797c5e-5b32-4be3-b11c-05e9e481f5a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3741894136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3741894136
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.3434392188
Short name T940
Test name
Test status
Simulation time 5945533152 ps
CPU time 8.41 seconds
Started Aug 11 04:26:55 PM PDT 24
Finished Aug 11 04:27:04 PM PDT 24
Peak memory 198044 kb
Host smart-4ac4d89a-9c67-4eef-b414-37f118bbef60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3434392188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3434392188
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1661180425
Short name T497
Test name
Test status
Simulation time 120237698982 ps
CPU time 232.4 seconds
Started Aug 11 04:27:03 PM PDT 24
Finished Aug 11 04:30:56 PM PDT 24
Peak memory 199708 kb
Host smart-6f804a1d-a4cc-4625-ab16-ba41b418cf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661180425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1661180425
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.932605130
Short name T689
Test name
Test status
Simulation time 531755240 ps
CPU time 1.22 seconds
Started Aug 11 04:26:54 PM PDT 24
Finished Aug 11 04:26:55 PM PDT 24
Peak memory 195264 kb
Host smart-18bb4a12-4c06-43df-a8c5-bc23187c5db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932605130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.932605130
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1751150242
Short name T1150
Test name
Test status
Simulation time 289811300 ps
CPU time 1.67 seconds
Started Aug 11 04:27:01 PM PDT 24
Finished Aug 11 04:27:03 PM PDT 24
Peak memory 199008 kb
Host smart-353384cc-e36d-44c0-9228-4567ff2d1df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751150242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1751150242
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.3006186023
Short name T684
Test name
Test status
Simulation time 292287567666 ps
CPU time 563.46 seconds
Started Aug 11 04:27:03 PM PDT 24
Finished Aug 11 04:36:27 PM PDT 24
Peak memory 199716 kb
Host smart-65c0e2c0-0ba2-4a92-b259-50c5e5952a9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006186023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3006186023
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2825516287
Short name T253
Test name
Test status
Simulation time 43016932588 ps
CPU time 136.61 seconds
Started Aug 11 04:27:05 PM PDT 24
Finished Aug 11 04:29:22 PM PDT 24
Peak memory 208092 kb
Host smart-c4b9a897-ef3b-41a9-b192-a441bc69d49f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825516287 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2825516287
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.2711973267
Short name T541
Test name
Test status
Simulation time 6827116127 ps
CPU time 6.3 seconds
Started Aug 11 04:27:21 PM PDT 24
Finished Aug 11 04:27:27 PM PDT 24
Peak memory 199620 kb
Host smart-bb6f7767-a152-46e6-b197-8d13be6ce1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711973267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2711973267
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.2736061447
Short name T827
Test name
Test status
Simulation time 42704880149 ps
CPU time 71.96 seconds
Started Aug 11 04:26:57 PM PDT 24
Finished Aug 11 04:28:09 PM PDT 24
Peak memory 200136 kb
Host smart-568ad57e-585d-4d5d-82ee-7352d9ebfbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736061447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2736061447
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.146425506
Short name T1086
Test name
Test status
Simulation time 13226900 ps
CPU time 0.58 seconds
Started Aug 11 04:27:08 PM PDT 24
Finished Aug 11 04:27:09 PM PDT 24
Peak memory 195176 kb
Host smart-87595568-e7d7-442d-82b0-8e44d5eaa5ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146425506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.146425506
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.537842532
Short name T173
Test name
Test status
Simulation time 40804045108 ps
CPU time 62.45 seconds
Started Aug 11 04:27:09 PM PDT 24
Finished Aug 11 04:28:12 PM PDT 24
Peak memory 199752 kb
Host smart-10548bdf-c2f3-491e-b1f1-ca2481539ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537842532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.537842532
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.4172792304
Short name T759
Test name
Test status
Simulation time 7902738244 ps
CPU time 12.16 seconds
Started Aug 11 04:27:06 PM PDT 24
Finished Aug 11 04:27:18 PM PDT 24
Peak memory 198224 kb
Host smart-af58440b-e6cd-4056-b927-a78e1fc708ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172792304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.4172792304
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.2854495855
Short name T49
Test name
Test status
Simulation time 96009266141 ps
CPU time 142.03 seconds
Started Aug 11 04:27:25 PM PDT 24
Finished Aug 11 04:29:47 PM PDT 24
Peak memory 199720 kb
Host smart-8305e3f4-cd58-430f-9ee7-1a021d7394b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854495855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2854495855
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1567844936
Short name T1037
Test name
Test status
Simulation time 46363854838 ps
CPU time 79.87 seconds
Started Aug 11 04:27:05 PM PDT 24
Finished Aug 11 04:28:25 PM PDT 24
Peak memory 198680 kb
Host smart-6fb921c9-2588-483b-8d4a-0d5dddbc5574
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567844936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1567844936
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2642498448
Short name T964
Test name
Test status
Simulation time 214377407537 ps
CPU time 405.89 seconds
Started Aug 11 04:27:12 PM PDT 24
Finished Aug 11 04:33:58 PM PDT 24
Peak memory 199680 kb
Host smart-cf39c06c-7d88-44cd-8467-95b8a7d9b7fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2642498448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2642498448
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.547536471
Short name T362
Test name
Test status
Simulation time 8407594669 ps
CPU time 5.87 seconds
Started Aug 11 04:27:09 PM PDT 24
Finished Aug 11 04:27:15 PM PDT 24
Peak memory 199704 kb
Host smart-70e38c05-ab09-41fa-a8db-25737b593547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547536471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.547536471
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.3087580414
Short name T1021
Test name
Test status
Simulation time 105934557662 ps
CPU time 101.46 seconds
Started Aug 11 04:27:06 PM PDT 24
Finished Aug 11 04:28:48 PM PDT 24
Peak memory 198800 kb
Host smart-fc91e8d2-3b74-4794-ba0c-394c717fb217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087580414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3087580414
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.479332879
Short name T433
Test name
Test status
Simulation time 14214191902 ps
CPU time 199.76 seconds
Started Aug 11 04:27:08 PM PDT 24
Finished Aug 11 04:30:28 PM PDT 24
Peak memory 199636 kb
Host smart-ae8dd453-ad01-4d9b-b82a-bf640e40d282
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=479332879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.479332879
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.4077503827
Short name T394
Test name
Test status
Simulation time 1939049755 ps
CPU time 1.85 seconds
Started Aug 11 04:27:04 PM PDT 24
Finished Aug 11 04:27:06 PM PDT 24
Peak memory 198136 kb
Host smart-78d38669-718c-4794-bbde-6fcc7b07b4cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4077503827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.4077503827
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1821669210
Short name T731
Test name
Test status
Simulation time 179017504191 ps
CPU time 102.31 seconds
Started Aug 11 04:27:19 PM PDT 24
Finished Aug 11 04:29:01 PM PDT 24
Peak memory 199796 kb
Host smart-c1dcb27e-8c46-4304-9caa-e64d3a8e62a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821669210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1821669210
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3848198282
Short name T1126
Test name
Test status
Simulation time 1472292749 ps
CPU time 2.71 seconds
Started Aug 11 04:27:11 PM PDT 24
Finished Aug 11 04:27:14 PM PDT 24
Peak memory 195492 kb
Host smart-7e0c217c-289d-481e-a2a7-3a59f8c09c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848198282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3848198282
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.4002444747
Short name T1171
Test name
Test status
Simulation time 699069346 ps
CPU time 2.48 seconds
Started Aug 11 04:26:57 PM PDT 24
Finished Aug 11 04:27:00 PM PDT 24
Peak memory 198564 kb
Host smart-d16b75d5-ed13-433b-80a3-3b88a34cdbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002444747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.4002444747
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.208952552
Short name T1083
Test name
Test status
Simulation time 123739839654 ps
CPU time 56.59 seconds
Started Aug 11 04:27:01 PM PDT 24
Finished Aug 11 04:27:58 PM PDT 24
Peak memory 199808 kb
Host smart-62dfdd45-57c3-458f-b73f-b8f73ba15129
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208952552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.208952552
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.1560319379
Short name T967
Test name
Test status
Simulation time 963596760 ps
CPU time 3.57 seconds
Started Aug 11 04:27:08 PM PDT 24
Finished Aug 11 04:27:11 PM PDT 24
Peak memory 199620 kb
Host smart-b7da0b4f-6b1c-4add-afb6-9ba48e23c950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560319379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1560319379
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2327366239
Short name T794
Test name
Test status
Simulation time 41938420441 ps
CPU time 34.09 seconds
Started Aug 11 04:26:57 PM PDT 24
Finished Aug 11 04:27:32 PM PDT 24
Peak memory 199696 kb
Host smart-c9ccdf49-725a-4ca8-bb1c-ac84d8002252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327366239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2327366239
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.2683238714
Short name T468
Test name
Test status
Simulation time 11786606 ps
CPU time 0.58 seconds
Started Aug 11 04:27:09 PM PDT 24
Finished Aug 11 04:27:09 PM PDT 24
Peak memory 194148 kb
Host smart-d3a90fbf-467a-4f65-934b-ef5248e21b83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683238714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2683238714
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.59037965
Short name T600
Test name
Test status
Simulation time 20484298355 ps
CPU time 13.06 seconds
Started Aug 11 04:27:14 PM PDT 24
Finished Aug 11 04:27:28 PM PDT 24
Peak memory 199676 kb
Host smart-a7130a52-d960-4f53-8b1c-3b98d8e95f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59037965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.59037965
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.2753649039
Short name T539
Test name
Test status
Simulation time 39613620314 ps
CPU time 17.91 seconds
Started Aug 11 04:27:00 PM PDT 24
Finished Aug 11 04:27:18 PM PDT 24
Peak memory 199796 kb
Host smart-9d21eb3c-3513-4614-b941-ca5de65fcc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753649039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2753649039
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3175536527
Short name T615
Test name
Test status
Simulation time 56843162317 ps
CPU time 22.8 seconds
Started Aug 11 04:27:21 PM PDT 24
Finished Aug 11 04:27:44 PM PDT 24
Peak memory 199688 kb
Host smart-2da4451d-780a-4c32-a23d-307e6f520651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175536527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3175536527
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2881348631
Short name T21
Test name
Test status
Simulation time 41155258913 ps
CPU time 39.66 seconds
Started Aug 11 04:27:20 PM PDT 24
Finished Aug 11 04:27:59 PM PDT 24
Peak memory 199488 kb
Host smart-40d688d4-829d-4f4d-9f3d-75816b3a206b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881348631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2881348631
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2362928113
Short name T692
Test name
Test status
Simulation time 105666490809 ps
CPU time 1098.64 seconds
Started Aug 11 04:27:15 PM PDT 24
Finished Aug 11 04:45:34 PM PDT 24
Peak memory 199796 kb
Host smart-d05f6021-f003-4231-89f9-91c2fbccb85a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2362928113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2362928113
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3283253076
Short name T377
Test name
Test status
Simulation time 7578015128 ps
CPU time 13.88 seconds
Started Aug 11 04:27:04 PM PDT 24
Finished Aug 11 04:27:18 PM PDT 24
Peak memory 198612 kb
Host smart-2c077205-f819-492a-9326-a2638ae294a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283253076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3283253076
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.358545791
Short name T540
Test name
Test status
Simulation time 8584715816 ps
CPU time 14.96 seconds
Started Aug 11 04:27:08 PM PDT 24
Finished Aug 11 04:27:24 PM PDT 24
Peak memory 199692 kb
Host smart-c0c590d5-ab51-45c8-b93d-db7ada3b98c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358545791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.358545791
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.1710006615
Short name T1072
Test name
Test status
Simulation time 17303560330 ps
CPU time 971.47 seconds
Started Aug 11 04:27:15 PM PDT 24
Finished Aug 11 04:43:26 PM PDT 24
Peak memory 199704 kb
Host smart-fb22b536-2fb7-4088-b89c-716303f4c3ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1710006615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1710006615
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3546562846
Short name T614
Test name
Test status
Simulation time 3029218590 ps
CPU time 11.57 seconds
Started Aug 11 04:27:07 PM PDT 24
Finished Aug 11 04:27:19 PM PDT 24
Peak memory 198764 kb
Host smart-2e9af7cc-f339-4c59-b09d-41310a3b73e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3546562846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3546562846
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.4071489410
Short name T1011
Test name
Test status
Simulation time 62333134429 ps
CPU time 87.04 seconds
Started Aug 11 04:27:18 PM PDT 24
Finished Aug 11 04:28:45 PM PDT 24
Peak memory 199632 kb
Host smart-e51a880d-d27d-492a-af03-6c906f1d3d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071489410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.4071489410
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.461277845
Short name T318
Test name
Test status
Simulation time 4812259026 ps
CPU time 2.26 seconds
Started Aug 11 04:27:02 PM PDT 24
Finished Aug 11 04:27:04 PM PDT 24
Peak memory 195820 kb
Host smart-59e0eef1-23ee-4925-93f8-db2c53104049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461277845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.461277845
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1910628933
Short name T320
Test name
Test status
Simulation time 5723368360 ps
CPU time 11.11 seconds
Started Aug 11 04:27:01 PM PDT 24
Finished Aug 11 04:27:13 PM PDT 24
Peak memory 199716 kb
Host smart-52703757-92a7-45be-88a6-7fe681bb8607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910628933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1910628933
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.1731738383
Short name T675
Test name
Test status
Simulation time 256538317777 ps
CPU time 1942.66 seconds
Started Aug 11 04:26:58 PM PDT 24
Finished Aug 11 04:59:21 PM PDT 24
Peak memory 208336 kb
Host smart-3d37d9a9-52ec-44dd-8fba-b1cddc4ded00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731738383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.1731738383
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.4294500725
Short name T336
Test name
Test status
Simulation time 157750826336 ps
CPU time 971.51 seconds
Started Aug 11 04:27:23 PM PDT 24
Finished Aug 11 04:43:35 PM PDT 24
Peak memory 224596 kb
Host smart-32420d3a-fa1d-47e7-81a6-c5126e8e9418
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294500725 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.4294500725
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.3711404967
Short name T1018
Test name
Test status
Simulation time 8550529199 ps
CPU time 4.25 seconds
Started Aug 11 04:27:16 PM PDT 24
Finished Aug 11 04:27:20 PM PDT 24
Peak memory 199656 kb
Host smart-439ea5cf-d566-4166-8747-439afac65769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711404967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3711404967
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2974604669
Short name T314
Test name
Test status
Simulation time 71059823459 ps
CPU time 49.01 seconds
Started Aug 11 04:27:10 PM PDT 24
Finished Aug 11 04:27:59 PM PDT 24
Peak memory 199772 kb
Host smart-e8447f4e-418e-4768-aad6-dfcc8cf818fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974604669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2974604669
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1162231101
Short name T545
Test name
Test status
Simulation time 43313088 ps
CPU time 0.56 seconds
Started Aug 11 04:27:12 PM PDT 24
Finished Aug 11 04:27:13 PM PDT 24
Peak memory 195168 kb
Host smart-21b88412-7114-4778-a012-99466d5758fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162231101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1162231101
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.308028162
Short name T566
Test name
Test status
Simulation time 83228987358 ps
CPU time 233.7 seconds
Started Aug 11 04:27:03 PM PDT 24
Finished Aug 11 04:30:57 PM PDT 24
Peak memory 199756 kb
Host smart-fbc60720-b49b-4ac3-a042-af88c535826b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308028162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.308028162
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3039966918
Short name T155
Test name
Test status
Simulation time 31014718135 ps
CPU time 22.04 seconds
Started Aug 11 04:26:59 PM PDT 24
Finished Aug 11 04:27:21 PM PDT 24
Peak memory 200080 kb
Host smart-3c8e1a08-d3a3-453d-95f5-8413bccf9554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039966918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3039966918
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.264022107
Short name T304
Test name
Test status
Simulation time 89114634194 ps
CPU time 40.09 seconds
Started Aug 11 04:27:17 PM PDT 24
Finished Aug 11 04:27:57 PM PDT 24
Peak memory 199748 kb
Host smart-7cc4d4b6-390c-44b7-bbbc-f6558d5cbac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264022107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.264022107
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3151180067
Short name T683
Test name
Test status
Simulation time 12132210737 ps
CPU time 18.78 seconds
Started Aug 11 04:26:59 PM PDT 24
Finished Aug 11 04:27:18 PM PDT 24
Peak memory 197480 kb
Host smart-57c4c7eb-1dff-49ea-b060-235413aac332
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151180067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3151180067
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.421257729
Short name T793
Test name
Test status
Simulation time 111222940804 ps
CPU time 886.36 seconds
Started Aug 11 04:27:08 PM PDT 24
Finished Aug 11 04:41:55 PM PDT 24
Peak memory 199732 kb
Host smart-48875946-c90a-4693-a96c-79413b62fbb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=421257729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.421257729
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3208656468
Short name T1128
Test name
Test status
Simulation time 11207080903 ps
CPU time 9.72 seconds
Started Aug 11 04:27:29 PM PDT 24
Finished Aug 11 04:27:38 PM PDT 24
Peak memory 199728 kb
Host smart-0f24ad8a-afda-42d3-a2b9-d0d68f5ab2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208656468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3208656468
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.3051006955
Short name T305
Test name
Test status
Simulation time 82556287738 ps
CPU time 43.51 seconds
Started Aug 11 04:27:10 PM PDT 24
Finished Aug 11 04:27:53 PM PDT 24
Peak memory 198368 kb
Host smart-bc97f06f-e0fe-4703-85d6-add5c17a654f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051006955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3051006955
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.705150857
Short name T751
Test name
Test status
Simulation time 13678429418 ps
CPU time 240.24 seconds
Started Aug 11 04:27:19 PM PDT 24
Finished Aug 11 04:31:19 PM PDT 24
Peak memory 199744 kb
Host smart-a3f7bb35-f8a3-4f43-92a8-aceebecc4d42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=705150857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.705150857
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.631032780
Short name T13
Test name
Test status
Simulation time 3321118380 ps
CPU time 7.55 seconds
Started Aug 11 04:26:59 PM PDT 24
Finished Aug 11 04:27:07 PM PDT 24
Peak memory 198132 kb
Host smart-489d9c48-c920-4456-b6bf-1de1e5b774cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=631032780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.631032780
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.3090027592
Short name T602
Test name
Test status
Simulation time 164003789671 ps
CPU time 32.25 seconds
Started Aug 11 04:27:20 PM PDT 24
Finished Aug 11 04:27:52 PM PDT 24
Peak memory 199800 kb
Host smart-3cc85517-f69d-4ed6-a0e3-b2d7b9905bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090027592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.3090027592
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.2439416345
Short name T1047
Test name
Test status
Simulation time 2061886394 ps
CPU time 4.06 seconds
Started Aug 11 04:27:14 PM PDT 24
Finished Aug 11 04:27:18 PM PDT 24
Peak memory 195304 kb
Host smart-48d9713e-235d-42ca-980c-5cad2e347269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439416345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2439416345
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.759460224
Short name T1105
Test name
Test status
Simulation time 462869882 ps
CPU time 1.24 seconds
Started Aug 11 04:27:13 PM PDT 24
Finished Aug 11 04:27:14 PM PDT 24
Peak memory 198116 kb
Host smart-c43cb184-2560-46ca-92ab-7f62eea1474e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759460224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.759460224
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.1830705534
Short name T513
Test name
Test status
Simulation time 352258721972 ps
CPU time 804.13 seconds
Started Aug 11 04:27:08 PM PDT 24
Finished Aug 11 04:40:33 PM PDT 24
Peak memory 210816 kb
Host smart-1008ba60-b4c0-4b07-891a-179e673407cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830705534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1830705534
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.3135018629
Short name T929
Test name
Test status
Simulation time 81652191640 ps
CPU time 552.11 seconds
Started Aug 11 04:27:00 PM PDT 24
Finished Aug 11 04:36:12 PM PDT 24
Peak memory 216388 kb
Host smart-8af6e193-1a0c-48e3-868f-33fa39372c46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135018629 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.3135018629
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.2344733406
Short name T785
Test name
Test status
Simulation time 1750224651 ps
CPU time 2.13 seconds
Started Aug 11 04:27:15 PM PDT 24
Finished Aug 11 04:27:18 PM PDT 24
Peak memory 198072 kb
Host smart-8b17f179-c1e5-46c8-9892-87da750aeef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344733406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2344733406
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1421649059
Short name T846
Test name
Test status
Simulation time 133546492828 ps
CPU time 64.12 seconds
Started Aug 11 04:27:06 PM PDT 24
Finished Aug 11 04:28:10 PM PDT 24
Peak memory 199808 kb
Host smart-90f73446-e13e-463f-8bab-926fe8497629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421649059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1421649059
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3462551596
Short name T364
Test name
Test status
Simulation time 11073179 ps
CPU time 0.51 seconds
Started Aug 11 04:27:09 PM PDT 24
Finished Aug 11 04:27:10 PM PDT 24
Peak memory 194060 kb
Host smart-a059ec15-3a58-49f5-a14f-6ed065c783bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462551596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3462551596
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3357188638
Short name T617
Test name
Test status
Simulation time 273373972454 ps
CPU time 200.21 seconds
Started Aug 11 04:27:19 PM PDT 24
Finished Aug 11 04:30:39 PM PDT 24
Peak memory 199768 kb
Host smart-0a78e918-001f-496b-83d0-db9b3b8a6496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357188638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3357188638
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2613944572
Short name T400
Test name
Test status
Simulation time 9678172146 ps
CPU time 17.11 seconds
Started Aug 11 04:27:16 PM PDT 24
Finished Aug 11 04:27:33 PM PDT 24
Peak memory 199624 kb
Host smart-7d945a64-c067-4a60-a578-8042c1714b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613944572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2613944572
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.3179935899
Short name T1070
Test name
Test status
Simulation time 34435334299 ps
CPU time 11.98 seconds
Started Aug 11 04:27:12 PM PDT 24
Finished Aug 11 04:27:24 PM PDT 24
Peak memory 199684 kb
Host smart-90da3b78-c068-48e1-847d-5eccea07f7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179935899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3179935899
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.1591930249
Short name T725
Test name
Test status
Simulation time 24049888701 ps
CPU time 45.33 seconds
Started Aug 11 04:27:31 PM PDT 24
Finished Aug 11 04:28:16 PM PDT 24
Peak memory 199788 kb
Host smart-f8fbdf4d-9378-4ca4-965b-9747a624011e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591930249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1591930249
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3229682448
Short name T551
Test name
Test status
Simulation time 105263487266 ps
CPU time 90.16 seconds
Started Aug 11 04:27:17 PM PDT 24
Finished Aug 11 04:28:48 PM PDT 24
Peak memory 199756 kb
Host smart-d7052dad-4e15-4758-a113-9a6f7fef4122
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3229682448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3229682448
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3989495475
Short name T851
Test name
Test status
Simulation time 3137875045 ps
CPU time 5.97 seconds
Started Aug 11 04:27:28 PM PDT 24
Finished Aug 11 04:27:34 PM PDT 24
Peak memory 198960 kb
Host smart-2dc74645-0b61-4684-beb1-a6fe5aa031e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989495475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3989495475
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.202290220
Short name T919
Test name
Test status
Simulation time 72118005585 ps
CPU time 121.58 seconds
Started Aug 11 04:27:18 PM PDT 24
Finished Aug 11 04:29:19 PM PDT 24
Peak memory 199832 kb
Host smart-46ef5bb3-0148-408d-bdf0-3c97bf952fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202290220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.202290220
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.1809921820
Short name T674
Test name
Test status
Simulation time 8465019502 ps
CPU time 90.08 seconds
Started Aug 11 04:27:18 PM PDT 24
Finished Aug 11 04:28:48 PM PDT 24
Peak memory 199628 kb
Host smart-6f06fbd2-b9bb-4f00-ab15-35886cce9fe8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1809921820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1809921820
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.351346244
Short name T487
Test name
Test status
Simulation time 6455334370 ps
CPU time 25.1 seconds
Started Aug 11 04:27:25 PM PDT 24
Finished Aug 11 04:27:50 PM PDT 24
Peak memory 197876 kb
Host smart-1405f6b4-ef2b-45e3-9aab-4369c38f2dfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=351346244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.351346244
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1003128173
Short name T766
Test name
Test status
Simulation time 78425602797 ps
CPU time 23.4 seconds
Started Aug 11 04:27:21 PM PDT 24
Finished Aug 11 04:27:45 PM PDT 24
Peak memory 199548 kb
Host smart-f4658638-7309-4cbf-8cff-8b542c86b57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003128173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1003128173
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1866176593
Short name T398
Test name
Test status
Simulation time 2898994829 ps
CPU time 4.63 seconds
Started Aug 11 04:27:21 PM PDT 24
Finished Aug 11 04:27:26 PM PDT 24
Peak memory 196376 kb
Host smart-9fefa896-b21b-463d-8837-70e3e58fdec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866176593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1866176593
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2766449768
Short name T315
Test name
Test status
Simulation time 953625801 ps
CPU time 1.53 seconds
Started Aug 11 04:27:12 PM PDT 24
Finished Aug 11 04:27:14 PM PDT 24
Peak memory 199512 kb
Host smart-9957c5e7-5eb8-437b-8081-849ac9a1f033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766449768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2766449768
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1250777625
Short name T862
Test name
Test status
Simulation time 337083337724 ps
CPU time 666.95 seconds
Started Aug 11 04:27:24 PM PDT 24
Finished Aug 11 04:38:31 PM PDT 24
Peak memory 224616 kb
Host smart-e9209138-483c-4912-8799-b9e11d1d0415
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250777625 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1250777625
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3702353490
Short name T931
Test name
Test status
Simulation time 1352248625 ps
CPU time 2.18 seconds
Started Aug 11 04:27:19 PM PDT 24
Finished Aug 11 04:27:21 PM PDT 24
Peak memory 198416 kb
Host smart-938d5ed8-381b-4b1c-8650-021a15c3c514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702353490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3702353490
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1083234007
Short name T654
Test name
Test status
Simulation time 62037753360 ps
CPU time 36.53 seconds
Started Aug 11 04:27:23 PM PDT 24
Finished Aug 11 04:28:00 PM PDT 24
Peak memory 199752 kb
Host smart-34f5d552-05ef-4232-96a2-f29340b314de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083234007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1083234007
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2619633611
Short name T384
Test name
Test status
Simulation time 36511195 ps
CPU time 0.54 seconds
Started Aug 11 04:27:29 PM PDT 24
Finished Aug 11 04:27:30 PM PDT 24
Peak memory 195184 kb
Host smart-9fb8b2ed-4543-41df-bd65-07ed9cd9a183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619633611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2619633611
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2469292474
Short name T752
Test name
Test status
Simulation time 223895551482 ps
CPU time 179.86 seconds
Started Aug 11 04:27:30 PM PDT 24
Finished Aug 11 04:30:30 PM PDT 24
Peak memory 199768 kb
Host smart-3e55ae54-bd48-4941-94b4-72dbaa041e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469292474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2469292474
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3892955648
Short name T143
Test name
Test status
Simulation time 23509154947 ps
CPU time 36.87 seconds
Started Aug 11 04:27:16 PM PDT 24
Finished Aug 11 04:27:53 PM PDT 24
Peak memory 199772 kb
Host smart-665e3538-90f0-4de2-978f-47bcfb1626d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892955648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3892955648
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.4115331446
Short name T1087
Test name
Test status
Simulation time 15667945187 ps
CPU time 22.62 seconds
Started Aug 11 04:27:16 PM PDT 24
Finished Aug 11 04:27:39 PM PDT 24
Peak memory 199800 kb
Host smart-3fe3ba85-ca45-461b-bce4-ba16ec5b668e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115331446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.4115331446
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.1901230461
Short name T343
Test name
Test status
Simulation time 94293945464 ps
CPU time 38.64 seconds
Started Aug 11 04:27:16 PM PDT 24
Finished Aug 11 04:27:54 PM PDT 24
Peak memory 199680 kb
Host smart-52f12073-206a-4d2d-a81b-6ed3daa9dcdb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901230461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1901230461
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.53453037
Short name T1051
Test name
Test status
Simulation time 87627225543 ps
CPU time 599.97 seconds
Started Aug 11 04:27:19 PM PDT 24
Finished Aug 11 04:37:20 PM PDT 24
Peak memory 199748 kb
Host smart-f109f47c-8ab4-4129-b014-2d7c87db7ddb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=53453037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.53453037
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3939946748
Short name T948
Test name
Test status
Simulation time 101865638 ps
CPU time 0.79 seconds
Started Aug 11 04:27:21 PM PDT 24
Finished Aug 11 04:27:22 PM PDT 24
Peak memory 195888 kb
Host smart-4b3f45ef-5484-4324-89e4-97f7d9c19038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939946748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3939946748
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3775421563
Short name T1169
Test name
Test status
Simulation time 186168300684 ps
CPU time 88.11 seconds
Started Aug 11 04:27:28 PM PDT 24
Finished Aug 11 04:28:56 PM PDT 24
Peak memory 199912 kb
Host smart-ec12318a-a771-4f79-af48-218a6995cb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775421563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3775421563
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3336092607
Short name T935
Test name
Test status
Simulation time 4985184462 ps
CPU time 294.25 seconds
Started Aug 11 04:27:26 PM PDT 24
Finished Aug 11 04:32:20 PM PDT 24
Peak memory 199668 kb
Host smart-ee12ab33-d873-4e60-b664-4467f164768c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3336092607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3336092607
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.2431446781
Short name T619
Test name
Test status
Simulation time 2430307537 ps
CPU time 4.04 seconds
Started Aug 11 04:27:20 PM PDT 24
Finished Aug 11 04:27:24 PM PDT 24
Peak memory 198760 kb
Host smart-18b83bea-b37e-4353-86c2-bb73bdbd4a1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2431446781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.2431446781
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3860199504
Short name T397
Test name
Test status
Simulation time 121770657727 ps
CPU time 408.25 seconds
Started Aug 11 04:27:27 PM PDT 24
Finished Aug 11 04:34:16 PM PDT 24
Peak memory 199704 kb
Host smart-bc92f460-0e37-41c4-ad8d-7611da481293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860199504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3860199504
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.1097593401
Short name T659
Test name
Test status
Simulation time 648974648 ps
CPU time 1.67 seconds
Started Aug 11 04:27:25 PM PDT 24
Finished Aug 11 04:27:27 PM PDT 24
Peak memory 195296 kb
Host smart-f7a79ecb-b38e-4e5b-8445-99628f54e310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097593401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1097593401
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.72173624
Short name T1153
Test name
Test status
Simulation time 518359437 ps
CPU time 1.99 seconds
Started Aug 11 04:27:13 PM PDT 24
Finished Aug 11 04:27:15 PM PDT 24
Peak memory 199408 kb
Host smart-6d543d02-0e68-4086-bc84-d4d453178e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72173624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.72173624
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.2301313866
Short name T1159
Test name
Test status
Simulation time 153390085132 ps
CPU time 227.96 seconds
Started Aug 11 04:27:26 PM PDT 24
Finished Aug 11 04:31:14 PM PDT 24
Peak memory 199824 kb
Host smart-0fb2fa18-0b14-47c0-a84a-75cfcd7db452
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301313866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2301313866
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.125039070
Short name T1168
Test name
Test status
Simulation time 672401145 ps
CPU time 1.76 seconds
Started Aug 11 04:27:23 PM PDT 24
Finished Aug 11 04:27:25 PM PDT 24
Peak memory 198432 kb
Host smart-42507a45-8b00-48ba-8dfd-7325b5175e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125039070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.125039070
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.2257267778
Short name T712
Test name
Test status
Simulation time 46971115073 ps
CPU time 13.48 seconds
Started Aug 11 04:27:20 PM PDT 24
Finished Aug 11 04:27:34 PM PDT 24
Peak memory 198700 kb
Host smart-efcd8682-51fe-482b-b636-63edc3a9b65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257267778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2257267778
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.658071742
Short name T963
Test name
Test status
Simulation time 22291079 ps
CPU time 0.61 seconds
Started Aug 11 04:27:36 PM PDT 24
Finished Aug 11 04:27:37 PM PDT 24
Peak memory 195128 kb
Host smart-904a1c8b-5f7d-426c-96e0-26b38d156a00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658071742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.658071742
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.525177976
Short name T550
Test name
Test status
Simulation time 149662698135 ps
CPU time 128.78 seconds
Started Aug 11 04:27:29 PM PDT 24
Finished Aug 11 04:29:38 PM PDT 24
Peak memory 199668 kb
Host smart-1b4e8e77-8aef-4776-b881-dc11ebb44e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525177976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.525177976
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.2939941181
Short name T177
Test name
Test status
Simulation time 42967690730 ps
CPU time 18.33 seconds
Started Aug 11 04:27:28 PM PDT 24
Finished Aug 11 04:27:47 PM PDT 24
Peak memory 199904 kb
Host smart-62895a5c-9ae0-4ab3-9342-1d92356046fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939941181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2939941181
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3335908992
Short name T1004
Test name
Test status
Simulation time 106118025290 ps
CPU time 41.76 seconds
Started Aug 11 04:27:23 PM PDT 24
Finished Aug 11 04:28:05 PM PDT 24
Peak memory 199656 kb
Host smart-2f179abc-7764-4886-a8ff-0729b5b5a63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335908992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3335908992
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2987489095
Short name T836
Test name
Test status
Simulation time 16515072498 ps
CPU time 29.85 seconds
Started Aug 11 04:27:21 PM PDT 24
Finished Aug 11 04:27:51 PM PDT 24
Peak memory 199696 kb
Host smart-09cb1645-a6bc-4380-a5b2-d69318ad2842
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987489095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2987489095
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3157517562
Short name T716
Test name
Test status
Simulation time 90798330045 ps
CPU time 254.69 seconds
Started Aug 11 04:27:35 PM PDT 24
Finished Aug 11 04:31:50 PM PDT 24
Peak memory 199700 kb
Host smart-b764052d-4556-40c8-83f9-2b0bfe6e821c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3157517562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3157517562
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2056676479
Short name T915
Test name
Test status
Simulation time 2879194275 ps
CPU time 5.55 seconds
Started Aug 11 04:27:21 PM PDT 24
Finished Aug 11 04:27:26 PM PDT 24
Peak memory 198352 kb
Host smart-85c0a4c3-47f6-4dbd-8466-1109b7e3759e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056676479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2056676479
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_perf.976092022
Short name T923
Test name
Test status
Simulation time 6662192390 ps
CPU time 344.62 seconds
Started Aug 11 04:27:17 PM PDT 24
Finished Aug 11 04:33:02 PM PDT 24
Peak memory 199700 kb
Host smart-685c3b2a-7b19-4e2f-b3f7-6d1975a1a7fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=976092022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.976092022
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.1753259716
Short name T567
Test name
Test status
Simulation time 5495364782 ps
CPU time 13.19 seconds
Started Aug 11 04:27:18 PM PDT 24
Finished Aug 11 04:27:31 PM PDT 24
Peak memory 197868 kb
Host smart-af718abd-75fe-4ff1-b26b-65541a362ced
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1753259716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.1753259716
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3823971619
Short name T415
Test name
Test status
Simulation time 3370074629 ps
CPU time 10.88 seconds
Started Aug 11 04:27:28 PM PDT 24
Finished Aug 11 04:27:39 PM PDT 24
Peak memory 199832 kb
Host smart-48a82747-8d15-496f-be5c-e3b67bd3aed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823971619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3823971619
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.99374331
Short name T474
Test name
Test status
Simulation time 40462737625 ps
CPU time 4.52 seconds
Started Aug 11 04:27:28 PM PDT 24
Finished Aug 11 04:27:32 PM PDT 24
Peak memory 195832 kb
Host smart-8fe75ea9-5e67-4222-b719-627125385362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99374331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.99374331
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3528372413
Short name T1027
Test name
Test status
Simulation time 5668144233 ps
CPU time 10.53 seconds
Started Aug 11 04:27:29 PM PDT 24
Finished Aug 11 04:27:40 PM PDT 24
Peak memory 199544 kb
Host smart-44dcbe60-2f73-4bce-834e-ec428c0a4088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528372413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3528372413
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1790036125
Short name T658
Test name
Test status
Simulation time 332528847108 ps
CPU time 983.16 seconds
Started Aug 11 04:27:30 PM PDT 24
Finished Aug 11 04:43:54 PM PDT 24
Peak memory 224608 kb
Host smart-b2fde834-ad13-4188-ab4b-cf7481d3e064
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790036125 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1790036125
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1574984555
Short name T612
Test name
Test status
Simulation time 543259091 ps
CPU time 1.84 seconds
Started Aug 11 04:27:24 PM PDT 24
Finished Aug 11 04:27:26 PM PDT 24
Peak memory 198932 kb
Host smart-f61331d5-fe8f-4f0f-9a18-b11e581553c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574984555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1574984555
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2087324918
Short name T607
Test name
Test status
Simulation time 38173284245 ps
CPU time 67.76 seconds
Started Aug 11 04:27:22 PM PDT 24
Finished Aug 11 04:28:29 PM PDT 24
Peak memory 199728 kb
Host smart-7c4db117-0ff4-4099-96dc-d51ad4b163f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087324918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2087324918
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2906641790
Short name T624
Test name
Test status
Simulation time 46528950 ps
CPU time 0.56 seconds
Started Aug 11 04:27:44 PM PDT 24
Finished Aug 11 04:27:45 PM PDT 24
Peak memory 195156 kb
Host smart-ea4ca610-b768-46f9-a3e2-4087de08b86c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906641790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2906641790
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.830491562
Short name T380
Test name
Test status
Simulation time 9175287216 ps
CPU time 8.24 seconds
Started Aug 11 04:27:23 PM PDT 24
Finished Aug 11 04:27:32 PM PDT 24
Peak memory 199688 kb
Host smart-c246a123-6edb-4bf7-b977-6186848c2fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830491562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.830491562
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.397226791
Short name T483
Test name
Test status
Simulation time 26293621311 ps
CPU time 44.17 seconds
Started Aug 11 04:27:21 PM PDT 24
Finished Aug 11 04:28:05 PM PDT 24
Peak memory 199736 kb
Host smart-68531572-1bb8-40f8-9de7-82420423bf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397226791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.397226791
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.2932659873
Short name T216
Test name
Test status
Simulation time 17019082657 ps
CPU time 20.1 seconds
Started Aug 11 04:27:26 PM PDT 24
Finished Aug 11 04:27:46 PM PDT 24
Peak memory 199824 kb
Host smart-b34d24d9-ff58-40fb-be8a-f50bd0cc1295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932659873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2932659873
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.1559779559
Short name T608
Test name
Test status
Simulation time 184172012246 ps
CPU time 170.02 seconds
Started Aug 11 04:27:30 PM PDT 24
Finished Aug 11 04:30:21 PM PDT 24
Peak memory 199520 kb
Host smart-49009fba-827e-4c3a-af5f-7fde36ffaa84
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559779559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.1559779559
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1129564714
Short name T685
Test name
Test status
Simulation time 52493395273 ps
CPU time 269.49 seconds
Started Aug 11 04:27:34 PM PDT 24
Finished Aug 11 04:32:04 PM PDT 24
Peak memory 199756 kb
Host smart-31265e38-2576-4521-a66f-81b4a630a595
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1129564714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1129564714
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.4132596094
Short name T442
Test name
Test status
Simulation time 3029612487 ps
CPU time 2.34 seconds
Started Aug 11 04:27:17 PM PDT 24
Finished Aug 11 04:27:20 PM PDT 24
Peak memory 199332 kb
Host smart-2f9703bd-cd12-4260-a946-a441806d6621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132596094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.4132596094
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.1984517992
Short name T885
Test name
Test status
Simulation time 38856476585 ps
CPU time 67.43 seconds
Started Aug 11 04:27:18 PM PDT 24
Finished Aug 11 04:28:25 PM PDT 24
Peak memory 199796 kb
Host smart-7e4ac43f-9dc6-49cb-9926-eb06f41b4e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984517992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1984517992
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.3985376565
Short name T922
Test name
Test status
Simulation time 10576574545 ps
CPU time 46.85 seconds
Started Aug 11 04:27:31 PM PDT 24
Finished Aug 11 04:28:18 PM PDT 24
Peak memory 199716 kb
Host smart-688be84d-f46e-4a8e-8a5e-e532dbf9f3f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3985376565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3985376565
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.824916482
Short name T353
Test name
Test status
Simulation time 4750224969 ps
CPU time 38.56 seconds
Started Aug 11 04:27:36 PM PDT 24
Finished Aug 11 04:28:15 PM PDT 24
Peak memory 198116 kb
Host smart-cc104d01-5318-4057-8ff7-3d8a27f767c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=824916482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.824916482
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2829191193
Short name T1112
Test name
Test status
Simulation time 92494601686 ps
CPU time 157.64 seconds
Started Aug 11 04:27:28 PM PDT 24
Finished Aug 11 04:30:05 PM PDT 24
Peak memory 199728 kb
Host smart-fcffacc4-cbfb-410b-be9a-e3f1a7611cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829191193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2829191193
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2958802615
Short name T627
Test name
Test status
Simulation time 38217957267 ps
CPU time 20.04 seconds
Started Aug 11 04:27:36 PM PDT 24
Finished Aug 11 04:27:56 PM PDT 24
Peak memory 195848 kb
Host smart-4a44458d-9b65-4f23-84ad-74d704e328b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958802615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2958802615
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.208469663
Short name T486
Test name
Test status
Simulation time 670023608 ps
CPU time 1.59 seconds
Started Aug 11 04:27:21 PM PDT 24
Finished Aug 11 04:27:23 PM PDT 24
Peak memory 199600 kb
Host smart-0a1a602f-e87c-4e29-a1a6-a3d3de47faa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208469663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.208469663
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.2174589470
Short name T784
Test name
Test status
Simulation time 67563786993 ps
CPU time 67.57 seconds
Started Aug 11 04:27:33 PM PDT 24
Finished Aug 11 04:28:41 PM PDT 24
Peak memory 199912 kb
Host smart-770cf1b8-3753-462c-a1f4-d6ea825784fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174589470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2174589470
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.2941037145
Short name T54
Test name
Test status
Simulation time 191159559619 ps
CPU time 250.81 seconds
Started Aug 11 04:27:43 PM PDT 24
Finished Aug 11 04:31:54 PM PDT 24
Peak memory 216328 kb
Host smart-10c1ab3d-b1b7-4b9f-be14-bbfae0d6114a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941037145 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.2941037145
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.3896423450
Short name T298
Test name
Test status
Simulation time 1512833970 ps
CPU time 1.36 seconds
Started Aug 11 04:27:36 PM PDT 24
Finished Aug 11 04:27:38 PM PDT 24
Peak memory 198136 kb
Host smart-9eabb275-cb7a-42e4-874f-024e49329713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896423450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3896423450
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.1446898012
Short name T310
Test name
Test status
Simulation time 161140212727 ps
CPU time 174.52 seconds
Started Aug 11 04:27:34 PM PDT 24
Finished Aug 11 04:30:29 PM PDT 24
Peak memory 199792 kb
Host smart-d3439cd1-318a-4c44-948b-eaa68dba85f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446898012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1446898012
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1458655701
Short name T668
Test name
Test status
Simulation time 33639328 ps
CPU time 0.54 seconds
Started Aug 11 04:27:39 PM PDT 24
Finished Aug 11 04:27:40 PM PDT 24
Peak memory 194540 kb
Host smart-ab6321f0-dcc7-46b9-b7d2-6f91fd30e46b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458655701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1458655701
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.1099878217
Short name T768
Test name
Test status
Simulation time 293825525330 ps
CPU time 248.28 seconds
Started Aug 11 04:27:43 PM PDT 24
Finished Aug 11 04:31:52 PM PDT 24
Peak memory 199664 kb
Host smart-799e0c90-5fd4-47b6-b613-2c4cdcaac62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099878217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1099878217
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3484330629
Short name T187
Test name
Test status
Simulation time 173083346116 ps
CPU time 16.27 seconds
Started Aug 11 04:27:45 PM PDT 24
Finished Aug 11 04:28:02 PM PDT 24
Peak memory 199716 kb
Host smart-63727f91-ffea-4b7d-9600-ce1b8621b6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484330629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3484330629
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.4216595191
Short name T289
Test name
Test status
Simulation time 96331078879 ps
CPU time 125.99 seconds
Started Aug 11 04:27:22 PM PDT 24
Finished Aug 11 04:29:28 PM PDT 24
Peak memory 199728 kb
Host smart-3e4771a1-187c-4c1c-8aaf-89102150c81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216595191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.4216595191
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.2389778856
Short name T777
Test name
Test status
Simulation time 16021227761 ps
CPU time 24.45 seconds
Started Aug 11 04:27:47 PM PDT 24
Finished Aug 11 04:28:11 PM PDT 24
Peak memory 198292 kb
Host smart-45f00425-6593-4530-b352-2c61e6c1a0e9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389778856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2389778856
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.602593434
Short name T981
Test name
Test status
Simulation time 208448281495 ps
CPU time 99.12 seconds
Started Aug 11 04:27:48 PM PDT 24
Finished Aug 11 04:29:27 PM PDT 24
Peak memory 199684 kb
Host smart-bc8364d4-dd81-40dd-a092-efa3371a7a20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=602593434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.602593434
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.673369616
Short name T124
Test name
Test status
Simulation time 3284274120 ps
CPU time 1.66 seconds
Started Aug 11 04:27:40 PM PDT 24
Finished Aug 11 04:27:42 PM PDT 24
Peak memory 198576 kb
Host smart-7de104a7-a5cb-4a8f-8c9c-70191d407e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673369616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.673369616
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3519202621
Short name T446
Test name
Test status
Simulation time 2819819014 ps
CPU time 5.66 seconds
Started Aug 11 04:27:26 PM PDT 24
Finished Aug 11 04:27:32 PM PDT 24
Peak memory 195888 kb
Host smart-8f9a33ba-9883-49a7-ac2f-4159b3517a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519202621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3519202621
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1421203419
Short name T529
Test name
Test status
Simulation time 14455069154 ps
CPU time 167.56 seconds
Started Aug 11 04:27:22 PM PDT 24
Finished Aug 11 04:30:10 PM PDT 24
Peak memory 199696 kb
Host smart-801b76ce-70f3-4494-8080-00f2bafcafd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1421203419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1421203419
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3982059656
Short name T1178
Test name
Test status
Simulation time 5580136748 ps
CPU time 12.19 seconds
Started Aug 11 04:27:37 PM PDT 24
Finished Aug 11 04:27:50 PM PDT 24
Peak memory 198784 kb
Host smart-91771402-cfaf-446c-8ced-db73efadd865
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3982059656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3982059656
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.820079669
Short name T288
Test name
Test status
Simulation time 111570627370 ps
CPU time 238.61 seconds
Started Aug 11 04:27:25 PM PDT 24
Finished Aug 11 04:31:24 PM PDT 24
Peak memory 199648 kb
Host smart-9feed2d6-7bbf-41f7-9369-2ce73559c94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820079669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.820079669
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.685279309
Short name T525
Test name
Test status
Simulation time 4462370236 ps
CPU time 2.19 seconds
Started Aug 11 04:27:35 PM PDT 24
Finished Aug 11 04:27:38 PM PDT 24
Peak memory 196252 kb
Host smart-ac45cada-15c2-49a9-8fd4-d048c8aedc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685279309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.685279309
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.2542990959
Short name T295
Test name
Test status
Simulation time 11089812801 ps
CPU time 11.94 seconds
Started Aug 11 04:27:33 PM PDT 24
Finished Aug 11 04:27:45 PM PDT 24
Peak memory 199832 kb
Host smart-be8fb5f1-705a-4cc1-8076-3384de5a578c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542990959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2542990959
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2005570096
Short name T775
Test name
Test status
Simulation time 147301242899 ps
CPU time 503.48 seconds
Started Aug 11 04:27:26 PM PDT 24
Finished Aug 11 04:35:50 PM PDT 24
Peak memory 199784 kb
Host smart-89278098-8e5a-4a05-9492-03d93257881d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005570096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2005570096
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.3211167107
Short name T171
Test name
Test status
Simulation time 381022057687 ps
CPU time 1246.56 seconds
Started Aug 11 04:27:48 PM PDT 24
Finished Aug 11 04:48:35 PM PDT 24
Peak memory 224388 kb
Host smart-78888686-f633-44a0-87dc-27a3228f15ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211167107 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.3211167107
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1910221142
Short name T422
Test name
Test status
Simulation time 822734738 ps
CPU time 3.76 seconds
Started Aug 11 04:27:33 PM PDT 24
Finished Aug 11 04:27:37 PM PDT 24
Peak memory 198156 kb
Host smart-8c02ea71-cabf-4919-919e-9e898cc1fb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910221142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1910221142
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.485146791
Short name T423
Test name
Test status
Simulation time 1799434346 ps
CPU time 3.73 seconds
Started Aug 11 04:27:29 PM PDT 24
Finished Aug 11 04:27:33 PM PDT 24
Peak memory 197428 kb
Host smart-0bcf3d62-ffc6-408b-95f9-90d44d731281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485146791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.485146791
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.3525546933
Short name T720
Test name
Test status
Simulation time 45593203 ps
CPU time 0.57 seconds
Started Aug 11 04:26:05 PM PDT 24
Finished Aug 11 04:26:06 PM PDT 24
Peak memory 195356 kb
Host smart-236c8892-3a5c-4a04-875c-5b0fbc204e45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525546933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3525546933
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.3909969308
Short name T1038
Test name
Test status
Simulation time 49144370704 ps
CPU time 78.75 seconds
Started Aug 11 04:26:22 PM PDT 24
Finished Aug 11 04:27:41 PM PDT 24
Peak memory 199700 kb
Host smart-bda48e3e-7b54-43c0-bf0f-11882d06c25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909969308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3909969308
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1044563763
Short name T1002
Test name
Test status
Simulation time 139114816947 ps
CPU time 38.89 seconds
Started Aug 11 04:26:34 PM PDT 24
Finished Aug 11 04:27:13 PM PDT 24
Peak memory 199632 kb
Host smart-e2ce687d-6cd2-4250-9dd2-8486308dffb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044563763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1044563763
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.987731194
Short name T1068
Test name
Test status
Simulation time 43610774179 ps
CPU time 29.03 seconds
Started Aug 11 04:26:04 PM PDT 24
Finished Aug 11 04:26:33 PM PDT 24
Peak memory 199700 kb
Host smart-54e49ecd-da0b-46a0-8e69-ad04d24b7ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987731194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.987731194
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.249406873
Short name T574
Test name
Test status
Simulation time 37505902058 ps
CPU time 59.85 seconds
Started Aug 11 04:26:05 PM PDT 24
Finished Aug 11 04:27:05 PM PDT 24
Peak memory 199668 kb
Host smart-7cb4efe0-b168-438c-88f7-75764560f483
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249406873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.249406873
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3443903202
Short name T361
Test name
Test status
Simulation time 151745140126 ps
CPU time 514.79 seconds
Started Aug 11 04:26:14 PM PDT 24
Finished Aug 11 04:34:49 PM PDT 24
Peak memory 199780 kb
Host smart-ed682b2f-1248-49e6-a76f-23061c6ce4cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3443903202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3443903202
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.644098278
Short name T726
Test name
Test status
Simulation time 9422663875 ps
CPU time 3.91 seconds
Started Aug 11 04:26:00 PM PDT 24
Finished Aug 11 04:26:04 PM PDT 24
Peak memory 199424 kb
Host smart-bf03a86d-198a-4549-88c9-cb2644160c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644098278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.644098278
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.2135538808
Short name T344
Test name
Test status
Simulation time 14335268486 ps
CPU time 11.04 seconds
Started Aug 11 04:26:00 PM PDT 24
Finished Aug 11 04:26:11 PM PDT 24
Peak memory 194280 kb
Host smart-2fa9f6ec-c590-4dca-948a-d462e53be93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135538808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2135538808
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.910383961
Short name T385
Test name
Test status
Simulation time 17444124557 ps
CPU time 261.61 seconds
Started Aug 11 04:26:04 PM PDT 24
Finished Aug 11 04:30:26 PM PDT 24
Peak memory 199656 kb
Host smart-fe0ed239-d593-48d6-a70a-1a6f98aaa39e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=910383961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.910383961
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.646127854
Short name T464
Test name
Test status
Simulation time 3492975456 ps
CPU time 23.26 seconds
Started Aug 11 04:26:08 PM PDT 24
Finished Aug 11 04:26:31 PM PDT 24
Peak memory 198884 kb
Host smart-49e71ff7-613e-47c4-a01e-1439854884a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=646127854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.646127854
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2963352453
Short name T151
Test name
Test status
Simulation time 29172076002 ps
CPU time 42.96 seconds
Started Aug 11 04:26:12 PM PDT 24
Finished Aug 11 04:26:55 PM PDT 24
Peak memory 199656 kb
Host smart-70b68c0f-e3b3-492e-af37-b19daec9900e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963352453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2963352453
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.3623106610
Short name T656
Test name
Test status
Simulation time 1799287636 ps
CPU time 3.19 seconds
Started Aug 11 04:26:01 PM PDT 24
Finished Aug 11 04:26:04 PM PDT 24
Peak memory 195260 kb
Host smart-fe38a9ac-42be-4354-9abc-e84fe0e39085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623106610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3623106610
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.569283116
Short name T27
Test name
Test status
Simulation time 58971745 ps
CPU time 0.86 seconds
Started Aug 11 04:26:35 PM PDT 24
Finished Aug 11 04:26:36 PM PDT 24
Peak memory 218032 kb
Host smart-5b06cf06-7d43-48a9-8d1a-82c4ae4d196b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569283116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.569283116
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.790237596
Short name T748
Test name
Test status
Simulation time 550318840 ps
CPU time 2 seconds
Started Aug 11 04:26:02 PM PDT 24
Finished Aug 11 04:26:04 PM PDT 24
Peak memory 198800 kb
Host smart-bec6f7fa-bf22-4bc1-807c-e562bdc1f41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790237596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.790237596
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.3977505298
Short name T562
Test name
Test status
Simulation time 56753126632 ps
CPU time 27.97 seconds
Started Aug 11 04:26:13 PM PDT 24
Finished Aug 11 04:26:41 PM PDT 24
Peak memory 199892 kb
Host smart-f91e0752-a720-4928-aa33-172428d9ae57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977505298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3977505298
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.2764573710
Short name T855
Test name
Test status
Simulation time 222914394361 ps
CPU time 972.7 seconds
Started Aug 11 04:26:37 PM PDT 24
Finished Aug 11 04:42:50 PM PDT 24
Peak memory 224504 kb
Host smart-d14e7f62-237b-4411-b72e-8e240c0e2b20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764573710 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2764573710
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.4159299943
Short name T451
Test name
Test status
Simulation time 1306464241 ps
CPU time 1.48 seconds
Started Aug 11 04:26:00 PM PDT 24
Finished Aug 11 04:26:01 PM PDT 24
Peak memory 199020 kb
Host smart-fe409142-e38a-4195-8369-15ae2e097ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159299943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.4159299943
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3896483739
Short name T889
Test name
Test status
Simulation time 112164641939 ps
CPU time 44.18 seconds
Started Aug 11 04:26:10 PM PDT 24
Finished Aug 11 04:26:54 PM PDT 24
Peak memory 199744 kb
Host smart-07dfeecd-0a43-4161-9114-7fdd68815d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896483739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3896483739
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.3268724119
Short name T876
Test name
Test status
Simulation time 12851270 ps
CPU time 0.57 seconds
Started Aug 11 04:27:33 PM PDT 24
Finished Aug 11 04:27:33 PM PDT 24
Peak memory 194544 kb
Host smart-f974ef98-4e98-44ff-86ec-47f94e6410de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268724119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3268724119
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2487567165
Short name T621
Test name
Test status
Simulation time 32619819288 ps
CPU time 64.01 seconds
Started Aug 11 04:27:49 PM PDT 24
Finished Aug 11 04:28:53 PM PDT 24
Peak memory 199660 kb
Host smart-15c6d7b6-0563-4e4d-84b3-15bc711a23ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487567165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2487567165
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2201415956
Short name T934
Test name
Test status
Simulation time 119104416573 ps
CPU time 87.32 seconds
Started Aug 11 04:27:36 PM PDT 24
Finished Aug 11 04:29:03 PM PDT 24
Peak memory 199772 kb
Host smart-ef69ea0d-14af-4441-bc53-3c93b7bc282f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201415956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2201415956
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.493279700
Short name T505
Test name
Test status
Simulation time 12499040987 ps
CPU time 18.2 seconds
Started Aug 11 04:27:54 PM PDT 24
Finished Aug 11 04:28:13 PM PDT 24
Peak memory 199512 kb
Host smart-9fa4b888-65ca-4bcf-ba3e-8d2848a03ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493279700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.493279700
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.2517794770
Short name T743
Test name
Test status
Simulation time 26838037788 ps
CPU time 10.87 seconds
Started Aug 11 04:27:45 PM PDT 24
Finished Aug 11 04:27:56 PM PDT 24
Peak memory 199696 kb
Host smart-e44de1e8-651a-4bdf-a392-33c9ea8464b6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517794770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2517794770
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3139859309
Short name T389
Test name
Test status
Simulation time 69108034297 ps
CPU time 319.69 seconds
Started Aug 11 04:27:51 PM PDT 24
Finished Aug 11 04:33:11 PM PDT 24
Peak memory 199696 kb
Host smart-79ef055c-e1d3-4764-99ec-dabdcb95855d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3139859309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3139859309
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.4234228543
Short name T710
Test name
Test status
Simulation time 9054928836 ps
CPU time 17.55 seconds
Started Aug 11 04:27:46 PM PDT 24
Finished Aug 11 04:28:04 PM PDT 24
Peak memory 198928 kb
Host smart-1c546e3a-f172-49d4-bb4c-d965f25ea773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234228543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.4234228543
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.2680598614
Short name T678
Test name
Test status
Simulation time 202370821066 ps
CPU time 109.81 seconds
Started Aug 11 04:27:46 PM PDT 24
Finished Aug 11 04:29:36 PM PDT 24
Peak memory 208140 kb
Host smart-ef5e1b55-99e6-427b-b074-22a5fe7f58ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680598614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2680598614
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.1805215241
Short name T1156
Test name
Test status
Simulation time 15792721874 ps
CPU time 76.18 seconds
Started Aug 11 04:27:43 PM PDT 24
Finished Aug 11 04:28:59 PM PDT 24
Peak memory 199292 kb
Host smart-81b824e0-0df2-4117-bdf9-fd5204938562
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1805215241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1805215241
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.4060675402
Short name T771
Test name
Test status
Simulation time 3702800991 ps
CPU time 10.75 seconds
Started Aug 11 04:27:38 PM PDT 24
Finished Aug 11 04:27:49 PM PDT 24
Peak memory 197712 kb
Host smart-1bb82daf-57f3-47fc-a5ad-afaa0645e7b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4060675402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.4060675402
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.14365802
Short name T174
Test name
Test status
Simulation time 42682933541 ps
CPU time 23.97 seconds
Started Aug 11 04:27:33 PM PDT 24
Finished Aug 11 04:27:57 PM PDT 24
Peak memory 199744 kb
Host smart-ea736a0b-44a7-4a50-8ce8-9b22e39c2af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14365802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.14365802
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.472236632
Short name T988
Test name
Test status
Simulation time 2016004194 ps
CPU time 3.4 seconds
Started Aug 11 04:27:36 PM PDT 24
Finished Aug 11 04:27:40 PM PDT 24
Peak memory 195452 kb
Host smart-90bfe9ed-80b1-43e8-97c7-f3bda45298f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472236632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.472236632
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3164577889
Short name T741
Test name
Test status
Simulation time 701773446 ps
CPU time 1.23 seconds
Started Aug 11 04:27:40 PM PDT 24
Finished Aug 11 04:27:41 PM PDT 24
Peak memory 199484 kb
Host smart-bdb0e800-f595-4b95-8664-0e76914b3f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164577889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3164577889
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.1805089741
Short name T1028
Test name
Test status
Simulation time 30310881669 ps
CPU time 49.09 seconds
Started Aug 11 04:27:38 PM PDT 24
Finished Aug 11 04:28:27 PM PDT 24
Peak memory 199720 kb
Host smart-ba305f9f-fc64-496e-85d1-09b87af6fb0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805089741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1805089741
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.246681058
Short name T510
Test name
Test status
Simulation time 258949442080 ps
CPU time 211.34 seconds
Started Aug 11 04:27:36 PM PDT 24
Finished Aug 11 04:31:07 PM PDT 24
Peak memory 216200 kb
Host smart-d2a944f1-dc52-48bb-85eb-afcb546ef9b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246681058 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.246681058
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.104670529
Short name T1010
Test name
Test status
Simulation time 2326473369 ps
CPU time 1.83 seconds
Started Aug 11 04:27:36 PM PDT 24
Finished Aug 11 04:27:38 PM PDT 24
Peak memory 198816 kb
Host smart-7142230a-be5a-4d90-b078-7b3251ce2a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104670529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.104670529
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_alert_test.2147505227
Short name T957
Test name
Test status
Simulation time 71592762 ps
CPU time 0.56 seconds
Started Aug 11 04:27:33 PM PDT 24
Finished Aug 11 04:27:34 PM PDT 24
Peak memory 195176 kb
Host smart-ae9733b3-ebbe-4f75-8315-a8899c8737eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147505227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2147505227
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2483478747
Short name T1101
Test name
Test status
Simulation time 140468257510 ps
CPU time 114.05 seconds
Started Aug 11 04:27:32 PM PDT 24
Finished Aug 11 04:29:26 PM PDT 24
Peak memory 199740 kb
Host smart-47fe466a-8e58-47d2-9e5f-f8a94d0b1e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483478747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2483478747
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2874378238
Short name T391
Test name
Test status
Simulation time 116876607508 ps
CPU time 77.17 seconds
Started Aug 11 04:27:33 PM PDT 24
Finished Aug 11 04:28:50 PM PDT 24
Peak memory 199756 kb
Host smart-b000facc-ba4e-4a2e-bab4-fe787560bbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874378238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2874378238
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3813819
Short name T823
Test name
Test status
Simulation time 79407292229 ps
CPU time 60.11 seconds
Started Aug 11 04:27:32 PM PDT 24
Finished Aug 11 04:28:32 PM PDT 24
Peak memory 199708 kb
Host smart-6e51439d-279b-4f93-b285-bbd2a4f63e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3813819
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.3510762567
Short name T565
Test name
Test status
Simulation time 6593501147 ps
CPU time 2.93 seconds
Started Aug 11 04:27:36 PM PDT 24
Finished Aug 11 04:27:39 PM PDT 24
Peak memory 196224 kb
Host smart-ec61c0c5-085e-4359-ac4a-9d51a0882dee
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510762567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3510762567
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3119076597
Short name T701
Test name
Test status
Simulation time 65910697154 ps
CPU time 279.14 seconds
Started Aug 11 04:27:47 PM PDT 24
Finished Aug 11 04:32:27 PM PDT 24
Peak memory 199796 kb
Host smart-cda9307d-6b11-43bf-a601-907992c2e893
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3119076597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3119076597
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1051250066
Short name T357
Test name
Test status
Simulation time 9509830449 ps
CPU time 6.13 seconds
Started Aug 11 04:27:47 PM PDT 24
Finished Aug 11 04:27:53 PM PDT 24
Peak memory 198692 kb
Host smart-7695cdfc-f6c4-4351-bf9a-5aced8c40d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051250066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1051250066
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.3048250489
Short name T844
Test name
Test status
Simulation time 17083779556 ps
CPU time 24.69 seconds
Started Aug 11 04:27:33 PM PDT 24
Finished Aug 11 04:27:58 PM PDT 24
Peak memory 199892 kb
Host smart-0dc1856e-6aa6-499f-b736-715b404e0fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048250489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3048250489
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.4035373662
Short name T1125
Test name
Test status
Simulation time 5813739934 ps
CPU time 129.89 seconds
Started Aug 11 04:27:48 PM PDT 24
Finished Aug 11 04:29:58 PM PDT 24
Peak memory 199716 kb
Host smart-40d55dfa-b53a-4fcc-992a-ed42f616bde3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4035373662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.4035373662
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.2108005176
Short name T354
Test name
Test status
Simulation time 5211938296 ps
CPU time 42.9 seconds
Started Aug 11 04:27:46 PM PDT 24
Finished Aug 11 04:28:29 PM PDT 24
Peak memory 198016 kb
Host smart-ffa9707b-6049-4c28-806c-2f26b48b99a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2108005176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2108005176
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.251967295
Short name T893
Test name
Test status
Simulation time 74077050317 ps
CPU time 92.6 seconds
Started Aug 11 04:27:32 PM PDT 24
Finished Aug 11 04:29:05 PM PDT 24
Peak memory 199736 kb
Host smart-10260d2e-7cba-4ced-ab2a-13802bd80f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251967295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.251967295
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.566601333
Short name T395
Test name
Test status
Simulation time 31423812278 ps
CPU time 13.13 seconds
Started Aug 11 04:27:33 PM PDT 24
Finished Aug 11 04:27:46 PM PDT 24
Peak memory 195624 kb
Host smart-ce95f1ac-0077-484e-833c-11ab1bb9fb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566601333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.566601333
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.1689193071
Short name T4
Test name
Test status
Simulation time 665374591 ps
CPU time 2.74 seconds
Started Aug 11 04:27:33 PM PDT 24
Finished Aug 11 04:27:36 PM PDT 24
Peak memory 199592 kb
Host smart-b7fd36b1-7885-448f-b1b5-25371e767d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689193071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1689193071
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.1470153771
Short name T1061
Test name
Test status
Simulation time 22267994811 ps
CPU time 204.18 seconds
Started Aug 11 04:27:31 PM PDT 24
Finished Aug 11 04:30:55 PM PDT 24
Peak memory 211240 kb
Host smart-022a21f4-190a-43cf-a36b-26ee545a703b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470153771 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.1470153771
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1130244403
Short name T990
Test name
Test status
Simulation time 6467745589 ps
CPU time 22.55 seconds
Started Aug 11 04:27:47 PM PDT 24
Finished Aug 11 04:28:09 PM PDT 24
Peak memory 199412 kb
Host smart-c53fa4f5-3558-427c-8676-a0d125d277e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130244403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1130244403
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.850261579
Short name T271
Test name
Test status
Simulation time 183749073918 ps
CPU time 83.66 seconds
Started Aug 11 04:27:44 PM PDT 24
Finished Aug 11 04:29:07 PM PDT 24
Peak memory 199808 kb
Host smart-d3fc18bd-276d-4ff0-8504-66265d4f02b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850261579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.850261579
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.956954768
Short name T866
Test name
Test status
Simulation time 40282536 ps
CPU time 0.54 seconds
Started Aug 11 04:27:40 PM PDT 24
Finished Aug 11 04:27:40 PM PDT 24
Peak memory 195344 kb
Host smart-8b62db40-aba7-4574-9024-9644ab5a97ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956954768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.956954768
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.3768643511
Short name T1117
Test name
Test status
Simulation time 103184315488 ps
CPU time 44.33 seconds
Started Aug 11 04:27:44 PM PDT 24
Finished Aug 11 04:28:29 PM PDT 24
Peak memory 199804 kb
Host smart-730da78a-03a9-415b-af3b-a1db6b9f13eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768643511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3768643511
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.850324838
Short name T465
Test name
Test status
Simulation time 128396679501 ps
CPU time 63.91 seconds
Started Aug 11 04:27:31 PM PDT 24
Finished Aug 11 04:28:35 PM PDT 24
Peak memory 199744 kb
Host smart-e58adc2d-56b0-4615-9efd-474b037cce21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850324838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.850324838
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.442939026
Short name T1176
Test name
Test status
Simulation time 21012752840 ps
CPU time 14.02 seconds
Started Aug 11 04:27:27 PM PDT 24
Finished Aug 11 04:27:41 PM PDT 24
Peak memory 199644 kb
Host smart-12842b21-11de-4b72-99db-b861610f957d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442939026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.442939026
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2344144805
Short name T733
Test name
Test status
Simulation time 160563644221 ps
CPU time 160.49 seconds
Started Aug 11 04:27:46 PM PDT 24
Finished Aug 11 04:30:27 PM PDT 24
Peak memory 199972 kb
Host smart-c11e981d-0764-4f02-90eb-f899ff52d46f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344144805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2344144805
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.1068389460
Short name T1154
Test name
Test status
Simulation time 142370993020 ps
CPU time 422.84 seconds
Started Aug 11 04:27:39 PM PDT 24
Finished Aug 11 04:34:42 PM PDT 24
Peak memory 199688 kb
Host smart-39df448a-73ed-4abe-b0ab-058a28390486
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1068389460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1068389460
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1525139943
Short name T811
Test name
Test status
Simulation time 1240956045 ps
CPU time 1.04 seconds
Started Aug 11 04:27:48 PM PDT 24
Finished Aug 11 04:27:49 PM PDT 24
Peak memory 195856 kb
Host smart-36c39ff6-6340-4e1c-9bd8-2e85e8fe00a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525139943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1525139943
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.1807169102
Short name T968
Test name
Test status
Simulation time 249595091575 ps
CPU time 113.89 seconds
Started Aug 11 04:27:32 PM PDT 24
Finished Aug 11 04:29:26 PM PDT 24
Peak memory 199644 kb
Host smart-208a1ac8-f39f-4589-be3c-4070d6d89086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807169102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1807169102
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.3402449088
Short name T800
Test name
Test status
Simulation time 21277406525 ps
CPU time 181.95 seconds
Started Aug 11 04:27:38 PM PDT 24
Finished Aug 11 04:30:40 PM PDT 24
Peak memory 199696 kb
Host smart-90573777-112a-4e2e-9353-dd08165712c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3402449088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3402449088
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.987731120
Short name T17
Test name
Test status
Simulation time 5921247635 ps
CPU time 23.18 seconds
Started Aug 11 04:27:37 PM PDT 24
Finished Aug 11 04:28:00 PM PDT 24
Peak memory 198260 kb
Host smart-313070bb-8787-47bf-8442-512d2ea69c43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=987731120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.987731120
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3587319168
Short name T300
Test name
Test status
Simulation time 85239852948 ps
CPU time 253.95 seconds
Started Aug 11 04:27:47 PM PDT 24
Finished Aug 11 04:32:01 PM PDT 24
Peak memory 199724 kb
Host smart-d8b8fdc1-1b6e-4073-9344-0ca00b44c1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587319168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3587319168
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.301469827
Short name T294
Test name
Test status
Simulation time 34104625335 ps
CPU time 27.27 seconds
Started Aug 11 04:27:55 PM PDT 24
Finished Aug 11 04:28:23 PM PDT 24
Peak memory 195920 kb
Host smart-7a36341b-0f81-4b47-a304-2ac16d350464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301469827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.301469827
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.4068059623
Short name T861
Test name
Test status
Simulation time 665998650 ps
CPU time 1.94 seconds
Started Aug 11 04:27:46 PM PDT 24
Finished Aug 11 04:27:49 PM PDT 24
Peak memory 199328 kb
Host smart-76353f77-d1e6-4c82-9b67-11ce7d535c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068059623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.4068059623
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.2964599502
Short name T560
Test name
Test status
Simulation time 202597109082 ps
CPU time 1528.52 seconds
Started Aug 11 04:27:47 PM PDT 24
Finished Aug 11 04:53:16 PM PDT 24
Peak memory 199780 kb
Host smart-84170406-84aa-4161-b804-ba5d28016b18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964599502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2964599502
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1441327008
Short name T1042
Test name
Test status
Simulation time 1187626627 ps
CPU time 1.92 seconds
Started Aug 11 04:27:43 PM PDT 24
Finished Aug 11 04:27:45 PM PDT 24
Peak memory 198204 kb
Host smart-83d60669-68f1-4cf3-a2d4-9f8602bf6ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441327008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1441327008
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.14901261
Short name T687
Test name
Test status
Simulation time 77925832136 ps
CPU time 37.5 seconds
Started Aug 11 04:27:32 PM PDT 24
Finished Aug 11 04:28:10 PM PDT 24
Peak memory 199620 kb
Host smart-34fb9e81-dc81-47f8-99d2-8fc71166a0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14901261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.14901261
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1450619665
Short name T843
Test name
Test status
Simulation time 15649073 ps
CPU time 0.57 seconds
Started Aug 11 04:27:45 PM PDT 24
Finished Aug 11 04:27:46 PM PDT 24
Peak memory 195148 kb
Host smart-4573382b-1f5e-4fd1-8b58-4946c6849752
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450619665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1450619665
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.4147011505
Short name T875
Test name
Test status
Simulation time 187804949412 ps
CPU time 64.67 seconds
Started Aug 11 04:27:41 PM PDT 24
Finished Aug 11 04:28:46 PM PDT 24
Peak memory 199724 kb
Host smart-0b6de6fb-7d71-4fb4-b0b3-f8b24a931470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147011505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.4147011505
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3721110271
Short name T750
Test name
Test status
Simulation time 196533958306 ps
CPU time 94.53 seconds
Started Aug 11 04:27:39 PM PDT 24
Finished Aug 11 04:29:14 PM PDT 24
Peak memory 199792 kb
Host smart-0e1efb29-8b54-4b0d-96ee-eb82942707ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721110271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3721110271
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2873380411
Short name T807
Test name
Test status
Simulation time 6946150182 ps
CPU time 10.36 seconds
Started Aug 11 04:27:37 PM PDT 24
Finished Aug 11 04:27:48 PM PDT 24
Peak memory 198108 kb
Host smart-054a42c6-73b2-4e2a-b140-52489e4e3ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873380411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2873380411
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.106592462
Short name T1144
Test name
Test status
Simulation time 87114125907 ps
CPU time 38.65 seconds
Started Aug 11 04:27:37 PM PDT 24
Finished Aug 11 04:28:16 PM PDT 24
Peak memory 195872 kb
Host smart-65e163e9-ae55-4ed6-924d-8b5cd0dd432d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106592462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.106592462
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3477962809
Short name T1108
Test name
Test status
Simulation time 45199775386 ps
CPU time 64.33 seconds
Started Aug 11 04:27:56 PM PDT 24
Finished Aug 11 04:29:01 PM PDT 24
Peak memory 199820 kb
Host smart-0c8deccf-5d6e-4d2e-9047-ed627a79939e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3477962809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3477962809
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3272221656
Short name T661
Test name
Test status
Simulation time 231796176 ps
CPU time 0.79 seconds
Started Aug 11 04:27:53 PM PDT 24
Finished Aug 11 04:27:54 PM PDT 24
Peak memory 195840 kb
Host smart-f2911d08-067d-470d-a708-20cee2e4e689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272221656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3272221656
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.4233604588
Short name T585
Test name
Test status
Simulation time 66514018442 ps
CPU time 115.89 seconds
Started Aug 11 04:27:45 PM PDT 24
Finished Aug 11 04:29:41 PM PDT 24
Peak memory 199876 kb
Host smart-94f5fbf3-1843-4601-92cf-5788edcb2e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233604588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.4233604588
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.3461675354
Short name T331
Test name
Test status
Simulation time 15036707479 ps
CPU time 764.72 seconds
Started Aug 11 04:27:49 PM PDT 24
Finished Aug 11 04:40:34 PM PDT 24
Peak memory 199628 kb
Host smart-e165b3a1-a545-4c0b-bf43-328eba3e381a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3461675354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.3461675354
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.4090836210
Short name T411
Test name
Test status
Simulation time 6016369897 ps
CPU time 11.96 seconds
Started Aug 11 04:27:34 PM PDT 24
Finished Aug 11 04:27:46 PM PDT 24
Peak memory 198772 kb
Host smart-561825ff-46e3-4aed-82b2-4856f0df9794
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4090836210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.4090836210
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.261428226
Short name T1149
Test name
Test status
Simulation time 49717422714 ps
CPU time 14.94 seconds
Started Aug 11 04:27:44 PM PDT 24
Finished Aug 11 04:27:59 PM PDT 24
Peak memory 199552 kb
Host smart-61736dbf-7ae2-4254-a65f-7f0fa26b2dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261428226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.261428226
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3199836675
Short name T734
Test name
Test status
Simulation time 36909325745 ps
CPU time 11.14 seconds
Started Aug 11 04:27:45 PM PDT 24
Finished Aug 11 04:27:56 PM PDT 24
Peak memory 195960 kb
Host smart-9af69b4f-c773-40c0-b10c-ae0db09f36e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199836675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3199836675
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.4179823211
Short name T634
Test name
Test status
Simulation time 691754273 ps
CPU time 2.66 seconds
Started Aug 11 04:27:40 PM PDT 24
Finished Aug 11 04:27:43 PM PDT 24
Peak memory 199560 kb
Host smart-ee07bc69-4d59-4c6c-9710-71a9b3996a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179823211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.4179823211
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.3070604731
Short name T520
Test name
Test status
Simulation time 132581113657 ps
CPU time 201.65 seconds
Started Aug 11 04:27:40 PM PDT 24
Finished Aug 11 04:31:02 PM PDT 24
Peak memory 200084 kb
Host smart-d1c3f4c2-399c-4d9d-97a7-ad97665912e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070604731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3070604731
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.914224038
Short name T117
Test name
Test status
Simulation time 74719504598 ps
CPU time 337.18 seconds
Started Aug 11 04:27:41 PM PDT 24
Finished Aug 11 04:33:19 PM PDT 24
Peak memory 215808 kb
Host smart-aed5ac24-57e9-4a52-9937-a115a4711489
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914224038 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.914224038
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.988171830
Short name T452
Test name
Test status
Simulation time 6565027719 ps
CPU time 15.49 seconds
Started Aug 11 04:27:33 PM PDT 24
Finished Aug 11 04:27:49 PM PDT 24
Peak memory 199148 kb
Host smart-898989e2-1549-4fa0-bd08-963f2fd77ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988171830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.988171830
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.92842746
Short name T705
Test name
Test status
Simulation time 194721155087 ps
CPU time 63.23 seconds
Started Aug 11 04:27:41 PM PDT 24
Finished Aug 11 04:28:45 PM PDT 24
Peak memory 199744 kb
Host smart-53a7a161-7e58-420f-8710-ea818a5bf27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92842746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.92842746
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2451454195
Short name T729
Test name
Test status
Simulation time 19334738 ps
CPU time 0.58 seconds
Started Aug 11 04:27:49 PM PDT 24
Finished Aug 11 04:27:50 PM PDT 24
Peak memory 195152 kb
Host smart-e30d0d22-2961-4fd6-b986-05c28f3f2d4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451454195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2451454195
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1086279949
Short name T145
Test name
Test status
Simulation time 109109146069 ps
CPU time 40.32 seconds
Started Aug 11 04:27:38 PM PDT 24
Finished Aug 11 04:28:18 PM PDT 24
Peak memory 199676 kb
Host smart-f4d55311-ba98-43c8-acd2-7519d423b533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086279949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1086279949
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.4291209878
Short name T1172
Test name
Test status
Simulation time 73266640175 ps
CPU time 14.96 seconds
Started Aug 11 04:27:36 PM PDT 24
Finished Aug 11 04:27:51 PM PDT 24
Peak memory 199808 kb
Host smart-a4bed8fa-bd42-49d1-9fe4-6bc914c38876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291209878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.4291209878
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3090540620
Short name T1030
Test name
Test status
Simulation time 48191567183 ps
CPU time 62.81 seconds
Started Aug 11 04:27:42 PM PDT 24
Finished Aug 11 04:28:45 PM PDT 24
Peak memory 199720 kb
Host smart-39454d37-3c4b-4a4d-9008-58a21d8e5856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090540620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3090540620
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.2819849663
Short name T977
Test name
Test status
Simulation time 18389386326 ps
CPU time 13.06 seconds
Started Aug 11 04:27:36 PM PDT 24
Finished Aug 11 04:27:49 PM PDT 24
Peak memory 199732 kb
Host smart-bc739248-3e79-457d-ad2d-1301923d9c71
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819849663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2819849663
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.4060531505
Short name T537
Test name
Test status
Simulation time 82248558629 ps
CPU time 394.24 seconds
Started Aug 11 04:27:46 PM PDT 24
Finished Aug 11 04:34:20 PM PDT 24
Peak memory 199816 kb
Host smart-f8535c74-4f30-49a8-bee6-5abef71e332e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4060531505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.4060531505
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1217189416
Short name T995
Test name
Test status
Simulation time 8672951813 ps
CPU time 15.72 seconds
Started Aug 11 04:27:42 PM PDT 24
Finished Aug 11 04:27:58 PM PDT 24
Peak memory 199724 kb
Host smart-65810936-ca3c-412c-98f0-5ed6a7230ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217189416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1217189416
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.3456664608
Short name T564
Test name
Test status
Simulation time 511938302921 ps
CPU time 55.61 seconds
Started Aug 11 04:27:59 PM PDT 24
Finished Aug 11 04:28:54 PM PDT 24
Peak memory 200560 kb
Host smart-230a7f13-7f3a-4f36-afaf-24b84562f689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456664608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3456664608
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.3840260361
Short name T816
Test name
Test status
Simulation time 15440985588 ps
CPU time 207.56 seconds
Started Aug 11 04:27:43 PM PDT 24
Finished Aug 11 04:31:11 PM PDT 24
Peak memory 199748 kb
Host smart-9318cbfc-e22a-48c8-9feb-05c4e64cefbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3840260361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3840260361
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2870624390
Short name T447
Test name
Test status
Simulation time 1922216198 ps
CPU time 6.04 seconds
Started Aug 11 04:27:43 PM PDT 24
Finished Aug 11 04:27:49 PM PDT 24
Peak memory 197908 kb
Host smart-b07fdc3e-2c77-4bc2-a74e-6ab9c524b1e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2870624390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2870624390
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.2757601835
Short name T393
Test name
Test status
Simulation time 409463043818 ps
CPU time 35.39 seconds
Started Aug 11 04:27:39 PM PDT 24
Finished Aug 11 04:28:15 PM PDT 24
Peak memory 199536 kb
Host smart-3767f26e-7d6e-4e65-8ca1-6add8518c74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757601835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2757601835
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2360293534
Short name T406
Test name
Test status
Simulation time 40500571508 ps
CPU time 61.1 seconds
Started Aug 11 04:27:37 PM PDT 24
Finished Aug 11 04:28:38 PM PDT 24
Peak memory 195712 kb
Host smart-5ae554c1-1b42-4cf5-8e06-b0a22f2c6b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360293534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2360293534
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1430559805
Short name T1139
Test name
Test status
Simulation time 86355557 ps
CPU time 0.87 seconds
Started Aug 11 04:27:45 PM PDT 24
Finished Aug 11 04:27:46 PM PDT 24
Peak memory 197100 kb
Host smart-2a2329ab-d7b3-4dd3-bde1-beb416ece3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430559805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1430559805
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.1770566462
Short name T905
Test name
Test status
Simulation time 263005271095 ps
CPU time 88.99 seconds
Started Aug 11 04:27:35 PM PDT 24
Finished Aug 11 04:29:04 PM PDT 24
Peak memory 215328 kb
Host smart-1cc09884-418c-4340-b158-cb350d2b3fc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770566462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1770566462
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.1966278163
Short name T200
Test name
Test status
Simulation time 99378609579 ps
CPU time 952.23 seconds
Started Aug 11 04:27:39 PM PDT 24
Finished Aug 11 04:43:31 PM PDT 24
Peak memory 226068 kb
Host smart-22f1374e-dec1-434c-b0fe-cf5b730687d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966278163 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.1966278163
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.4139706535
Short name T1026
Test name
Test status
Simulation time 951166386 ps
CPU time 2.76 seconds
Started Aug 11 04:27:40 PM PDT 24
Finished Aug 11 04:27:43 PM PDT 24
Peak memory 199604 kb
Host smart-3e06e145-dd19-4026-b55b-0c44049ef97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139706535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.4139706535
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.4292942023
Short name T1029
Test name
Test status
Simulation time 20383574337 ps
CPU time 33.83 seconds
Started Aug 11 04:27:41 PM PDT 24
Finished Aug 11 04:28:15 PM PDT 24
Peak memory 199664 kb
Host smart-6cd75dde-ba5f-4300-9c99-3c3a54d27275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292942023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.4292942023
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1921429844
Short name T1164
Test name
Test status
Simulation time 19145531 ps
CPU time 0.55 seconds
Started Aug 11 04:27:54 PM PDT 24
Finished Aug 11 04:27:55 PM PDT 24
Peak memory 195120 kb
Host smart-46de69d7-c53b-48e9-9e4c-358517f6ce5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921429844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1921429844
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.93178253
Short name T405
Test name
Test status
Simulation time 33930452170 ps
CPU time 54.07 seconds
Started Aug 11 04:27:39 PM PDT 24
Finished Aug 11 04:28:33 PM PDT 24
Peak memory 199644 kb
Host smart-e15729ca-64ae-485e-9bcb-b43b3e7c6637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93178253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.93178253
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.2943693955
Short name T950
Test name
Test status
Simulation time 64110929921 ps
CPU time 33.46 seconds
Started Aug 11 04:27:36 PM PDT 24
Finished Aug 11 04:28:10 PM PDT 24
Peak memory 199724 kb
Host smart-48f8529e-2fc4-4add-ab5d-153019fbb444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943693955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2943693955
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.1227077900
Short name T1100
Test name
Test status
Simulation time 9983487651 ps
CPU time 5.32 seconds
Started Aug 11 04:27:35 PM PDT 24
Finished Aug 11 04:27:41 PM PDT 24
Peak memory 199748 kb
Host smart-e6757141-2347-476d-a809-ee4363ef4b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227077900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.1227077900
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3796579184
Short name T481
Test name
Test status
Simulation time 222556094991 ps
CPU time 221.9 seconds
Started Aug 11 04:27:44 PM PDT 24
Finished Aug 11 04:31:26 PM PDT 24
Peak memory 198840 kb
Host smart-9cceebbd-5c67-45ce-af23-07326be886a2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796579184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3796579184
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.4061273569
Short name T1080
Test name
Test status
Simulation time 216720381470 ps
CPU time 491.71 seconds
Started Aug 11 04:27:46 PM PDT 24
Finished Aug 11 04:35:58 PM PDT 24
Peak memory 199724 kb
Host smart-404117d2-1c77-4ac4-8f28-0a2fa7b75fb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4061273569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.4061273569
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.2201184738
Short name T1009
Test name
Test status
Simulation time 4135621644 ps
CPU time 4.27 seconds
Started Aug 11 04:27:49 PM PDT 24
Finished Aug 11 04:27:54 PM PDT 24
Peak memory 196732 kb
Host smart-cf481f73-8826-4dc9-8873-5c924bec33b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201184738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2201184738
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.4156833225
Short name T955
Test name
Test status
Simulation time 19744235675 ps
CPU time 29.56 seconds
Started Aug 11 04:28:01 PM PDT 24
Finished Aug 11 04:28:30 PM PDT 24
Peak memory 196104 kb
Host smart-d6fa49ed-60be-4eee-92d4-61182efcc426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156833225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.4156833225
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.2697537627
Short name T740
Test name
Test status
Simulation time 10202142751 ps
CPU time 329.17 seconds
Started Aug 11 04:27:46 PM PDT 24
Finished Aug 11 04:33:15 PM PDT 24
Peak memory 199796 kb
Host smart-d65c9e6d-145f-477a-990d-5aed66c9f1e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2697537627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2697537627
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.4252196225
Short name T1121
Test name
Test status
Simulation time 4613722715 ps
CPU time 37.12 seconds
Started Aug 11 04:27:48 PM PDT 24
Finished Aug 11 04:28:26 PM PDT 24
Peak memory 198892 kb
Host smart-344dd617-ec75-41e7-9d04-3f7bf2ea95b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4252196225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.4252196225
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3405318495
Short name T1151
Test name
Test status
Simulation time 139818083817 ps
CPU time 29.27 seconds
Started Aug 11 04:27:47 PM PDT 24
Finished Aug 11 04:28:16 PM PDT 24
Peak memory 199708 kb
Host smart-9afd0957-c9df-4170-a0e1-ceaa846fe2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405318495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3405318495
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.4084304177
Short name T426
Test name
Test status
Simulation time 3302125907 ps
CPU time 1.92 seconds
Started Aug 11 04:27:35 PM PDT 24
Finished Aug 11 04:27:37 PM PDT 24
Peak memory 196060 kb
Host smart-af891edd-6467-4014-975e-5b4a620ab36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084304177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.4084304177
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2546688865
Short name T291
Test name
Test status
Simulation time 663519828 ps
CPU time 2.79 seconds
Started Aug 11 04:27:41 PM PDT 24
Finished Aug 11 04:27:44 PM PDT 24
Peak memory 199572 kb
Host smart-1baf5d39-d966-4944-bbc0-18abfb4036ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546688865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2546688865
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2877939136
Short name T1124
Test name
Test status
Simulation time 65133764419 ps
CPU time 89.96 seconds
Started Aug 11 04:27:44 PM PDT 24
Finished Aug 11 04:29:14 PM PDT 24
Peak memory 199784 kb
Host smart-3195e92b-e141-4c09-b2e6-dd61ee1e80f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877939136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2877939136
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.3536245732
Short name T835
Test name
Test status
Simulation time 258951278115 ps
CPU time 1083.26 seconds
Started Aug 11 04:27:46 PM PDT 24
Finished Aug 11 04:45:49 PM PDT 24
Peak memory 224700 kb
Host smart-4d17391a-6029-4349-874c-cf8ab9373c6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536245732 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.3536245732
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.1544047240
Short name T557
Test name
Test status
Simulation time 1104580431 ps
CPU time 2.09 seconds
Started Aug 11 04:27:58 PM PDT 24
Finished Aug 11 04:28:00 PM PDT 24
Peak memory 197748 kb
Host smart-452bceaf-702b-43d0-86dc-e1448223728b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544047240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1544047240
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2526255877
Short name T277
Test name
Test status
Simulation time 84353276133 ps
CPU time 81.52 seconds
Started Aug 11 04:27:42 PM PDT 24
Finished Aug 11 04:29:03 PM PDT 24
Peak memory 199736 kb
Host smart-73287984-c281-4410-a1d0-7eef677ef6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526255877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2526255877
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2469347465
Short name T604
Test name
Test status
Simulation time 32677765 ps
CPU time 0.53 seconds
Started Aug 11 04:27:40 PM PDT 24
Finished Aug 11 04:27:41 PM PDT 24
Peak memory 195164 kb
Host smart-1b2a0ebc-f01e-4a34-86a9-5ee4ca2851ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469347465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2469347465
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1306361644
Short name T1045
Test name
Test status
Simulation time 74274392056 ps
CPU time 20.95 seconds
Started Aug 11 04:27:47 PM PDT 24
Finished Aug 11 04:28:08 PM PDT 24
Peak memory 199732 kb
Host smart-fe68b1a7-e556-4950-911c-bccd026a792b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306361644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1306361644
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1430600255
Short name T764
Test name
Test status
Simulation time 79281527123 ps
CPU time 29.33 seconds
Started Aug 11 04:27:42 PM PDT 24
Finished Aug 11 04:28:11 PM PDT 24
Peak memory 199636 kb
Host smart-a0f6006c-877c-499e-998e-c35b5c198dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430600255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1430600255
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2042091796
Short name T618
Test name
Test status
Simulation time 74651739767 ps
CPU time 148.55 seconds
Started Aug 11 04:27:42 PM PDT 24
Finished Aug 11 04:30:10 PM PDT 24
Peak memory 199652 kb
Host smart-d5fe8652-02e7-4954-abb2-a3063de63687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042091796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2042091796
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.2363656297
Short name T1022
Test name
Test status
Simulation time 14951378944 ps
CPU time 13.58 seconds
Started Aug 11 04:27:46 PM PDT 24
Finished Aug 11 04:28:00 PM PDT 24
Peak memory 199320 kb
Host smart-221e9efe-0356-4fbd-becb-208fa8a756b1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363656297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2363656297
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.250187485
Short name T270
Test name
Test status
Simulation time 66509842176 ps
CPU time 165.2 seconds
Started Aug 11 04:27:48 PM PDT 24
Finished Aug 11 04:30:33 PM PDT 24
Peak memory 199704 kb
Host smart-7c507ff0-3575-4952-b947-7c4d1ad5fa7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=250187485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.250187485
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.24075616
Short name T437
Test name
Test status
Simulation time 6268529911 ps
CPU time 4.69 seconds
Started Aug 11 04:27:47 PM PDT 24
Finished Aug 11 04:27:52 PM PDT 24
Peak memory 198556 kb
Host smart-97db94f5-dbac-4edc-9197-97f6ad5c0769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24075616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.24075616
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.996702645
Short name T667
Test name
Test status
Simulation time 197554169181 ps
CPU time 198.84 seconds
Started Aug 11 04:27:47 PM PDT 24
Finished Aug 11 04:31:06 PM PDT 24
Peak memory 208132 kb
Host smart-a1bfd732-30c8-499d-9b88-9329b2b821bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996702645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.996702645
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.687566168
Short name T421
Test name
Test status
Simulation time 11249908117 ps
CPU time 289.41 seconds
Started Aug 11 04:27:48 PM PDT 24
Finished Aug 11 04:32:38 PM PDT 24
Peak memory 199756 kb
Host smart-ec7461c7-a043-4d89-8633-51e71c7866e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=687566168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.687566168
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.859939656
Short name T681
Test name
Test status
Simulation time 1916648033 ps
CPU time 3.5 seconds
Started Aug 11 04:27:45 PM PDT 24
Finished Aug 11 04:27:49 PM PDT 24
Peak memory 197680 kb
Host smart-4fd6fed3-931d-440e-8e87-ab0d141e5891
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=859939656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.859939656
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.4083560259
Short name T993
Test name
Test status
Simulation time 29046412215 ps
CPU time 19.26 seconds
Started Aug 11 04:27:42 PM PDT 24
Finished Aug 11 04:28:01 PM PDT 24
Peak memory 199684 kb
Host smart-904ce003-63f0-4f37-ba5d-ac4eafe7a4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083560259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.4083560259
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.4161804369
Short name T1078
Test name
Test status
Simulation time 2851757054 ps
CPU time 1.83 seconds
Started Aug 11 04:27:40 PM PDT 24
Finished Aug 11 04:27:42 PM PDT 24
Peak memory 195540 kb
Host smart-42d77256-7640-401e-8f45-14f97c3af8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161804369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.4161804369
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3268295608
Short name T542
Test name
Test status
Simulation time 720027816 ps
CPU time 1.49 seconds
Started Aug 11 04:27:40 PM PDT 24
Finished Aug 11 04:27:41 PM PDT 24
Peak memory 197912 kb
Host smart-392e83bf-5eab-4ec8-9d32-61ddcca1cd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268295608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3268295608
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.358684225
Short name T106
Test name
Test status
Simulation time 103426463703 ps
CPU time 95.47 seconds
Started Aug 11 04:27:41 PM PDT 24
Finished Aug 11 04:29:16 PM PDT 24
Peak memory 215872 kb
Host smart-79e68bc6-454b-486f-8331-569793fde918
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358684225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.358684225
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1390400155
Short name T611
Test name
Test status
Simulation time 82439261362 ps
CPU time 2341.5 seconds
Started Aug 11 04:27:52 PM PDT 24
Finished Aug 11 05:06:54 PM PDT 24
Peak memory 216400 kb
Host smart-743ae82e-250b-4ee6-b11e-7e8fa4e3df32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390400155 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1390400155
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2925645010
Short name T368
Test name
Test status
Simulation time 2344049036 ps
CPU time 2.23 seconds
Started Aug 11 04:27:46 PM PDT 24
Finished Aug 11 04:27:48 PM PDT 24
Peak memory 198432 kb
Host smart-e4c218d1-99ba-48a4-a933-19079bbf944e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925645010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2925645010
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.4054772557
Short name T485
Test name
Test status
Simulation time 54231448601 ps
CPU time 86.54 seconds
Started Aug 11 04:27:49 PM PDT 24
Finished Aug 11 04:29:15 PM PDT 24
Peak memory 199664 kb
Host smart-22e762e6-7139-4ff2-9444-793b68d332d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054772557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.4054772557
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1251357531
Short name T366
Test name
Test status
Simulation time 37139310 ps
CPU time 0.56 seconds
Started Aug 11 04:27:53 PM PDT 24
Finished Aug 11 04:27:54 PM PDT 24
Peak memory 195432 kb
Host smart-5a7c8738-485f-483e-80e1-1e77f995414c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251357531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1251357531
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.950586145
Short name T761
Test name
Test status
Simulation time 22990537924 ps
CPU time 18.51 seconds
Started Aug 11 04:27:51 PM PDT 24
Finished Aug 11 04:28:10 PM PDT 24
Peak memory 199692 kb
Host smart-4808205d-0fc4-4f1e-b6d7-eb3847a66d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950586145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.950586145
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1312270421
Short name T375
Test name
Test status
Simulation time 35446349857 ps
CPU time 64.01 seconds
Started Aug 11 04:27:45 PM PDT 24
Finished Aug 11 04:28:49 PM PDT 24
Peak memory 199684 kb
Host smart-079ccebb-e371-4364-a680-599638abb381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312270421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1312270421
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.995482415
Short name T730
Test name
Test status
Simulation time 148566414567 ps
CPU time 62.05 seconds
Started Aug 11 04:27:48 PM PDT 24
Finished Aug 11 04:28:50 PM PDT 24
Peak memory 199788 kb
Host smart-bd51d44d-2a98-4d8f-b05d-6a59e0ebad87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995482415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.995482415
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.4148530417
Short name T1138
Test name
Test status
Simulation time 186096267700 ps
CPU time 150.91 seconds
Started Aug 11 04:27:47 PM PDT 24
Finished Aug 11 04:30:18 PM PDT 24
Peak memory 197904 kb
Host smart-df4a323a-5bd4-4f97-95c9-3b4e26709952
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148530417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.4148530417
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.3235009541
Short name T332
Test name
Test status
Simulation time 155556555528 ps
CPU time 989.65 seconds
Started Aug 11 04:27:50 PM PDT 24
Finished Aug 11 04:44:20 PM PDT 24
Peak memory 199696 kb
Host smart-3d47e046-6a19-4321-bab4-197209405a4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3235009541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3235009541
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2815486907
Short name T367
Test name
Test status
Simulation time 6601964274 ps
CPU time 11.74 seconds
Started Aug 11 04:27:50 PM PDT 24
Finished Aug 11 04:28:02 PM PDT 24
Peak memory 199132 kb
Host smart-d0e68db7-4933-4b3c-ae9d-59c84b81ce69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815486907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2815486907
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.1454398483
Short name T522
Test name
Test status
Simulation time 156265021420 ps
CPU time 58.74 seconds
Started Aug 11 04:27:51 PM PDT 24
Finished Aug 11 04:28:50 PM PDT 24
Peak memory 207976 kb
Host smart-1ad9341b-c52e-4ecb-b6aa-42c75118e444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454398483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.1454398483
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.4253622949
Short name T676
Test name
Test status
Simulation time 19494874069 ps
CPU time 164.81 seconds
Started Aug 11 04:27:50 PM PDT 24
Finished Aug 11 04:30:35 PM PDT 24
Peak memory 199648 kb
Host smart-87ccbc14-48f7-4ee7-940e-5e903591db50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4253622949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.4253622949
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.498524933
Short name T429
Test name
Test status
Simulation time 4058071653 ps
CPU time 4.6 seconds
Started Aug 11 04:27:43 PM PDT 24
Finished Aug 11 04:27:48 PM PDT 24
Peak memory 197984 kb
Host smart-f62762a0-58d7-420d-94d2-087f543c7a79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=498524933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.498524933
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.2026814254
Short name T499
Test name
Test status
Simulation time 351396510317 ps
CPU time 34.61 seconds
Started Aug 11 04:27:54 PM PDT 24
Finished Aug 11 04:28:29 PM PDT 24
Peak memory 199636 kb
Host smart-e4416f48-6289-4a48-9856-b85ad8f524f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026814254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2026814254
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.789277128
Short name T1132
Test name
Test status
Simulation time 33360416526 ps
CPU time 47.02 seconds
Started Aug 11 04:27:50 PM PDT 24
Finished Aug 11 04:28:37 PM PDT 24
Peak memory 195896 kb
Host smart-ced0f8f5-3fab-408b-b3ce-d446d98942bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789277128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.789277128
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.2236161900
Short name T620
Test name
Test status
Simulation time 880367639 ps
CPU time 2.05 seconds
Started Aug 11 04:27:41 PM PDT 24
Finished Aug 11 04:27:43 PM PDT 24
Peak memory 198476 kb
Host smart-20f8aa33-7260-443a-8d19-2c4fd78a8b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236161900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2236161900
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.1993681087
Short name T278
Test name
Test status
Simulation time 46771932406 ps
CPU time 79.1 seconds
Started Aug 11 04:27:58 PM PDT 24
Finished Aug 11 04:29:18 PM PDT 24
Peak memory 199652 kb
Host smart-31581866-77c9-46ff-b47d-beb9f4c46570
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993681087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1993681087
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.119350199
Short name T1158
Test name
Test status
Simulation time 97488907492 ps
CPU time 443.36 seconds
Started Aug 11 04:27:58 PM PDT 24
Finished Aug 11 04:35:22 PM PDT 24
Peak memory 216212 kb
Host smart-918bbc00-8cd1-4061-b05e-7dede402af02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119350199 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.119350199
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.714726773
Short name T646
Test name
Test status
Simulation time 2117601964 ps
CPU time 2.25 seconds
Started Aug 11 04:27:57 PM PDT 24
Finished Aug 11 04:27:59 PM PDT 24
Peak memory 198892 kb
Host smart-5ddde7d9-0091-4467-9fe3-a644fa75c73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714726773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.714726773
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2048272485
Short name T578
Test name
Test status
Simulation time 117083419721 ps
CPU time 37.54 seconds
Started Aug 11 04:27:46 PM PDT 24
Finished Aug 11 04:28:24 PM PDT 24
Peak memory 199748 kb
Host smart-f23b4cb8-a04a-4b29-abef-f8f6b68dc081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048272485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2048272485
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2995101513
Short name T932
Test name
Test status
Simulation time 22594216 ps
CPU time 0.55 seconds
Started Aug 11 04:28:02 PM PDT 24
Finished Aug 11 04:28:03 PM PDT 24
Peak memory 195104 kb
Host smart-277d63b1-75d1-433b-a93b-2b800bc682f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995101513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2995101513
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1849659927
Short name T324
Test name
Test status
Simulation time 155697158581 ps
CPU time 376.72 seconds
Started Aug 11 04:27:59 PM PDT 24
Finished Aug 11 04:34:16 PM PDT 24
Peak memory 199716 kb
Host smart-12bb1bf7-540f-4603-8460-107bf115def9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849659927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1849659927
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.325196866
Short name T153
Test name
Test status
Simulation time 74803841359 ps
CPU time 31.63 seconds
Started Aug 11 04:27:54 PM PDT 24
Finished Aug 11 04:28:25 PM PDT 24
Peak memory 199808 kb
Host smart-aa81ca08-ee2e-43dd-9c75-241c0817b114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325196866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.325196866
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.2357031860
Short name T632
Test name
Test status
Simulation time 95742125020 ps
CPU time 31.55 seconds
Started Aug 11 04:27:51 PM PDT 24
Finished Aug 11 04:28:22 PM PDT 24
Peak memory 199772 kb
Host smart-07847958-5a25-41ce-8c43-2eaaef521a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357031860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2357031860
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.4007603615
Short name T867
Test name
Test status
Simulation time 78059600786 ps
CPU time 127.68 seconds
Started Aug 11 04:27:46 PM PDT 24
Finished Aug 11 04:29:54 PM PDT 24
Peak memory 199724 kb
Host smart-4f52b25e-b8de-4756-bfee-76c2bb705403
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007603615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.4007603615
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2072125716
Short name T371
Test name
Test status
Simulation time 86344420607 ps
CPU time 580.72 seconds
Started Aug 11 04:27:53 PM PDT 24
Finished Aug 11 04:37:34 PM PDT 24
Peak memory 199704 kb
Host smart-5e2ebbed-ff46-4887-beb4-d34e307ccd9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2072125716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2072125716
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.2640698373
Short name T643
Test name
Test status
Simulation time 2643815021 ps
CPU time 2.2 seconds
Started Aug 11 04:27:55 PM PDT 24
Finished Aug 11 04:27:58 PM PDT 24
Peak memory 197432 kb
Host smart-c5f79714-32d5-499a-ac9a-7701c215bf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640698373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2640698373
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.382509690
Short name T877
Test name
Test status
Simulation time 139095077331 ps
CPU time 48.48 seconds
Started Aug 11 04:28:03 PM PDT 24
Finished Aug 11 04:28:52 PM PDT 24
Peak memory 199120 kb
Host smart-ecb9b28e-9136-49d4-b183-7324735a53bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382509690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.382509690
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.2884445331
Short name T894
Test name
Test status
Simulation time 29353280231 ps
CPU time 411.44 seconds
Started Aug 11 04:27:56 PM PDT 24
Finished Aug 11 04:34:48 PM PDT 24
Peak memory 199896 kb
Host smart-e65f9c40-1385-4a31-837d-95159c54b6cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2884445331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2884445331
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1479947887
Short name T75
Test name
Test status
Simulation time 5347729397 ps
CPU time 10.9 seconds
Started Aug 11 04:28:02 PM PDT 24
Finished Aug 11 04:28:13 PM PDT 24
Peak memory 198760 kb
Host smart-9aab1b70-88fb-4867-ac65-1df1563168a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1479947887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1479947887
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1093453424
Short name T167
Test name
Test status
Simulation time 48265749597 ps
CPU time 49.21 seconds
Started Aug 11 04:27:54 PM PDT 24
Finished Aug 11 04:28:43 PM PDT 24
Peak memory 199716 kb
Host smart-bee7c9ea-a5bc-4d31-961c-e2677b6b5915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093453424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1093453424
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.297915660
Short name T849
Test name
Test status
Simulation time 28679403853 ps
CPU time 21.2 seconds
Started Aug 11 04:27:55 PM PDT 24
Finished Aug 11 04:28:16 PM PDT 24
Peak memory 195764 kb
Host smart-9f10b3ed-3cf4-48bf-9b8c-0b479a269521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297915660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.297915660
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.1816941586
Short name T470
Test name
Test status
Simulation time 5373727368 ps
CPU time 16.18 seconds
Started Aug 11 04:28:04 PM PDT 24
Finished Aug 11 04:28:21 PM PDT 24
Peak memory 199684 kb
Host smart-f0dce49b-70b2-4ffe-8cd1-c41e38c777a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816941586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.1816941586
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.585546666
Short name T477
Test name
Test status
Simulation time 127270821871 ps
CPU time 84.76 seconds
Started Aug 11 04:27:59 PM PDT 24
Finished Aug 11 04:29:24 PM PDT 24
Peak memory 199656 kb
Host smart-bcff5a3f-8e28-47d5-a838-41a91a55be6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585546666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.585546666
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.2157534156
Short name T1073
Test name
Test status
Simulation time 72715617596 ps
CPU time 425.74 seconds
Started Aug 11 04:27:58 PM PDT 24
Finished Aug 11 04:35:04 PM PDT 24
Peak memory 216296 kb
Host smart-1f486428-df19-4472-a0fc-d3e95eb363fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157534156 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2157534156
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.2746849196
Short name T430
Test name
Test status
Simulation time 1192663029 ps
CPU time 3.79 seconds
Started Aug 11 04:27:54 PM PDT 24
Finished Aug 11 04:27:58 PM PDT 24
Peak memory 199440 kb
Host smart-e97f1909-4524-4b0d-b584-3d156237c04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746849196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2746849196
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.360055684
Short name T108
Test name
Test status
Simulation time 80932827381 ps
CPU time 41.86 seconds
Started Aug 11 04:27:49 PM PDT 24
Finished Aug 11 04:28:31 PM PDT 24
Peak memory 199708 kb
Host smart-e705ec34-66b6-4356-83d0-952c15a4c9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360055684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.360055684
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1809192873
Short name T24
Test name
Test status
Simulation time 41464416 ps
CPU time 0.57 seconds
Started Aug 11 04:27:57 PM PDT 24
Finished Aug 11 04:27:58 PM PDT 24
Peak memory 195104 kb
Host smart-45a0304a-55a3-49c9-b6ce-8530a9743d36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809192873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1809192873
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.2037533380
Short name T381
Test name
Test status
Simulation time 9213379835 ps
CPU time 14.7 seconds
Started Aug 11 04:27:57 PM PDT 24
Finished Aug 11 04:28:12 PM PDT 24
Peak memory 199584 kb
Host smart-e6ed7c40-2ef3-415f-a167-a20fbda85497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037533380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2037533380
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2288968807
Short name T796
Test name
Test status
Simulation time 39741126484 ps
CPU time 23.41 seconds
Started Aug 11 04:27:51 PM PDT 24
Finished Aug 11 04:28:15 PM PDT 24
Peak memory 199692 kb
Host smart-105578fb-a13d-4fce-98fe-39a307956711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288968807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2288968807
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.2179144618
Short name T770
Test name
Test status
Simulation time 72553999691 ps
CPU time 125.17 seconds
Started Aug 11 04:27:58 PM PDT 24
Finished Aug 11 04:30:04 PM PDT 24
Peak memory 199732 kb
Host smart-a993fbf7-8727-4228-8fa3-ee612c784f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179144618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2179144618
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.1932513013
Short name T73
Test name
Test status
Simulation time 55840372981 ps
CPU time 54.15 seconds
Started Aug 11 04:28:02 PM PDT 24
Finished Aug 11 04:28:56 PM PDT 24
Peak memory 199696 kb
Host smart-d3d1ac21-5c37-4382-8b16-e9c7399b5235
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932513013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1932513013
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.4077501726
Short name T735
Test name
Test status
Simulation time 76870400716 ps
CPU time 84.34 seconds
Started Aug 11 04:27:53 PM PDT 24
Finished Aug 11 04:29:18 PM PDT 24
Peak memory 199808 kb
Host smart-267d6410-bacf-4a7e-969a-2396a53ff775
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4077501726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.4077501726
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.3051281084
Short name T502
Test name
Test status
Simulation time 7605910188 ps
CPU time 6.44 seconds
Started Aug 11 04:27:54 PM PDT 24
Finished Aug 11 04:28:00 PM PDT 24
Peak memory 198012 kb
Host smart-13c1368d-8e3d-411c-9115-fb1539c591bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051281084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3051281084
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2679282066
Short name T970
Test name
Test status
Simulation time 196540579649 ps
CPU time 106.92 seconds
Started Aug 11 04:27:48 PM PDT 24
Finished Aug 11 04:29:35 PM PDT 24
Peak memory 199840 kb
Host smart-0100d545-2f3d-43ec-8c8b-36e16c1f64db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679282066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2679282066
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.451467804
Short name T645
Test name
Test status
Simulation time 7381620728 ps
CPU time 433.4 seconds
Started Aug 11 04:27:50 PM PDT 24
Finished Aug 11 04:35:04 PM PDT 24
Peak memory 199736 kb
Host smart-0485f32f-c7ca-4d79-95c9-0906f83eb99e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=451467804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.451467804
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.738978215
Short name T352
Test name
Test status
Simulation time 5407121294 ps
CPU time 13.56 seconds
Started Aug 11 04:27:53 PM PDT 24
Finished Aug 11 04:28:07 PM PDT 24
Peak memory 199008 kb
Host smart-886044cb-f3fb-47bd-9d08-322c64da97f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=738978215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.738978215
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1746030975
Short name T788
Test name
Test status
Simulation time 98384805956 ps
CPU time 118.41 seconds
Started Aug 11 04:28:01 PM PDT 24
Finished Aug 11 04:29:59 PM PDT 24
Peak memory 199704 kb
Host smart-a4e95644-1b17-4eba-b5f4-a3db02658881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746030975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1746030975
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3790542150
Short name T1046
Test name
Test status
Simulation time 4072767717 ps
CPU time 6.53 seconds
Started Aug 11 04:27:59 PM PDT 24
Finished Aug 11 04:28:06 PM PDT 24
Peak memory 196280 kb
Host smart-ef2452e3-0ba2-44ba-8963-598620b49675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790542150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3790542150
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.437251920
Short name T1116
Test name
Test status
Simulation time 467295596 ps
CPU time 1.78 seconds
Started Aug 11 04:27:50 PM PDT 24
Finished Aug 11 04:27:52 PM PDT 24
Peak memory 198456 kb
Host smart-ff0e23fa-a453-4b44-acea-69871b4a280a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437251920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.437251920
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2595663032
Short name T15
Test name
Test status
Simulation time 257611370 ps
CPU time 0.68 seconds
Started Aug 11 04:27:54 PM PDT 24
Finished Aug 11 04:27:55 PM PDT 24
Peak memory 195580 kb
Host smart-95a502b1-700d-4c41-9a12-56754f66601e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595663032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2595663032
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1449533593
Short name T989
Test name
Test status
Simulation time 29078821959 ps
CPU time 403.2 seconds
Started Aug 11 04:27:48 PM PDT 24
Finished Aug 11 04:34:31 PM PDT 24
Peak memory 208060 kb
Host smart-d505959e-64b9-4f13-a5ca-922eeece4d6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449533593 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1449533593
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.3817188411
Short name T402
Test name
Test status
Simulation time 602604280 ps
CPU time 1.28 seconds
Started Aug 11 04:27:57 PM PDT 24
Finished Aug 11 04:27:58 PM PDT 24
Peak memory 197968 kb
Host smart-2f83e1bb-51c9-4113-8be1-01eb65121704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817188411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.3817188411
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2767656705
Short name T462
Test name
Test status
Simulation time 6285194737 ps
CPU time 10.44 seconds
Started Aug 11 04:27:49 PM PDT 24
Finished Aug 11 04:27:59 PM PDT 24
Peak memory 198440 kb
Host smart-addab713-703d-4889-9d8e-6ac0aeeb815c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767656705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2767656705
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.941945181
Short name T821
Test name
Test status
Simulation time 52204169 ps
CPU time 0.58 seconds
Started Aug 11 04:26:03 PM PDT 24
Finished Aug 11 04:26:04 PM PDT 24
Peak memory 195400 kb
Host smart-0371fd79-d8de-4767-88e1-dab746ea1f50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941945181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.941945181
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.2889499899
Short name T728
Test name
Test status
Simulation time 152682112964 ps
CPU time 50.97 seconds
Started Aug 11 04:26:12 PM PDT 24
Finished Aug 11 04:27:03 PM PDT 24
Peak memory 199560 kb
Host smart-08fc211a-64e0-4ad9-b5d6-7219df447f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889499899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2889499899
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.3483831287
Short name T508
Test name
Test status
Simulation time 54292119696 ps
CPU time 79.75 seconds
Started Aug 11 04:26:39 PM PDT 24
Finished Aug 11 04:27:59 PM PDT 24
Peak memory 199780 kb
Host smart-00dedc25-b885-4d0b-8b20-0653d1bc503a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483831287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3483831287
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.2679652896
Short name T217
Test name
Test status
Simulation time 99585376561 ps
CPU time 140.61 seconds
Started Aug 11 04:26:35 PM PDT 24
Finished Aug 11 04:28:56 PM PDT 24
Peak memory 199704 kb
Host smart-f9b42ede-5ca1-4189-b390-0446726d2ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679652896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2679652896
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1089526783
Short name T924
Test name
Test status
Simulation time 40362993744 ps
CPU time 71.99 seconds
Started Aug 11 04:26:10 PM PDT 24
Finished Aug 11 04:27:22 PM PDT 24
Peak memory 199644 kb
Host smart-62346a0b-0091-44ee-9fdd-38d1fc950d56
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089526783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1089526783
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.3271549606
Short name T928
Test name
Test status
Simulation time 157820315546 ps
CPU time 404.05 seconds
Started Aug 11 04:25:57 PM PDT 24
Finished Aug 11 04:32:41 PM PDT 24
Peak memory 199728 kb
Host smart-7786a2df-36bf-4c12-a9b8-365bbb0319ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3271549606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3271549606
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.189140306
Short name T749
Test name
Test status
Simulation time 4137546730 ps
CPU time 8.6 seconds
Started Aug 11 04:26:02 PM PDT 24
Finished Aug 11 04:26:11 PM PDT 24
Peak memory 199532 kb
Host smart-9f1f43e8-4042-4a3b-907c-76093f49a2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189140306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.189140306
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3285637390
Short name T448
Test name
Test status
Simulation time 20304445796 ps
CPU time 6.87 seconds
Started Aug 11 04:26:01 PM PDT 24
Finished Aug 11 04:26:08 PM PDT 24
Peak memory 194304 kb
Host smart-6c4e632b-050a-404a-b990-1de6b5b99638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285637390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3285637390
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.3533729616
Short name T1106
Test name
Test status
Simulation time 16399942731 ps
CPU time 854.8 seconds
Started Aug 11 04:26:05 PM PDT 24
Finished Aug 11 04:40:20 PM PDT 24
Peak memory 199788 kb
Host smart-22463368-c896-4ed7-9368-f78ec60480b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3533729616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3533729616
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2179288690
Short name T732
Test name
Test status
Simulation time 2476669766 ps
CPU time 19.13 seconds
Started Aug 11 04:26:04 PM PDT 24
Finished Aug 11 04:26:24 PM PDT 24
Peak memory 198248 kb
Host smart-8b6ad3bc-cfee-47df-aee0-8a9d28550552
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2179288690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2179288690
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1343447096
Short name T184
Test name
Test status
Simulation time 30029297855 ps
CPU time 56.35 seconds
Started Aug 11 04:26:16 PM PDT 24
Finished Aug 11 04:27:13 PM PDT 24
Peak memory 199736 kb
Host smart-6cd43ce8-2b17-4518-976e-8d88eb69a058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343447096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1343447096
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.4087342085
Short name T311
Test name
Test status
Simulation time 3295519758 ps
CPU time 1.83 seconds
Started Aug 11 04:26:00 PM PDT 24
Finished Aug 11 04:26:02 PM PDT 24
Peak memory 196276 kb
Host smart-f784794d-d271-4a30-bbde-ba905c21fb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087342085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.4087342085
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3089001650
Short name T598
Test name
Test status
Simulation time 485062276 ps
CPU time 1.94 seconds
Started Aug 11 04:26:13 PM PDT 24
Finished Aug 11 04:26:15 PM PDT 24
Peak memory 198500 kb
Host smart-8c8f49b7-bc86-434b-b0b5-729a4713fee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089001650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3089001650
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.735288691
Short name T857
Test name
Test status
Simulation time 176186733076 ps
CPU time 287.13 seconds
Started Aug 11 04:26:10 PM PDT 24
Finished Aug 11 04:30:58 PM PDT 24
Peak memory 208136 kb
Host smart-e3c8edbe-d00e-439f-a51e-ff3ea8ee720b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735288691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.735288691
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.3187794789
Short name T778
Test name
Test status
Simulation time 177117589058 ps
CPU time 206.72 seconds
Started Aug 11 04:26:22 PM PDT 24
Finished Aug 11 04:29:49 PM PDT 24
Peak memory 214024 kb
Host smart-07437ae3-0c38-434b-8347-9468e0e8439e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187794789 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.3187794789
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1206606616
Short name T853
Test name
Test status
Simulation time 6934841070 ps
CPU time 14.93 seconds
Started Aug 11 04:26:05 PM PDT 24
Finished Aug 11 04:26:20 PM PDT 24
Peak memory 199616 kb
Host smart-a829d5ee-525b-4808-a976-c0ababe4273c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206606616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1206606616
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.113987473
Short name T637
Test name
Test status
Simulation time 12019747332 ps
CPU time 18.18 seconds
Started Aug 11 04:26:01 PM PDT 24
Finished Aug 11 04:26:19 PM PDT 24
Peak memory 199664 kb
Host smart-8dc57165-402c-4071-9ec5-a9d607b17838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113987473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.113987473
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2004744309
Short name T148
Test name
Test status
Simulation time 24883272718 ps
CPU time 12.9 seconds
Started Aug 11 04:27:52 PM PDT 24
Finished Aug 11 04:28:05 PM PDT 24
Peak memory 199584 kb
Host smart-46406124-e92d-4fa5-a5a0-57a99d3a4780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004744309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2004744309
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.167740780
Short name T797
Test name
Test status
Simulation time 60798750832 ps
CPU time 918.93 seconds
Started Aug 11 04:27:52 PM PDT 24
Finished Aug 11 04:43:11 PM PDT 24
Peak memory 230252 kb
Host smart-da4d0105-9850-4434-b5cc-2d9c5662a36a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167740780 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.167740780
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2580581715
Short name T626
Test name
Test status
Simulation time 29676503130 ps
CPU time 30.99 seconds
Started Aug 11 04:27:51 PM PDT 24
Finished Aug 11 04:28:22 PM PDT 24
Peak memory 199792 kb
Host smart-fd05678d-048b-46c2-b8be-1c9e1fd3c5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580581715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2580581715
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1181500605
Short name T709
Test name
Test status
Simulation time 35898572906 ps
CPU time 412.38 seconds
Started Aug 11 04:27:57 PM PDT 24
Finished Aug 11 04:34:50 PM PDT 24
Peak memory 216380 kb
Host smart-988f8022-c364-42cf-9f88-c248d4329264
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181500605 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1181500605
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2613225702
Short name T232
Test name
Test status
Simulation time 25156065763 ps
CPU time 37.75 seconds
Started Aug 11 04:27:59 PM PDT 24
Finished Aug 11 04:28:37 PM PDT 24
Peak memory 199656 kb
Host smart-f213669b-5b8f-44ef-a38d-af20c02c6267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613225702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2613225702
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1665384426
Short name T404
Test name
Test status
Simulation time 110255323881 ps
CPU time 374.9 seconds
Started Aug 11 04:27:56 PM PDT 24
Finished Aug 11 04:34:11 PM PDT 24
Peak memory 215984 kb
Host smart-7c85212d-224c-42cf-937e-c6574c3e1bcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665384426 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1665384426
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1403350940
Short name T170
Test name
Test status
Simulation time 56682814942 ps
CPU time 40.95 seconds
Started Aug 11 04:27:53 PM PDT 24
Finished Aug 11 04:28:34 PM PDT 24
Peak memory 199772 kb
Host smart-19463ca4-8fb0-4228-81fe-db0c759e11b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403350940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1403350940
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3617210428
Short name T639
Test name
Test status
Simulation time 93007416986 ps
CPU time 416.13 seconds
Started Aug 11 04:28:06 PM PDT 24
Finished Aug 11 04:35:03 PM PDT 24
Peak memory 216428 kb
Host smart-68be467c-2b19-4b13-a3d2-b8bcc80c661e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617210428 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3617210428
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3591243819
Short name T623
Test name
Test status
Simulation time 107352341145 ps
CPU time 45.44 seconds
Started Aug 11 04:27:57 PM PDT 24
Finished Aug 11 04:28:42 PM PDT 24
Peak memory 199712 kb
Host smart-e637876b-236f-4c13-be6d-fdaddbf7ba92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591243819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3591243819
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.315800241
Short name T20
Test name
Test status
Simulation time 103614469514 ps
CPU time 595.57 seconds
Started Aug 11 04:27:57 PM PDT 24
Finished Aug 11 04:37:53 PM PDT 24
Peak memory 216296 kb
Host smart-9373eb77-4b9d-4f93-a565-c66fc7cd830d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315800241 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.315800241
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1470570591
Short name T1160
Test name
Test status
Simulation time 78391837878 ps
CPU time 157.01 seconds
Started Aug 11 04:27:58 PM PDT 24
Finished Aug 11 04:30:35 PM PDT 24
Peak memory 199680 kb
Host smart-26acf010-f46d-4397-a2d4-8292ed02e68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470570591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1470570591
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2546009227
Short name T118
Test name
Test status
Simulation time 171636076233 ps
CPU time 156.29 seconds
Started Aug 11 04:28:00 PM PDT 24
Finished Aug 11 04:30:36 PM PDT 24
Peak memory 215600 kb
Host smart-480879cf-8fb4-419a-9efc-6c1fe3f76cb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546009227 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2546009227
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1057347860
Short name T46
Test name
Test status
Simulation time 33506332315 ps
CPU time 26.14 seconds
Started Aug 11 04:28:00 PM PDT 24
Finished Aug 11 04:28:26 PM PDT 24
Peak memory 199676 kb
Host smart-b4edee71-9af8-4354-b0f5-fdc5241d0362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057347860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1057347860
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.2913206072
Short name T655
Test name
Test status
Simulation time 29940813465 ps
CPU time 501.11 seconds
Started Aug 11 04:27:59 PM PDT 24
Finished Aug 11 04:36:20 PM PDT 24
Peak memory 216668 kb
Host smart-8f285cdd-5dfd-42be-b83d-c8657084afe4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913206072 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.2913206072
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2756379580
Short name T47
Test name
Test status
Simulation time 18755632221 ps
CPU time 15.23 seconds
Started Aug 11 04:28:01 PM PDT 24
Finished Aug 11 04:28:16 PM PDT 24
Peak memory 199720 kb
Host smart-76cd1a64-1883-49f6-ad4c-6c7b89da77c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756379580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2756379580
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.4134675692
Short name T1096
Test name
Test status
Simulation time 26252748531 ps
CPU time 286.44 seconds
Started Aug 11 04:27:54 PM PDT 24
Finished Aug 11 04:32:41 PM PDT 24
Peak memory 216128 kb
Host smart-7b957376-3ba7-4ca3-abd1-7f28788a4dae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134675692 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.4134675692
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.545886430
Short name T119
Test name
Test status
Simulation time 29123556977 ps
CPU time 39.91 seconds
Started Aug 11 04:28:02 PM PDT 24
Finished Aug 11 04:28:42 PM PDT 24
Peak memory 199744 kb
Host smart-ef8979d1-f2f7-4aca-8a44-9628bbca752d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545886430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.545886430
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.2630601551
Short name T1001
Test name
Test status
Simulation time 17212816457 ps
CPU time 122.91 seconds
Started Aug 11 04:28:00 PM PDT 24
Finished Aug 11 04:30:03 PM PDT 24
Peak memory 208104 kb
Host smart-ff79d856-fd78-4eab-8b74-b5c45e515198
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630601551 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.2630601551
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.2724156727
Short name T746
Test name
Test status
Simulation time 47183357654 ps
CPU time 27.22 seconds
Started Aug 11 04:28:01 PM PDT 24
Finished Aug 11 04:28:28 PM PDT 24
Peak memory 199684 kb
Host smart-5cc9be82-ddbe-466d-9d9f-b676fb9f8d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724156727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2724156727
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.2268562581
Short name T878
Test name
Test status
Simulation time 11458681 ps
CPU time 0.6 seconds
Started Aug 11 04:26:17 PM PDT 24
Finished Aug 11 04:26:18 PM PDT 24
Peak memory 194556 kb
Host smart-0eba38e3-1c89-436e-906d-4777363d8f95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268562581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2268562581
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1429887779
Short name T164
Test name
Test status
Simulation time 140529174699 ps
CPU time 52.46 seconds
Started Aug 11 04:26:06 PM PDT 24
Finished Aug 11 04:26:59 PM PDT 24
Peak memory 199644 kb
Host smart-b5758414-2830-4126-b8d4-da9352a030a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429887779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1429887779
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.105643774
Short name T1085
Test name
Test status
Simulation time 113478671812 ps
CPU time 46.5 seconds
Started Aug 11 04:25:59 PM PDT 24
Finished Aug 11 04:26:46 PM PDT 24
Peak memory 199692 kb
Host smart-ddb0c0cb-3bbb-477d-801d-fe89fe20be4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105643774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.105643774
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.2829642247
Short name T215
Test name
Test status
Simulation time 155867711447 ps
CPU time 62.6 seconds
Started Aug 11 04:26:32 PM PDT 24
Finished Aug 11 04:27:35 PM PDT 24
Peak memory 199684 kb
Host smart-f58c0942-6b12-457b-b291-8b2c99c6a4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829642247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2829642247
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.3694297219
Short name T1071
Test name
Test status
Simulation time 35436975177 ps
CPU time 19 seconds
Started Aug 11 04:26:22 PM PDT 24
Finished Aug 11 04:26:41 PM PDT 24
Peak memory 199704 kb
Host smart-72491935-f9c0-4f24-8cea-16c68048e096
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694297219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3694297219
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.729916228
Short name T77
Test name
Test status
Simulation time 98155605360 ps
CPU time 257.1 seconds
Started Aug 11 04:26:05 PM PDT 24
Finished Aug 11 04:30:22 PM PDT 24
Peak memory 199652 kb
Host smart-6fb2d42d-20c1-4f9e-9a09-b3646d4841d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=729916228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.729916228
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.693463238
Short name T662
Test name
Test status
Simulation time 11346537868 ps
CPU time 6.93 seconds
Started Aug 11 04:26:23 PM PDT 24
Finished Aug 11 04:26:30 PM PDT 24
Peak memory 199252 kb
Host smart-cfbe0009-56fe-4d1d-9d31-6bb8bb9866d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693463238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.693463238
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.215630783
Short name T1069
Test name
Test status
Simulation time 124705218946 ps
CPU time 15.19 seconds
Started Aug 11 04:26:10 PM PDT 24
Finished Aug 11 04:26:26 PM PDT 24
Peak memory 195944 kb
Host smart-21eb4487-f21e-4bf7-9b69-b994d5253ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215630783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.215630783
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.585275720
Short name T492
Test name
Test status
Simulation time 30056972555 ps
CPU time 392.98 seconds
Started Aug 11 04:26:23 PM PDT 24
Finished Aug 11 04:32:56 PM PDT 24
Peak memory 199636 kb
Host smart-5947d600-fec4-49f4-b020-d292d3250dfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=585275720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.585275720
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3309521766
Short name T1092
Test name
Test status
Simulation time 3675286431 ps
CPU time 28.73 seconds
Started Aug 11 04:26:29 PM PDT 24
Finished Aug 11 04:26:58 PM PDT 24
Peak memory 197796 kb
Host smart-d9c76fd0-a32a-407a-b47f-90e564be37aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3309521766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3309521766
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.4285637317
Short name T976
Test name
Test status
Simulation time 110841454368 ps
CPU time 32.93 seconds
Started Aug 11 04:26:12 PM PDT 24
Finished Aug 11 04:26:45 PM PDT 24
Peak memory 199720 kb
Host smart-167915e9-748d-4352-8346-561e6d0c6c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285637317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.4285637317
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1495657629
Short name T531
Test name
Test status
Simulation time 43765911021 ps
CPU time 16.02 seconds
Started Aug 11 04:26:02 PM PDT 24
Finished Aug 11 04:26:18 PM PDT 24
Peak memory 196296 kb
Host smart-314480f5-ff87-4732-a2f7-ccc0dceb4524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495657629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1495657629
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.1600122029
Short name T803
Test name
Test status
Simulation time 310767926 ps
CPU time 1.56 seconds
Started Aug 11 04:26:31 PM PDT 24
Finished Aug 11 04:26:33 PM PDT 24
Peak memory 199420 kb
Host smart-2742c939-5883-40ce-98d1-599d8aa3bb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600122029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1600122029
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.3838699352
Short name T781
Test name
Test status
Simulation time 18201464023 ps
CPU time 35.44 seconds
Started Aug 11 04:26:43 PM PDT 24
Finished Aug 11 04:27:19 PM PDT 24
Peak memory 199828 kb
Host smart-db8e646e-b9dc-43a0-bfb5-e1e3791bed1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838699352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3838699352
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1612086820
Short name T34
Test name
Test status
Simulation time 103433590688 ps
CPU time 501.43 seconds
Started Aug 11 04:26:23 PM PDT 24
Finished Aug 11 04:34:44 PM PDT 24
Peak memory 216412 kb
Host smart-cb790f11-9f02-4fb8-b71a-2920c6f92d68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612086820 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1612086820
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.137886427
Short name T495
Test name
Test status
Simulation time 866157082 ps
CPU time 2.82 seconds
Started Aug 11 04:26:02 PM PDT 24
Finished Aug 11 04:26:05 PM PDT 24
Peak memory 198708 kb
Host smart-e2d87ab9-7171-432b-a008-13401e36ebb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137886427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.137886427
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.867733319
Short name T346
Test name
Test status
Simulation time 62221338898 ps
CPU time 14.42 seconds
Started Aug 11 04:26:09 PM PDT 24
Finished Aug 11 04:26:23 PM PDT 24
Peak memory 199628 kb
Host smart-63d95b63-e7df-4efd-9241-aba8cc710316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867733319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.867733319
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1987940957
Short name T690
Test name
Test status
Simulation time 155683282617 ps
CPU time 57.31 seconds
Started Aug 11 04:27:59 PM PDT 24
Finished Aug 11 04:28:56 PM PDT 24
Peak memory 200080 kb
Host smart-5e150d8f-cba2-4354-bfed-c7330445afec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987940957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1987940957
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.704748833
Short name T218
Test name
Test status
Simulation time 72503722794 ps
CPU time 115.24 seconds
Started Aug 11 04:28:01 PM PDT 24
Finished Aug 11 04:29:57 PM PDT 24
Peak memory 199684 kb
Host smart-73015262-b803-4876-b05b-2f80b33943b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704748833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.704748833
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1482138075
Short name T1052
Test name
Test status
Simulation time 448211158115 ps
CPU time 425.3 seconds
Started Aug 11 04:28:02 PM PDT 24
Finished Aug 11 04:35:08 PM PDT 24
Peak memory 216288 kb
Host smart-699e5787-3479-4770-8b31-47f7506aa849
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482138075 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1482138075
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.4104146578
Short name T206
Test name
Test status
Simulation time 14843391004 ps
CPU time 22.27 seconds
Started Aug 11 04:28:00 PM PDT 24
Finished Aug 11 04:28:22 PM PDT 24
Peak memory 199708 kb
Host smart-06e003f5-2275-4d0f-adac-abf003c7ac55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104146578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.4104146578
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3396202884
Short name T62
Test name
Test status
Simulation time 94457855531 ps
CPU time 1857.07 seconds
Started Aug 11 04:28:04 PM PDT 24
Finished Aug 11 04:59:07 PM PDT 24
Peak memory 224428 kb
Host smart-198c3261-3627-4938-9ed7-e627185c39e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396202884 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3396202884
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3006494811
Short name T958
Test name
Test status
Simulation time 56441699209 ps
CPU time 21.8 seconds
Started Aug 11 04:28:06 PM PDT 24
Finished Aug 11 04:28:28 PM PDT 24
Peak memory 199752 kb
Host smart-3bd1b9a2-b2ed-4b22-b496-078c58c17a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006494811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3006494811
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.834641720
Short name T29
Test name
Test status
Simulation time 152144467672 ps
CPU time 41.66 seconds
Started Aug 11 04:27:59 PM PDT 24
Finished Aug 11 04:28:41 PM PDT 24
Peak memory 199628 kb
Host smart-6d843a39-c894-42d9-8f53-a46b263b298e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834641720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.834641720
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.2630979797
Short name T250
Test name
Test status
Simulation time 420560720879 ps
CPU time 823.04 seconds
Started Aug 11 04:27:56 PM PDT 24
Finished Aug 11 04:41:39 PM PDT 24
Peak memory 232480 kb
Host smart-3e8ea2e2-e3e3-40ea-8a7f-6303b8547331
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630979797 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.2630979797
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2808555998
Short name T756
Test name
Test status
Simulation time 43015553358 ps
CPU time 33.42 seconds
Started Aug 11 04:28:04 PM PDT 24
Finished Aug 11 04:28:38 PM PDT 24
Peak memory 199772 kb
Host smart-afc6c6d4-957a-4a94-b989-55b53765876b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808555998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2808555998
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.1433627910
Short name T116
Test name
Test status
Simulation time 183262232561 ps
CPU time 473.09 seconds
Started Aug 11 04:28:01 PM PDT 24
Finished Aug 11 04:35:55 PM PDT 24
Peak memory 224508 kb
Host smart-a770bcaf-df00-4026-a27b-e52671146609
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433627910 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.1433627910
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1927988464
Short name T1060
Test name
Test status
Simulation time 91304351295 ps
CPU time 43.22 seconds
Started Aug 11 04:28:01 PM PDT 24
Finished Aug 11 04:28:44 PM PDT 24
Peak memory 199724 kb
Host smart-fd11539f-9c68-42bd-96d2-4baa4c74a864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927988464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1927988464
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.1038782964
Short name T1098
Test name
Test status
Simulation time 41248965913 ps
CPU time 483.94 seconds
Started Aug 11 04:28:04 PM PDT 24
Finished Aug 11 04:36:08 PM PDT 24
Peak memory 216384 kb
Host smart-2355ff58-844f-4145-8581-3a22dfbc7ed8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038782964 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.1038782964
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.2024419817
Short name T432
Test name
Test status
Simulation time 28052129242 ps
CPU time 12.3 seconds
Started Aug 11 04:27:56 PM PDT 24
Finished Aug 11 04:28:09 PM PDT 24
Peak memory 198256 kb
Host smart-e545ce8e-0baf-4b06-a179-1609a3539d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024419817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2024419817
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.3461458918
Short name T60
Test name
Test status
Simulation time 44056680202 ps
CPU time 491.01 seconds
Started Aug 11 04:27:57 PM PDT 24
Finished Aug 11 04:36:08 PM PDT 24
Peak memory 216300 kb
Host smart-3e579586-bb4f-4f89-95f0-7cd5962fd7f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461458918 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.3461458918
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2001305156
Short name T556
Test name
Test status
Simulation time 41634569335 ps
CPU time 14.17 seconds
Started Aug 11 04:27:57 PM PDT 24
Finished Aug 11 04:28:11 PM PDT 24
Peak memory 199772 kb
Host smart-471af541-66b7-47df-8011-c1ee1ff9065f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001305156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2001305156
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2151066720
Short name T1110
Test name
Test status
Simulation time 68976484207 ps
CPU time 534.94 seconds
Started Aug 11 04:28:01 PM PDT 24
Finished Aug 11 04:36:56 PM PDT 24
Peak memory 224740 kb
Host smart-30495e6c-8b92-463c-ab2d-5b44a603c169
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151066720 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2151066720
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.2407301075
Short name T292
Test name
Test status
Simulation time 53561589139 ps
CPU time 46.54 seconds
Started Aug 11 04:28:02 PM PDT 24
Finished Aug 11 04:28:49 PM PDT 24
Peak memory 199772 kb
Host smart-22e2941b-a3c6-4c03-9adc-5774294786b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407301075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2407301075
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.494546294
Short name T59
Test name
Test status
Simulation time 212474960883 ps
CPU time 832.98 seconds
Started Aug 11 04:27:57 PM PDT 24
Finished Aug 11 04:41:51 PM PDT 24
Peak memory 216360 kb
Host smart-d61c3724-bef4-4a53-b43f-739f33013447
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494546294 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.494546294
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.3061375087
Short name T427
Test name
Test status
Simulation time 37071798 ps
CPU time 0.55 seconds
Started Aug 11 04:26:17 PM PDT 24
Finished Aug 11 04:26:18 PM PDT 24
Peak memory 195136 kb
Host smart-24ff311b-cdd4-40a1-8e61-6255e966c171
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061375087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3061375087
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.1710446136
Short name T946
Test name
Test status
Simulation time 203762824875 ps
CPU time 40.28 seconds
Started Aug 11 04:26:13 PM PDT 24
Finished Aug 11 04:26:53 PM PDT 24
Peak memory 199708 kb
Host smart-433d87cc-9397-44df-9dc4-caff390312f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710446136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1710446136
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.298240883
Short name T136
Test name
Test status
Simulation time 71356224109 ps
CPU time 25.99 seconds
Started Aug 11 04:26:10 PM PDT 24
Finished Aug 11 04:26:37 PM PDT 24
Peak memory 199680 kb
Host smart-a4a77922-ed06-4eac-9d2a-f5429786b4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298240883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.298240883
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.3705464620
Short name T580
Test name
Test status
Simulation time 66078882366 ps
CPU time 160.64 seconds
Started Aug 11 04:26:07 PM PDT 24
Finished Aug 11 04:28:48 PM PDT 24
Peak memory 199740 kb
Host smart-ba4736ef-2195-4c78-9ac3-5ace492f30e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705464620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.3705464620
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.2333280005
Short name T665
Test name
Test status
Simulation time 40189901200 ps
CPU time 10.55 seconds
Started Aug 11 04:26:15 PM PDT 24
Finished Aug 11 04:26:26 PM PDT 24
Peak memory 199612 kb
Host smart-f6b7fdd9-6e08-44a8-9d01-34214d6a2e14
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333280005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2333280005
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.34827048
Short name T319
Test name
Test status
Simulation time 108378206617 ps
CPU time 117.9 seconds
Started Aug 11 04:26:01 PM PDT 24
Finished Aug 11 04:27:59 PM PDT 24
Peak memory 199752 kb
Host smart-77ca3d39-205e-4833-aa57-5e2da3b3222b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34827048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.34827048
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.336928038
Short name T10
Test name
Test status
Simulation time 11793713759 ps
CPU time 22.43 seconds
Started Aug 11 04:25:59 PM PDT 24
Finished Aug 11 04:26:22 PM PDT 24
Peak memory 199712 kb
Host smart-2940611e-7565-488c-b5ae-50696d363e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336928038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.336928038
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.2353341420
Short name T1104
Test name
Test status
Simulation time 56656002255 ps
CPU time 83.1 seconds
Started Aug 11 04:26:20 PM PDT 24
Finished Aug 11 04:27:43 PM PDT 24
Peak memory 199524 kb
Host smart-a15ba29c-3e87-4dfb-b98a-287dd7f62bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353341420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2353341420
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.3100623346
Short name T949
Test name
Test status
Simulation time 14214069598 ps
CPU time 176.41 seconds
Started Aug 11 04:26:11 PM PDT 24
Finished Aug 11 04:29:07 PM PDT 24
Peak memory 199684 kb
Host smart-dbc5e2c9-3ddb-412b-a53b-6fc907e8654f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3100623346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3100623346
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.2654677587
Short name T52
Test name
Test status
Simulation time 3608739731 ps
CPU time 14.43 seconds
Started Aug 11 04:26:14 PM PDT 24
Finished Aug 11 04:26:28 PM PDT 24
Peak memory 198460 kb
Host smart-8bdd50f7-fdbb-4ab9-a4d4-504bb4c1cabf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2654677587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2654677587
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1732174776
Short name T590
Test name
Test status
Simulation time 63906165798 ps
CPU time 115.44 seconds
Started Aug 11 04:26:15 PM PDT 24
Finished Aug 11 04:28:11 PM PDT 24
Peak memory 199624 kb
Host smart-2755afa4-4ac1-4cba-bb3c-c6e3b4c49633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732174776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1732174776
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.2575032641
Short name T386
Test name
Test status
Simulation time 5006413311 ps
CPU time 5.45 seconds
Started Aug 11 04:26:39 PM PDT 24
Finished Aug 11 04:26:45 PM PDT 24
Peak memory 196368 kb
Host smart-02a61ef0-229c-4afb-9c39-ddc4d4487ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575032641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2575032641
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2688387030
Short name T491
Test name
Test status
Simulation time 495822022 ps
CPU time 1.09 seconds
Started Aug 11 04:26:10 PM PDT 24
Finished Aug 11 04:26:11 PM PDT 24
Peak memory 198464 kb
Host smart-efcc7e21-2f6e-4c0d-8952-ce8280fc8673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688387030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2688387030
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.2938150718
Short name T757
Test name
Test status
Simulation time 54067234850 ps
CPU time 93.87 seconds
Started Aug 11 04:26:24 PM PDT 24
Finished Aug 11 04:27:58 PM PDT 24
Peak memory 199528 kb
Host smart-69362c8a-745f-4e8b-8e5d-76a87c8ffc71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938150718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2938150718
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.1527802981
Short name T1044
Test name
Test status
Simulation time 547281784 ps
CPU time 1.37 seconds
Started Aug 11 04:26:14 PM PDT 24
Finished Aug 11 04:26:15 PM PDT 24
Peak memory 198292 kb
Host smart-e98eda77-d0f5-4fd2-a26b-5ee95f6b5510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527802981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1527802981
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2114207058
Short name T874
Test name
Test status
Simulation time 84248495581 ps
CPU time 52.37 seconds
Started Aug 11 04:26:19 PM PDT 24
Finished Aug 11 04:27:11 PM PDT 24
Peak memory 199672 kb
Host smart-156a8d3d-8e30-400b-bd02-f3194e129106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114207058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2114207058
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2173831368
Short name T138
Test name
Test status
Simulation time 20755084981 ps
CPU time 14.8 seconds
Started Aug 11 04:27:57 PM PDT 24
Finished Aug 11 04:28:12 PM PDT 24
Peak memory 199780 kb
Host smart-5086581c-c92d-4af5-b75c-d21b73b4820d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173831368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2173831368
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.2017617192
Short name T57
Test name
Test status
Simulation time 48432559767 ps
CPU time 381.3 seconds
Started Aug 11 04:28:01 PM PDT 24
Finished Aug 11 04:34:22 PM PDT 24
Peak memory 215476 kb
Host smart-12bda8da-fc3e-4505-9116-69dd31b0e5e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017617192 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.2017617192
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1864101492
Short name T372
Test name
Test status
Simulation time 9683924193 ps
CPU time 14.79 seconds
Started Aug 11 04:28:18 PM PDT 24
Finished Aug 11 04:28:33 PM PDT 24
Peak memory 199328 kb
Host smart-804637fd-d86f-4ad3-a8e7-928b2783e0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864101492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1864101492
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.1798790623
Short name T1005
Test name
Test status
Simulation time 14117580565 ps
CPU time 31.67 seconds
Started Aug 11 04:28:01 PM PDT 24
Finished Aug 11 04:28:33 PM PDT 24
Peak memory 199688 kb
Host smart-af30f388-8ccd-4850-9931-bbe3e64350be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798790623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1798790623
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3356418566
Short name T183
Test name
Test status
Simulation time 1220674479182 ps
CPU time 1204.37 seconds
Started Aug 11 04:28:32 PM PDT 24
Finished Aug 11 04:48:36 PM PDT 24
Peak memory 224688 kb
Host smart-cfcdb200-66a8-4a03-997d-17f08c55270e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356418566 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3356418566
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.4069049985
Short name T920
Test name
Test status
Simulation time 205327861589 ps
CPU time 60.52 seconds
Started Aug 11 04:27:58 PM PDT 24
Finished Aug 11 04:28:58 PM PDT 24
Peak memory 199672 kb
Host smart-d2fddde0-00a5-4c31-8e5c-f8ef404f51f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069049985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.4069049985
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3453344808
Short name T1161
Test name
Test status
Simulation time 28180889703 ps
CPU time 545.66 seconds
Started Aug 11 04:28:00 PM PDT 24
Finished Aug 11 04:37:06 PM PDT 24
Peak memory 215236 kb
Host smart-5108cb5b-9a7d-4ad1-92a1-4a327710900f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453344808 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3453344808
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.2880034480
Short name T264
Test name
Test status
Simulation time 30657628962 ps
CPU time 21.54 seconds
Started Aug 11 04:28:01 PM PDT 24
Finished Aug 11 04:28:22 PM PDT 24
Peak memory 199836 kb
Host smart-35e2d24b-c5bc-4110-bcc8-48d450942ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880034480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2880034480
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1897354900
Short name T1063
Test name
Test status
Simulation time 217078686137 ps
CPU time 743.47 seconds
Started Aug 11 04:28:02 PM PDT 24
Finished Aug 11 04:40:26 PM PDT 24
Peak memory 213684 kb
Host smart-72b35b21-346c-42f4-8bc8-9192ba9fdbe4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897354900 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1897354900
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1730413749
Short name T649
Test name
Test status
Simulation time 299223422941 ps
CPU time 399.01 seconds
Started Aug 11 04:28:04 PM PDT 24
Finished Aug 11 04:34:43 PM PDT 24
Peak memory 209452 kb
Host smart-efb6e856-6aa7-4ec2-98ee-0864eb4f0920
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730413749 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1730413749
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.2236124255
Short name T150
Test name
Test status
Simulation time 106374197490 ps
CPU time 94.29 seconds
Started Aug 11 04:28:03 PM PDT 24
Finished Aug 11 04:29:37 PM PDT 24
Peak memory 199752 kb
Host smart-ee4574d7-6455-44f0-a638-e301d939ae82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236124255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.2236124255
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.3803262281
Short name T917
Test name
Test status
Simulation time 97526436080 ps
CPU time 641.75 seconds
Started Aug 11 04:28:02 PM PDT 24
Finished Aug 11 04:38:44 PM PDT 24
Peak memory 216284 kb
Host smart-607227fd-edf9-449c-8d04-f3ad6ec2781c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803262281 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.3803262281
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3150589752
Short name T235
Test name
Test status
Simulation time 12495310373 ps
CPU time 23.15 seconds
Started Aug 11 04:28:07 PM PDT 24
Finished Aug 11 04:28:30 PM PDT 24
Peak memory 199792 kb
Host smart-a9d977e9-b60d-4de1-bffb-9d480bbe66b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150589752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3150589752
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.3518466630
Short name T1123
Test name
Test status
Simulation time 165579284468 ps
CPU time 801.38 seconds
Started Aug 11 04:28:28 PM PDT 24
Finished Aug 11 04:41:50 PM PDT 24
Peak memory 215076 kb
Host smart-146c7412-5e14-4c2e-892a-5115c7c6a8f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518466630 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3518466630
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2641046958
Short name T196
Test name
Test status
Simulation time 8895552100 ps
CPU time 14.63 seconds
Started Aug 11 04:28:02 PM PDT 24
Finished Aug 11 04:28:17 PM PDT 24
Peak memory 199228 kb
Host smart-9ec8b91b-5564-4f67-8d7d-6e05114310fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641046958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2641046958
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.3949038653
Short name T132
Test name
Test status
Simulation time 414771109242 ps
CPU time 615.57 seconds
Started Aug 11 04:28:08 PM PDT 24
Finished Aug 11 04:38:24 PM PDT 24
Peak memory 216160 kb
Host smart-5b9e2208-e65d-4b1f-a5de-04d80f5103f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949038653 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.3949038653
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1444367116
Short name T425
Test name
Test status
Simulation time 21950852 ps
CPU time 0.53 seconds
Started Aug 11 04:26:29 PM PDT 24
Finished Aug 11 04:26:29 PM PDT 24
Peak memory 195104 kb
Host smart-b40e0d0f-37a0-44dc-addb-45f6e4dfcd61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444367116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1444367116
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3949373760
Short name T605
Test name
Test status
Simulation time 88650110585 ps
CPU time 123.3 seconds
Started Aug 11 04:26:02 PM PDT 24
Finished Aug 11 04:28:05 PM PDT 24
Peak memory 199664 kb
Host smart-71021177-b0ba-4c34-997d-d5e836b4dd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949373760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3949373760
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.3618083433
Short name T517
Test name
Test status
Simulation time 164755024516 ps
CPU time 65.46 seconds
Started Aug 11 04:26:10 PM PDT 24
Finished Aug 11 04:27:16 PM PDT 24
Peak memory 199672 kb
Host smart-addb8bde-af34-441a-9f6e-4bde13e75867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618083433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3618083433
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.16456593
Short name T262
Test name
Test status
Simulation time 54282069840 ps
CPU time 184.19 seconds
Started Aug 11 04:26:01 PM PDT 24
Finished Aug 11 04:29:06 PM PDT 24
Peak memory 199716 kb
Host smart-3639c53a-0bdd-4298-950b-51297c37ec76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16456593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.16456593
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.1338968150
Short name T455
Test name
Test status
Simulation time 53615185746 ps
CPU time 215.99 seconds
Started Aug 11 04:26:13 PM PDT 24
Finished Aug 11 04:29:49 PM PDT 24
Peak memory 199688 kb
Host smart-6eeb277e-ba7f-40a5-9b61-437ae15c1001
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1338968150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1338968150
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.3378892565
Short name T769
Test name
Test status
Simulation time 4091448670 ps
CPU time 3.94 seconds
Started Aug 11 04:26:11 PM PDT 24
Finished Aug 11 04:26:15 PM PDT 24
Peak memory 198948 kb
Host smart-01333360-a2ca-4ff7-bf98-2442e5579956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378892565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3378892565
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.3427000760
Short name T30
Test name
Test status
Simulation time 9542943432 ps
CPU time 13.06 seconds
Started Aug 11 04:26:17 PM PDT 24
Finished Aug 11 04:26:30 PM PDT 24
Peak memory 195320 kb
Host smart-abd8c6bf-e527-443c-b898-70ea015035c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427000760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3427000760
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.17186152
Short name T833
Test name
Test status
Simulation time 19415213517 ps
CPU time 137.23 seconds
Started Aug 11 04:26:21 PM PDT 24
Finished Aug 11 04:28:38 PM PDT 24
Peak memory 199692 kb
Host smart-f6105778-daac-4382-b92c-a589f6b7e60a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=17186152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.17186152
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3949468415
Short name T374
Test name
Test status
Simulation time 2250289621 ps
CPU time 3.21 seconds
Started Aug 11 04:26:03 PM PDT 24
Finished Aug 11 04:26:06 PM PDT 24
Peak memory 198364 kb
Host smart-1dbfeac8-e079-4871-b86a-30aafa4d2d56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3949468415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3949468415
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3255863671
Short name T518
Test name
Test status
Simulation time 205263132898 ps
CPU time 120.6 seconds
Started Aug 11 04:26:30 PM PDT 24
Finished Aug 11 04:28:31 PM PDT 24
Peak memory 199716 kb
Host smart-7372f940-4b02-4dc1-b93c-dcc4e58b524a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255863671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3255863671
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1806912138
Short name T125
Test name
Test status
Simulation time 1406674880 ps
CPU time 2.84 seconds
Started Aug 11 04:26:46 PM PDT 24
Finished Aug 11 04:26:49 PM PDT 24
Peak memory 195224 kb
Host smart-8c7f673a-710f-402f-a894-fec56c442374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806912138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1806912138
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.4261054814
Short name T280
Test name
Test status
Simulation time 5882049063 ps
CPU time 3.76 seconds
Started Aug 11 04:26:11 PM PDT 24
Finished Aug 11 04:26:15 PM PDT 24
Peak memory 199028 kb
Host smart-0b101139-f9a0-496b-b19d-ea87915f6329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261054814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.4261054814
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.2357351543
Short name T478
Test name
Test status
Simulation time 457932925916 ps
CPU time 424.44 seconds
Started Aug 11 04:26:39 PM PDT 24
Finished Aug 11 04:33:44 PM PDT 24
Peak memory 199784 kb
Host smart-0971ba2b-54f8-439d-8842-e3f11210bef7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357351543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2357351543
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.380479596
Short name T660
Test name
Test status
Simulation time 25208740608 ps
CPU time 673.86 seconds
Started Aug 11 04:26:09 PM PDT 24
Finished Aug 11 04:37:23 PM PDT 24
Peak memory 209132 kb
Host smart-82f96d0c-3875-459c-920b-301661a05945
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380479596 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.380479596
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.996190296
Short name T595
Test name
Test status
Simulation time 1243356284 ps
CPU time 3.01 seconds
Started Aug 11 04:26:21 PM PDT 24
Finished Aug 11 04:26:24 PM PDT 24
Peak memory 198664 kb
Host smart-f584a470-7680-49a6-9d0c-b2fa123631a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996190296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.996190296
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.1350403398
Short name T1058
Test name
Test status
Simulation time 97455890222 ps
CPU time 45.81 seconds
Started Aug 11 04:26:00 PM PDT 24
Finished Aug 11 04:26:46 PM PDT 24
Peak memory 199724 kb
Host smart-0168ad8c-50f2-4e1b-b2f2-2240292886fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350403398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1350403398
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.882827504
Short name T856
Test name
Test status
Simulation time 77284532846 ps
CPU time 206.12 seconds
Started Aug 11 04:28:02 PM PDT 24
Finished Aug 11 04:31:28 PM PDT 24
Peak memory 199772 kb
Host smart-e8080471-f979-4caa-b5b1-5c8e6378e188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882827504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.882827504
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.771351541
Short name T467
Test name
Test status
Simulation time 133262789155 ps
CPU time 773.65 seconds
Started Aug 11 04:28:24 PM PDT 24
Finished Aug 11 04:41:18 PM PDT 24
Peak memory 224596 kb
Host smart-49093de9-239d-48f0-b00a-405663a56462
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771351541 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.771351541
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3109814148
Short name T841
Test name
Test status
Simulation time 13020886283 ps
CPU time 27.66 seconds
Started Aug 11 04:28:02 PM PDT 24
Finished Aug 11 04:28:30 PM PDT 24
Peak memory 199684 kb
Host smart-6bd16c99-2615-48e7-babc-9945bdecc94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109814148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3109814148
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3997445397
Short name T901
Test name
Test status
Simulation time 52020657746 ps
CPU time 413.73 seconds
Started Aug 11 04:28:04 PM PDT 24
Finished Aug 11 04:34:58 PM PDT 24
Peak memory 216288 kb
Host smart-1c320ec1-db1c-4765-a31b-9a1aac088bf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997445397 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3997445397
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.4255745232
Short name T248
Test name
Test status
Simulation time 56167302745 ps
CPU time 53.05 seconds
Started Aug 11 04:28:04 PM PDT 24
Finished Aug 11 04:28:58 PM PDT 24
Peak memory 200124 kb
Host smart-fb31cd53-84d8-41ba-8eab-5ea428c7b2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255745232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.4255745232
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.709656572
Short name T33
Test name
Test status
Simulation time 20089079797 ps
CPU time 226.19 seconds
Started Aug 11 04:28:18 PM PDT 24
Finished Aug 11 04:32:04 PM PDT 24
Peak memory 216428 kb
Host smart-731824ed-79e4-4dc1-9a8f-695070987be0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709656572 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.709656572
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.4252453079
Short name T205
Test name
Test status
Simulation time 91085100322 ps
CPU time 44.25 seconds
Started Aug 11 04:28:40 PM PDT 24
Finished Aug 11 04:29:24 PM PDT 24
Peak memory 199720 kb
Host smart-d73c804a-86b1-4c92-a9bf-37790fcdda5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252453079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.4252453079
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2505714351
Short name T652
Test name
Test status
Simulation time 153170797006 ps
CPU time 320.51 seconds
Started Aug 11 04:28:36 PM PDT 24
Finished Aug 11 04:33:57 PM PDT 24
Peak memory 216316 kb
Host smart-349cd441-108e-433a-b3e8-127f2fe7ae9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505714351 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2505714351
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.4242483327
Short name T795
Test name
Test status
Simulation time 41130560634 ps
CPU time 54.28 seconds
Started Aug 11 04:28:39 PM PDT 24
Finished Aug 11 04:29:34 PM PDT 24
Peak memory 199708 kb
Host smart-40531662-d808-47ad-b6c1-a7f9072d176a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242483327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.4242483327
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.4191982062
Short name T12
Test name
Test status
Simulation time 51269579040 ps
CPU time 596.35 seconds
Started Aug 11 04:28:08 PM PDT 24
Finished Aug 11 04:38:05 PM PDT 24
Peak memory 216412 kb
Host smart-8b87de6c-cfd1-4b9b-96ce-5e523cfe905b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191982062 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.4191982062
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2832738093
Short name T930
Test name
Test status
Simulation time 60498581453 ps
CPU time 97.47 seconds
Started Aug 11 04:28:03 PM PDT 24
Finished Aug 11 04:29:40 PM PDT 24
Peak memory 199672 kb
Host smart-066e71b2-bfe3-4623-81e8-bc7365a5b191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832738093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2832738093
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.647784028
Short name T755
Test name
Test status
Simulation time 26262400791 ps
CPU time 283.99 seconds
Started Aug 11 04:28:09 PM PDT 24
Finished Aug 11 04:32:53 PM PDT 24
Peak memory 215528 kb
Host smart-7010f2d0-ca78-417a-adc2-191645435d1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647784028 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.647784028
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.773771581
Short name T349
Test name
Test status
Simulation time 96254708452 ps
CPU time 240.06 seconds
Started Aug 11 04:28:06 PM PDT 24
Finished Aug 11 04:32:06 PM PDT 24
Peak memory 199772 kb
Host smart-1834a969-42a6-4c37-b303-95e40bee68be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773771581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.773771581
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.2120111552
Short name T1145
Test name
Test status
Simulation time 85226283398 ps
CPU time 274.73 seconds
Started Aug 11 04:28:06 PM PDT 24
Finished Aug 11 04:32:41 PM PDT 24
Peak memory 216300 kb
Host smart-76c6c393-cd12-488d-99df-c67c6c839884
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120111552 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.2120111552
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.497223958
Short name T387
Test name
Test status
Simulation time 38925794073 ps
CPU time 13.78 seconds
Started Aug 11 04:28:02 PM PDT 24
Finished Aug 11 04:28:16 PM PDT 24
Peak memory 199688 kb
Host smart-548c6dc4-765f-4d1f-9140-a011ab939374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497223958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.497223958
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.2144545507
Short name T1179
Test name
Test status
Simulation time 472720025616 ps
CPU time 1184.26 seconds
Started Aug 11 04:28:10 PM PDT 24
Finished Aug 11 04:47:54 PM PDT 24
Peak memory 216248 kb
Host smart-cd709ca0-11d3-434b-9309-7af2ffbf1bf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144545507 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.2144545507
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.4121734881
Short name T226
Test name
Test status
Simulation time 34161035789 ps
CPU time 29.89 seconds
Started Aug 11 04:28:07 PM PDT 24
Finished Aug 11 04:28:37 PM PDT 24
Peak memory 200084 kb
Host smart-2552aacc-08b3-49b0-ab09-6c00f98e5167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121734881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.4121734881
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.583559265
Short name T115
Test name
Test status
Simulation time 58869994918 ps
CPU time 234.93 seconds
Started Aug 11 04:28:08 PM PDT 24
Finished Aug 11 04:32:03 PM PDT 24
Peak memory 212952 kb
Host smart-9ff038b7-b2cf-427c-acf5-144b7a576aab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583559265 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.583559265
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.248312747
Short name T591
Test name
Test status
Simulation time 20949926970 ps
CPU time 17 seconds
Started Aug 11 04:28:10 PM PDT 24
Finished Aug 11 04:28:27 PM PDT 24
Peak memory 199888 kb
Host smart-14050190-5f2f-4f62-9693-656c86b111f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248312747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.248312747
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2476005990
Short name T1076
Test name
Test status
Simulation time 35939584383 ps
CPU time 688.47 seconds
Started Aug 11 04:28:08 PM PDT 24
Finished Aug 11 04:39:36 PM PDT 24
Peak memory 216284 kb
Host smart-bd1bff1b-398d-4bcf-b0a4-0bef0dc69fd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476005990 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2476005990
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.1644423771
Short name T438
Test name
Test status
Simulation time 15038686 ps
CPU time 0.55 seconds
Started Aug 11 04:26:24 PM PDT 24
Finished Aug 11 04:26:25 PM PDT 24
Peak memory 195084 kb
Host smart-4cfc79ca-3ac4-4765-bd14-93a2f636d8fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644423771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1644423771
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.4077605475
Short name T622
Test name
Test status
Simulation time 126244621035 ps
CPU time 140.88 seconds
Started Aug 11 04:26:21 PM PDT 24
Finished Aug 11 04:28:42 PM PDT 24
Peak memory 199624 kb
Host smart-95456de1-a545-4062-8f19-411845c414e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077605475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.4077605475
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.3217227422
Short name T1166
Test name
Test status
Simulation time 48182520147 ps
CPU time 17.76 seconds
Started Aug 11 04:26:20 PM PDT 24
Finished Aug 11 04:26:38 PM PDT 24
Peak memory 199748 kb
Host smart-135000d8-6f31-43e1-ba1a-e49c0ed47a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217227422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3217227422
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.2569094881
Short name T814
Test name
Test status
Simulation time 171693307496 ps
CPU time 48.01 seconds
Started Aug 11 04:26:19 PM PDT 24
Finished Aug 11 04:27:07 PM PDT 24
Peak memory 199856 kb
Host smart-41e7f049-2c6d-409c-b998-1ff43c8a95ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569094881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2569094881
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.1714619413
Short name T813
Test name
Test status
Simulation time 20139454067 ps
CPU time 44.67 seconds
Started Aug 11 04:26:33 PM PDT 24
Finished Aug 11 04:27:18 PM PDT 24
Peak memory 199700 kb
Host smart-f8151b64-11e0-472f-a10a-e193bf21d800
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714619413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1714619413
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.3449234512
Short name T837
Test name
Test status
Simulation time 178052849212 ps
CPU time 523.23 seconds
Started Aug 11 04:26:14 PM PDT 24
Finished Aug 11 04:34:57 PM PDT 24
Peak memory 199656 kb
Host smart-1f5d4c9e-09d1-42c3-811c-ce0dfd2da813
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3449234512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3449234512
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.674699566
Short name T1155
Test name
Test status
Simulation time 1942485053 ps
CPU time 1.74 seconds
Started Aug 11 04:26:21 PM PDT 24
Finished Aug 11 04:26:23 PM PDT 24
Peak memory 197596 kb
Host smart-03517622-6c74-4b11-b3a1-cd15ba940668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674699566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.674699566
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1025619937
Short name T927
Test name
Test status
Simulation time 94783547322 ps
CPU time 83.23 seconds
Started Aug 11 04:26:06 PM PDT 24
Finished Aug 11 04:27:30 PM PDT 24
Peak memory 199856 kb
Host smart-f8ebe074-ac51-46e1-a5c2-5aa68b37158f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025619937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1025619937
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.2346905284
Short name T703
Test name
Test status
Simulation time 17329186624 ps
CPU time 924.51 seconds
Started Aug 11 04:26:11 PM PDT 24
Finished Aug 11 04:41:35 PM PDT 24
Peak memory 199740 kb
Host smart-aca1579e-bb04-4591-a94c-c47b94125287
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2346905284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2346905284
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.806937876
Short name T791
Test name
Test status
Simulation time 3388934773 ps
CPU time 6.66 seconds
Started Aug 11 04:26:32 PM PDT 24
Finished Aug 11 04:26:39 PM PDT 24
Peak memory 198836 kb
Host smart-a937d2de-933b-4d1f-a05d-7273d8498ab0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=806937876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.806937876
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.179158672
Short name T1146
Test name
Test status
Simulation time 68510388550 ps
CPU time 53.35 seconds
Started Aug 11 04:26:45 PM PDT 24
Finished Aug 11 04:27:38 PM PDT 24
Peak memory 200148 kb
Host smart-39e12a7b-25d6-4ca2-89d9-3ef915a537ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179158672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.179158672
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1254730611
Short name T871
Test name
Test status
Simulation time 4555415289 ps
CPU time 0.94 seconds
Started Aug 11 04:26:19 PM PDT 24
Finished Aug 11 04:26:20 PM PDT 24
Peak memory 195888 kb
Host smart-028968dc-3fa0-4c11-9c46-e628e1def7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254730611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1254730611
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1924640394
Short name T888
Test name
Test status
Simulation time 6077342465 ps
CPU time 24.19 seconds
Started Aug 11 04:26:41 PM PDT 24
Finished Aug 11 04:27:06 PM PDT 24
Peak memory 200052 kb
Host smart-5b6ca9a6-d0ac-4236-a3a5-bbfb6f250378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924640394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1924640394
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.124804498
Short name T547
Test name
Test status
Simulation time 234437280196 ps
CPU time 337.05 seconds
Started Aug 11 04:26:27 PM PDT 24
Finished Aug 11 04:32:04 PM PDT 24
Peak memory 208148 kb
Host smart-0cf37a96-b399-427f-a701-c9679e6d5af1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124804498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.124804498
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.761827999
Short name T572
Test name
Test status
Simulation time 47569482807 ps
CPU time 610.79 seconds
Started Aug 11 04:26:13 PM PDT 24
Finished Aug 11 04:36:23 PM PDT 24
Peak memory 224628 kb
Host smart-f180af81-ef9b-459a-97e0-e7a035e4ab70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761827999 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.761827999
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.3639154080
Short name T860
Test name
Test status
Simulation time 6421865197 ps
CPU time 14.99 seconds
Started Aug 11 04:26:44 PM PDT 24
Finished Aug 11 04:26:59 PM PDT 24
Peak memory 199740 kb
Host smart-f0a17725-9c03-48af-a436-72d1d30c3314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639154080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3639154080
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2127018780
Short name T850
Test name
Test status
Simulation time 16308748744 ps
CPU time 15.57 seconds
Started Aug 11 04:26:27 PM PDT 24
Finished Aug 11 04:26:43 PM PDT 24
Peak memory 199696 kb
Host smart-8bd6bd11-a70c-426e-a893-0099d409f9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127018780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2127018780
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.4188888451
Short name T302
Test name
Test status
Simulation time 73337589931 ps
CPU time 173.48 seconds
Started Aug 11 04:28:08 PM PDT 24
Finished Aug 11 04:31:02 PM PDT 24
Peak memory 199740 kb
Host smart-624f6dae-88bb-4e3c-841c-dafd306eab00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188888451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.4188888451
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.2698239133
Short name T306
Test name
Test status
Simulation time 254149697581 ps
CPU time 572.08 seconds
Started Aug 11 04:28:03 PM PDT 24
Finished Aug 11 04:37:36 PM PDT 24
Peak memory 224648 kb
Host smart-55b1faa3-e045-4828-85a7-24e3db76ed6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698239133 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2698239133
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.284835844
Short name T186
Test name
Test status
Simulation time 37622402801 ps
CPU time 16.81 seconds
Started Aug 11 04:28:03 PM PDT 24
Finished Aug 11 04:28:20 PM PDT 24
Peak memory 199576 kb
Host smart-446dd08b-3373-46a3-9458-f41190200dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284835844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.284835844
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.155886
Short name T340
Test name
Test status
Simulation time 14236757452 ps
CPU time 229.39 seconds
Started Aug 11 04:28:02 PM PDT 24
Finished Aug 11 04:31:52 PM PDT 24
Peak memory 209924 kb
Host smart-5ede26de-99d9-4131-887b-3a9e0c265f5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155886 -assert nopostproc
+UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.155886
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3378833109
Short name T379
Test name
Test status
Simulation time 34112566250 ps
CPU time 12.7 seconds
Started Aug 11 04:28:26 PM PDT 24
Finished Aug 11 04:28:39 PM PDT 24
Peak memory 199740 kb
Host smart-327815fa-8222-4215-809e-a96c8c54cdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378833109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3378833109
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.1231332982
Short name T185
Test name
Test status
Simulation time 253904358446 ps
CPU time 337.28 seconds
Started Aug 11 04:28:14 PM PDT 24
Finished Aug 11 04:33:51 PM PDT 24
Peak memory 224764 kb
Host smart-ccd3aee4-1615-4aba-b27a-b4beed0e2b72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231332982 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.1231332982
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1380096576
Short name T635
Test name
Test status
Simulation time 121944941038 ps
CPU time 103.42 seconds
Started Aug 11 04:28:04 PM PDT 24
Finished Aug 11 04:29:48 PM PDT 24
Peak memory 199792 kb
Host smart-0f089237-bb8e-4b3b-9545-c2a58ff64f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380096576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1380096576
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3505784784
Short name T722
Test name
Test status
Simulation time 207122949119 ps
CPU time 1310.55 seconds
Started Aug 11 04:28:41 PM PDT 24
Finished Aug 11 04:50:32 PM PDT 24
Peak memory 225724 kb
Host smart-0a8da081-5813-4b3f-897b-6011859d057d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505784784 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3505784784
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3013583776
Short name T786
Test name
Test status
Simulation time 194480331727 ps
CPU time 17.86 seconds
Started Aug 11 04:28:26 PM PDT 24
Finished Aug 11 04:28:44 PM PDT 24
Peak memory 199652 kb
Host smart-51e52909-4e7a-4fd3-991a-c455aaa42362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013583776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3013583776
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1609738979
Short name T263
Test name
Test status
Simulation time 125778656403 ps
CPU time 401.88 seconds
Started Aug 11 04:28:09 PM PDT 24
Finished Aug 11 04:34:51 PM PDT 24
Peak memory 210328 kb
Host smart-252a3e64-6c6b-44d7-a723-bfb887916781
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609738979 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1609738979
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3745571211
Short name T1120
Test name
Test status
Simulation time 173464892706 ps
CPU time 81.53 seconds
Started Aug 11 04:28:34 PM PDT 24
Finished Aug 11 04:29:56 PM PDT 24
Peak memory 199724 kb
Host smart-60661bd5-8791-4658-8651-a064162ecc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745571211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3745571211
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.1225740850
Short name T112
Test name
Test status
Simulation time 85704454063 ps
CPU time 937.66 seconds
Started Aug 11 04:28:08 PM PDT 24
Finished Aug 11 04:43:46 PM PDT 24
Peak memory 216208 kb
Host smart-7ea285eb-7833-4376-9ce2-e85fd4992340
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225740850 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.1225740850
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.2020197360
Short name T1049
Test name
Test status
Simulation time 102360260201 ps
CPU time 34.62 seconds
Started Aug 11 04:28:26 PM PDT 24
Finished Aug 11 04:29:00 PM PDT 24
Peak memory 199560 kb
Host smart-03f38b6f-e924-47b9-9c7a-6358c31a1cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020197360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2020197360
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.1204315434
Short name T521
Test name
Test status
Simulation time 79666595355 ps
CPU time 858.7 seconds
Started Aug 11 04:28:07 PM PDT 24
Finished Aug 11 04:42:26 PM PDT 24
Peak memory 216340 kb
Host smart-b9236fab-6f84-4e5a-b409-38af07d1eb40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204315434 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.1204315434
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.1300338472
Short name T801
Test name
Test status
Simulation time 13035234739 ps
CPU time 20.81 seconds
Started Aug 11 04:28:37 PM PDT 24
Finished Aug 11 04:28:58 PM PDT 24
Peak memory 199724 kb
Host smart-7e82df2d-a077-4085-83b0-e808a4652d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300338472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1300338472
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1066192511
Short name T243
Test name
Test status
Simulation time 278493199305 ps
CPU time 1156.79 seconds
Started Aug 11 04:28:12 PM PDT 24
Finished Aug 11 04:47:30 PM PDT 24
Peak memory 216244 kb
Host smart-2514715b-3a60-4c58-a205-38b6bbb135a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066192511 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1066192511
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.574042331
Short name T281
Test name
Test status
Simulation time 123248187045 ps
CPU time 75 seconds
Started Aug 11 04:28:10 PM PDT 24
Finished Aug 11 04:29:25 PM PDT 24
Peak memory 200112 kb
Host smart-e74ff430-6351-4ac6-8284-0c76914fc41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574042331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.574042331
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.2566836375
Short name T339
Test name
Test status
Simulation time 342652756064 ps
CPU time 816.54 seconds
Started Aug 11 04:28:12 PM PDT 24
Finished Aug 11 04:41:49 PM PDT 24
Peak memory 224632 kb
Host smart-fee8b639-e4f5-4b65-a902-7a407fedd5d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566836375 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.2566836375
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.763539256
Short name T504
Test name
Test status
Simulation time 112656705685 ps
CPU time 171 seconds
Started Aug 11 04:28:09 PM PDT 24
Finished Aug 11 04:31:00 PM PDT 24
Peak memory 199768 kb
Host smart-13953864-90b5-4ea5-b355-f146696022ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763539256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.763539256
Directory /workspace/99.uart_fifo_reset/latest
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