Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	80912	1			T1	9		T2	21		T3	3033
all_values[1]	80912	1			T1	9		T2	21		T3	3033
all_values[2]	80912	1			T1	9		T2	21		T3	3033
all_values[3]	80912	1			T1	9		T2	21		T3	3033
all_values[4]	80912	1			T1	9		T2	21		T3	3033
all_values[5]	80912	1			T1	9		T2	21		T3	3033
all_values[6]	80912	1			T1	9		T2	21		T3	3033
all_values[7]	80912	1			T1	9		T2	21		T3	3033
all_values[8]	80912	1			T1	9		T2	21		T3	3033

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

365227

1

T1

41

T2

84

T3

14302

auto[1]

362981

1

T1

40

T2

105

T3

12995

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

661898

1

T1

64

T2

145

T3

26036

auto[1]

66310

1

T1

17

T2

44

T3

1261

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	22819	1			T3	1153		T6	7		T12	63
all_values[0]	auto[0]	auto[1]	17275	1			T1	5		T2	4		T3	529
all_values[0]	auto[1]	auto[0]	25771	1			T3	1115		T6	18		T12	8
all_values[0]	auto[1]	auto[1]	15047	1			T1	4		T2	17		T3	236
all_values[1]	auto[0]	auto[0]	39290	1			T1	3		T2	17		T3	1861
all_values[1]	auto[0]	auto[1]	1326	1			T6	8		T9	14		T40	4
all_values[1]	auto[1]	auto[0]	38976	1			T1	6		T2	4		T3	1172
all_values[1]	auto[1]	auto[1]	1320	1			T6	5		T10	9		T103	2
all_values[2]	auto[0]	auto[0]	35234	1			T1	2		T2	20		T3	1893
all_values[2]	auto[0]	auto[1]	2220	1			T1	1		T2	1		T3	10
all_values[2]	auto[1]	auto[0]	41458	1			T1	5		T3	1130		T6	1
all_values[2]	auto[1]	auto[1]	2000	1			T1	1		T6	1		T10	1
all_values[3]	auto[0]	auto[0]	43633	1			T1	7		T2	17		T3	1543
all_values[3]	auto[0]	auto[1]	269	1			T9	1		T13	1		T39	1
all_values[3]	auto[1]	auto[0]	36763	1			T1	2		T2	3		T3	1490
all_values[3]	auto[1]	auto[1]	247	1			T2	1		T67	1		T23	2
all_values[4]	auto[0]	auto[0]	40133	1			T1	7		T2	4		T3	1856
all_values[4]	auto[0]	auto[1]	311	1			T15	11		T16	2		T17	10
all_values[4]	auto[1]	auto[0]	40135	1			T1	2		T2	17		T3	1177
all_values[4]	auto[1]	auto[1]	333	1			T9	2		T15	15		T16	1
all_values[5]	auto[0]	auto[0]	41176	1			T1	3		T3	1185		T4	2
all_values[5]	auto[0]	auto[1]	139	1			T16	1		T34	3		T68	1
all_values[5]	auto[1]	auto[0]	39484	1			T1	6		T2	21		T3	1848
all_values[5]	auto[1]	auto[1]	113	1			T16	2		T34	1		T69	1
all_values[6]	auto[0]	auto[0]	40126	1			T1	3		T3	1028		T4	2
all_values[6]	auto[0]	auto[1]	131	1			T16	1		T32	1		T68	1
all_values[6]	auto[1]	auto[0]	40515	1			T1	6		T2	21		T3	2005
all_values[6]	auto[1]	auto[1]	140	1			T16	1		T32	1		T34	1
all_values[7]	auto[0]	auto[0]	40456	1			T1	7		T2	21		T3	1055
all_values[7]	auto[0]	auto[1]	254	1			T9	1		T15	2		T16	2
all_values[7]	auto[1]	auto[0]	39991	1			T1	2		T3	1978		T6	22
all_values[7]	auto[1]	auto[1]	211	1			T13	3		T21	4		T71	5
all_values[8]	auto[0]	auto[0]	29131	1			T3	2157		T9	7		T12	27
all_values[8]	auto[0]	auto[1]	11304	1			T1	3		T3	32		T4	2
all_values[8]	auto[1]	auto[0]	26807	1			T1	3		T3	390		T6	27
all_values[8]	auto[1]	auto[1]	13670	1			T1	3		T2	21		T3	454