Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2588

1

T1

6

T2

1

T3

1

auto[UartRx]

2588

1

T1

6

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4535	1			T1	9		T2	2		T3	2
values[1]	46	1			T20	1		T32	2		T33	2
values[2]	47	1			T20	1		T28	1		T32	1
values[3]	58	1			T20	1		T28	2		T30	1
values[4]	47	1			T30	1		T33	1		T34	1
values[5]	61	1			T32	1		T33	2		T34	1
values[6]	58	1			T22	1		T28	1		T29	3
values[7]	56	1			T20	2		T29	2		T30	1
values[8]	76	1			T1	1		T22	1		T28	3
values[9]	61	1			T22	2		T20	3		T28	1
values[10]	90	1			T1	2		T22	2		T20	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2365	1			T1	4		T2	1		T3	1
auto[UartTx]	values[1]	19	1			T32	1		T33	1		T318	1
auto[UartTx]	values[2]	13	1			T69	1		T319	1		T110	1
auto[UartTx]	values[3]	19	1			T28	1		T113	2		T96	1
auto[UartTx]	values[4]	17	1			T30	1		T292	1		T92	1
auto[UartTx]	values[5]	24	1			T32	1		T33	1		T91	1
auto[UartTx]	values[6]	23	1			T28	1		T94	1		T96	1
auto[UartTx]	values[7]	25	1			T20	2		T29	2		T32	2
auto[UartTx]	values[8]	23	1			T1	1		T28	1		T31	1
auto[UartTx]	values[9]	22	1			T22	1		T20	1		T33	1
auto[UartTx]	values[10]	24	1			T1	1		T22	1		T20	1
auto[UartRx]	values[0]	2170	1			T1	5		T2	1		T3	1
auto[UartRx]	values[1]	27	1			T20	1		T32	1		T33	1
auto[UartRx]	values[2]	34	1			T20	1		T28	1		T32	1
auto[UartRx]	values[3]	39	1			T20	1		T28	1		T30	1
auto[UartRx]	values[4]	30	1			T33	1		T34	1		T91	1
auto[UartRx]	values[5]	37	1			T33	1		T34	1		T91	1
auto[UartRx]	values[6]	35	1			T22	1		T29	3		T31	1
auto[UartRx]	values[7]	31	1			T30	1		T31	1		T33	1
auto[UartRx]	values[8]	53	1			T22	1		T28	2		T31	2
auto[UartRx]	values[9]	39	1			T22	1		T20	2		T28	1
auto[UartRx]	values[10]	66	1			T1	1		T22	1		T29	1