Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1901	1			T1	4		T2	1		T4	1
auto[BaudRate115200]	1525	1			T1	4		T2	2		T4	1
auto[BaudRate230400]	1528	1			T1	5		T3	3		T6	1
auto[BaudRate128Kbps]	1547	1			T1	2		T2	1		T3	3
auto[BaudRate256Kbps]	1672	1			T1	6		T2	2		T3	1
auto[BaudRate1Mbps]	1548	1			T3	2		T6	4		T10	2
auto[BaudRate1p5Mbps]	1010	1			T3	1		T10	1		T65	1

---

Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1074	1			T65	5		T19	2		T70	12
freqs[25]	971	1			T36	8		T67	7		T28	27
freqs[48]	514	1			T12	6		T21	41		T71	3
freqs[50]	400	1			T6	10		T37	8		T22	9
freqs[100]	988	1			T3	10		T10	8		T14	4

---

Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	162	1			T65	1		T70	12		T123	1
auto[BaudRate9600]	freqs[25]	177	1			T36	1		T67	1		T28	2
auto[BaudRate9600]	freqs[48]	71	1			T12	2		T21	7		T120	1
auto[BaudRate9600]	freqs[50]	77	1			T149	1		T294	1		T32	2
auto[BaudRate9600]	freqs[100]	155	1			T14	4		T20	2		T126	1
auto[BaudRate115200]	freqs[24]	164	1			T65	1		T17	1		T132	1
auto[BaudRate115200]	freqs[25]	130	1			T36	1		T67	1		T28	4
auto[BaudRate115200]	freqs[48]	74	1			T12	2		T21	4		T71	2
auto[BaudRate115200]	freqs[50]	61	1			T6	1		T37	1		T22	3
auto[BaudRate115200]	freqs[100]	134	1			T20	3		T126	1		T115	3
auto[BaudRate230400]	freqs[24]	170	1			T65	1		T19	1		T17	2
auto[BaudRate230400]	freqs[25]	173	1			T36	1		T28	2		T182	1
auto[BaudRate230400]	freqs[48]	73	1			T12	1		T21	3		T128	2
auto[BaudRate230400]	freqs[50]	50	1			T6	1		T37	2		T22	4
auto[BaudRate230400]	freqs[100]	110	1			T3	3		T10	2		T20	3
auto[BaudRate128Kbps]	freqs[24]	150	1			T132	2		T123	1		T246	2
auto[BaudRate128Kbps]	freqs[25]	144	1			T67	1		T28	5		T182	2
auto[BaudRate128Kbps]	freqs[48]	58	1			T12	1		T21	5		T71	1
auto[BaudRate128Kbps]	freqs[50]	54	1			T6	2		T37	2		T22	2
auto[BaudRate128Kbps]	freqs[100]	129	1			T3	3		T10	2		T20	2
auto[BaudRate256Kbps]	freqs[24]	155	1			T65	1		T19	1		T132	1
auto[BaudRate256Kbps]	freqs[25]	152	1			T36	4		T67	4		T28	8
auto[BaudRate256Kbps]	freqs[48]	79	1			T21	4		T128	2		T120	1
auto[BaudRate256Kbps]	freqs[50]	60	1			T6	2		T149	1		T32	1
auto[BaudRate256Kbps]	freqs[100]	144	1			T3	1		T10	1		T20	3
auto[BaudRate1Mbps]	freqs[24]	183	1			T132	1		T123	1		T152	1
auto[BaudRate1Mbps]	freqs[25]	128	1			T36	1		T28	5		T182	1
auto[BaudRate1Mbps]	freqs[48]	86	1			T21	9		T120	3		T125	1
auto[BaudRate1Mbps]	freqs[50]	54	1			T6	4		T37	1		T149	3
auto[BaudRate1Mbps]	freqs[100]	178	1			T3	2		T10	2		T20	5
auto[BaudRate1p5Mbps]	freqs[25]	67	1			T28	1		T252	1		T212	2
auto[BaudRate1p5Mbps]	freqs[48]	73	1			T21	9		T128	1		T125	1
auto[BaudRate1p5Mbps]	freqs[50]	44	1			T37	2		T149	1		T32	4
auto[BaudRate1p5Mbps]	freqs[100]	138	1			T3	1		T10	1		T20	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded