Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.39	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	15	115	88.46

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	15	115	88.46	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	24382372	1			T1	15		T2	15		T3	140119
all_levels[1]	168803	1			T1	2		T3	218		T6	2
all_levels[2]	1844	1			T6	1		T10	1		T12	10
all_levels[3]	884	1			T1	1		T6	1		T10	2
all_levels[4]	599	1			T10	2		T12	4		T36	1
all_levels[5]	412	1			T6	1		T10	4		T103	2
all_levels[6]	340	1			T1	1		T6	1		T10	2
all_levels[7]	248	1			T10	1		T36	2		T40	1
all_levels[8]	217	1			T10	2		T66	1		T36	1
all_levels[9]	167	1			T6	2		T10	5		T40	1
all_levels[10]	166	1			T6	1		T10	4		T36	1
all_levels[11]	162	1			T10	3		T65	1		T66	1
all_levels[12]	125	1			T10	3		T65	1		T114	1
all_levels[13]	113	1			T6	1		T115	2		T114	1
all_levels[14]	107	1			T10	1		T36	1		T116	1
all_levels[15]	120	1			T10	1		T117	1		T115	3
all_levels[16]	87	1			T115	1		T100	2		T101	4
all_levels[17]	99	1			T40	1		T118	1		T16	1
all_levels[18]	63	1			T10	1		T40	1		T119	1
all_levels[19]	55	1			T23	1		T120	1		T121	1
all_levels[20]	69	1			T10	1		T115	1		T114	1
all_levels[21]	53	1			T6	2		T117	1		T115	1
all_levels[22]	49	1			T11	1		T36	1		T40	1
all_levels[23]	41	1			T122	1		T123	1		T124	1
all_levels[24]	54	1			T39	1		T125	1		T121	1
all_levels[25]	46	1			T13	1		T82	1		T83	1
all_levels[26]	36	1			T40	1		T126	1		T127	1
all_levels[27]	35	1			T39	1		T23	1		T128	1
all_levels[28]	40	1			T10	1		T66	2		T103	3
all_levels[29]	37	1			T129	1		T130	2		T131	1
all_levels[30]	30	1			T11	1		T66	1		T132	2
all_levels[31]	32	1			T133	1		T132	1		T102	2
all_levels[32]	23	1			T100	1		T134	1		T135	1
all_levels[33]	22	1			T117	1		T136	1		T124	2
all_levels[34]	28	1			T6	1		T122	1		T137	1
all_levels[35]	17	1			T6	1		T138	1		T139	2
all_levels[36]	20	1			T128	1		T121	1		T138	1
all_levels[37]	17	1			T40	1		T129	1		T86	1
all_levels[38]	15	1			T82	1		T131	1		T140	1
all_levels[39]	23	1			T23	1		T141	1		T82	1
all_levels[40]	19	1			T40	1		T117	1		T115	1
all_levels[41]	8	1			T142	1		T143	1		T144	1
all_levels[42]	17	1			T125	1		T138	1		T141	1
all_levels[43]	11	1			T134	2		T145	2		T146	2
all_levels[44]	16	1			T23	1		T115	1		T128	1
all_levels[45]	8	1			T129	1		T123	1		T147	1
all_levels[46]	13	1			T10	1		T40	1		T130	1
all_levels[47]	13	1			T123	1		T146	1		T148	1
all_levels[48]	11	1			T6	1		T40	2		T128	1
all_levels[49]	6	1			T149	1		T120	1		T84	1
all_levels[50]	12	1			T6	2		T150	3		T151	1
all_levels[51]	13	1			T6	1		T40	1		T138	1
all_levels[52]	8	1			T115	1		T123	1		T152	1
all_levels[53]	16	1			T153	1		T154	1		T155	1
all_levels[54]	10	1			T156	1		T157	1		T158	1
all_levels[55]	11	1			T149	1		T131	1		T159	1
all_levels[56]	10	1			T120	1		T130	1		T160	1
all_levels[57]	2	1			T6	1		T161	1		-	-
all_levels[58]	8	1			T137	1		T138	1		T162	1
all_levels[59]	4	1			T90	1		T163	1		T164	1
all_levels[60]	8	1			T102	1		T165	2		T166	1
all_levels[61]	6	1			T13	1		T167	1		T157	1
all_levels[62]	2	1			T168	1		T164	1		-	-
all_levels[63]	10	1			T6	2		T169	1		T170	2
all_levels[64]	90	1			T2	1		T13	1		T39	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24553921

1

T1

18

T2

12

T3

140141

auto[1]

4081

1

T1

1

T2

4

T5

1

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	15	115	88.46	15

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[22]]	[auto[1]]	0	1	1
[all_levels[37]]	[auto[1]]	0	1	1
[all_levels[40] , all_levels[41]]	[auto[1]]	--	--	2
[all_levels[45]]	[auto[1]]	0	1	1
[all_levels[47] , all_levels[48] , all_levels[49]]	[auto[1]]	--	--	3
[all_levels[51]]	[auto[1]]	0	1	1
[all_levels[55]]	[auto[1]]	0	1	1
[all_levels[57] , all_levels[58] , all_levels[59]]	[auto[1]]	--	--	3
[all_levels[61] , all_levels[62]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	24378703	1			T1	14		T2	11		T3	140119
all_levels[0]	auto[1]	3669	1			T1	1		T2	4		T5	1
all_levels[1]	auto[0]	168705	1			T1	2		T3	218		T6	1
all_levels[1]	auto[1]	98	1			T6	1		T12	3		T103	1
all_levels[2]	auto[0]	1823	1			T6	1		T10	1		T12	10
all_levels[2]	auto[1]	21	1			T104	1		T171	1		T172	1
all_levels[3]	auto[0]	873	1			T1	1		T6	1		T10	2
all_levels[3]	auto[1]	11	1			T134	1		T173	1		T174	1
all_levels[4]	auto[0]	579	1			T10	2		T12	4		T36	1
all_levels[4]	auto[1]	20	1			T104	1		T100	2		T136	4
all_levels[5]	auto[0]	401	1			T6	1		T10	4		T103	2
all_levels[5]	auto[1]	11	1			T104	2		T119	2		T146	1
all_levels[6]	auto[0]	327	1			T1	1		T6	1		T10	2
all_levels[6]	auto[1]	13	1			T133	1		T86	1		T147	1
all_levels[7]	auto[0]	235	1			T10	1		T36	2		T40	1
all_levels[7]	auto[1]	13	1			T174	1		T175	1		T176	1
all_levels[8]	auto[0]	208	1			T10	2		T66	1		T36	1
all_levels[8]	auto[1]	9	1			T177	1		T104	1		T157	1
all_levels[9]	auto[0]	164	1			T6	2		T10	5		T40	1
all_levels[9]	auto[1]	3	1			T84	1		T178	1		T179	1
all_levels[10]	auto[0]	154	1			T6	1		T10	4		T36	1
all_levels[10]	auto[1]	12	1			T137	3		T180	1		T181	1
all_levels[11]	auto[0]	152	1			T10	3		T65	1		T66	1
all_levels[11]	auto[1]	10	1			T182	1		T183	1		T184	2
all_levels[12]	auto[0]	111	1			T10	3		T65	1		T114	1
all_levels[12]	auto[1]	14	1			T156	2		T185	1		T186	2
all_levels[13]	auto[0]	100	1			T6	1		T115	1		T114	1
all_levels[13]	auto[1]	13	1			T115	1		T125	1		T147	1
all_levels[14]	auto[0]	96	1			T10	1		T36	1		T116	1
all_levels[14]	auto[1]	11	1			T128	1		T187	1		T188	2
all_levels[15]	auto[0]	104	1			T10	1		T117	1		T115	2
all_levels[15]	auto[1]	16	1			T115	1		T189	3		T137	1
all_levels[16]	auto[0]	81	1			T115	1		T100	1		T101	4
all_levels[16]	auto[1]	6	1			T100	1		T190	1		T191	1
all_levels[17]	auto[0]	91	1			T40	1		T118	1		T16	1
all_levels[17]	auto[1]	8	1			T142	4		T192	1		T193	1
all_levels[18]	auto[0]	57	1			T10	1		T40	1		T119	1
all_levels[18]	auto[1]	6	1			T194	1		T195	1		T185	2
all_levels[19]	auto[0]	50	1			T23	1		T120	1		T121	1
all_levels[19]	auto[1]	5	1			T196	1		T197	1		T198	1
all_levels[20]	auto[0]	64	1			T10	1		T115	1		T114	1
all_levels[20]	auto[1]	5	1			T199	1		T200	2		T193	1
all_levels[21]	auto[0]	51	1			T6	2		T117	1		T115	1
all_levels[21]	auto[1]	2	1			T201	1		T202	1		-	-
all_levels[22]	auto[0]	49	1			T11	1		T36	1		T40	1
all_levels[23]	auto[0]	40	1			T122	1		T123	1		T124	1
all_levels[23]	auto[1]	1	1			T203	1		-	-		-	-
all_levels[24]	auto[0]	46	1			T39	1		T125	1		T121	1
all_levels[24]	auto[1]	8	1			T204	1		T198	1		T205	1
all_levels[25]	auto[0]	42	1			T13	1		T82	1		T83	1
all_levels[25]	auto[1]	4	1			T187	1		T172	2		T206	1
all_levels[26]	auto[0]	32	1			T40	1		T126	1		T127	1
all_levels[26]	auto[1]	4	1			T207	1		T208	1		T179	2
all_levels[27]	auto[0]	31	1			T39	1		T23	1		T128	1
all_levels[27]	auto[1]	4	1			T121	1		T209	2		T210	1
all_levels[28]	auto[0]	34	1			T10	1		T66	1		T103	1
all_levels[28]	auto[1]	6	1			T66	1		T103	2		T89	1
all_levels[29]	auto[0]	32	1			T129	1		T130	2		T131	1
all_levels[29]	auto[1]	5	1			T173	1		T211	1		T192	2
all_levels[30]	auto[0]	26	1			T11	1		T66	1		T132	2
all_levels[30]	auto[1]	4	1			T212	2		T213	2		-	-
all_levels[31]	auto[0]	21	1			T133	1		T132	1		T102	1
all_levels[31]	auto[1]	11	1			T102	1		T214	1		T215	2
all_levels[32]	auto[0]	21	1			T100	1		T134	1		T135	1
all_levels[32]	auto[1]	2	1			T216	2		-	-		-	-
all_levels[33]	auto[0]	18	1			T117	1		T136	1		T124	2
all_levels[33]	auto[1]	4	1			T217	2		T218	2		-	-
all_levels[34]	auto[0]	24	1			T6	1		T122	1		T137	1
all_levels[34]	auto[1]	4	1			T136	2		T84	1		T219	1
all_levels[35]	auto[0]	16	1			T6	1		T138	1		T139	1
all_levels[35]	auto[1]	1	1			T139	1		-	-		-	-
all_levels[36]	auto[0]	15	1			T128	1		T121	1		T138	1
all_levels[36]	auto[1]	5	1			T135	4		T220	1		-	-
all_levels[37]	auto[0]	17	1			T40	1		T129	1		T86	1
all_levels[38]	auto[0]	12	1			T82	1		T131	1		T140	1
all_levels[38]	auto[1]	3	1			T221	1		T222	2		-	-
all_levels[39]	auto[0]	18	1			T23	1		T141	1		T82	1
all_levels[39]	auto[1]	5	1			T220	2		T223	1		T193	1
all_levels[40]	auto[0]	19	1			T40	1		T117	1		T115	1
all_levels[41]	auto[0]	8	1			T142	1		T143	1		T144	1
all_levels[42]	auto[0]	16	1			T125	1		T138	1		T141	1
all_levels[42]	auto[1]	1	1			T224	1		-	-		-	-
all_levels[43]	auto[0]	10	1			T134	2		T145	1		T146	2
all_levels[43]	auto[1]	1	1			T145	1		-	-		-	-
all_levels[44]	auto[0]	15	1			T23	1		T115	1		T128	1
all_levels[44]	auto[1]	1	1			T225	1		-	-		-	-
all_levels[45]	auto[0]	8	1			T129	1		T123	1		T147	1
all_levels[46]	auto[0]	12	1			T10	1		T40	1		T130	1
all_levels[46]	auto[1]	1	1			T226	1		-	-		-	-
all_levels[47]	auto[0]	13	1			T123	1		T146	1		T148	1
all_levels[48]	auto[0]	11	1			T6	1		T40	2		T128	1
all_levels[49]	auto[0]	6	1			T149	1		T120	1		T84	1
all_levels[50]	auto[0]	8	1			T6	1		T150	2		T151	1
all_levels[50]	auto[1]	4	1			T6	1		T150	1		T227	2
all_levels[51]	auto[0]	13	1			T6	1		T40	1		T138	1
all_levels[52]	auto[0]	7	1			T115	1		T123	1		T152	1
all_levels[52]	auto[1]	1	1			T228	1		-	-		-	-
all_levels[53]	auto[0]	13	1			T153	1		T154	1		T155	1
all_levels[53]	auto[1]	3	1			T229	1		T202	1		T230	1
all_levels[54]	auto[0]	9	1			T156	1		T157	1		T158	1
all_levels[54]	auto[1]	1	1			T231	1		-	-		-	-
all_levels[55]	auto[0]	11	1			T149	1		T131	1		T159	1
all_levels[56]	auto[0]	8	1			T120	1		T130	1		T160	1
all_levels[56]	auto[1]	2	1			T232	2		-	-		-	-
all_levels[57]	auto[0]	2	1			T6	1		T161	1		-	-
all_levels[58]	auto[0]	8	1			T137	1		T138	1		T162	1
all_levels[59]	auto[0]	4	1			T90	1		T163	1		T164	1
all_levels[60]	auto[0]	6	1			T102	1		T165	1		T166	1
all_levels[60]	auto[1]	2	1			T165	1		T233	1		-	-
all_levels[61]	auto[0]	6	1			T13	1		T167	1		T157	1
all_levels[62]	auto[0]	2	1			T168	1		T164	1		-	-
all_levels[63]	auto[0]	5	1			T6	1		T169	1		T170	1
all_levels[63]	auto[1]	5	1			T6	1		T170	1		T201	2
all_levels[64]	auto[0]	78	1			T2	1		T13	1		T39	1
all_levels[64]	auto[1]	12	1			T137	1		T234	1		T170	2