Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
87.50 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 1 7 87.50


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 1 7 87.50 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 1 7 87.50


User Defined Bins for cp_watermark_lvl

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
all_levels[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 945 1 T99 4 T100 21 T16 6
all_levels[1] 577 1 T40 4 T101 2 T102 7
all_levels[2] 353 1 T6 8 T103 2 T104 9
all_levels[3] 297 1 T6 5 T15 13 T21 23
all_levels[4] 286 1 T9 14 T10 9 T40 4
all_levels[5] 132 1 T17 16 T95 2 T105 4
all_levels[6] 50 1 T15 6 T71 4 T106 7

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