Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	80912	1			T1	9		T2	21		T3	3033
all_pins[1]	80912	1			T1	9		T2	21		T3	3033
all_pins[2]	80912	1			T1	9		T2	21		T3	3033
all_pins[3]	80912	1			T1	9		T2	21		T3	3033
all_pins[4]	80912	1			T1	9		T2	21		T3	3033
all_pins[5]	80912	1			T1	9		T2	21		T3	3033
all_pins[6]	80912	1			T1	9		T2	21		T3	3033
all_pins[7]	80912	1			T1	9		T2	21		T3	3033
all_pins[8]	80912	1			T1	9		T2	21		T3	3033

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	694335	1			T1	72		T2	147		T3	26607
values[0x1]	33873	1			T1	9		T2	42		T3	690
transitions[0x0=>0x1]	26802	1			T1	9		T2	24		T3	598
transitions[0x1=>0x0]	26622	1			T1	9		T2	25		T3	598

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	65816	1			T1	5		T2	4		T3	2797
all_pins[0]	values[0x1]	15096	1			T1	4		T2	17		T3	236
all_pins[0]	transitions[0x0=>0x1]	14722	1			T1	4		T2	17		T3	236
all_pins[0]	transitions[0x1=>0x0]	941	1			T6	5		T10	9		T103	2
all_pins[1]	values[0x0]	79597	1			T1	9		T2	21		T3	3033
all_pins[1]	values[0x1]	1315	1			T6	5		T10	9		T103	2
all_pins[1]	transitions[0x0=>0x1]	1218	1			T6	5		T10	9		T103	2
all_pins[1]	transitions[0x1=>0x0]	1951	1			T1	1		T6	1		T9	1
all_pins[2]	values[0x0]	78864	1			T1	8		T2	21		T3	3033
all_pins[2]	values[0x1]	2048	1			T1	1		T6	1		T9	1
all_pins[2]	transitions[0x0=>0x1]	1984	1			T1	1		T6	1		T9	1
all_pins[2]	transitions[0x1=>0x0]	183	1			T2	1		T67	1		T15	2
all_pins[3]	values[0x0]	80665	1			T1	9		T2	20		T3	3033
all_pins[3]	values[0x1]	247	1			T2	1		T67	1		T23	2
all_pins[3]	transitions[0x0=>0x1]	210	1			T2	1		T67	1		T23	2
all_pins[3]	transitions[0x1=>0x0]	296	1			T9	2		T15	15		T21	4
all_pins[4]	values[0x0]	80579	1			T1	9		T2	21		T3	3033
all_pins[4]	values[0x1]	333	1			T9	2		T15	15		T16	1
all_pins[4]	transitions[0x0=>0x1]	283	1			T9	2		T15	12		T21	3
all_pins[4]	transitions[0x1=>0x0]	96	1			T16	1		T34	1		T95	1
all_pins[5]	values[0x0]	80766	1			T1	9		T2	21		T3	3033
all_pins[5]	values[0x1]	146	1			T15	3		T16	2		T21	1
all_pins[5]	transitions[0x0=>0x1]	118	1			T15	3		T16	2		T21	1
all_pins[5]	transitions[0x1=>0x0]	720	1			T1	1		T2	3		T6	2
all_pins[6]	values[0x0]	80164	1			T1	8		T2	18		T3	3033
all_pins[6]	values[0x1]	748	1			T1	1		T2	3		T6	2
all_pins[6]	transitions[0x0=>0x1]	709	1			T1	1		T2	3		T6	2
all_pins[6]	transitions[0x1=>0x0]	172	1			T13	3		T21	4		T71	5
all_pins[7]	values[0x0]	80701	1			T1	9		T2	21		T3	3033
all_pins[7]	values[0x1]	211	1			T13	3		T21	4		T71	5
all_pins[7]	transitions[0x0=>0x1]	120	1			T13	3		T101	1		T238	1
all_pins[7]	transitions[0x1=>0x0]	13638	1			T1	3		T2	21		T3	454
all_pins[8]	values[0x0]	67183	1			T1	6		T3	2579		T4	2
all_pins[8]	values[0x1]	13729	1			T1	3		T2	21		T3	454
all_pins[8]	transitions[0x0=>0x1]	7438	1			T1	3		T2	3		T3	362
all_pins[8]	transitions[0x1=>0x0]	8625	1			T1	4		T3	144		T9	25