Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	5063291	1			T1	10		T2	11		T3	263495
all_levels[1]	671881	1			T1	2		T2	6		T3	5025
all_levels[2]	409340	1			T1	1		T3	5027		T6	1
all_levels[3]	166191	1			T1	1		T3	5046		T35	36
all_levels[4]	227106	1			T1	1		T3	5014		T10	2
all_levels[5]	177768	1			T1	3		T3	5033		T6	1
all_levels[6]	167981	1			T3	5042		T10	2		T65	2
all_levels[7]	202360	1			T3	5039		T65	3		T35	35
all_levels[8]	515359	1			T3	325043		T65	2		T35	42
all_levels[9]	195480	1			T3	4491		T65	2		T35	46
all_levels[10]	438631	1			T3	4492		T65	2		T35	29
all_levels[11]	742097	1			T3	4500		T35	39		T36	1
all_levels[12]	188499	1			T3	4487		T10	3		T13	2
all_levels[13]	504372	1			T3	347223		T35	35		T37	85
all_levels[14]	209631	1			T3	4490		T6	2		T12	2
all_levels[15]	142708	1			T3	4497		T6	2		T12	3
all_levels[16]	225225	1			T3	4512		T6	1		T65	1
all_levels[17]	160435	1			T3	6601		T6	1		T65	4
all_levels[18]	144716	1			T3	6633		T65	1		T35	33
all_levels[19]	169561	1			T3	6614		T6	3		T11	4
all_levels[20]	187258	1			T3	6622		T35	35		T37	84
all_levels[21]	474028	1			T3	6633		T65	1		T35	33
all_levels[22]	182811	1			T3	6643		T65	1		T35	37
all_levels[23]	214955	1			T3	6575		T65	8		T35	29
all_levels[24]	376019	1			T3	6639		T13	5		T65	2
all_levels[25]	318215	1			T3	6611		T65	1		T35	42
all_levels[26]	184584	1			T3	6604		T10	8		T35	34
all_levels[27]	136045	1			T3	6647		T35	39		T36	6
all_levels[28]	152651	1			T3	6603		T6	16		T65	2
all_levels[29]	190216	1			T3	6633		T65	4		T35	31
all_levels[30]	133660	1			T3	6637		T65	2		T35	32
all_levels[31]	653556	1			T3	33019		T35	630		T37	84
all_levels[32]	10631112	1			T3	273242		T12	80		T65	4

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24553921

1

T1

18

T2

12

T3

140141

auto[1]

3821

1

T2

5

T3

1

T5

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	5061061	1			T1	10		T2	8		T3	263494
all_levels[0]	auto[1]	2230	1			T2	3		T3	1		T5	1
all_levels[1]	auto[0]	671648	1			T1	2		T2	4		T3	5025
all_levels[1]	auto[1]	233	1			T2	2		T6	2		T11	2
all_levels[2]	auto[0]	409312	1			T1	1		T3	5027		T6	1
all_levels[2]	auto[1]	28	1			T260	2		T287	1		T196	1
all_levels[3]	auto[0]	166070	1			T1	1		T3	5046		T35	36
all_levels[3]	auto[1]	121	1			T104	3		T15	12		T17	3
all_levels[4]	auto[0]	227068	1			T1	1		T3	5014		T10	2
all_levels[4]	auto[1]	38	1			T117	1		T100	2		T119	1
all_levels[5]	auto[0]	177742	1			T1	3		T3	5033		T6	1
all_levels[5]	auto[1]	26	1			T167	1		T204	1		T185	1
all_levels[6]	auto[0]	167953	1			T3	5042		T10	2		T65	2
all_levels[6]	auto[1]	28	1			T134	1		T147	1		T199	2
all_levels[7]	auto[0]	202299	1			T3	5039		T65	3		T35	35
all_levels[7]	auto[1]	61	1			T118	1		T283	1		T307	6
all_levels[8]	auto[0]	515331	1			T3	325043		T65	2		T35	42
all_levels[8]	auto[1]	28	1			T265	4		T173	1		T147	1
all_levels[9]	auto[0]	195463	1			T3	4491		T65	2		T35	46
all_levels[9]	auto[1]	17	1			T321	1		T154	1		T322	2
all_levels[10]	auto[0]	438606	1			T3	4492		T65	2		T35	29
all_levels[10]	auto[1]	25	1			T267	1		T262	1		T234	3
all_levels[11]	auto[0]	742066	1			T3	4500		T35	39		T36	1
all_levels[11]	auto[1]	31	1			T177	2		T182	2		T293	1
all_levels[12]	auto[0]	188460	1			T3	4487		T10	2		T13	2
all_levels[12]	auto[1]	39	1			T10	1		T23	1		T133	2
all_levels[13]	auto[0]	504356	1			T3	347223		T35	35		T37	85
all_levels[13]	auto[1]	16	1			T277	2		T234	1		T322	1
all_levels[14]	auto[0]	209611	1			T3	4490		T6	2		T12	1
all_levels[14]	auto[1]	20	1			T12	1		T149	1		T134	2
all_levels[15]	auto[0]	142590	1			T3	4497		T6	2		T12	3
all_levels[15]	auto[1]	118	1			T15	5		T271	3		T125	1
all_levels[16]	auto[0]	225215	1			T3	4512		T6	1		T65	1
all_levels[16]	auto[1]	10	1			T315	1		T122	1		T263	1
all_levels[17]	auto[0]	160416	1			T3	6601		T6	1		T65	4
all_levels[17]	auto[1]	19	1			T116	1		T256	1		T134	1
all_levels[18]	auto[0]	144707	1			T3	6633		T65	1		T35	33
all_levels[18]	auto[1]	9	1			T66	1		T104	1		T287	1
all_levels[19]	auto[0]	169539	1			T3	6614		T6	1		T11	2
all_levels[19]	auto[1]	22	1			T6	2		T11	2		T37	1
all_levels[20]	auto[0]	187236	1			T3	6622		T35	35		T37	84
all_levels[20]	auto[1]	22	1			T41	1		T115	3		T136	1
all_levels[21]	auto[0]	474007	1			T3	6633		T65	1		T35	33
all_levels[21]	auto[1]	21	1			T125	2		T249	1		T323	1
all_levels[22]	auto[0]	182789	1			T3	6643		T65	1		T35	37
all_levels[22]	auto[1]	22	1			T100	2		T124	1		T282	2
all_levels[23]	auto[0]	214934	1			T3	6575		T65	8		T35	29
all_levels[23]	auto[1]	21	1			T102	2		T106	1		T174	1
all_levels[24]	auto[0]	376002	1			T3	6639		T13	4		T65	2
all_levels[24]	auto[1]	17	1			T13	1		T260	1		T301	1
all_levels[25]	auto[0]	318198	1			T3	6611		T65	1		T35	42
all_levels[25]	auto[1]	17	1			T238	1		T324	1		T325	1
all_levels[26]	auto[0]	184564	1			T3	6604		T10	8		T35	34
all_levels[26]	auto[1]	20	1			T100	1		T251	1		T142	2
all_levels[27]	auto[0]	136034	1			T3	6647		T35	39		T36	6
all_levels[27]	auto[1]	11	1			T196	1		T324	1		T221	1
all_levels[28]	auto[0]	152630	1			T3	6603		T6	15		T65	2
all_levels[28]	auto[1]	21	1			T6	1		T256	1		T84	1
all_levels[29]	auto[0]	190200	1			T3	6633		T65	4		T35	31
all_levels[29]	auto[1]	16	1			T102	1		T89	1		T197	1
all_levels[30]	auto[0]	133645	1			T3	6637		T65	2		T35	32
all_levels[30]	auto[1]	15	1			T189	4		T139	2		T145	1
all_levels[31]	auto[0]	653546	1			T3	33019		T35	630		T37	84
all_levels[31]	auto[1]	10	1			T82	1		T89	2		T301	1
all_levels[32]	auto[0]	10630623	1			T3	273242		T12	78		T65	3
all_levels[32]	auto[1]	489	1			T12	2		T65	1		T38	1