Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	596	1			T16	7		T32	4		T34	4
all_values[1]	596	1			T16	7		T32	4		T34	4
all_values[2]	596	1			T16	7		T32	4		T34	4
all_values[3]	596	1			T16	7		T32	4		T34	4
all_values[4]	596	1			T16	7		T32	4		T34	4
all_values[5]	596	1			T16	7		T32	4		T34	4
all_values[6]	596	1			T16	7		T32	4		T34	4
all_values[7]	596	1			T16	7		T32	4		T34	4
all_values[8]	596	1			T16	7		T32	4		T34	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2948

1

T16

32

T32

24

T34

18

auto[1]

2416

1

T16

31

T32

12

T34

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1827

1

T16

17

T32

15

T34

14

auto[1]

3537

1

T16

46

T32

21

T34

22

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3206

1

T16

31

T32

23

T34

23

auto[1]

2158

1

T16

32

T32

13

T34

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	189	1			T16	3		T32	2		T34	1
all_values[0]	auto[0]	auto[1]	auto[1]	162	1			T16	1		T34	1		T68	1
all_values[0]	auto[1]	auto[0]	auto[1]	132	1			T16	1		T32	1		T34	1
all_values[0]	auto[1]	auto[1]	auto[1]	113	1			T16	2		T32	1		T34	1
all_values[1]	auto[0]	auto[0]	auto[0]	187	1			T32	2		T34	2		T68	3
all_values[1]	auto[0]	auto[1]	auto[0]	174	1			T16	1		T34	1		T68	1
all_values[1]	auto[1]	auto[0]	auto[1]	137	1			T16	4		T32	1		T68	3
all_values[1]	auto[1]	auto[1]	auto[1]	98	1			T16	2		T32	1		T34	1
all_values[2]	auto[0]	auto[0]	auto[0]	161	1			T34	2		T68	4		T95	4
all_values[2]	auto[0]	auto[0]	auto[1]	51	1			T16	2		T32	1		T69	2
all_values[2]	auto[0]	auto[1]	auto[0]	94	1			T16	1		T32	2		T107	2
all_values[2]	auto[0]	auto[1]	auto[1]	69	1			T34	1		T69	1		T108	2
all_values[2]	auto[1]	auto[0]	auto[1]	127	1			T16	2		T68	2		T69	2
all_values[2]	auto[1]	auto[1]	auto[1]	94	1			T16	2		T32	1		T34	1
all_values[3]	auto[0]	auto[0]	auto[0]	120	1			T32	1		T34	1		T68	1
all_values[3]	auto[0]	auto[0]	auto[1]	58	1			T16	1		T32	1		T108	2
all_values[3]	auto[0]	auto[1]	auto[0]	114	1			T16	3		T68	6		T69	1
all_values[3]	auto[0]	auto[1]	auto[1]	70	1			T34	2		T69	1		T108	1
all_values[3]	auto[1]	auto[0]	auto[1]	121	1			T16	2		T32	2		T69	2
all_values[3]	auto[1]	auto[1]	auto[1]	113	1			T16	1		T34	1		T69	3
all_values[4]	auto[0]	auto[0]	auto[0]	131	1			T16	1		T32	2		T34	1
all_values[4]	auto[0]	auto[0]	auto[1]	60	1			T16	1		T68	1		T108	2
all_values[4]	auto[0]	auto[1]	auto[0]	119	1			T16	1		T32	2		T34	3
all_values[4]	auto[0]	auto[1]	auto[1]	48	1			T109	1		T110	1		T111	3
all_values[4]	auto[1]	auto[0]	auto[1]	135	1			T16	2		T68	1		T69	1
all_values[4]	auto[1]	auto[1]	auto[1]	103	1			T16	2		T68	1		T69	1
all_values[5]	auto[0]	auto[0]	auto[0]	141	1			T68	3		T69	1		T108	3
all_values[5]	auto[0]	auto[0]	auto[1]	67	1			T34	2		T69	3		T112	1
all_values[5]	auto[0]	auto[1]	auto[0]	115	1			T16	2		T32	4		T68	1
all_values[5]	auto[0]	auto[1]	auto[1]	58	1			T16	3		T95	2		T113	3
all_values[5]	auto[1]	auto[0]	auto[1]	128	1			T16	2		T34	2		T68	2
all_values[5]	auto[1]	auto[1]	auto[1]	87	1			T68	1		T108	1		T112	1
all_values[6]	auto[0]	auto[0]	auto[0]	142	1			T16	1		T32	2		T34	1
all_values[6]	auto[0]	auto[0]	auto[1]	53	1			T16	1		T69	1		T108	1
all_values[6]	auto[0]	auto[1]	auto[0]	93	1			T16	3		T34	2		T68	2
all_values[6]	auto[0]	auto[1]	auto[1]	55	1			T32	1		T68	2		T69	1
all_values[6]	auto[1]	auto[0]	auto[1]	142	1			T16	1		T32	1		T34	1
all_values[6]	auto[1]	auto[1]	auto[1]	111	1			T16	1		T68	1		T113	1
all_values[7]	auto[0]	auto[0]	auto[0]	132	1			T16	3		T34	1		T68	1
all_values[7]	auto[0]	auto[0]	auto[1]	54	1			T16	1		T32	1		T113	1
all_values[7]	auto[0]	auto[1]	auto[0]	104	1			T16	1		T68	2		T69	1
all_values[7]	auto[0]	auto[1]	auto[1]	55	1			T34	1		T95	1		T112	1
all_values[7]	auto[1]	auto[0]	auto[1]	140	1			T16	2		T32	3		T68	4
all_values[7]	auto[1]	auto[1]	auto[1]	111	1			T34	2		T108	1		T95	2
all_values[8]	auto[0]	auto[0]	auto[1]	183	1			T32	2		T34	1		T68	2
all_values[8]	auto[0]	auto[1]	auto[1]	147	1			T16	1		T68	1		T69	2
all_values[8]	auto[1]	auto[0]	auto[1]	157	1			T16	2		T32	2		T34	2
all_values[8]	auto[1]	auto[1]	auto[1]	109	1			T16	4		T34	1		T68	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal