Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.10 97.65 100.00 98.38 100.00 99.44


Total test records in report: 1319
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T1259 /workspace/coverage/cover_reg_top/9.uart_csr_rw.598294284 Aug 12 05:00:28 PM PDT 24 Aug 12 05:00:29 PM PDT 24 58054404 ps
T1260 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1885708933 Aug 12 05:00:35 PM PDT 24 Aug 12 05:00:36 PM PDT 24 19900054 ps
T1261 /workspace/coverage/cover_reg_top/3.uart_csr_rw.3361489983 Aug 12 05:00:27 PM PDT 24 Aug 12 05:00:28 PM PDT 24 16094930 ps
T1262 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3113368566 Aug 12 05:00:26 PM PDT 24 Aug 12 05:00:27 PM PDT 24 24359625 ps
T75 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2505701245 Aug 12 05:00:19 PM PDT 24 Aug 12 05:00:21 PM PDT 24 171281352 ps
T1263 /workspace/coverage/cover_reg_top/30.uart_intr_test.1930011893 Aug 12 05:00:49 PM PDT 24 Aug 12 05:00:50 PM PDT 24 14304035 ps
T1264 /workspace/coverage/cover_reg_top/39.uart_intr_test.8505882 Aug 12 05:00:49 PM PDT 24 Aug 12 05:00:49 PM PDT 24 16251879 ps
T1265 /workspace/coverage/cover_reg_top/16.uart_tl_errors.1209289153 Aug 12 05:00:36 PM PDT 24 Aug 12 05:00:38 PM PDT 24 215913007 ps
T1266 /workspace/coverage/cover_reg_top/2.uart_csr_rw.3821168766 Aug 12 05:00:29 PM PDT 24 Aug 12 05:00:30 PM PDT 24 17060535 ps
T1267 /workspace/coverage/cover_reg_top/0.uart_tl_errors.3659829823 Aug 12 05:00:11 PM PDT 24 Aug 12 05:00:13 PM PDT 24 445081217 ps
T1268 /workspace/coverage/cover_reg_top/45.uart_intr_test.2315289567 Aug 12 05:00:47 PM PDT 24 Aug 12 05:00:48 PM PDT 24 24719121 ps
T1269 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3943980477 Aug 12 05:00:29 PM PDT 24 Aug 12 05:00:31 PM PDT 24 171495958 ps
T52 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.4215021859 Aug 12 05:00:19 PM PDT 24 Aug 12 05:00:19 PM PDT 24 14462466 ps
T1270 /workspace/coverage/cover_reg_top/10.uart_intr_test.2761074513 Aug 12 05:00:26 PM PDT 24 Aug 12 05:00:26 PM PDT 24 28809329 ps
T1271 /workspace/coverage/cover_reg_top/6.uart_intr_test.1565582081 Aug 12 05:00:27 PM PDT 24 Aug 12 05:00:28 PM PDT 24 46096230 ps
T1272 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.21515343 Aug 12 05:00:28 PM PDT 24 Aug 12 05:00:29 PM PDT 24 34718046 ps
T1273 /workspace/coverage/cover_reg_top/31.uart_intr_test.3284841581 Aug 12 05:00:49 PM PDT 24 Aug 12 05:00:50 PM PDT 24 16568679 ps
T1274 /workspace/coverage/cover_reg_top/24.uart_intr_test.1390333648 Aug 12 05:00:51 PM PDT 24 Aug 12 05:00:52 PM PDT 24 23157336 ps
T53 /workspace/coverage/cover_reg_top/16.uart_csr_rw.1856234019 Aug 12 05:00:37 PM PDT 24 Aug 12 05:00:38 PM PDT 24 17715850 ps
T1275 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3735842675 Aug 12 05:00:18 PM PDT 24 Aug 12 05:00:19 PM PDT 24 19021794 ps
T1276 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1324328772 Aug 12 05:00:19 PM PDT 24 Aug 12 05:00:20 PM PDT 24 28804853 ps
T1277 /workspace/coverage/cover_reg_top/7.uart_tl_errors.1324946405 Aug 12 05:00:27 PM PDT 24 Aug 12 05:00:29 PM PDT 24 351948521 ps
T78 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3104625533 Aug 12 05:00:23 PM PDT 24 Aug 12 05:00:25 PM PDT 24 339305323 ps
T1278 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.4287607051 Aug 12 05:00:25 PM PDT 24 Aug 12 05:00:27 PM PDT 24 404100078 ps
T1279 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1182134978 Aug 12 05:00:37 PM PDT 24 Aug 12 05:00:38 PM PDT 24 30904877 ps
T1280 /workspace/coverage/cover_reg_top/48.uart_intr_test.555493612 Aug 12 05:00:49 PM PDT 24 Aug 12 05:00:50 PM PDT 24 48330889 ps
T1281 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.642986310 Aug 12 05:00:37 PM PDT 24 Aug 12 05:00:38 PM PDT 24 170766442 ps
T1282 /workspace/coverage/cover_reg_top/40.uart_intr_test.94507737 Aug 12 05:00:48 PM PDT 24 Aug 12 05:00:49 PM PDT 24 19819335 ps
T1283 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2698284955 Aug 12 05:00:19 PM PDT 24 Aug 12 05:00:20 PM PDT 24 14495169 ps
T1284 /workspace/coverage/cover_reg_top/27.uart_intr_test.509818504 Aug 12 05:00:45 PM PDT 24 Aug 12 05:00:46 PM PDT 24 18606684 ps
T237 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3002008799 Aug 12 05:00:25 PM PDT 24 Aug 12 05:00:26 PM PDT 24 623922464 ps
T1285 /workspace/coverage/cover_reg_top/3.uart_tl_errors.2872890873 Aug 12 05:00:19 PM PDT 24 Aug 12 05:00:20 PM PDT 24 466305897 ps
T1286 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.133065354 Aug 12 05:00:27 PM PDT 24 Aug 12 05:00:29 PM PDT 24 75139871 ps
T1287 /workspace/coverage/cover_reg_top/12.uart_intr_test.1290943207 Aug 12 05:00:35 PM PDT 24 Aug 12 05:00:36 PM PDT 24 26046158 ps
T1288 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3323420069 Aug 12 05:00:38 PM PDT 24 Aug 12 05:00:40 PM PDT 24 45778468 ps
T1289 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2472320274 Aug 12 05:00:34 PM PDT 24 Aug 12 05:00:36 PM PDT 24 247325473 ps
T1290 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.4276923219 Aug 12 05:00:35 PM PDT 24 Aug 12 05:00:36 PM PDT 24 30528519 ps
T1291 /workspace/coverage/cover_reg_top/41.uart_intr_test.1935668501 Aug 12 05:00:53 PM PDT 24 Aug 12 05:00:53 PM PDT 24 16079075 ps
T1292 /workspace/coverage/cover_reg_top/28.uart_intr_test.1414958454 Aug 12 05:00:46 PM PDT 24 Aug 12 05:00:46 PM PDT 24 16288221 ps
T1293 /workspace/coverage/cover_reg_top/0.uart_csr_rw.1466081407 Aug 12 05:00:11 PM PDT 24 Aug 12 05:00:12 PM PDT 24 50710103 ps
T1294 /workspace/coverage/cover_reg_top/5.uart_csr_rw.599108110 Aug 12 05:00:34 PM PDT 24 Aug 12 05:00:35 PM PDT 24 101978937 ps
T1295 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.832446835 Aug 12 05:00:26 PM PDT 24 Aug 12 05:00:27 PM PDT 24 138336358 ps
T1296 /workspace/coverage/cover_reg_top/33.uart_intr_test.905675577 Aug 12 05:00:46 PM PDT 24 Aug 12 05:00:47 PM PDT 24 49711265 ps
T54 /workspace/coverage/cover_reg_top/18.uart_csr_rw.225462203 Aug 12 05:00:38 PM PDT 24 Aug 12 05:00:39 PM PDT 24 18426121 ps
T1297 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3948413051 Aug 12 05:00:35 PM PDT 24 Aug 12 05:00:37 PM PDT 24 186775598 ps
T1298 /workspace/coverage/cover_reg_top/5.uart_intr_test.1125327077 Aug 12 05:00:29 PM PDT 24 Aug 12 05:00:30 PM PDT 24 13860985 ps
T1299 /workspace/coverage/cover_reg_top/13.uart_intr_test.3069931899 Aug 12 05:00:35 PM PDT 24 Aug 12 05:00:36 PM PDT 24 42124869 ps
T1300 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1230408056 Aug 12 05:00:37 PM PDT 24 Aug 12 05:00:38 PM PDT 24 56168302 ps
T55 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1501637074 Aug 12 05:00:19 PM PDT 24 Aug 12 05:00:20 PM PDT 24 74945300 ps
T1301 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3185636249 Aug 12 05:00:26 PM PDT 24 Aug 12 05:00:27 PM PDT 24 70006034 ps
T79 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3632399487 Aug 12 05:00:36 PM PDT 24 Aug 12 05:00:38 PM PDT 24 96677494 ps
T1302 /workspace/coverage/cover_reg_top/49.uart_intr_test.770856031 Aug 12 05:00:52 PM PDT 24 Aug 12 05:00:52 PM PDT 24 40484440 ps
T1303 /workspace/coverage/cover_reg_top/11.uart_tl_errors.4010896342 Aug 12 05:00:25 PM PDT 24 Aug 12 05:00:27 PM PDT 24 63962877 ps
T1304 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3301175670 Aug 12 05:00:24 PM PDT 24 Aug 12 05:00:25 PM PDT 24 141975750 ps
T1305 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3139696180 Aug 12 05:00:26 PM PDT 24 Aug 12 05:00:26 PM PDT 24 29000627 ps
T1306 /workspace/coverage/cover_reg_top/17.uart_intr_test.1175950278 Aug 12 05:00:36 PM PDT 24 Aug 12 05:00:37 PM PDT 24 24433835 ps
T1307 /workspace/coverage/cover_reg_top/25.uart_intr_test.246613877 Aug 12 05:00:49 PM PDT 24 Aug 12 05:00:49 PM PDT 24 17515527 ps
T1308 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2763587018 Aug 12 05:00:34 PM PDT 24 Aug 12 05:00:35 PM PDT 24 24082584 ps
T1309 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3318522081 Aug 12 05:00:28 PM PDT 24 Aug 12 05:00:29 PM PDT 24 59163628 ps
T1310 /workspace/coverage/cover_reg_top/32.uart_intr_test.2898214613 Aug 12 05:00:53 PM PDT 24 Aug 12 05:00:54 PM PDT 24 23957607 ps
T1311 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.4145804916 Aug 12 05:00:20 PM PDT 24 Aug 12 05:00:22 PM PDT 24 341782514 ps
T1312 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.96513277 Aug 12 05:00:20 PM PDT 24 Aug 12 05:00:20 PM PDT 24 12714599 ps
T1313 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1752899547 Aug 12 05:00:14 PM PDT 24 Aug 12 05:00:15 PM PDT 24 21078206 ps
T1314 /workspace/coverage/cover_reg_top/16.uart_intr_test.2517283062 Aug 12 05:00:36 PM PDT 24 Aug 12 05:00:36 PM PDT 24 42038567 ps
T1315 /workspace/coverage/cover_reg_top/42.uart_intr_test.665629562 Aug 12 05:00:47 PM PDT 24 Aug 12 05:00:48 PM PDT 24 37413320 ps
T1316 /workspace/coverage/cover_reg_top/1.uart_tl_errors.1716217943 Aug 12 05:00:28 PM PDT 24 Aug 12 05:00:29 PM PDT 24 74488969 ps
T1317 /workspace/coverage/cover_reg_top/46.uart_intr_test.1255627163 Aug 12 05:00:49 PM PDT 24 Aug 12 05:00:50 PM PDT 24 48926970 ps
T1318 /workspace/coverage/cover_reg_top/1.uart_intr_test.3150606010 Aug 12 05:00:20 PM PDT 24 Aug 12 05:00:21 PM PDT 24 13857591 ps
T1319 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.510922767 Aug 12 05:00:36 PM PDT 24 Aug 12 05:00:37 PM PDT 24 39649982 ps

Test location /workspace/coverage/default/47.uart_fifo_full.1231673731
Short name T10
Test name
Test status
Simulation time 41197862489 ps
CPU time 69.94 seconds
Started Aug 12 05:05:57 PM PDT 24
Finished Aug 12 05:07:07 PM PDT 24
Peak memory 200712 kb
Host smart-4a96e606-f7ce-48ae-8bfb-807fb0b47926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231673731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1231673731
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_stress_all.243185396
Short name T21
Test name
Test status
Simulation time 300104466927 ps
CPU time 648.4 seconds
Started Aug 12 05:04:22 PM PDT 24
Finished Aug 12 05:15:11 PM PDT 24
Peak memory 217412 kb
Host smart-cc0412fd-7a92-4f4e-a88b-f500b80366a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243185396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.243185396
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1843358235
Short name T1
Test name
Test status
Simulation time 13027377865 ps
CPU time 15.16 seconds
Started Aug 12 05:05:09 PM PDT 24
Finished Aug 12 05:05:25 PM PDT 24
Peak memory 217288 kb
Host smart-ba3cbe2b-c63b-44f5-b336-20d85d3c4b4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843358235 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1843358235
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_stress_all.570962533
Short name T23
Test name
Test status
Simulation time 306698380643 ps
CPU time 241.06 seconds
Started Aug 12 05:05:33 PM PDT 24
Finished Aug 12 05:09:34 PM PDT 24
Peak memory 217412 kb
Host smart-97563df8-aba1-4a24-b7d4-95ebd39e1d2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570962533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.570962533
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all.3154594849
Short name T40
Test name
Test status
Simulation time 340088240912 ps
CPU time 144.25 seconds
Started Aug 12 05:04:10 PM PDT 24
Finished Aug 12 05:06:35 PM PDT 24
Peak memory 209096 kb
Host smart-70ef54a7-efb1-42fa-819d-95e196001067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154594849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3154594849
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all.3327982539
Short name T16
Test name
Test status
Simulation time 232544912225 ps
CPU time 35.94 seconds
Started Aug 12 05:05:05 PM PDT 24
Finished Aug 12 05:05:41 PM PDT 24
Peak memory 200756 kb
Host smart-360b7406-3a40-44e1-934a-5ca00117b08a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327982539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3327982539
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all.4130760527
Short name T283
Test name
Test status
Simulation time 244919791790 ps
CPU time 2287.47 seconds
Started Aug 12 05:03:47 PM PDT 24
Finished Aug 12 05:41:54 PM PDT 24
Peak memory 217028 kb
Host smart-46efad64-65ca-420e-9350-e6d935068c2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130760527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.4130760527
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all.638973788
Short name T122
Test name
Test status
Simulation time 216880892334 ps
CPU time 98.16 seconds
Started Aug 12 05:04:56 PM PDT 24
Finished Aug 12 05:06:34 PM PDT 24
Peak memory 217388 kb
Host smart-1e726dba-f3e5-4aca-91ec-ff1e31e1e2bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638973788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.638973788
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all.4150687280
Short name T101
Test name
Test status
Simulation time 362196702180 ps
CPU time 741.27 seconds
Started Aug 12 05:04:57 PM PDT 24
Finished Aug 12 05:17:18 PM PDT 24
Peak memory 200756 kb
Host smart-30ef7adf-5396-481e-a60e-0dcea1b26405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150687280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.4150687280
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all.2002261193
Short name T134
Test name
Test status
Simulation time 244189389782 ps
CPU time 622.07 seconds
Started Aug 12 05:05:38 PM PDT 24
Finished Aug 12 05:16:00 PM PDT 24
Peak memory 200712 kb
Host smart-82faf2c6-ac18-4146-a9f2-5697d2bf115a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002261193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2002261193
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2203812951
Short name T132
Test name
Test status
Simulation time 49787359231 ps
CPU time 29.29 seconds
Started Aug 12 05:05:19 PM PDT 24
Finished Aug 12 05:05:48 PM PDT 24
Peak memory 200816 kb
Host smart-42547578-18d5-44e7-b60a-f7282991d8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203812951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2203812951
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2536865009
Short name T80
Test name
Test status
Simulation time 66430137 ps
CPU time 0.8 seconds
Started Aug 12 05:03:42 PM PDT 24
Finished Aug 12 05:03:43 PM PDT 24
Peak memory 219008 kb
Host smart-445c0e44-54fa-4e8b-a9b4-88afff2c9f78
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536865009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2536865009
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.4270144644
Short name T65
Test name
Test status
Simulation time 160596233709 ps
CPU time 121.49 seconds
Started Aug 12 05:06:44 PM PDT 24
Finished Aug 12 05:08:46 PM PDT 24
Peak memory 200716 kb
Host smart-5facd308-92ca-4b4d-990a-122546dab02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270144644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.4270144644
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_alert_test.185844377
Short name T8
Test name
Test status
Simulation time 24226668 ps
CPU time 0.54 seconds
Started Aug 12 05:03:52 PM PDT 24
Finished Aug 12 05:03:53 PM PDT 24
Peak memory 196088 kb
Host smart-0c979d94-3d54-4f21-a98d-18db2ebd5329
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185844377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.185844377
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1920595230
Short name T50
Test name
Test status
Simulation time 13225948 ps
CPU time 0.66 seconds
Started Aug 12 05:00:18 PM PDT 24
Finished Aug 12 05:00:19 PM PDT 24
Peak memory 195468 kb
Host smart-2a31943f-1e68-45b4-a098-589c5a5dff10
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920595230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1920595230
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3683454174
Short name T89
Test name
Test status
Simulation time 154248117026 ps
CPU time 82.61 seconds
Started Aug 12 05:06:23 PM PDT 24
Finished Aug 12 05:07:45 PM PDT 24
Peak memory 200800 kb
Host smart-a2316383-9ec5-4e9e-9cb7-cb4202589d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683454174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3683454174
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.863086973
Short name T138
Test name
Test status
Simulation time 73165912150 ps
CPU time 8.56 seconds
Started Aug 12 05:05:11 PM PDT 24
Finished Aug 12 05:05:20 PM PDT 24
Peak memory 200816 kb
Host smart-f91e2022-8b41-4a98-8523-225cab3e1e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863086973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.863086973
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.3640235322
Short name T240
Test name
Test status
Simulation time 77304091601 ps
CPU time 640.01 seconds
Started Aug 12 05:06:00 PM PDT 24
Finished Aug 12 05:16:40 PM PDT 24
Peak memory 200704 kb
Host smart-d19fa1c7-c8c5-4664-902b-424c214547c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3640235322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3640235322
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3570922178
Short name T99
Test name
Test status
Simulation time 73797946365 ps
CPU time 159.15 seconds
Started Aug 12 05:05:02 PM PDT 24
Finished Aug 12 05:07:41 PM PDT 24
Peak memory 200936 kb
Host smart-04e6d6e6-87dd-4cb2-b897-f0d4d804feb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570922178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3570922178
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2505701245
Short name T75
Test name
Test status
Simulation time 171281352 ps
CPU time 1.27 seconds
Started Aug 12 05:00:19 PM PDT 24
Finished Aug 12 05:00:21 PM PDT 24
Peak memory 199424 kb
Host smart-7a3cbfaf-1d2c-44cb-9ec8-21b698ba1ca6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505701245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2505701245
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.3485044495
Short name T6
Test name
Test status
Simulation time 43142245026 ps
CPU time 48.42 seconds
Started Aug 12 05:04:35 PM PDT 24
Finished Aug 12 05:05:24 PM PDT 24
Peak memory 200840 kb
Host smart-3ecf361e-df8b-411c-8655-c1fb26b9e021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485044495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3485044495
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all.1286288030
Short name T142
Test name
Test status
Simulation time 156344422372 ps
CPU time 144.95 seconds
Started Aug 12 05:03:56 PM PDT 24
Finished Aug 12 05:06:21 PM PDT 24
Peak memory 209152 kb
Host smart-08b8aed2-9c45-4cae-a6bd-1f31eb269a9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286288030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1286288030
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.2699867873
Short name T152
Test name
Test status
Simulation time 69508190063 ps
CPU time 51.82 seconds
Started Aug 12 05:04:09 PM PDT 24
Finished Aug 12 05:05:01 PM PDT 24
Peak memory 200812 kb
Host smart-2ad599d6-8b17-4e85-a345-8809cfce182a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699867873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2699867873
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3438390649
Short name T36
Test name
Test status
Simulation time 123873391598 ps
CPU time 49.25 seconds
Started Aug 12 05:05:33 PM PDT 24
Finished Aug 12 05:06:23 PM PDT 24
Peak memory 200668 kb
Host smart-cc7f79b7-77a2-4ff6-914a-5bfef7d118b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438390649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3438390649
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1431337123
Short name T84
Test name
Test status
Simulation time 79672112911 ps
CPU time 75.83 seconds
Started Aug 12 05:06:43 PM PDT 24
Finished Aug 12 05:07:59 PM PDT 24
Peak memory 200752 kb
Host smart-32ad35e7-ef57-4c8d-8871-ad329b11e3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431337123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1431337123
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.4114315461
Short name T131
Test name
Test status
Simulation time 169342627920 ps
CPU time 36.68 seconds
Started Aug 12 05:04:11 PM PDT 24
Finished Aug 12 05:04:48 PM PDT 24
Peak memory 200808 kb
Host smart-c8ac10ce-b28e-4192-8c1d-9cedda5d5672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114315461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.4114315461
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.591476646
Short name T306
Test name
Test status
Simulation time 261539839375 ps
CPU time 201.75 seconds
Started Aug 12 05:06:30 PM PDT 24
Finished Aug 12 05:09:53 PM PDT 24
Peak memory 200612 kb
Host smart-729b9dca-95b4-4f35-9be9-f1899bc5ab1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591476646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.591476646
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1367110367
Short name T34
Test name
Test status
Simulation time 9247517519 ps
CPU time 51.53 seconds
Started Aug 12 05:06:25 PM PDT 24
Finished Aug 12 05:07:17 PM PDT 24
Peak memory 209904 kb
Host smart-794d5224-6d63-41d0-8b35-7388593cca6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367110367 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1367110367
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2364375611
Short name T63
Test name
Test status
Simulation time 19849495 ps
CPU time 0.66 seconds
Started Aug 12 05:00:19 PM PDT 24
Finished Aug 12 05:00:20 PM PDT 24
Peak memory 195808 kb
Host smart-182037f8-7e66-4c5d-b5f9-cd6136225608
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364375611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2364375611
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/default/11.uart_intr.230004729
Short name T15
Test name
Test status
Simulation time 35166299115 ps
CPU time 59.8 seconds
Started Aug 12 05:04:01 PM PDT 24
Finished Aug 12 05:05:01 PM PDT 24
Peak memory 200852 kb
Host smart-9f37f7c8-9d67-4259-98d8-62ad157e084f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230004729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.230004729
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/49.uart_stress_all.537743868
Short name T153
Test name
Test status
Simulation time 334717223582 ps
CPU time 204.08 seconds
Started Aug 12 05:06:06 PM PDT 24
Finished Aug 12 05:09:30 PM PDT 24
Peak memory 200684 kb
Host smart-748b4a44-4bbf-4fca-8c2c-a2dddc58de42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537743868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.537743868
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.88710382
Short name T234
Test name
Test status
Simulation time 50720059068 ps
CPU time 30.2 seconds
Started Aug 12 05:06:35 PM PDT 24
Finished Aug 12 05:07:05 PM PDT 24
Peak memory 200796 kb
Host smart-36cdedf5-5e63-4e0c-88bf-cb4c937ede16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88710382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.88710382
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.378565110
Short name T33
Test name
Test status
Simulation time 7516099737 ps
CPU time 49.92 seconds
Started Aug 12 05:06:19 PM PDT 24
Finished Aug 12 05:07:09 PM PDT 24
Peak memory 200968 kb
Host smart-a4614ca0-5c70-4a86-8bc7-236d67a32821
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378565110 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.378565110
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.703650211
Short name T464
Test name
Test status
Simulation time 255587304971 ps
CPU time 56.81 seconds
Started Aug 12 05:06:05 PM PDT 24
Finished Aug 12 05:07:02 PM PDT 24
Peak memory 200788 kb
Host smart-cfa0ec7e-32dc-42f9-93c6-15d2a75278ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703650211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.703650211
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.555064646
Short name T157
Test name
Test status
Simulation time 54886741229 ps
CPU time 101.75 seconds
Started Aug 12 05:06:44 PM PDT 24
Finished Aug 12 05:08:26 PM PDT 24
Peak memory 200596 kb
Host smart-04bb5cb3-f88c-4d0f-913d-b4d9cccb0f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555064646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.555064646
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1015306575
Short name T136
Test name
Test status
Simulation time 55710158088 ps
CPU time 35.2 seconds
Started Aug 12 05:06:31 PM PDT 24
Finished Aug 12 05:07:06 PM PDT 24
Peak memory 200640 kb
Host smart-7e475915-083a-4059-9cef-625bac76fc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015306575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1015306575
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3747001269
Short name T172
Test name
Test status
Simulation time 192329318507 ps
CPU time 71.73 seconds
Started Aug 12 05:05:19 PM PDT 24
Finished Aug 12 05:06:30 PM PDT 24
Peak memory 200820 kb
Host smart-8cbd3b61-1369-490f-81e1-1edd481ea427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747001269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3747001269
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3632399487
Short name T79
Test name
Test status
Simulation time 96677494 ps
CPU time 1.35 seconds
Started Aug 12 05:00:36 PM PDT 24
Finished Aug 12 05:00:38 PM PDT 24
Peak memory 199412 kb
Host smart-a441638f-04af-4b25-a512-83ff8a1eb4b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632399487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3632399487
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1854632447
Short name T173
Test name
Test status
Simulation time 85307893152 ps
CPU time 98.19 seconds
Started Aug 12 05:04:25 PM PDT 24
Finished Aug 12 05:06:03 PM PDT 24
Peak memory 200808 kb
Host smart-27d8ea94-c4f0-4fc8-b225-fd300e052b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854632447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1854632447
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.1048033842
Short name T102
Test name
Test status
Simulation time 87190685073 ps
CPU time 99.26 seconds
Started Aug 12 05:07:11 PM PDT 24
Finished Aug 12 05:08:50 PM PDT 24
Peak memory 200672 kb
Host smart-d0b8b8da-9cad-4b25-ab34-34c8c40d5f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048033842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1048033842
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_perf.3913372210
Short name T268
Test name
Test status
Simulation time 21909874605 ps
CPU time 968.62 seconds
Started Aug 12 05:04:54 PM PDT 24
Finished Aug 12 05:21:03 PM PDT 24
Peak memory 200756 kb
Host smart-ee16b60e-7484-466d-ae59-197716213da2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3913372210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3913372210
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1356075484
Short name T97
Test name
Test status
Simulation time 5917850273 ps
CPU time 38.55 seconds
Started Aug 12 05:04:34 PM PDT 24
Finished Aug 12 05:05:12 PM PDT 24
Peak memory 209040 kb
Host smart-60e95c5c-defc-47db-86e7-79c2825ed7e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356075484 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1356075484
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.145616394
Short name T164
Test name
Test status
Simulation time 80920296283 ps
CPU time 36.27 seconds
Started Aug 12 05:06:30 PM PDT 24
Finished Aug 12 05:07:06 PM PDT 24
Peak memory 200760 kb
Host smart-1a541a08-286f-4d0a-8a2d-e922d6ea9160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145616394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.145616394
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3020651381
Short name T185
Test name
Test status
Simulation time 36804819315 ps
CPU time 29.76 seconds
Started Aug 12 05:06:29 PM PDT 24
Finished Aug 12 05:06:59 PM PDT 24
Peak memory 200784 kb
Host smart-add7392e-b259-47fc-8dc5-1be1f5d129f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020651381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3020651381
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1325908210
Short name T226
Test name
Test status
Simulation time 74740548923 ps
CPU time 103.72 seconds
Started Aug 12 05:06:35 PM PDT 24
Finished Aug 12 05:08:19 PM PDT 24
Peak memory 200664 kb
Host smart-50dd228d-8e1f-4c7a-a7a5-a452c1e7b721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325908210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1325908210
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.4026840975
Short name T115
Test name
Test status
Simulation time 57113289921 ps
CPU time 98.09 seconds
Started Aug 12 05:06:42 PM PDT 24
Finished Aug 12 05:08:21 PM PDT 24
Peak memory 200580 kb
Host smart-effd1958-8c63-44d2-a44c-933501ab135b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026840975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.4026840975
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.1577916594
Short name T827
Test name
Test status
Simulation time 7757084504 ps
CPU time 40.22 seconds
Started Aug 12 05:04:26 PM PDT 24
Finished Aug 12 05:05:07 PM PDT 24
Peak memory 216232 kb
Host smart-aa404451-fc9d-43f7-9f6d-d4d86598902b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577916594 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1577916594
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.4070658654
Short name T953
Test name
Test status
Simulation time 145900481656 ps
CPU time 223.18 seconds
Started Aug 12 05:06:07 PM PDT 24
Finished Aug 12 05:09:51 PM PDT 24
Peak memory 200812 kb
Host smart-eb23128f-5165-48c2-aaff-18552bf7a27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070658654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.4070658654
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2211240070
Short name T196
Test name
Test status
Simulation time 121024279960 ps
CPU time 68.99 seconds
Started Aug 12 05:06:29 PM PDT 24
Finished Aug 12 05:07:38 PM PDT 24
Peak memory 200648 kb
Host smart-a5365cf7-ec6a-435b-8747-05d3f43267f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211240070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2211240070
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_stress_all.3655906672
Short name T527
Test name
Test status
Simulation time 223983122601 ps
CPU time 1379.79 seconds
Started Aug 12 05:04:02 PM PDT 24
Finished Aug 12 05:27:02 PM PDT 24
Peak memory 200832 kb
Host smart-9d6625c6-001e-4159-bc06-6834f744e3e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655906672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3655906672
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3668755605
Short name T900
Test name
Test status
Simulation time 83599652686 ps
CPU time 157.87 seconds
Started Aug 12 05:06:49 PM PDT 24
Finished Aug 12 05:09:27 PM PDT 24
Peak memory 200740 kb
Host smart-dc446dc8-9dbb-46b2-8f6d-6cbb9b889679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668755605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3668755605
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3985529487
Short name T141
Test name
Test status
Simulation time 34006794855 ps
CPU time 58.98 seconds
Started Aug 12 05:04:41 PM PDT 24
Finished Aug 12 05:05:40 PM PDT 24
Peak memory 200672 kb
Host smart-02077907-5d50-4f96-b914-ee3a8073a4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985529487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3985529487
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.882098963
Short name T220
Test name
Test status
Simulation time 61154830904 ps
CPU time 32.14 seconds
Started Aug 12 05:06:05 PM PDT 24
Finished Aug 12 05:06:38 PM PDT 24
Peak memory 200660 kb
Host smart-a34ec9e6-0fa9-49b0-9a2d-07f0dbb46777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882098963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.882098963
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3549423615
Short name T228
Test name
Test status
Simulation time 122763787104 ps
CPU time 67.12 seconds
Started Aug 12 05:06:23 PM PDT 24
Finished Aug 12 05:07:30 PM PDT 24
Peak memory 200780 kb
Host smart-a2493827-452f-43ba-9db5-fd09297ca40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549423615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3549423615
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.4230843327
Short name T74
Test name
Test status
Simulation time 146276519 ps
CPU time 0.99 seconds
Started Aug 12 05:00:29 PM PDT 24
Finished Aug 12 05:00:30 PM PDT 24
Peak memory 199160 kb
Host smart-c3ca6d20-473b-41e5-b256-fb1ef6211fef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230843327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.4230843327
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.3947019991
Short name T279
Test name
Test status
Simulation time 92085873229 ps
CPU time 626.06 seconds
Started Aug 12 05:03:45 PM PDT 24
Finished Aug 12 05:14:11 PM PDT 24
Peak memory 200756 kb
Host smart-fd05db3b-ea9b-4821-bcb1-92575816eb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947019991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3947019991
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1480384924
Short name T176
Test name
Test status
Simulation time 175784096731 ps
CPU time 216.66 seconds
Started Aug 12 05:06:35 PM PDT 24
Finished Aug 12 05:10:12 PM PDT 24
Peak memory 200732 kb
Host smart-7ae090b7-566c-4699-bab3-2e9dab693b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480384924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1480384924
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.354264098
Short name T32
Test name
Test status
Simulation time 7729760464 ps
CPU time 49.66 seconds
Started Aug 12 05:04:07 PM PDT 24
Finished Aug 12 05:04:56 PM PDT 24
Peak memory 217368 kb
Host smart-c2ea51c1-5557-4927-83ef-640344725494
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354264098 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.354264098
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.803324286
Short name T202
Test name
Test status
Simulation time 93422424629 ps
CPU time 37.23 seconds
Started Aug 12 05:06:51 PM PDT 24
Finished Aug 12 05:07:28 PM PDT 24
Peak memory 200656 kb
Host smart-b5618ad1-b90a-4c28-895a-28bef4c68c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803324286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.803324286
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.169260129
Short name T1084
Test name
Test status
Simulation time 142548418608 ps
CPU time 122.1 seconds
Started Aug 12 05:06:56 PM PDT 24
Finished Aug 12 05:08:58 PM PDT 24
Peak memory 200728 kb
Host smart-f768ee7c-0e0c-462f-bf48-edcc657246ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169260129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.169260129
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_noise_filter.15820242
Short name T640
Test name
Test status
Simulation time 162701202394 ps
CPU time 68.29 seconds
Started Aug 12 05:03:33 PM PDT 24
Finished Aug 12 05:04:41 PM PDT 24
Peak memory 201136 kb
Host smart-2dcdeba3-0b08-41c4-b3c2-1f9e3c0aa071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15820242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.15820242
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3836994558
Short name T181
Test name
Test status
Simulation time 146438761951 ps
CPU time 50.66 seconds
Started Aug 12 05:06:32 PM PDT 24
Finished Aug 12 05:07:22 PM PDT 24
Peak memory 200672 kb
Host smart-d9afde73-8129-43e9-913c-57e51c9b8c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836994558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3836994558
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.1828450177
Short name T69
Test name
Test status
Simulation time 3662319045 ps
CPU time 37.95 seconds
Started Aug 12 05:04:04 PM PDT 24
Finished Aug 12 05:04:42 PM PDT 24
Peak memory 217260 kb
Host smart-7adfd1c2-0eab-4ff6-853c-7d6217940a5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828450177 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1828450177
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.709564125
Short name T209
Test name
Test status
Simulation time 165696078089 ps
CPU time 50 seconds
Started Aug 12 05:06:30 PM PDT 24
Finished Aug 12 05:07:21 PM PDT 24
Peak memory 200756 kb
Host smart-62e84e45-87ab-4333-ab5a-71cbcae1c304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709564125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.709564125
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.2847331345
Short name T207
Test name
Test status
Simulation time 132437335539 ps
CPU time 306.34 seconds
Started Aug 12 05:06:27 PM PDT 24
Finished Aug 12 05:11:34 PM PDT 24
Peak memory 200712 kb
Host smart-19318cee-3e19-4ad9-aabb-a594ec9f812e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847331345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2847331345
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.2379360329
Short name T225
Test name
Test status
Simulation time 109520745365 ps
CPU time 55.28 seconds
Started Aug 12 05:06:37 PM PDT 24
Finished Aug 12 05:07:33 PM PDT 24
Peak memory 200828 kb
Host smart-7a3cf7c1-8c40-4bc5-a3cf-61952ca90a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379360329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2379360329
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.4247892255
Short name T301
Test name
Test status
Simulation time 42621546173 ps
CPU time 38.42 seconds
Started Aug 12 05:04:15 PM PDT 24
Finished Aug 12 05:04:54 PM PDT 24
Peak memory 200612 kb
Host smart-be21dca6-712e-4103-9378-73a09a4c8ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247892255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.4247892255
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.4203492476
Short name T218
Test name
Test status
Simulation time 172996946512 ps
CPU time 388.73 seconds
Started Aug 12 05:06:35 PM PDT 24
Finished Aug 12 05:13:05 PM PDT 24
Peak memory 200752 kb
Host smart-70c418d4-b798-417f-aa5a-92943a019b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203492476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.4203492476
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1578572822
Short name T224
Test name
Test status
Simulation time 342656454413 ps
CPU time 135.42 seconds
Started Aug 12 05:06:37 PM PDT 24
Finished Aug 12 05:08:53 PM PDT 24
Peak memory 200844 kb
Host smart-57068ca6-7fa9-4fa3-8683-f1fdb99b22fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578572822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1578572822
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1842098470
Short name T221
Test name
Test status
Simulation time 21748080476 ps
CPU time 33.5 seconds
Started Aug 12 05:06:43 PM PDT 24
Finished Aug 12 05:07:17 PM PDT 24
Peak memory 200664 kb
Host smart-8ff7519d-ec06-487f-b6ec-60e914223852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842098470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1842098470
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3567907270
Short name T145
Test name
Test status
Simulation time 70478572639 ps
CPU time 33.15 seconds
Started Aug 12 05:06:45 PM PDT 24
Finished Aug 12 05:07:18 PM PDT 24
Peak memory 200752 kb
Host smart-7f8d1f8d-e831-4130-85ae-b77435d26ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567907270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3567907270
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2836516948
Short name T165
Test name
Test status
Simulation time 71134509057 ps
CPU time 41.29 seconds
Started Aug 12 05:06:50 PM PDT 24
Finished Aug 12 05:07:32 PM PDT 24
Peak memory 200828 kb
Host smart-9f4e3fc1-a843-4639-b6c8-bed9bdbfedfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836516948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2836516948
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1920695793
Short name T213
Test name
Test status
Simulation time 56780166519 ps
CPU time 30.55 seconds
Started Aug 12 05:06:51 PM PDT 24
Finished Aug 12 05:07:21 PM PDT 24
Peak memory 200676 kb
Host smart-3c138703-4a32-491f-8d41-149a250a6af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920695793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1920695793
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3619081489
Short name T139
Test name
Test status
Simulation time 302630790217 ps
CPU time 121.8 seconds
Started Aug 12 05:07:12 PM PDT 24
Finished Aug 12 05:09:14 PM PDT 24
Peak memory 200740 kb
Host smart-cdd1041f-c7fa-4bf1-9578-4c91858cbbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619081489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3619081489
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2498197817
Short name T203
Test name
Test status
Simulation time 25879841590 ps
CPU time 39.37 seconds
Started Aug 12 05:07:11 PM PDT 24
Finished Aug 12 05:07:51 PM PDT 24
Peak memory 200708 kb
Host smart-d1b43b81-514f-4c7e-9195-6b6356490a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498197817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2498197817
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_stress_all.42912298
Short name T231
Test name
Test status
Simulation time 162587076051 ps
CPU time 123.05 seconds
Started Aug 12 05:04:53 PM PDT 24
Finished Aug 12 05:06:56 PM PDT 24
Peak memory 200824 kb
Host smart-ccb0c4dd-a29a-4fb5-a171-9d59b537b818
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42912298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.42912298
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1855723377
Short name T232
Test name
Test status
Simulation time 112546843124 ps
CPU time 43.64 seconds
Started Aug 12 05:03:33 PM PDT 24
Finished Aug 12 05:04:21 PM PDT 24
Peak memory 200628 kb
Host smart-ee876fbf-f7cb-4c30-8ab0-2626af68fde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855723377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1855723377
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2539801314
Short name T216
Test name
Test status
Simulation time 73493053935 ps
CPU time 29.79 seconds
Started Aug 12 05:05:34 PM PDT 24
Finished Aug 12 05:06:04 PM PDT 24
Peak memory 200764 kb
Host smart-50850939-d746-45e1-a19e-48d6fac0f620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539801314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2539801314
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2316670746
Short name T46
Test name
Test status
Simulation time 60130570 ps
CPU time 0.67 seconds
Started Aug 12 05:00:18 PM PDT 24
Finished Aug 12 05:00:19 PM PDT 24
Peak memory 194972 kb
Host smart-cc39c813-9f24-44f3-ba99-2c153acb0199
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316670746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2316670746
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3390890416
Short name T1212
Test name
Test status
Simulation time 188618633 ps
CPU time 1.42 seconds
Started Aug 12 05:00:13 PM PDT 24
Finished Aug 12 05:00:14 PM PDT 24
Peak memory 197888 kb
Host smart-fe665999-b411-46cb-9fd6-b3f6eb96ef7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390890416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3390890416
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1752899547
Short name T1313
Test name
Test status
Simulation time 21078206 ps
CPU time 0.59 seconds
Started Aug 12 05:00:14 PM PDT 24
Finished Aug 12 05:00:15 PM PDT 24
Peak memory 195476 kb
Host smart-2bbfeb5f-a6dc-4df6-aafa-20b0aa388af0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752899547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1752899547
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2570727417
Short name T1194
Test name
Test status
Simulation time 120002518 ps
CPU time 0.84 seconds
Started Aug 12 05:00:18 PM PDT 24
Finished Aug 12 05:00:19 PM PDT 24
Peak memory 199860 kb
Host smart-93f769fe-52a1-46c0-8e01-15656e39f2e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570727417 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2570727417
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.1466081407
Short name T1293
Test name
Test status
Simulation time 50710103 ps
CPU time 0.62 seconds
Started Aug 12 05:00:11 PM PDT 24
Finished Aug 12 05:00:12 PM PDT 24
Peak memory 195448 kb
Host smart-bfc36058-0346-4c9e-ae9c-297037ed8b63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466081407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1466081407
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.4126295927
Short name T1198
Test name
Test status
Simulation time 153282207 ps
CPU time 0.56 seconds
Started Aug 12 05:00:18 PM PDT 24
Finished Aug 12 05:00:19 PM PDT 24
Peak memory 194512 kb
Host smart-e551041d-f943-43f1-bd40-7477fab9458a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126295927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.4126295927
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.96513277
Short name T1312
Test name
Test status
Simulation time 12714599 ps
CPU time 0.67 seconds
Started Aug 12 05:00:20 PM PDT 24
Finished Aug 12 05:00:20 PM PDT 24
Peak memory 194408 kb
Host smart-ce27dc93-f309-46b5-ba9b-c77d1baf0ef6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96513277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_o
utstanding.96513277
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3659829823
Short name T1267
Test name
Test status
Simulation time 445081217 ps
CPU time 2.26 seconds
Started Aug 12 05:00:11 PM PDT 24
Finished Aug 12 05:00:13 PM PDT 24
Peak memory 200072 kb
Host smart-85645e93-5944-4cab-a5bc-f4fea825714e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659829823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3659829823
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2973898170
Short name T1229
Test name
Test status
Simulation time 70934361 ps
CPU time 0.92 seconds
Started Aug 12 05:00:18 PM PDT 24
Finished Aug 12 05:00:19 PM PDT 24
Peak memory 199024 kb
Host smart-dc7ec6fc-a6e4-42a7-a872-8b6f6c3b91b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973898170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2973898170
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.306947592
Short name T1223
Test name
Test status
Simulation time 891274230 ps
CPU time 2.22 seconds
Started Aug 12 05:00:20 PM PDT 24
Finished Aug 12 05:00:22 PM PDT 24
Peak memory 198012 kb
Host smart-d5a05b46-39f0-443e-967f-d91ff330c77e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306947592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.306947592
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3735842675
Short name T1275
Test name
Test status
Simulation time 19021794 ps
CPU time 0.62 seconds
Started Aug 12 05:00:18 PM PDT 24
Finished Aug 12 05:00:19 PM PDT 24
Peak memory 195372 kb
Host smart-1baa7bbb-cdb4-484a-8e93-977baa064b27
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735842675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3735842675
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1581342987
Short name T1249
Test name
Test status
Simulation time 59920532 ps
CPU time 0.85 seconds
Started Aug 12 05:00:19 PM PDT 24
Finished Aug 12 05:00:20 PM PDT 24
Peak memory 199856 kb
Host smart-7eb0cda0-837f-418a-b014-d8492cbc7b9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581342987 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1581342987
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3150606010
Short name T1318
Test name
Test status
Simulation time 13857591 ps
CPU time 0.59 seconds
Started Aug 12 05:00:20 PM PDT 24
Finished Aug 12 05:00:21 PM PDT 24
Peak memory 194416 kb
Host smart-bab67f62-0f34-42ac-8401-7bdcb396f30e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150606010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3150606010
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2698284955
Short name T1283
Test name
Test status
Simulation time 14495169 ps
CPU time 0.69 seconds
Started Aug 12 05:00:19 PM PDT 24
Finished Aug 12 05:00:20 PM PDT 24
Peak memory 196060 kb
Host smart-6379922c-bb13-4e05-8e45-2a75765d9c40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698284955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2698284955
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1716217943
Short name T1316
Test name
Test status
Simulation time 74488969 ps
CPU time 1.01 seconds
Started Aug 12 05:00:28 PM PDT 24
Finished Aug 12 05:00:29 PM PDT 24
Peak memory 199900 kb
Host smart-34e658bb-49a9-41b5-9b50-b30a5a25f622
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716217943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1716217943
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.4145804916
Short name T1311
Test name
Test status
Simulation time 341782514 ps
CPU time 1.35 seconds
Started Aug 12 05:00:20 PM PDT 24
Finished Aug 12 05:00:22 PM PDT 24
Peak memory 199388 kb
Host smart-d78b36a6-8163-47e8-94cd-ff02d1b8e3cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145804916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.4145804916
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3185636249
Short name T1301
Test name
Test status
Simulation time 70006034 ps
CPU time 0.67 seconds
Started Aug 12 05:00:26 PM PDT 24
Finished Aug 12 05:00:27 PM PDT 24
Peak memory 197888 kb
Host smart-108dc06f-b8b3-4d69-978a-ecf7d6c83e49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185636249 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3185636249
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3760952937
Short name T51
Test name
Test status
Simulation time 18397049 ps
CPU time 0.62 seconds
Started Aug 12 05:00:26 PM PDT 24
Finished Aug 12 05:00:27 PM PDT 24
Peak memory 195504 kb
Host smart-504211d5-3781-46e3-915e-91c4427ad881
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760952937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3760952937
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2761074513
Short name T1270
Test name
Test status
Simulation time 28809329 ps
CPU time 0.57 seconds
Started Aug 12 05:00:26 PM PDT 24
Finished Aug 12 05:00:26 PM PDT 24
Peak memory 194464 kb
Host smart-b91dbdc8-bc79-49d8-81d3-14c9e669d30f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761074513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2761074513
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.21515343
Short name T1272
Test name
Test status
Simulation time 34718046 ps
CPU time 0.81 seconds
Started Aug 12 05:00:28 PM PDT 24
Finished Aug 12 05:00:29 PM PDT 24
Peak memory 197184 kb
Host smart-606a9630-69f5-46b9-832a-5423e3fda240
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21515343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr_
outstanding.21515343
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3041972751
Short name T1206
Test name
Test status
Simulation time 76001755 ps
CPU time 1.13 seconds
Started Aug 12 05:00:25 PM PDT 24
Finished Aug 12 05:00:26 PM PDT 24
Peak memory 199824 kb
Host smart-6de6b50f-bdfd-433e-9092-f6801503d9f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041972751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3041972751
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2763587018
Short name T1308
Test name
Test status
Simulation time 24082584 ps
CPU time 0.76 seconds
Started Aug 12 05:00:34 PM PDT 24
Finished Aug 12 05:00:35 PM PDT 24
Peak memory 199316 kb
Host smart-091d0224-9a82-408d-bc10-416c41a758ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763587018 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2763587018
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.1605708617
Short name T48
Test name
Test status
Simulation time 43454725 ps
CPU time 0.62 seconds
Started Aug 12 05:00:35 PM PDT 24
Finished Aug 12 05:00:36 PM PDT 24
Peak memory 195544 kb
Host smart-65c0d9c1-cc32-413e-b7f3-e2cf9c6e65b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605708617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1605708617
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1163202982
Short name T1248
Test name
Test status
Simulation time 39124488 ps
CPU time 0.59 seconds
Started Aug 12 05:00:37 PM PDT 24
Finished Aug 12 05:00:38 PM PDT 24
Peak memory 194464 kb
Host smart-094cbf30-d0f8-489d-9319-a24e7a6b5ba8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163202982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1163202982
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1217927532
Short name T58
Test name
Test status
Simulation time 26389237 ps
CPU time 0.68 seconds
Started Aug 12 05:00:36 PM PDT 24
Finished Aug 12 05:00:37 PM PDT 24
Peak memory 196512 kb
Host smart-b36f9b1f-022c-4629-86f4-a0587d15aa16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217927532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1217927532
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.4010896342
Short name T1303
Test name
Test status
Simulation time 63962877 ps
CPU time 1.79 seconds
Started Aug 12 05:00:25 PM PDT 24
Finished Aug 12 05:00:27 PM PDT 24
Peak memory 199976 kb
Host smart-388c403d-ec68-4018-9fa3-05f5b9625bd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010896342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.4010896342
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3104625533
Short name T78
Test name
Test status
Simulation time 339305323 ps
CPU time 1.23 seconds
Started Aug 12 05:00:23 PM PDT 24
Finished Aug 12 05:00:25 PM PDT 24
Peak memory 199416 kb
Host smart-1d698097-f8d5-447b-bd7f-412a4fb8f8a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104625533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3104625533
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1885708933
Short name T1260
Test name
Test status
Simulation time 19900054 ps
CPU time 0.74 seconds
Started Aug 12 05:00:35 PM PDT 24
Finished Aug 12 05:00:36 PM PDT 24
Peak memory 198812 kb
Host smart-0338ee2c-2969-483f-a6f4-fcc352112de8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885708933 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1885708933
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2810437580
Short name T60
Test name
Test status
Simulation time 16925449 ps
CPU time 0.65 seconds
Started Aug 12 05:00:38 PM PDT 24
Finished Aug 12 05:00:39 PM PDT 24
Peak memory 195592 kb
Host smart-b05ee729-0297-4e63-a212-84c5db40d764
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810437580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2810437580
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1290943207
Short name T1287
Test name
Test status
Simulation time 26046158 ps
CPU time 0.59 seconds
Started Aug 12 05:00:35 PM PDT 24
Finished Aug 12 05:00:36 PM PDT 24
Peak memory 194412 kb
Host smart-62361d46-cb83-4ddb-8d73-eec6094c6980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290943207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1290943207
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3437858315
Short name T61
Test name
Test status
Simulation time 141570259 ps
CPU time 0.67 seconds
Started Aug 12 05:00:34 PM PDT 24
Finished Aug 12 05:00:35 PM PDT 24
Peak memory 195572 kb
Host smart-16762534-2b28-4875-8d92-594531794380
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437858315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3437858315
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1974677108
Short name T1202
Test name
Test status
Simulation time 172666504 ps
CPU time 1.63 seconds
Started Aug 12 05:00:34 PM PDT 24
Finished Aug 12 05:00:36 PM PDT 24
Peak memory 200044 kb
Host smart-53ef24e1-a492-4616-b13c-ee3e8907f43e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974677108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1974677108
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3323420069
Short name T1288
Test name
Test status
Simulation time 45778468 ps
CPU time 1.15 seconds
Started Aug 12 05:00:38 PM PDT 24
Finished Aug 12 05:00:40 PM PDT 24
Peak memory 200188 kb
Host smart-47bf23d0-704f-4bf4-b541-a2f14168c503
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323420069 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3323420069
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.3014995224
Short name T42
Test name
Test status
Simulation time 25223897 ps
CPU time 0.66 seconds
Started Aug 12 05:00:38 PM PDT 24
Finished Aug 12 05:00:39 PM PDT 24
Peak memory 195504 kb
Host smart-e6f56f26-a02d-471b-8893-d871756465ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014995224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3014995224
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3069931899
Short name T1299
Test name
Test status
Simulation time 42124869 ps
CPU time 0.58 seconds
Started Aug 12 05:00:35 PM PDT 24
Finished Aug 12 05:00:36 PM PDT 24
Peak memory 194432 kb
Host smart-9311e867-5bf3-4411-9ce9-56c4431e8c23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069931899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3069931899
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2217214106
Short name T1216
Test name
Test status
Simulation time 41373258 ps
CPU time 0.67 seconds
Started Aug 12 05:00:37 PM PDT 24
Finished Aug 12 05:00:38 PM PDT 24
Peak memory 196052 kb
Host smart-01703e11-c053-4d2d-a3e9-7a7432d4fa2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217214106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.2217214106
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3714961741
Short name T1210
Test name
Test status
Simulation time 95184989 ps
CPU time 1.89 seconds
Started Aug 12 05:00:38 PM PDT 24
Finished Aug 12 05:00:40 PM PDT 24
Peak memory 199996 kb
Host smart-ed9563fa-8a6b-492e-89a4-3579382e9879
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714961741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3714961741
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2472320274
Short name T1289
Test name
Test status
Simulation time 247325473 ps
CPU time 1.31 seconds
Started Aug 12 05:00:34 PM PDT 24
Finished Aug 12 05:00:36 PM PDT 24
Peak memory 199296 kb
Host smart-5a88f898-4853-4181-9def-1a0c6b7a99e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472320274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2472320274
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.286300129
Short name T1243
Test name
Test status
Simulation time 12818734 ps
CPU time 0.67 seconds
Started Aug 12 05:00:36 PM PDT 24
Finished Aug 12 05:00:37 PM PDT 24
Peak memory 197460 kb
Host smart-8c05407c-dbd2-425b-9850-29c65e0c4808
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286300129 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.286300129
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1360448765
Short name T1207
Test name
Test status
Simulation time 71207752 ps
CPU time 0.62 seconds
Started Aug 12 05:00:35 PM PDT 24
Finished Aug 12 05:00:36 PM PDT 24
Peak memory 195456 kb
Host smart-689225e8-b510-48af-bc9c-08310c810778
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360448765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1360448765
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.2766793616
Short name T1246
Test name
Test status
Simulation time 33459273 ps
CPU time 0.56 seconds
Started Aug 12 05:00:34 PM PDT 24
Finished Aug 12 05:00:35 PM PDT 24
Peak memory 194456 kb
Host smart-7edbdc04-addd-45cc-a949-7659adb5d315
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766793616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2766793616
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3351978024
Short name T59
Test name
Test status
Simulation time 17155638 ps
CPU time 0.77 seconds
Started Aug 12 05:00:38 PM PDT 24
Finished Aug 12 05:00:38 PM PDT 24
Peak memory 197064 kb
Host smart-72689704-c400-4a3b-b9b3-d9df499eabd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351978024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.3351978024
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1168298829
Short name T1244
Test name
Test status
Simulation time 30735099 ps
CPU time 1.77 seconds
Started Aug 12 05:00:39 PM PDT 24
Finished Aug 12 05:00:41 PM PDT 24
Peak memory 200084 kb
Host smart-230e06ae-3363-49c1-a2e6-23a3898566d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168298829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1168298829
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3044350353
Short name T73
Test name
Test status
Simulation time 50792280 ps
CPU time 0.95 seconds
Started Aug 12 05:00:34 PM PDT 24
Finished Aug 12 05:00:35 PM PDT 24
Peak memory 198988 kb
Host smart-fcfe0147-1e04-4baf-8ffe-d73f5adfc4b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044350353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3044350353
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3095331722
Short name T1197
Test name
Test status
Simulation time 27173864 ps
CPU time 0.87 seconds
Started Aug 12 05:00:37 PM PDT 24
Finished Aug 12 05:00:38 PM PDT 24
Peak memory 199860 kb
Host smart-c52924f2-c663-46a7-962d-f80668f0eb30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095331722 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3095331722
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.522436242
Short name T1258
Test name
Test status
Simulation time 19571257 ps
CPU time 0.68 seconds
Started Aug 12 05:00:34 PM PDT 24
Finished Aug 12 05:00:34 PM PDT 24
Peak memory 195392 kb
Host smart-dccf7a8a-59f7-4a8d-9ea0-f5968172e28d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522436242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.522436242
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.1008952581
Short name T1256
Test name
Test status
Simulation time 14297290 ps
CPU time 0.58 seconds
Started Aug 12 05:00:44 PM PDT 24
Finished Aug 12 05:00:44 PM PDT 24
Peak memory 194300 kb
Host smart-98add83e-3c6d-44cc-9647-ca1b09229fd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008952581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.1008952581
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1230408056
Short name T1300
Test name
Test status
Simulation time 56168302 ps
CPU time 0.64 seconds
Started Aug 12 05:00:37 PM PDT 24
Finished Aug 12 05:00:38 PM PDT 24
Peak memory 194540 kb
Host smart-319c3329-9ebf-4236-bf7f-57bd9fb76a66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230408056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1230408056
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3017330562
Short name T1224
Test name
Test status
Simulation time 459767158 ps
CPU time 2.15 seconds
Started Aug 12 05:00:37 PM PDT 24
Finished Aug 12 05:00:39 PM PDT 24
Peak memory 200064 kb
Host smart-59aad9d8-06e4-4478-8f97-2f876d967a29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017330562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3017330562
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.4104732472
Short name T236
Test name
Test status
Simulation time 295304041 ps
CPU time 1.41 seconds
Started Aug 12 05:00:37 PM PDT 24
Finished Aug 12 05:00:39 PM PDT 24
Peak memory 199608 kb
Host smart-57dee2a5-bb8b-4fa5-8517-f639db8c4cb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104732472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.4104732472
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1663830016
Short name T1251
Test name
Test status
Simulation time 19022563 ps
CPU time 0.7 seconds
Started Aug 12 05:00:34 PM PDT 24
Finished Aug 12 05:00:35 PM PDT 24
Peak memory 198152 kb
Host smart-e0b55ca8-9a3c-48df-ab1f-af9ae2fe6e87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663830016 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1663830016
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1856234019
Short name T53
Test name
Test status
Simulation time 17715850 ps
CPU time 0.65 seconds
Started Aug 12 05:00:37 PM PDT 24
Finished Aug 12 05:00:38 PM PDT 24
Peak memory 195484 kb
Host smart-da5a5f31-150d-4958-ae8b-d78a04af88c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856234019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1856234019
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2517283062
Short name T1314
Test name
Test status
Simulation time 42038567 ps
CPU time 0.61 seconds
Started Aug 12 05:00:36 PM PDT 24
Finished Aug 12 05:00:36 PM PDT 24
Peak memory 194440 kb
Host smart-cf25dc34-427a-42f3-ab5a-9bc399b20183
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517283062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2517283062
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1126273363
Short name T1254
Test name
Test status
Simulation time 18627569 ps
CPU time 0.77 seconds
Started Aug 12 05:00:38 PM PDT 24
Finished Aug 12 05:00:39 PM PDT 24
Peak memory 197008 kb
Host smart-66c2eae0-7312-4071-aab0-32575a1a4879
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126273363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1126273363
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1209289153
Short name T1265
Test name
Test status
Simulation time 215913007 ps
CPU time 2.02 seconds
Started Aug 12 05:00:36 PM PDT 24
Finished Aug 12 05:00:38 PM PDT 24
Peak memory 200064 kb
Host smart-52226b0e-6c2f-429e-a26b-a4b874eb3f6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209289153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1209289153
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.642986310
Short name T1281
Test name
Test status
Simulation time 170766442 ps
CPU time 0.99 seconds
Started Aug 12 05:00:37 PM PDT 24
Finished Aug 12 05:00:38 PM PDT 24
Peak memory 199036 kb
Host smart-674a7f40-253b-4b62-8e21-0227dc74e374
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642986310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.642986310
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3948413051
Short name T1297
Test name
Test status
Simulation time 186775598 ps
CPU time 1.42 seconds
Started Aug 12 05:00:35 PM PDT 24
Finished Aug 12 05:00:37 PM PDT 24
Peak memory 200116 kb
Host smart-3ede4333-3692-49d9-b621-d6c38f135031
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948413051 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3948413051
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.4048103880
Short name T1215
Test name
Test status
Simulation time 53388358 ps
CPU time 0.57 seconds
Started Aug 12 05:00:36 PM PDT 24
Finished Aug 12 05:00:37 PM PDT 24
Peak memory 195472 kb
Host smart-65a692c1-b013-4e37-84a7-5872e631ec50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048103880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.4048103880
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.1175950278
Short name T1306
Test name
Test status
Simulation time 24433835 ps
CPU time 0.6 seconds
Started Aug 12 05:00:36 PM PDT 24
Finished Aug 12 05:00:37 PM PDT 24
Peak memory 194548 kb
Host smart-c2cef064-65f4-4a29-9c11-b12a261406ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175950278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.1175950278
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1182134978
Short name T1279
Test name
Test status
Simulation time 30904877 ps
CPU time 0.77 seconds
Started Aug 12 05:00:37 PM PDT 24
Finished Aug 12 05:00:38 PM PDT 24
Peak memory 197136 kb
Host smart-83e437af-fe3f-43cc-a9b0-0f9ca3d7a859
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182134978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.1182134978
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.650203282
Short name T1201
Test name
Test status
Simulation time 206377757 ps
CPU time 2.14 seconds
Started Aug 12 05:00:36 PM PDT 24
Finished Aug 12 05:00:39 PM PDT 24
Peak memory 198888 kb
Host smart-d413b568-4fee-4875-822f-3900669daa14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650203282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.650203282
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.510922767
Short name T1319
Test name
Test status
Simulation time 39649982 ps
CPU time 0.91 seconds
Started Aug 12 05:00:36 PM PDT 24
Finished Aug 12 05:00:37 PM PDT 24
Peak memory 198856 kb
Host smart-e9749b09-62ef-4f97-b4e3-bdfeeac1dac5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510922767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.510922767
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.4276923219
Short name T1290
Test name
Test status
Simulation time 30528519 ps
CPU time 1.48 seconds
Started Aug 12 05:00:35 PM PDT 24
Finished Aug 12 05:00:36 PM PDT 24
Peak memory 199940 kb
Host smart-5aa6e2c2-fff7-4971-a942-effe75305f69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276923219 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.4276923219
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.225462203
Short name T54
Test name
Test status
Simulation time 18426121 ps
CPU time 0.62 seconds
Started Aug 12 05:00:38 PM PDT 24
Finished Aug 12 05:00:39 PM PDT 24
Peak memory 195420 kb
Host smart-475589d2-c48c-4c29-b7bc-dc528962e267
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225462203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.225462203
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.986027978
Short name T1193
Test name
Test status
Simulation time 11277297 ps
CPU time 0.57 seconds
Started Aug 12 05:00:37 PM PDT 24
Finished Aug 12 05:00:38 PM PDT 24
Peak memory 194420 kb
Host smart-beb8a437-6bdc-4ed8-a224-2b99fb52a182
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986027978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.986027978
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.99158413
Short name T64
Test name
Test status
Simulation time 150736246 ps
CPU time 0.66 seconds
Started Aug 12 05:00:36 PM PDT 24
Finished Aug 12 05:00:37 PM PDT 24
Peak memory 195592 kb
Host smart-2c281c30-5fe9-45ab-a9b6-123c68dee174
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99158413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr_
outstanding.99158413
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.1459474419
Short name T1195
Test name
Test status
Simulation time 199806853 ps
CPU time 2.02 seconds
Started Aug 12 05:00:36 PM PDT 24
Finished Aug 12 05:00:39 PM PDT 24
Peak memory 199108 kb
Host smart-39b4f239-4ba5-4e75-938a-8e19be5fcae7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459474419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1459474419
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3256333179
Short name T235
Test name
Test status
Simulation time 149573744 ps
CPU time 0.96 seconds
Started Aug 12 05:00:35 PM PDT 24
Finished Aug 12 05:00:36 PM PDT 24
Peak memory 199324 kb
Host smart-d915242b-8d37-4d3c-9066-f82da28e8e9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256333179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3256333179
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.157912534
Short name T1219
Test name
Test status
Simulation time 54869624 ps
CPU time 0.84 seconds
Started Aug 12 05:00:51 PM PDT 24
Finished Aug 12 05:00:52 PM PDT 24
Peak memory 199740 kb
Host smart-433c8aaf-885c-4d53-ac98-458bc8202486
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157912534 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.157912534
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.3496741168
Short name T1242
Test name
Test status
Simulation time 13788341 ps
CPU time 0.58 seconds
Started Aug 12 05:00:54 PM PDT 24
Finished Aug 12 05:00:55 PM PDT 24
Peak memory 195416 kb
Host smart-3e30fdfc-0ccf-4bf8-93ed-55e80edc5b89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496741168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3496741168
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3953121171
Short name T1226
Test name
Test status
Simulation time 77655876 ps
CPU time 0.59 seconds
Started Aug 12 05:00:48 PM PDT 24
Finished Aug 12 05:00:48 PM PDT 24
Peak memory 194520 kb
Host smart-7be47e65-7dbc-4ce2-924d-1650297d1b4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953121171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3953121171
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.4143420068
Short name T1239
Test name
Test status
Simulation time 108892205 ps
CPU time 0.75 seconds
Started Aug 12 05:00:48 PM PDT 24
Finished Aug 12 05:00:49 PM PDT 24
Peak memory 196644 kb
Host smart-570861a2-c4a0-4582-85a2-0845094720e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143420068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.4143420068
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3536842994
Short name T1228
Test name
Test status
Simulation time 150366420 ps
CPU time 1.44 seconds
Started Aug 12 05:00:49 PM PDT 24
Finished Aug 12 05:00:51 PM PDT 24
Peak memory 200052 kb
Host smart-abd6a3e8-82cc-4415-a92a-930601090703
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536842994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3536842994
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.335674303
Short name T72
Test name
Test status
Simulation time 1293002469 ps
CPU time 1.38 seconds
Started Aug 12 05:00:47 PM PDT 24
Finished Aug 12 05:00:48 PM PDT 24
Peak memory 199604 kb
Host smart-8d51269c-9f69-4d34-89c1-cf4591c1509d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335674303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.335674303
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1501637074
Short name T55
Test name
Test status
Simulation time 74945300 ps
CPU time 0.65 seconds
Started Aug 12 05:00:19 PM PDT 24
Finished Aug 12 05:00:20 PM PDT 24
Peak memory 195484 kb
Host smart-1cbd70ca-bc4d-4b1f-84f2-acc8a7d010ec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501637074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1501637074
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3678866243
Short name T49
Test name
Test status
Simulation time 60579513 ps
CPU time 2.18 seconds
Started Aug 12 05:00:17 PM PDT 24
Finished Aug 12 05:00:19 PM PDT 24
Peak memory 197136 kb
Host smart-a8f2055d-6c73-4752-a62c-8687c5607514
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678866243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3678866243
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.386568801
Short name T47
Test name
Test status
Simulation time 44075452 ps
CPU time 0.59 seconds
Started Aug 12 05:00:19 PM PDT 24
Finished Aug 12 05:00:20 PM PDT 24
Peak memory 195444 kb
Host smart-7a84493c-fce6-4f3e-96c8-36c592579228
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386568801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.386568801
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1324328772
Short name T1276
Test name
Test status
Simulation time 28804853 ps
CPU time 0.74 seconds
Started Aug 12 05:00:19 PM PDT 24
Finished Aug 12 05:00:20 PM PDT 24
Peak memory 198096 kb
Host smart-291e9a73-4905-4e1f-aa59-0ec27a2c4a9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324328772 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1324328772
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.3821168766
Short name T1266
Test name
Test status
Simulation time 17060535 ps
CPU time 0.6 seconds
Started Aug 12 05:00:29 PM PDT 24
Finished Aug 12 05:00:30 PM PDT 24
Peak memory 195576 kb
Host smart-bb8855e6-7a97-4d2d-b881-37e98850ae2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821168766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3821168766
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3116644307
Short name T1253
Test name
Test status
Simulation time 12537137 ps
CPU time 0.59 seconds
Started Aug 12 05:00:19 PM PDT 24
Finished Aug 12 05:00:20 PM PDT 24
Peak memory 194484 kb
Host smart-c3819212-913b-4bee-985f-37fec651716f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116644307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3116644307
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2316671720
Short name T56
Test name
Test status
Simulation time 48338607 ps
CPU time 0.67 seconds
Started Aug 12 05:00:20 PM PDT 24
Finished Aug 12 05:00:21 PM PDT 24
Peak memory 195476 kb
Host smart-14ff193b-5581-44ae-8147-f4347840c295
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316671720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2316671720
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.1817577697
Short name T1218
Test name
Test status
Simulation time 156087921 ps
CPU time 1.87 seconds
Started Aug 12 05:00:29 PM PDT 24
Finished Aug 12 05:00:31 PM PDT 24
Peak memory 200120 kb
Host smart-94db00c8-9fa2-400e-a94f-3a50f7588448
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817577697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.1817577697
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1879056627
Short name T76
Test name
Test status
Simulation time 175390771 ps
CPU time 1.34 seconds
Started Aug 12 05:00:17 PM PDT 24
Finished Aug 12 05:00:18 PM PDT 24
Peak memory 199408 kb
Host smart-b622eb66-06a0-41a5-b329-3e22e430d9be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879056627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1879056627
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.1689444022
Short name T1240
Test name
Test status
Simulation time 13436694 ps
CPU time 0.6 seconds
Started Aug 12 05:00:50 PM PDT 24
Finished Aug 12 05:00:51 PM PDT 24
Peak memory 194472 kb
Host smart-f00200d0-0f00-4599-adaf-b08c46729361
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689444022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1689444022
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.4224919964
Short name T1189
Test name
Test status
Simulation time 31471585 ps
CPU time 0.58 seconds
Started Aug 12 05:00:52 PM PDT 24
Finished Aug 12 05:00:53 PM PDT 24
Peak memory 194536 kb
Host smart-2decff04-6266-4580-ae8b-daa9b8a5ddd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224919964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.4224919964
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.3310265548
Short name T1196
Test name
Test status
Simulation time 15196066 ps
CPU time 0.57 seconds
Started Aug 12 05:00:48 PM PDT 24
Finished Aug 12 05:00:49 PM PDT 24
Peak memory 194492 kb
Host smart-41cc6184-3f07-4076-a1d0-0b251bad8336
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310265548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.3310265548
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.4083405516
Short name T1241
Test name
Test status
Simulation time 17023693 ps
CPU time 0.57 seconds
Started Aug 12 05:00:49 PM PDT 24
Finished Aug 12 05:00:49 PM PDT 24
Peak memory 194524 kb
Host smart-6b1e49aa-b6a8-463b-a7f6-27693cd30f79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083405516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.4083405516
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1390333648
Short name T1274
Test name
Test status
Simulation time 23157336 ps
CPU time 0.6 seconds
Started Aug 12 05:00:51 PM PDT 24
Finished Aug 12 05:00:52 PM PDT 24
Peak memory 194752 kb
Host smart-f4b52212-80ce-4535-a2d1-07fec2c69b00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390333648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1390333648
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.246613877
Short name T1307
Test name
Test status
Simulation time 17515527 ps
CPU time 0.6 seconds
Started Aug 12 05:00:49 PM PDT 24
Finished Aug 12 05:00:49 PM PDT 24
Peak memory 194480 kb
Host smart-ccdd17e8-26e2-4aa7-8852-9b3e79675c36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246613877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.246613877
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1327217705
Short name T1236
Test name
Test status
Simulation time 20547506 ps
CPU time 0.57 seconds
Started Aug 12 05:00:50 PM PDT 24
Finished Aug 12 05:00:51 PM PDT 24
Peak memory 194548 kb
Host smart-2511e127-ca83-4072-9f62-8c283a4e40f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327217705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1327217705
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.509818504
Short name T1284
Test name
Test status
Simulation time 18606684 ps
CPU time 0.57 seconds
Started Aug 12 05:00:45 PM PDT 24
Finished Aug 12 05:00:46 PM PDT 24
Peak memory 194512 kb
Host smart-a7e05ab6-89a0-4a67-a5ab-a6ea395b83f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509818504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.509818504
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.1414958454
Short name T1292
Test name
Test status
Simulation time 16288221 ps
CPU time 0.57 seconds
Started Aug 12 05:00:46 PM PDT 24
Finished Aug 12 05:00:46 PM PDT 24
Peak memory 194424 kb
Host smart-fb0c60de-14f3-4f3c-9ba8-c5e05492297e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414958454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1414958454
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2566729520
Short name T1247
Test name
Test status
Simulation time 41048383 ps
CPU time 0.58 seconds
Started Aug 12 05:00:49 PM PDT 24
Finished Aug 12 05:00:49 PM PDT 24
Peak memory 194544 kb
Host smart-bfef4c61-7371-4463-92f7-bb85f97feb75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566729520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2566729520
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3036437924
Short name T44
Test name
Test status
Simulation time 44541126 ps
CPU time 0.66 seconds
Started Aug 12 05:00:28 PM PDT 24
Finished Aug 12 05:00:29 PM PDT 24
Peak memory 195472 kb
Host smart-1cb5064e-1a1b-468b-87ea-39d9c6781ed5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036437924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3036437924
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1208461508
Short name T43
Test name
Test status
Simulation time 58258749 ps
CPU time 2.17 seconds
Started Aug 12 05:00:34 PM PDT 24
Finished Aug 12 05:00:36 PM PDT 24
Peak memory 198056 kb
Host smart-0def1e94-0eaa-4524-9215-08d0fdb03827
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208461508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1208461508
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.4215021859
Short name T52
Test name
Test status
Simulation time 14462466 ps
CPU time 0.59 seconds
Started Aug 12 05:00:19 PM PDT 24
Finished Aug 12 05:00:19 PM PDT 24
Peak memory 195500 kb
Host smart-6dcc89fe-0761-4a03-a349-b47890bb6773
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215021859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.4215021859
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2505781958
Short name T1205
Test name
Test status
Simulation time 212527135 ps
CPU time 0.82 seconds
Started Aug 12 05:00:29 PM PDT 24
Finished Aug 12 05:00:30 PM PDT 24
Peak memory 198748 kb
Host smart-cf1d1df8-78d7-4bf0-8787-4d1dca7f547e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505781958 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2505781958
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3361489983
Short name T1261
Test name
Test status
Simulation time 16094930 ps
CPU time 0.6 seconds
Started Aug 12 05:00:27 PM PDT 24
Finished Aug 12 05:00:28 PM PDT 24
Peak memory 195528 kb
Host smart-8edfc057-b30e-414f-9d7f-a69dc03be65d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361489983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3361489983
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.207004610
Short name T1250
Test name
Test status
Simulation time 10622898 ps
CPU time 0.57 seconds
Started Aug 12 05:00:29 PM PDT 24
Finished Aug 12 05:00:29 PM PDT 24
Peak memory 194520 kb
Host smart-b2b0d377-daef-4c0e-b8ea-c67d605559bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207004610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.207004610
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2018172073
Short name T57
Test name
Test status
Simulation time 175429144 ps
CPU time 0.78 seconds
Started Aug 12 05:00:29 PM PDT 24
Finished Aug 12 05:00:29 PM PDT 24
Peak memory 197584 kb
Host smart-3b3e34ff-3474-4f55-bd5f-7a0229c1afb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018172073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2018172073
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2872890873
Short name T1285
Test name
Test status
Simulation time 466305897 ps
CPU time 1.63 seconds
Started Aug 12 05:00:19 PM PDT 24
Finished Aug 12 05:00:20 PM PDT 24
Peak memory 200192 kb
Host smart-61a241a6-4a08-4242-8ed1-c3e2ab70d236
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872890873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2872890873
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3943980477
Short name T1269
Test name
Test status
Simulation time 171495958 ps
CPU time 1.33 seconds
Started Aug 12 05:00:29 PM PDT 24
Finished Aug 12 05:00:31 PM PDT 24
Peak memory 199316 kb
Host smart-3dfca730-fe20-40e6-85c5-4d9d4d166051
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943980477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3943980477
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1930011893
Short name T1263
Test name
Test status
Simulation time 14304035 ps
CPU time 0.59 seconds
Started Aug 12 05:00:49 PM PDT 24
Finished Aug 12 05:00:50 PM PDT 24
Peak memory 194388 kb
Host smart-e6c36479-7156-4824-bcf5-20b1740e0c31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930011893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1930011893
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3284841581
Short name T1273
Test name
Test status
Simulation time 16568679 ps
CPU time 0.59 seconds
Started Aug 12 05:00:49 PM PDT 24
Finished Aug 12 05:00:50 PM PDT 24
Peak memory 194412 kb
Host smart-89349eac-a9da-4c25-9b04-7236d3510720
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284841581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3284841581
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2898214613
Short name T1310
Test name
Test status
Simulation time 23957607 ps
CPU time 0.64 seconds
Started Aug 12 05:00:53 PM PDT 24
Finished Aug 12 05:00:54 PM PDT 24
Peak memory 194468 kb
Host smart-468a2c52-9c95-41fc-96f9-21c471422f81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898214613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2898214613
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.905675577
Short name T1296
Test name
Test status
Simulation time 49711265 ps
CPU time 0.59 seconds
Started Aug 12 05:00:46 PM PDT 24
Finished Aug 12 05:00:47 PM PDT 24
Peak memory 194488 kb
Host smart-8fb80ae5-6a2e-4ae5-8016-6eea02a246b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905675577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.905675577
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.3203458630
Short name T1232
Test name
Test status
Simulation time 52300949 ps
CPU time 0.6 seconds
Started Aug 12 05:00:50 PM PDT 24
Finished Aug 12 05:00:51 PM PDT 24
Peak memory 194540 kb
Host smart-8d1c9c95-1ca9-45a0-b66d-4772f400e80d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203458630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3203458630
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3910862204
Short name T1234
Test name
Test status
Simulation time 14791310 ps
CPU time 0.57 seconds
Started Aug 12 05:00:50 PM PDT 24
Finished Aug 12 05:00:51 PM PDT 24
Peak memory 194540 kb
Host smart-97bee4a8-3142-4393-9bf7-3c035071f53b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910862204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3910862204
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2953765811
Short name T1213
Test name
Test status
Simulation time 16063738 ps
CPU time 0.57 seconds
Started Aug 12 05:00:47 PM PDT 24
Finished Aug 12 05:00:48 PM PDT 24
Peak memory 194544 kb
Host smart-cb10e3d9-0dc6-49d0-b69c-37639ed4d9c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953765811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2953765811
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1240485530
Short name T1235
Test name
Test status
Simulation time 13952000 ps
CPU time 0.57 seconds
Started Aug 12 05:00:51 PM PDT 24
Finished Aug 12 05:00:51 PM PDT 24
Peak memory 194480 kb
Host smart-5d7d1f75-637c-4873-9837-afbc4cb7765e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240485530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1240485530
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.4191783831
Short name T1211
Test name
Test status
Simulation time 46908021 ps
CPU time 0.59 seconds
Started Aug 12 05:00:47 PM PDT 24
Finished Aug 12 05:00:47 PM PDT 24
Peak memory 194520 kb
Host smart-44297b10-5ed7-4922-aa2d-86f278709baf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191783831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.4191783831
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.8505882
Short name T1264
Test name
Test status
Simulation time 16251879 ps
CPU time 0.6 seconds
Started Aug 12 05:00:49 PM PDT 24
Finished Aug 12 05:00:49 PM PDT 24
Peak memory 194504 kb
Host smart-5444c561-866b-401b-9373-a9f38a8a4ee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8505882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.8505882
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.529514604
Short name T45
Test name
Test status
Simulation time 66442206 ps
CPU time 0.69 seconds
Started Aug 12 05:00:24 PM PDT 24
Finished Aug 12 05:00:25 PM PDT 24
Peak memory 195088 kb
Host smart-b6e01864-ef0a-470d-b404-cfafd6e091dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529514604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.529514604
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.4287607051
Short name T1278
Test name
Test status
Simulation time 404100078 ps
CPU time 2.2 seconds
Started Aug 12 05:00:25 PM PDT 24
Finished Aug 12 05:00:27 PM PDT 24
Peak memory 197860 kb
Host smart-ddeec4cd-caa9-43c3-b4e1-5eed1a7b458d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287607051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.4287607051
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3886522643
Short name T1252
Test name
Test status
Simulation time 18721474 ps
CPU time 0.62 seconds
Started Aug 12 05:00:20 PM PDT 24
Finished Aug 12 05:00:21 PM PDT 24
Peak memory 195500 kb
Host smart-2e28c3d5-126d-4fb4-b131-2f706f74dc50
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886522643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3886522643
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1808833991
Short name T1255
Test name
Test status
Simulation time 87936688 ps
CPU time 0.87 seconds
Started Aug 12 05:00:25 PM PDT 24
Finished Aug 12 05:00:26 PM PDT 24
Peak memory 198864 kb
Host smart-d4b34bec-89a8-4bc7-bd97-2e9720d6e2da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808833991 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1808833991
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1786800475
Short name T1257
Test name
Test status
Simulation time 22144416 ps
CPU time 0.59 seconds
Started Aug 12 05:00:20 PM PDT 24
Finished Aug 12 05:00:21 PM PDT 24
Peak memory 195500 kb
Host smart-35c823bf-8df0-4abf-b68a-ae74e916fa37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786800475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1786800475
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.732681005
Short name T1225
Test name
Test status
Simulation time 18538675 ps
CPU time 0.54 seconds
Started Aug 12 05:00:28 PM PDT 24
Finished Aug 12 05:00:28 PM PDT 24
Peak memory 194464 kb
Host smart-62f38f81-dc1c-4425-b40d-05d271ddbe79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732681005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.732681005
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3796310278
Short name T1230
Test name
Test status
Simulation time 31671547 ps
CPU time 0.77 seconds
Started Aug 12 05:00:26 PM PDT 24
Finished Aug 12 05:00:27 PM PDT 24
Peak memory 197144 kb
Host smart-a0d7a60e-5439-465f-9616-86db9c68d808
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796310278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.3796310278
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1199093564
Short name T1214
Test name
Test status
Simulation time 123726691 ps
CPU time 1.25 seconds
Started Aug 12 05:00:19 PM PDT 24
Finished Aug 12 05:00:20 PM PDT 24
Peak memory 200100 kb
Host smart-1c6a5aaa-5eba-4935-bfc9-ac40f11d2ebe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199093564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1199093564
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.94507737
Short name T1282
Test name
Test status
Simulation time 19819335 ps
CPU time 0.56 seconds
Started Aug 12 05:00:48 PM PDT 24
Finished Aug 12 05:00:49 PM PDT 24
Peak memory 194472 kb
Host smart-21e2ab0a-9bde-4c5b-8e5b-1dddf8b5f211
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94507737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.94507737
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1935668501
Short name T1291
Test name
Test status
Simulation time 16079075 ps
CPU time 0.58 seconds
Started Aug 12 05:00:53 PM PDT 24
Finished Aug 12 05:00:53 PM PDT 24
Peak memory 194492 kb
Host smart-638b31ca-aed5-4fb5-adda-da60ca1f82ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935668501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1935668501
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.665629562
Short name T1315
Test name
Test status
Simulation time 37413320 ps
CPU time 0.57 seconds
Started Aug 12 05:00:47 PM PDT 24
Finished Aug 12 05:00:48 PM PDT 24
Peak memory 194340 kb
Host smart-fe03fe93-e525-40c9-bfbc-ba070cb3bb28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665629562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.665629562
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3425308802
Short name T1200
Test name
Test status
Simulation time 39312628 ps
CPU time 0.56 seconds
Started Aug 12 05:00:49 PM PDT 24
Finished Aug 12 05:00:50 PM PDT 24
Peak memory 194456 kb
Host smart-7887edb3-2daa-4879-8c15-0d9b4c75647d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425308802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3425308802
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2697653559
Short name T1227
Test name
Test status
Simulation time 16397014 ps
CPU time 0.58 seconds
Started Aug 12 05:00:53 PM PDT 24
Finished Aug 12 05:00:54 PM PDT 24
Peak memory 194456 kb
Host smart-10b1ef20-0523-4c46-8cc2-b788f2e5eef5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697653559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2697653559
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2315289567
Short name T1268
Test name
Test status
Simulation time 24719121 ps
CPU time 0.56 seconds
Started Aug 12 05:00:47 PM PDT 24
Finished Aug 12 05:00:48 PM PDT 24
Peak memory 194544 kb
Host smart-a6a30151-0723-43c9-accc-91d0ddc3ea9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315289567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2315289567
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1255627163
Short name T1317
Test name
Test status
Simulation time 48926970 ps
CPU time 0.57 seconds
Started Aug 12 05:00:49 PM PDT 24
Finished Aug 12 05:00:50 PM PDT 24
Peak memory 194548 kb
Host smart-c1b48308-10ee-40a4-94b8-cde2c3fcedbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255627163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1255627163
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.2507845982
Short name T1191
Test name
Test status
Simulation time 38009803 ps
CPU time 0.59 seconds
Started Aug 12 05:00:48 PM PDT 24
Finished Aug 12 05:00:48 PM PDT 24
Peak memory 194416 kb
Host smart-c028d345-1a8a-44fb-92bb-779fd4b2cebd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507845982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2507845982
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.555493612
Short name T1280
Test name
Test status
Simulation time 48330889 ps
CPU time 0.57 seconds
Started Aug 12 05:00:49 PM PDT 24
Finished Aug 12 05:00:50 PM PDT 24
Peak memory 194484 kb
Host smart-d3fe132d-8f73-4b6c-97f1-f73491b4c05f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555493612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.555493612
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.770856031
Short name T1302
Test name
Test status
Simulation time 40484440 ps
CPU time 0.58 seconds
Started Aug 12 05:00:52 PM PDT 24
Finished Aug 12 05:00:52 PM PDT 24
Peak memory 194552 kb
Host smart-b73cb617-c71b-4993-a172-ceb8b03fd345
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770856031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.770856031
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.975556156
Short name T1204
Test name
Test status
Simulation time 47662874 ps
CPU time 0.8 seconds
Started Aug 12 05:00:29 PM PDT 24
Finished Aug 12 05:00:30 PM PDT 24
Peak memory 199816 kb
Host smart-90973aa1-6e81-4890-bacd-fe80e8b24c18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975556156 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.975556156
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.599108110
Short name T1294
Test name
Test status
Simulation time 101978937 ps
CPU time 0.62 seconds
Started Aug 12 05:00:34 PM PDT 24
Finished Aug 12 05:00:35 PM PDT 24
Peak memory 195496 kb
Host smart-7fb316a0-bc4c-4db2-ba4a-6dbccc203637
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599108110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.599108110
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.1125327077
Short name T1298
Test name
Test status
Simulation time 13860985 ps
CPU time 0.55 seconds
Started Aug 12 05:00:29 PM PDT 24
Finished Aug 12 05:00:30 PM PDT 24
Peak memory 194536 kb
Host smart-034fa19a-0873-442c-9ab1-23c623613f5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125327077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1125327077
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1603612755
Short name T1238
Test name
Test status
Simulation time 82956775 ps
CPU time 0.7 seconds
Started Aug 12 05:00:26 PM PDT 24
Finished Aug 12 05:00:27 PM PDT 24
Peak memory 195924 kb
Host smart-27823c66-2dab-4ba4-82c7-ef7db445eb1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603612755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.1603612755
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3657573796
Short name T1199
Test name
Test status
Simulation time 126179964 ps
CPU time 2.38 seconds
Started Aug 12 05:00:27 PM PDT 24
Finished Aug 12 05:00:30 PM PDT 24
Peak memory 200112 kb
Host smart-2555cc22-cdd9-476a-919e-b84bf40fdc19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657573796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3657573796
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3256260360
Short name T77
Test name
Test status
Simulation time 206595289 ps
CPU time 1.45 seconds
Started Aug 12 05:00:25 PM PDT 24
Finished Aug 12 05:00:27 PM PDT 24
Peak memory 199676 kb
Host smart-8855d3f3-e573-4570-ac16-cbf1aef458d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256260360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3256260360
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2351541491
Short name T1237
Test name
Test status
Simulation time 64883983 ps
CPU time 0.76 seconds
Started Aug 12 05:00:27 PM PDT 24
Finished Aug 12 05:00:28 PM PDT 24
Peak memory 197908 kb
Host smart-95c8edf9-f910-42c8-b60b-4f4fbc58659c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351541491 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2351541491
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1360387682
Short name T1231
Test name
Test status
Simulation time 55393854 ps
CPU time 0.57 seconds
Started Aug 12 05:00:25 PM PDT 24
Finished Aug 12 05:00:26 PM PDT 24
Peak memory 195380 kb
Host smart-fe80e58c-5d2e-40e6-9ff0-2ae984cdbffb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360387682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1360387682
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1565582081
Short name T1271
Test name
Test status
Simulation time 46096230 ps
CPU time 0.61 seconds
Started Aug 12 05:00:27 PM PDT 24
Finished Aug 12 05:00:28 PM PDT 24
Peak memory 194416 kb
Host smart-75544359-ca04-4353-9c4b-d8a5dd6c3914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565582081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1565582081
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3452102497
Short name T62
Test name
Test status
Simulation time 55097583 ps
CPU time 0.68 seconds
Started Aug 12 05:00:25 PM PDT 24
Finished Aug 12 05:00:26 PM PDT 24
Peak memory 195804 kb
Host smart-8c40392e-f294-4cf1-ab45-df354e25d2be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452102497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.3452102497
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1524682446
Short name T1233
Test name
Test status
Simulation time 44912558 ps
CPU time 2.33 seconds
Started Aug 12 05:00:27 PM PDT 24
Finished Aug 12 05:00:29 PM PDT 24
Peak memory 200064 kb
Host smart-d2e0e32a-f3dc-42d3-addf-716917caf996
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524682446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1524682446
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.133065354
Short name T1286
Test name
Test status
Simulation time 75139871 ps
CPU time 1.18 seconds
Started Aug 12 05:00:27 PM PDT 24
Finished Aug 12 05:00:29 PM PDT 24
Peak memory 199328 kb
Host smart-fd1d049b-f6d2-406e-8ad2-658b24413db0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133065354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.133065354
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2633606708
Short name T1222
Test name
Test status
Simulation time 43492263 ps
CPU time 0.71 seconds
Started Aug 12 05:00:28 PM PDT 24
Finished Aug 12 05:00:29 PM PDT 24
Peak memory 198528 kb
Host smart-9e4f9012-56b9-405d-b987-bb19fac7c179
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633606708 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2633606708
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.736515361
Short name T1209
Test name
Test status
Simulation time 16280883 ps
CPU time 0.6 seconds
Started Aug 12 05:00:25 PM PDT 24
Finished Aug 12 05:00:26 PM PDT 24
Peak memory 195500 kb
Host smart-f72fc16c-34cd-4f9a-83cb-781e3beaa39f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736515361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.736515361
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.3249373142
Short name T1203
Test name
Test status
Simulation time 77242758 ps
CPU time 0.58 seconds
Started Aug 12 05:00:25 PM PDT 24
Finished Aug 12 05:00:25 PM PDT 24
Peak memory 193532 kb
Host smart-0b9acc01-22f9-4a00-bacf-2505f44ff389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249373142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3249373142
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2233210416
Short name T1220
Test name
Test status
Simulation time 138046479 ps
CPU time 0.75 seconds
Started Aug 12 05:00:24 PM PDT 24
Finished Aug 12 05:00:25 PM PDT 24
Peak memory 196908 kb
Host smart-18982a1f-a1c4-453c-902b-b17d03559690
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233210416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2233210416
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1324946405
Short name T1277
Test name
Test status
Simulation time 351948521 ps
CPU time 2.13 seconds
Started Aug 12 05:00:27 PM PDT 24
Finished Aug 12 05:00:29 PM PDT 24
Peak memory 200108 kb
Host smart-c7b939fe-79dc-4a6f-8819-e6024e43f20b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324946405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1324946405
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3301175670
Short name T1304
Test name
Test status
Simulation time 141975750 ps
CPU time 1.33 seconds
Started Aug 12 05:00:24 PM PDT 24
Finished Aug 12 05:00:25 PM PDT 24
Peak memory 199400 kb
Host smart-d3dec522-f391-4513-abe9-f03e8e080f15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301175670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3301175670
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3139696180
Short name T1305
Test name
Test status
Simulation time 29000627 ps
CPU time 0.83 seconds
Started Aug 12 05:00:26 PM PDT 24
Finished Aug 12 05:00:26 PM PDT 24
Peak memory 198996 kb
Host smart-a9d943da-8526-42d7-938b-bae8a1eb1f41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139696180 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3139696180
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.320898657
Short name T1221
Test name
Test status
Simulation time 21240528 ps
CPU time 0.59 seconds
Started Aug 12 05:00:25 PM PDT 24
Finished Aug 12 05:00:26 PM PDT 24
Peak memory 195492 kb
Host smart-a1ba1215-2ce1-49b3-9c77-7992823fb1da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320898657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.320898657
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.3293187362
Short name T1192
Test name
Test status
Simulation time 116057845 ps
CPU time 0.58 seconds
Started Aug 12 05:00:25 PM PDT 24
Finished Aug 12 05:00:26 PM PDT 24
Peak memory 194432 kb
Host smart-cb6d54e8-8c79-4bc2-adb6-a1a65d01109f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293187362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3293187362
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2009356718
Short name T1245
Test name
Test status
Simulation time 84223832 ps
CPU time 0.77 seconds
Started Aug 12 05:00:24 PM PDT 24
Finished Aug 12 05:00:25 PM PDT 24
Peak memory 196924 kb
Host smart-38ac417d-6858-42bd-8cc6-77794290cf40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009356718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.2009356718
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3768248555
Short name T1208
Test name
Test status
Simulation time 33184151 ps
CPU time 1.65 seconds
Started Aug 12 05:00:26 PM PDT 24
Finished Aug 12 05:00:28 PM PDT 24
Peak memory 200176 kb
Host smart-a0561fce-8f6a-41fa-841b-b2e80b287712
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768248555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3768248555
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.832446835
Short name T1295
Test name
Test status
Simulation time 138336358 ps
CPU time 1.07 seconds
Started Aug 12 05:00:26 PM PDT 24
Finished Aug 12 05:00:27 PM PDT 24
Peak memory 199196 kb
Host smart-747acc47-7695-4a44-8be0-1a0ea51e8a1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832446835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.832446835
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3318522081
Short name T1309
Test name
Test status
Simulation time 59163628 ps
CPU time 0.84 seconds
Started Aug 12 05:00:28 PM PDT 24
Finished Aug 12 05:00:29 PM PDT 24
Peak memory 199812 kb
Host smart-49e73d61-7524-4012-a532-9998e5b6b0bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318522081 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3318522081
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.598294284
Short name T1259
Test name
Test status
Simulation time 58054404 ps
CPU time 0.67 seconds
Started Aug 12 05:00:28 PM PDT 24
Finished Aug 12 05:00:29 PM PDT 24
Peak memory 195572 kb
Host smart-6997b0d3-5108-4a82-8425-7a022573b98d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598294284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.598294284
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.2764327458
Short name T1190
Test name
Test status
Simulation time 57319935 ps
CPU time 0.59 seconds
Started Aug 12 05:00:25 PM PDT 24
Finished Aug 12 05:00:25 PM PDT 24
Peak memory 194560 kb
Host smart-491dcb57-2b86-46b7-8aa7-63844a065d6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764327458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2764327458
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3113368566
Short name T1262
Test name
Test status
Simulation time 24359625 ps
CPU time 0.66 seconds
Started Aug 12 05:00:26 PM PDT 24
Finished Aug 12 05:00:27 PM PDT 24
Peak memory 195480 kb
Host smart-337f565d-9458-4624-a25d-50e929518bd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113368566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.3113368566
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.3828554667
Short name T1217
Test name
Test status
Simulation time 766830522 ps
CPU time 1.19 seconds
Started Aug 12 05:00:34 PM PDT 24
Finished Aug 12 05:00:35 PM PDT 24
Peak memory 200168 kb
Host smart-645c7b75-c7b0-4819-bf52-79123ea02888
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828554667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3828554667
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3002008799
Short name T237
Test name
Test status
Simulation time 623922464 ps
CPU time 1.38 seconds
Started Aug 12 05:00:25 PM PDT 24
Finished Aug 12 05:00:26 PM PDT 24
Peak memory 199300 kb
Host smart-8674beca-ab9a-41a7-84fd-a633fdc71533
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002008799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3002008799
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2274288800
Short name T1167
Test name
Test status
Simulation time 21112902 ps
CPU time 0.56 seconds
Started Aug 12 05:03:32 PM PDT 24
Finished Aug 12 05:03:33 PM PDT 24
Peak memory 196040 kb
Host smart-4ece9548-00ec-4e84-b1a6-e7d606801cba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274288800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2274288800
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2525495447
Short name T418
Test name
Test status
Simulation time 9046317301 ps
CPU time 14.11 seconds
Started Aug 12 05:03:41 PM PDT 24
Finished Aug 12 05:03:55 PM PDT 24
Peak memory 200780 kb
Host smart-2b3cdcc3-1b44-4701-ad71-144400202e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525495447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2525495447
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.2398609878
Short name T937
Test name
Test status
Simulation time 177703376534 ps
CPU time 107.81 seconds
Started Aug 12 05:03:36 PM PDT 24
Finished Aug 12 05:05:24 PM PDT 24
Peak memory 200808 kb
Host smart-c867658f-722d-4796-8a5e-8d7fa35a8094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398609878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2398609878
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.1153335186
Short name T1007
Test name
Test status
Simulation time 29471224165 ps
CPU time 11.41 seconds
Started Aug 12 05:03:27 PM PDT 24
Finished Aug 12 05:03:39 PM PDT 24
Peak memory 200600 kb
Host smart-c88c9fb4-2e2d-4f11-8f1d-9f051818640c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153335186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1153335186
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1593704503
Short name T892
Test name
Test status
Simulation time 60137750344 ps
CPU time 305.75 seconds
Started Aug 12 05:03:28 PM PDT 24
Finished Aug 12 05:08:34 PM PDT 24
Peak memory 200824 kb
Host smart-648b4be4-700e-48e4-88bc-edad50bd4563
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1593704503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1593704503
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1800992440
Short name T737
Test name
Test status
Simulation time 7049307471 ps
CPU time 5.23 seconds
Started Aug 12 05:03:28 PM PDT 24
Finished Aug 12 05:03:33 PM PDT 24
Peak memory 199868 kb
Host smart-ee3c98a7-d2f1-455c-866a-6fc6e7947943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800992440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1800992440
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_perf.3487343246
Short name T1163
Test name
Test status
Simulation time 11539040710 ps
CPU time 65.22 seconds
Started Aug 12 05:03:37 PM PDT 24
Finished Aug 12 05:04:42 PM PDT 24
Peak memory 200748 kb
Host smart-32934922-70d7-4ccc-bd06-0c109e37d6b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3487343246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3487343246
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.1408162103
Short name T918
Test name
Test status
Simulation time 5566215886 ps
CPU time 4.65 seconds
Started Aug 12 05:03:30 PM PDT 24
Finished Aug 12 05:03:35 PM PDT 24
Peak memory 198892 kb
Host smart-2b584187-c06c-45ff-ab61-dfbc003df0f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1408162103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1408162103
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2291785858
Short name T90
Test name
Test status
Simulation time 32557821588 ps
CPU time 14.32 seconds
Started Aug 12 05:03:30 PM PDT 24
Finished Aug 12 05:03:45 PM PDT 24
Peak memory 200840 kb
Host smart-652d7882-579b-4a51-b709-2d6c379873ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291785858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2291785858
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.2080620042
Short name T727
Test name
Test status
Simulation time 33994421156 ps
CPU time 13.18 seconds
Started Aug 12 05:03:39 PM PDT 24
Finished Aug 12 05:03:52 PM PDT 24
Peak memory 196632 kb
Host smart-d58ab07d-265a-4bc4-999f-5de42371da4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080620042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2080620042
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.3935984234
Short name T620
Test name
Test status
Simulation time 430617891 ps
CPU time 1.78 seconds
Started Aug 12 05:03:33 PM PDT 24
Finished Aug 12 05:03:35 PM PDT 24
Peak memory 200332 kb
Host smart-d63cb6c8-71c5-44b9-962c-5f1d0612ecad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935984234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3935984234
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.343914518
Short name T980
Test name
Test status
Simulation time 264990825285 ps
CPU time 1009.49 seconds
Started Aug 12 05:03:33 PM PDT 24
Finished Aug 12 05:20:23 PM PDT 24
Peak memory 209372 kb
Host smart-ede49ad1-3c72-4c4c-9029-593561edf7d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343914518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.343914518
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.2497536770
Short name T1006
Test name
Test status
Simulation time 17008487741 ps
CPU time 44.28 seconds
Started Aug 12 05:03:29 PM PDT 24
Finished Aug 12 05:04:13 PM PDT 24
Peak memory 210532 kb
Host smart-b8cfdd85-51f0-4407-b44f-87aaa3daafa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497536770 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.2497536770
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2730291070
Short name T1177
Test name
Test status
Simulation time 7631595581 ps
CPU time 11.28 seconds
Started Aug 12 05:03:31 PM PDT 24
Finished Aug 12 05:03:43 PM PDT 24
Peak memory 200524 kb
Host smart-10f4f237-9d4a-4c69-89a7-63c6b2877c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730291070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2730291070
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2329471289
Short name T1071
Test name
Test status
Simulation time 79340199806 ps
CPU time 156.95 seconds
Started Aug 12 05:03:30 PM PDT 24
Finished Aug 12 05:06:07 PM PDT 24
Peak memory 200760 kb
Host smart-c9c66fb9-9546-452f-beda-2e8b5f950514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329471289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2329471289
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3670542666
Short name T289
Test name
Test status
Simulation time 92860569062 ps
CPU time 37.52 seconds
Started Aug 12 05:03:28 PM PDT 24
Finished Aug 12 05:04:05 PM PDT 24
Peak memory 200824 kb
Host smart-18226e25-c80d-400f-9b57-0e1790dd5563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670542666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3670542666
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.4089415751
Short name T788
Test name
Test status
Simulation time 109647375983 ps
CPU time 81.8 seconds
Started Aug 12 05:03:24 PM PDT 24
Finished Aug 12 05:04:46 PM PDT 24
Peak memory 200796 kb
Host smart-1b076933-5bc1-4595-9e61-0cd4d117efb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089415751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.4089415751
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2843376803
Short name T1086
Test name
Test status
Simulation time 38742688651 ps
CPU time 24.53 seconds
Started Aug 12 05:03:28 PM PDT 24
Finished Aug 12 05:03:52 PM PDT 24
Peak memory 200656 kb
Host smart-801c202a-2c39-41c6-8d95-c4e61c912c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843376803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2843376803
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.1757993378
Short name T557
Test name
Test status
Simulation time 29856720819 ps
CPU time 47.04 seconds
Started Aug 12 05:03:31 PM PDT 24
Finished Aug 12 05:04:18 PM PDT 24
Peak memory 199992 kb
Host smart-70329455-122b-4aff-8687-7e63e99b9997
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757993378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1757993378
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3689958783
Short name T241
Test name
Test status
Simulation time 73699577953 ps
CPU time 403.74 seconds
Started Aug 12 05:03:43 PM PDT 24
Finished Aug 12 05:10:27 PM PDT 24
Peak memory 200812 kb
Host smart-8cfe1f7e-95fc-4bca-986b-54a2048aec63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3689958783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3689958783
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.2221691902
Short name T597
Test name
Test status
Simulation time 289688338 ps
CPU time 0.83 seconds
Started Aug 12 05:03:42 PM PDT 24
Finished Aug 12 05:03:43 PM PDT 24
Peak memory 196716 kb
Host smart-88e0a65d-8ea1-4453-b19f-916ed74e06a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221691902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2221691902
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.3500572881
Short name T379
Test name
Test status
Simulation time 98119652072 ps
CPU time 97.86 seconds
Started Aug 12 05:03:32 PM PDT 24
Finished Aug 12 05:05:15 PM PDT 24
Peak memory 200200 kb
Host smart-1f34c480-7b04-45cc-877a-f92cd227d528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500572881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3500572881
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.3298062708
Short name T443
Test name
Test status
Simulation time 24331302746 ps
CPU time 1295.72 seconds
Started Aug 12 05:03:41 PM PDT 24
Finished Aug 12 05:25:17 PM PDT 24
Peak memory 200756 kb
Host smart-2722e005-e0c3-4764-b7ef-b447dc0e1626
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3298062708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3298062708
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2539429049
Short name T359
Test name
Test status
Simulation time 7628950760 ps
CPU time 18.75 seconds
Started Aug 12 05:03:31 PM PDT 24
Finished Aug 12 05:03:50 PM PDT 24
Peak memory 197984 kb
Host smart-0094ce93-0b76-4d23-a286-cd44ebf0f2bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2539429049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2539429049
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.1268595694
Short name T1110
Test name
Test status
Simulation time 124085823291 ps
CPU time 220.66 seconds
Started Aug 12 05:03:40 PM PDT 24
Finished Aug 12 05:07:20 PM PDT 24
Peak memory 200764 kb
Host smart-1f7e7c20-0d63-497c-8ebd-153c84c25b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268595694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1268595694
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.359456685
Short name T1174
Test name
Test status
Simulation time 32208378567 ps
CPU time 45.73 seconds
Started Aug 12 05:03:34 PM PDT 24
Finished Aug 12 05:04:20 PM PDT 24
Peak memory 196704 kb
Host smart-ce0818fa-e6ec-4f44-983e-4c1b08162b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359456685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.359456685
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.619322593
Short name T81
Test name
Test status
Simulation time 196915740 ps
CPU time 0.84 seconds
Started Aug 12 05:03:32 PM PDT 24
Finished Aug 12 05:03:33 PM PDT 24
Peak memory 218988 kb
Host smart-99233484-7e3e-4833-9288-8ec59d3dc949
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619322593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.619322593
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3243102374
Short name T661
Test name
Test status
Simulation time 444906467 ps
CPU time 1.58 seconds
Started Aug 12 05:03:33 PM PDT 24
Finished Aug 12 05:03:34 PM PDT 24
Peak memory 199112 kb
Host smart-24c1109d-3f85-4755-9bc5-c7c0a2a46dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243102374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3243102374
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.1784889876
Short name T757
Test name
Test status
Simulation time 206686964786 ps
CPU time 546 seconds
Started Aug 12 05:03:38 PM PDT 24
Finished Aug 12 05:12:44 PM PDT 24
Peak memory 200724 kb
Host smart-162551c4-51eb-4368-a7ea-fae4cd24581b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784889876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1784889876
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.937876122
Short name T636
Test name
Test status
Simulation time 523323720 ps
CPU time 17.77 seconds
Started Aug 12 05:03:41 PM PDT 24
Finished Aug 12 05:03:59 PM PDT 24
Peak memory 200904 kb
Host smart-466f0679-c27f-4008-9b47-ef3231805927
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937876122 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.937876122
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.295418734
Short name T1135
Test name
Test status
Simulation time 1379527445 ps
CPU time 1.58 seconds
Started Aug 12 05:03:48 PM PDT 24
Finished Aug 12 05:03:50 PM PDT 24
Peak memory 199368 kb
Host smart-ea0a8b7e-88dd-4dc0-8e63-e32ba3e005af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295418734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.295418734
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.3162189958
Short name T1121
Test name
Test status
Simulation time 112248478215 ps
CPU time 216.24 seconds
Started Aug 12 05:03:26 PM PDT 24
Finished Aug 12 05:07:02 PM PDT 24
Peak memory 200820 kb
Host smart-dc1883ae-b0dc-4ad8-a1ed-715baca0f8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162189958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3162189958
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.3527412522
Short name T1075
Test name
Test status
Simulation time 64483379 ps
CPU time 0.56 seconds
Started Aug 12 05:04:05 PM PDT 24
Finished Aug 12 05:04:05 PM PDT 24
Peak memory 196000 kb
Host smart-d414fd29-beb2-4445-a2a1-bad8d7b7cebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527412522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3527412522
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2468166536
Short name T785
Test name
Test status
Simulation time 53154887257 ps
CPU time 87.58 seconds
Started Aug 12 05:03:58 PM PDT 24
Finished Aug 12 05:05:25 PM PDT 24
Peak memory 200788 kb
Host smart-254d9171-c522-4f05-8de2-e33bb7721b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468166536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2468166536
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3632054977
Short name T963
Test name
Test status
Simulation time 22270232498 ps
CPU time 16.85 seconds
Started Aug 12 05:03:49 PM PDT 24
Finished Aug 12 05:04:06 PM PDT 24
Peak memory 200676 kb
Host smart-87f7e0b0-9a3f-4e87-aae0-d94273ab4d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632054977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3632054977
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.3052081155
Short name T104
Test name
Test status
Simulation time 15310337779 ps
CPU time 26.65 seconds
Started Aug 12 05:04:00 PM PDT 24
Finished Aug 12 05:04:27 PM PDT 24
Peak memory 200732 kb
Host smart-b5356a85-5d3b-4484-aeb1-710cd65a3c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052081155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3052081155
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.1709353935
Short name T270
Test name
Test status
Simulation time 39476817767 ps
CPU time 72.21 seconds
Started Aug 12 05:04:06 PM PDT 24
Finished Aug 12 05:05:18 PM PDT 24
Peak memory 200808 kb
Host smart-f8f9f32b-f874-408c-a535-ed2c482b7c29
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709353935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1709353935
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.1942787411
Short name T1053
Test name
Test status
Simulation time 84061675064 ps
CPU time 142.24 seconds
Started Aug 12 05:03:48 PM PDT 24
Finished Aug 12 05:06:10 PM PDT 24
Peak memory 200700 kb
Host smart-f251cc07-a233-4052-9175-a37f73a55ebd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1942787411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1942787411
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.75690157
Short name T1017
Test name
Test status
Simulation time 3682185546 ps
CPU time 6.6 seconds
Started Aug 12 05:03:53 PM PDT 24
Finished Aug 12 05:04:00 PM PDT 24
Peak memory 198200 kb
Host smart-e7d2086f-6a6c-48f5-815a-689ef2d93a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75690157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.75690157
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.2180261303
Short name T258
Test name
Test status
Simulation time 95176487858 ps
CPU time 21.42 seconds
Started Aug 12 05:03:59 PM PDT 24
Finished Aug 12 05:04:20 PM PDT 24
Peak memory 208972 kb
Host smart-d628b0f3-df5a-406c-bfb2-5bf70c9bbfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180261303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2180261303
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.4189734558
Short name T553
Test name
Test status
Simulation time 23209230817 ps
CPU time 171.11 seconds
Started Aug 12 05:03:57 PM PDT 24
Finished Aug 12 05:06:48 PM PDT 24
Peak memory 200772 kb
Host smart-fb6ad94a-f6cf-41e8-b8bd-9b4d559c358e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4189734558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.4189734558
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.987055151
Short name T1079
Test name
Test status
Simulation time 1481170159 ps
CPU time 5.84 seconds
Started Aug 12 05:04:00 PM PDT 24
Finished Aug 12 05:04:06 PM PDT 24
Peak memory 198888 kb
Host smart-a3784326-9f21-4859-8695-ec7a9d43257f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=987055151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.987055151
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.756201733
Short name T400
Test name
Test status
Simulation time 24142263016 ps
CPU time 11.55 seconds
Started Aug 12 05:03:55 PM PDT 24
Finished Aug 12 05:04:06 PM PDT 24
Peak memory 200804 kb
Host smart-0fca5d2c-b0ec-43a3-b9e0-5160daa7c794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756201733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.756201733
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3520106524
Short name T551
Test name
Test status
Simulation time 2054614262 ps
CPU time 3.73 seconds
Started Aug 12 05:04:05 PM PDT 24
Finished Aug 12 05:04:09 PM PDT 24
Peak memory 196164 kb
Host smart-0667fbe5-608f-441f-ace8-7461c834b37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520106524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3520106524
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.1274866179
Short name T356
Test name
Test status
Simulation time 661460345 ps
CPU time 1.15 seconds
Started Aug 12 05:03:58 PM PDT 24
Finished Aug 12 05:04:00 PM PDT 24
Peak memory 200596 kb
Host smart-cd14976b-1588-49d8-8bf7-a3127fb995ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274866179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1274866179
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.520183052
Short name T1022
Test name
Test status
Simulation time 565429707509 ps
CPU time 615.1 seconds
Started Aug 12 05:04:05 PM PDT 24
Finished Aug 12 05:14:20 PM PDT 24
Peak memory 200680 kb
Host smart-1259c675-4ed4-4e8e-a3c6-89c7ff88b791
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520183052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.520183052
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1852762263
Short name T318
Test name
Test status
Simulation time 4145228186 ps
CPU time 45.37 seconds
Started Aug 12 05:03:58 PM PDT 24
Finished Aug 12 05:04:43 PM PDT 24
Peak memory 216428 kb
Host smart-bdec4705-ab2c-4dd3-a58d-10bf56ac4880
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852762263 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1852762263
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.2939269905
Short name T828
Test name
Test status
Simulation time 1244049127 ps
CPU time 2.21 seconds
Started Aug 12 05:03:56 PM PDT 24
Finished Aug 12 05:03:58 PM PDT 24
Peak memory 199436 kb
Host smart-30b4ab02-2811-45dc-bfb4-d971da14f9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939269905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.2939269905
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3013168869
Short name T250
Test name
Test status
Simulation time 76162442581 ps
CPU time 184.73 seconds
Started Aug 12 05:04:00 PM PDT 24
Finished Aug 12 05:07:05 PM PDT 24
Peak memory 200820 kb
Host smart-eea977ed-278d-4ee8-ae75-6b687eb8072c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013168869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3013168869
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3433387254
Short name T806
Test name
Test status
Simulation time 107080711221 ps
CPU time 17.34 seconds
Started Aug 12 05:06:29 PM PDT 24
Finished Aug 12 05:06:46 PM PDT 24
Peak memory 200808 kb
Host smart-eaa0eece-5aaa-498e-869c-4c0d024ccea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433387254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3433387254
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.639935482
Short name T178
Test name
Test status
Simulation time 131168643496 ps
CPU time 72.81 seconds
Started Aug 12 05:06:27 PM PDT 24
Finished Aug 12 05:07:40 PM PDT 24
Peak memory 200736 kb
Host smart-49056581-5d4a-4c48-8b4c-f7dcc507ec1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639935482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.639935482
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1765543276
Short name T459
Test name
Test status
Simulation time 11565511544 ps
CPU time 10.55 seconds
Started Aug 12 05:06:32 PM PDT 24
Finished Aug 12 05:06:42 PM PDT 24
Peak memory 200732 kb
Host smart-a1f24530-ba1f-4756-9bce-a6266b39a99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765543276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1765543276
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.1452199335
Short name T979
Test name
Test status
Simulation time 124174066428 ps
CPU time 231.38 seconds
Started Aug 12 05:06:27 PM PDT 24
Finished Aug 12 05:10:19 PM PDT 24
Peak memory 200908 kb
Host smart-5146142e-a5eb-42e3-9784-aac01987119b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452199335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1452199335
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.999460320
Short name T495
Test name
Test status
Simulation time 42854773710 ps
CPU time 15.64 seconds
Started Aug 12 05:06:27 PM PDT 24
Finished Aug 12 05:06:43 PM PDT 24
Peak memory 200748 kb
Host smart-6330a766-613b-4b77-b4c3-5b9844ac749a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999460320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.999460320
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.577374514
Short name T504
Test name
Test status
Simulation time 184324724043 ps
CPU time 75.54 seconds
Started Aug 12 05:06:31 PM PDT 24
Finished Aug 12 05:07:47 PM PDT 24
Peak memory 200720 kb
Host smart-9334b3c4-57e8-41fb-ad29-75226397c804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577374514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.577374514
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2728783642
Short name T133
Test name
Test status
Simulation time 20062349860 ps
CPU time 33.61 seconds
Started Aug 12 05:06:27 PM PDT 24
Finished Aug 12 05:07:01 PM PDT 24
Peak memory 200724 kb
Host smart-e928d8d8-ff26-4224-99aa-375cf09bf4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728783642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2728783642
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.195562086
Short name T256
Test name
Test status
Simulation time 29866223297 ps
CPU time 59.73 seconds
Started Aug 12 05:06:28 PM PDT 24
Finished Aug 12 05:07:28 PM PDT 24
Peak memory 200664 kb
Host smart-e927bba8-4cdd-4e08-ae15-a999453be1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195562086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.195562086
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.799205912
Short name T641
Test name
Test status
Simulation time 14067426 ps
CPU time 0.55 seconds
Started Aug 12 05:03:54 PM PDT 24
Finished Aug 12 05:03:55 PM PDT 24
Peak memory 196016 kb
Host smart-64011e8f-b20e-4f47-b4c0-44ca71e2ed68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799205912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.799205912
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.1349057351
Short name T839
Test name
Test status
Simulation time 63015963092 ps
CPU time 32.43 seconds
Started Aug 12 05:04:09 PM PDT 24
Finished Aug 12 05:04:41 PM PDT 24
Peak memory 200764 kb
Host smart-5472b2ad-626b-42f7-800d-bf0067b458db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349057351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.1349057351
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.4165108668
Short name T832
Test name
Test status
Simulation time 289414900841 ps
CPU time 232.13 seconds
Started Aug 12 05:04:01 PM PDT 24
Finished Aug 12 05:07:54 PM PDT 24
Peak memory 200708 kb
Host smart-b4564eaa-eb38-4ec5-9875-bebc1e4b9858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165108668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.4165108668
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2904031712
Short name T719
Test name
Test status
Simulation time 106678884956 ps
CPU time 184.22 seconds
Started Aug 12 05:03:59 PM PDT 24
Finished Aug 12 05:07:03 PM PDT 24
Peak memory 200676 kb
Host smart-136489ea-20c7-41bd-9669-047bb6341087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904031712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2904031712
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.1440504917
Short name T494
Test name
Test status
Simulation time 67583339084 ps
CPU time 134.62 seconds
Started Aug 12 05:03:56 PM PDT 24
Finished Aug 12 05:06:11 PM PDT 24
Peak memory 200732 kb
Host smart-6e2e31e7-6b85-4dac-90eb-894745d8efc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1440504917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1440504917
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2397269162
Short name T560
Test name
Test status
Simulation time 1604569842 ps
CPU time 3.08 seconds
Started Aug 12 05:04:01 PM PDT 24
Finished Aug 12 05:04:04 PM PDT 24
Peak memory 198244 kb
Host smart-04a1c2c8-25fd-41ad-a38f-0d3fff0ba367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397269162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2397269162
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.3392741950
Short name T1033
Test name
Test status
Simulation time 61621598905 ps
CPU time 146.16 seconds
Started Aug 12 05:03:54 PM PDT 24
Finished Aug 12 05:06:20 PM PDT 24
Peak memory 200936 kb
Host smart-e9f5c0ed-8aac-4f5c-8bcc-dc3c8d91ac43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392741950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3392741950
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.3955153966
Short name T37
Test name
Test status
Simulation time 5194927221 ps
CPU time 155.17 seconds
Started Aug 12 05:03:57 PM PDT 24
Finished Aug 12 05:06:33 PM PDT 24
Peak memory 200700 kb
Host smart-0b246d7c-f9c7-4c2b-ae3e-0b1199668674
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3955153966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3955153966
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3240169656
Short name T360
Test name
Test status
Simulation time 2728599256 ps
CPU time 1.47 seconds
Started Aug 12 05:04:01 PM PDT 24
Finished Aug 12 05:04:03 PM PDT 24
Peak memory 199356 kb
Host smart-76fa18ef-2de1-4ba0-85ed-1408e7c1e0f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3240169656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3240169656
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3581175745
Short name T660
Test name
Test status
Simulation time 44915277995 ps
CPU time 18.16 seconds
Started Aug 12 05:03:59 PM PDT 24
Finished Aug 12 05:04:17 PM PDT 24
Peak memory 199092 kb
Host smart-3ef8dac7-537c-4275-8602-6992f16658b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581175745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3581175745
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.3679665368
Short name T693
Test name
Test status
Simulation time 41190323179 ps
CPU time 31.88 seconds
Started Aug 12 05:03:57 PM PDT 24
Finished Aug 12 05:04:30 PM PDT 24
Peak memory 196608 kb
Host smart-2da9bbfa-5e50-471c-b55f-59ca4ffb7705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679665368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3679665368
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3698469144
Short name T296
Test name
Test status
Simulation time 5443293383 ps
CPU time 8.37 seconds
Started Aug 12 05:03:59 PM PDT 24
Finished Aug 12 05:04:08 PM PDT 24
Peak memory 200412 kb
Host smart-906bc4f9-1ec0-4ce7-a59c-57afcd616e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698469144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3698469144
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2795375244
Short name T1034
Test name
Test status
Simulation time 2329370600 ps
CPU time 2.62 seconds
Started Aug 12 05:04:10 PM PDT 24
Finished Aug 12 05:04:13 PM PDT 24
Peak memory 199868 kb
Host smart-4b7e1ad6-8e58-44a8-a12d-72f6d8c3167e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795375244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2795375244
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.1199624070
Short name T1028
Test name
Test status
Simulation time 47927615314 ps
CPU time 170.57 seconds
Started Aug 12 05:03:57 PM PDT 24
Finished Aug 12 05:06:48 PM PDT 24
Peak memory 200600 kb
Host smart-8f988126-e059-4985-9f29-bf21d162577e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199624070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1199624070
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1140365088
Short name T959
Test name
Test status
Simulation time 21068935594 ps
CPU time 9.98 seconds
Started Aug 12 05:06:28 PM PDT 24
Finished Aug 12 05:06:38 PM PDT 24
Peak memory 200724 kb
Host smart-7009f2b3-395f-4f32-b1d5-db4ed7d3d89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140365088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1140365088
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.3982687507
Short name T664
Test name
Test status
Simulation time 88784606882 ps
CPU time 37.17 seconds
Started Aug 12 05:06:27 PM PDT 24
Finished Aug 12 05:07:04 PM PDT 24
Peak memory 200800 kb
Host smart-ab4e0923-78e3-4d2e-9f17-725257854791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982687507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3982687507
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3004445952
Short name T1171
Test name
Test status
Simulation time 20398047673 ps
CPU time 31.37 seconds
Started Aug 12 05:06:30 PM PDT 24
Finished Aug 12 05:07:02 PM PDT 24
Peak memory 200668 kb
Host smart-9dfc2d2b-253c-4a86-a603-d657cd3c9cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004445952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3004445952
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1142521471
Short name T587
Test name
Test status
Simulation time 203089094098 ps
CPU time 39.77 seconds
Started Aug 12 05:06:31 PM PDT 24
Finished Aug 12 05:07:11 PM PDT 24
Peak memory 200528 kb
Host smart-f5ada9e8-e3d6-414f-beaf-8915b2878e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142521471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1142521471
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1948269946
Short name T740
Test name
Test status
Simulation time 35708754271 ps
CPU time 56.41 seconds
Started Aug 12 05:06:28 PM PDT 24
Finished Aug 12 05:07:25 PM PDT 24
Peak memory 200808 kb
Host smart-7d57ee80-ec29-4e76-903e-d310ee045444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948269946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1948269946
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2551586072
Short name T804
Test name
Test status
Simulation time 13624492 ps
CPU time 0.58 seconds
Started Aug 12 05:04:09 PM PDT 24
Finished Aug 12 05:04:10 PM PDT 24
Peak memory 196332 kb
Host smart-f7faf4e4-109b-4545-ab16-db1cb06a279a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551586072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2551586072
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3946886175
Short name T627
Test name
Test status
Simulation time 48145051844 ps
CPU time 26.74 seconds
Started Aug 12 05:04:00 PM PDT 24
Finished Aug 12 05:04:27 PM PDT 24
Peak memory 200788 kb
Host smart-cdf9adcc-064a-423c-809f-82455b476fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946886175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3946886175
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.3875306068
Short name T474
Test name
Test status
Simulation time 14812825778 ps
CPU time 11.64 seconds
Started Aug 12 05:04:05 PM PDT 24
Finished Aug 12 05:04:16 PM PDT 24
Peak memory 200196 kb
Host smart-d27adb67-ce08-4765-9a25-929d2c0a8619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875306068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3875306068
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.762971173
Short name T987
Test name
Test status
Simulation time 19406844368 ps
CPU time 43.56 seconds
Started Aug 12 05:04:02 PM PDT 24
Finished Aug 12 05:04:45 PM PDT 24
Peak memory 200784 kb
Host smart-a8a5dad5-14ff-460e-920c-b0d199e3e42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762971173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.762971173
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.450633356
Short name T413
Test name
Test status
Simulation time 25680730044 ps
CPU time 9.57 seconds
Started Aug 12 05:04:04 PM PDT 24
Finished Aug 12 05:04:14 PM PDT 24
Peak memory 198772 kb
Host smart-982363bb-d903-40cd-b152-d2cd67c53907
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450633356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.450633356
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1073321481
Short name T956
Test name
Test status
Simulation time 69964000504 ps
CPU time 292.72 seconds
Started Aug 12 05:03:57 PM PDT 24
Finished Aug 12 05:08:50 PM PDT 24
Peak memory 200716 kb
Host smart-bfb8a78e-e71f-42d4-8362-e515f50a9977
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1073321481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1073321481
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.3403656566
Short name T1142
Test name
Test status
Simulation time 2583635065 ps
CPU time 2.73 seconds
Started Aug 12 05:03:59 PM PDT 24
Finished Aug 12 05:04:02 PM PDT 24
Peak memory 197124 kb
Host smart-dfa7d51a-cb46-4952-aafe-ac8e0987f28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403656566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3403656566
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2758533235
Short name T948
Test name
Test status
Simulation time 27310220686 ps
CPU time 25.89 seconds
Started Aug 12 05:04:05 PM PDT 24
Finished Aug 12 05:04:31 PM PDT 24
Peak memory 200900 kb
Host smart-77e88be4-cfe6-45bc-880d-551e35f0ff84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758533235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2758533235
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.1088521817
Short name T513
Test name
Test status
Simulation time 13013814815 ps
CPU time 120.38 seconds
Started Aug 12 05:04:00 PM PDT 24
Finished Aug 12 05:06:01 PM PDT 24
Peak memory 200752 kb
Host smart-93875fc7-9f14-4b78-b248-24c800ede005
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1088521817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1088521817
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.377989589
Short name T877
Test name
Test status
Simulation time 6645300700 ps
CPU time 30.78 seconds
Started Aug 12 05:03:59 PM PDT 24
Finished Aug 12 05:04:30 PM PDT 24
Peak memory 198956 kb
Host smart-67e43698-b00b-4f16-9307-dcc8247578a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=377989589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.377989589
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.3804264529
Short name T169
Test name
Test status
Simulation time 96147291425 ps
CPU time 30.72 seconds
Started Aug 12 05:03:58 PM PDT 24
Finished Aug 12 05:04:29 PM PDT 24
Peak memory 200312 kb
Host smart-673ff5ed-3299-4ad3-8855-fd705751231b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804264529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3804264529
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.4070740882
Short name T304
Test name
Test status
Simulation time 3601106963 ps
CPU time 1.38 seconds
Started Aug 12 05:04:04 PM PDT 24
Finished Aug 12 05:04:06 PM PDT 24
Peak memory 196868 kb
Host smart-cb2879c9-7c50-4301-81ab-cabe2451d090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070740882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.4070740882
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2130338230
Short name T637
Test name
Test status
Simulation time 102606716 ps
CPU time 0.88 seconds
Started Aug 12 05:04:01 PM PDT 24
Finished Aug 12 05:04:03 PM PDT 24
Peak memory 197928 kb
Host smart-4bb43b50-63c1-4132-99cf-c149b26516ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130338230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2130338230
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.4090623901
Short name T697
Test name
Test status
Simulation time 8470468303 ps
CPU time 59.8 seconds
Started Aug 12 05:04:05 PM PDT 24
Finished Aug 12 05:05:05 PM PDT 24
Peak memory 217536 kb
Host smart-4d587bcc-0d43-4c0d-b1fc-09eb23251196
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090623901 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.4090623901
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.2824362289
Short name T680
Test name
Test status
Simulation time 2101684817 ps
CPU time 2.09 seconds
Started Aug 12 05:04:01 PM PDT 24
Finished Aug 12 05:04:04 PM PDT 24
Peak memory 200080 kb
Host smart-6f380482-1be3-49c6-b18b-644d308c3f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824362289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2824362289
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.3919604122
Short name T909
Test name
Test status
Simulation time 34589676579 ps
CPU time 58.35 seconds
Started Aug 12 05:04:03 PM PDT 24
Finished Aug 12 05:05:02 PM PDT 24
Peak memory 200756 kb
Host smart-dc5fc792-48f6-42d2-a574-60d97ae73fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919604122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3919604122
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3664831170
Short name T2
Test name
Test status
Simulation time 228914151626 ps
CPU time 16.86 seconds
Started Aug 12 05:06:29 PM PDT 24
Finished Aug 12 05:06:46 PM PDT 24
Peak memory 200532 kb
Host smart-75ea04d0-bc7e-4580-a4a2-05f04a70ebbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664831170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3664831170
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.3136422986
Short name T882
Test name
Test status
Simulation time 128564780515 ps
CPU time 216.75 seconds
Started Aug 12 05:06:29 PM PDT 24
Finished Aug 12 05:10:06 PM PDT 24
Peak memory 200764 kb
Host smart-8def68a6-32d2-448d-a5b8-d45f6317b115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136422986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3136422986
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2325803235
Short name T675
Test name
Test status
Simulation time 33672030090 ps
CPU time 49.54 seconds
Started Aug 12 05:06:30 PM PDT 24
Finished Aug 12 05:07:20 PM PDT 24
Peak memory 200668 kb
Host smart-6705d8d8-09e6-44de-8ad3-14c09ee4d721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325803235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2325803235
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3590087326
Short name T128
Test name
Test status
Simulation time 37183460625 ps
CPU time 29.83 seconds
Started Aug 12 05:06:29 PM PDT 24
Finished Aug 12 05:06:59 PM PDT 24
Peak memory 200744 kb
Host smart-c05a632a-c8f4-4acf-924e-671acb327830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590087326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3590087326
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3009131499
Short name T201
Test name
Test status
Simulation time 12130528412 ps
CPU time 12.24 seconds
Started Aug 12 05:06:30 PM PDT 24
Finished Aug 12 05:06:42 PM PDT 24
Peak memory 200644 kb
Host smart-c9f95ddd-2d4e-41ca-b68a-2ee56fa60b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009131499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3009131499
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.2700821689
Short name T1029
Test name
Test status
Simulation time 160940613896 ps
CPU time 320.23 seconds
Started Aug 12 05:06:27 PM PDT 24
Finished Aug 12 05:11:47 PM PDT 24
Peak memory 200740 kb
Host smart-60df1a8e-a3e6-4d51-9743-299ae3bf4f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700821689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.2700821689
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.3281484620
Short name T374
Test name
Test status
Simulation time 44702577768 ps
CPU time 14.07 seconds
Started Aug 12 05:06:29 PM PDT 24
Finished Aug 12 05:06:43 PM PDT 24
Peak memory 200832 kb
Host smart-f8a43244-f4b1-4cc0-b22b-cb08485fb6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281484620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3281484620
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.3036168083
Short name T183
Test name
Test status
Simulation time 31076846191 ps
CPU time 20.29 seconds
Started Aug 12 05:06:28 PM PDT 24
Finished Aug 12 05:06:49 PM PDT 24
Peak memory 200752 kb
Host smart-97a79996-f849-4a0d-a55f-b2d6629d2e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036168083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3036168083
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2194034587
Short name T1049
Test name
Test status
Simulation time 123565519397 ps
CPU time 26.29 seconds
Started Aug 12 05:06:29 PM PDT 24
Finished Aug 12 05:06:56 PM PDT 24
Peak memory 200700 kb
Host smart-4514a153-c308-44c5-86f5-2321cddb2cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194034587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2194034587
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2635344229
Short name T761
Test name
Test status
Simulation time 50203176 ps
CPU time 0.55 seconds
Started Aug 12 05:04:13 PM PDT 24
Finished Aug 12 05:04:14 PM PDT 24
Peak memory 196048 kb
Host smart-54bbd400-ac0d-4ed8-8f79-8a72479a41d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635344229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2635344229
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.2150291555
Short name T393
Test name
Test status
Simulation time 34075053504 ps
CPU time 17.32 seconds
Started Aug 12 05:04:06 PM PDT 24
Finished Aug 12 05:04:23 PM PDT 24
Peak memory 200808 kb
Host smart-e07e2755-fa7f-436c-a0c9-843045b3e902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150291555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2150291555
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2339149725
Short name T847
Test name
Test status
Simulation time 120650173333 ps
CPU time 37.49 seconds
Started Aug 12 05:04:14 PM PDT 24
Finished Aug 12 05:04:52 PM PDT 24
Peak memory 200704 kb
Host smart-da44bc49-84a1-4a40-b7b9-4f48aae57669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339149725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2339149725
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2753984646
Short name T321
Test name
Test status
Simulation time 18742145548 ps
CPU time 30.84 seconds
Started Aug 12 05:04:15 PM PDT 24
Finished Aug 12 05:04:46 PM PDT 24
Peak memory 200652 kb
Host smart-7d316dab-ed12-473a-9283-c7acf9065ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753984646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2753984646
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2755997849
Short name T805
Test name
Test status
Simulation time 9487670029 ps
CPU time 4.21 seconds
Started Aug 12 05:04:05 PM PDT 24
Finished Aug 12 05:04:10 PM PDT 24
Peak memory 197612 kb
Host smart-d08baa71-fe13-4856-9122-3353eb73b0fe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755997849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2755997849
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.777731051
Short name T35
Test name
Test status
Simulation time 72496431353 ps
CPU time 236.04 seconds
Started Aug 12 05:04:05 PM PDT 24
Finished Aug 12 05:08:01 PM PDT 24
Peak memory 200744 kb
Host smart-aaf4962b-689f-4622-8856-f563c3eb24f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=777731051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.777731051
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.4245561613
Short name T768
Test name
Test status
Simulation time 9150455118 ps
CPU time 17.03 seconds
Started Aug 12 05:04:08 PM PDT 24
Finished Aug 12 05:04:25 PM PDT 24
Peak memory 199636 kb
Host smart-fec9d088-8648-4602-9262-ac140fd2f898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245561613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.4245561613
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.1859905880
Short name T245
Test name
Test status
Simulation time 36830994325 ps
CPU time 23.57 seconds
Started Aug 12 05:04:16 PM PDT 24
Finished Aug 12 05:04:40 PM PDT 24
Peak memory 200976 kb
Host smart-02d5253e-33c5-4748-a94d-600eb24aafaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859905880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.1859905880
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.142213308
Short name T738
Test name
Test status
Simulation time 4760814216 ps
CPU time 104.31 seconds
Started Aug 12 05:04:21 PM PDT 24
Finished Aug 12 05:06:05 PM PDT 24
Peak memory 200636 kb
Host smart-8e1c448d-2e1a-414a-891b-43eadd9889c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=142213308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.142213308
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.1587728708
Short name T415
Test name
Test status
Simulation time 2634998918 ps
CPU time 4.67 seconds
Started Aug 12 05:04:05 PM PDT 24
Finished Aug 12 05:04:10 PM PDT 24
Peak memory 198628 kb
Host smart-fb21e85d-c579-4fd3-abf7-e1b36e969c6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1587728708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1587728708
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3326359071
Short name T558
Test name
Test status
Simulation time 24651928522 ps
CPU time 23.41 seconds
Started Aug 12 05:04:09 PM PDT 24
Finished Aug 12 05:04:33 PM PDT 24
Peak memory 200640 kb
Host smart-910c3851-b0d0-451c-af8f-e34d3215152b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326359071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3326359071
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.1387020088
Short name T622
Test name
Test status
Simulation time 3788049251 ps
CPU time 2.21 seconds
Started Aug 12 05:03:56 PM PDT 24
Finished Aug 12 05:03:59 PM PDT 24
Peak memory 197312 kb
Host smart-00ced5ff-ddb7-4259-834d-91f46acd12b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387020088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1387020088
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1782145659
Short name T912
Test name
Test status
Simulation time 5551029598 ps
CPU time 6.69 seconds
Started Aug 12 05:04:09 PM PDT 24
Finished Aug 12 05:04:16 PM PDT 24
Peak memory 200756 kb
Host smart-e4ea64cb-1f25-4159-b30e-88da53bb1aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782145659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1782145659
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.3974458564
Short name T986
Test name
Test status
Simulation time 304713191348 ps
CPU time 123.92 seconds
Started Aug 12 05:04:09 PM PDT 24
Finished Aug 12 05:06:14 PM PDT 24
Peak memory 217064 kb
Host smart-cc9b7c2c-a15a-4510-ac11-53e40429d37a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974458564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3974458564
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.3371012754
Short name T292
Test name
Test status
Simulation time 8002157339 ps
CPU time 27.58 seconds
Started Aug 12 05:04:11 PM PDT 24
Finished Aug 12 05:04:39 PM PDT 24
Peak memory 209340 kb
Host smart-479c33d0-b76f-4fa5-be79-df232ba9950b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371012754 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.3371012754
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.2793065550
Short name T261
Test name
Test status
Simulation time 388091478 ps
CPU time 1.42 seconds
Started Aug 12 05:04:16 PM PDT 24
Finished Aug 12 05:04:18 PM PDT 24
Peak memory 198708 kb
Host smart-f0a21d01-3912-4264-a89f-b8399307bf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793065550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2793065550
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2515206702
Short name T729
Test name
Test status
Simulation time 134926936330 ps
CPU time 69.88 seconds
Started Aug 12 05:04:15 PM PDT 24
Finished Aug 12 05:05:25 PM PDT 24
Peak memory 200764 kb
Host smart-c72e3044-8fda-426e-8e93-7c8abc58d766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515206702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2515206702
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.3662501146
Short name T662
Test name
Test status
Simulation time 18051958439 ps
CPU time 13.95 seconds
Started Aug 12 05:06:28 PM PDT 24
Finished Aug 12 05:06:42 PM PDT 24
Peak memory 200816 kb
Host smart-88b838a4-57f3-4d65-a1a9-b1175c91d9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662501146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3662501146
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.438827042
Short name T1112
Test name
Test status
Simulation time 44323581533 ps
CPU time 37.49 seconds
Started Aug 12 05:06:29 PM PDT 24
Finished Aug 12 05:07:06 PM PDT 24
Peak memory 200736 kb
Host smart-d907c98d-f6ca-48c1-bbc9-cc9f6b708d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438827042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.438827042
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3313986353
Short name T206
Test name
Test status
Simulation time 141656332757 ps
CPU time 19.43 seconds
Started Aug 12 05:06:27 PM PDT 24
Finished Aug 12 05:06:47 PM PDT 24
Peak memory 200688 kb
Host smart-693e4470-faf7-4e56-ab99-804d18004780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313986353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3313986353
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.547916701
Short name T1159
Test name
Test status
Simulation time 41730095128 ps
CPU time 19.55 seconds
Started Aug 12 05:06:32 PM PDT 24
Finished Aug 12 05:06:52 PM PDT 24
Peak memory 200764 kb
Host smart-cbb998a7-4b72-43a5-9463-a6d89569c7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547916701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.547916701
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.889047191
Short name T192
Test name
Test status
Simulation time 34713257216 ps
CPU time 30.61 seconds
Started Aug 12 05:06:34 PM PDT 24
Finished Aug 12 05:07:05 PM PDT 24
Peak memory 200804 kb
Host smart-00e64016-daad-4910-a82e-fd3581a237ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889047191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.889047191
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.2947175446
Short name T536
Test name
Test status
Simulation time 32494672133 ps
CPU time 53.99 seconds
Started Aug 12 05:06:36 PM PDT 24
Finished Aug 12 05:07:30 PM PDT 24
Peak memory 200676 kb
Host smart-9f26d6f1-a6ab-4648-8cf0-5f1455ef7ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947175446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2947175446
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1610402203
Short name T1094
Test name
Test status
Simulation time 61828045589 ps
CPU time 105.58 seconds
Started Aug 12 05:06:36 PM PDT 24
Finished Aug 12 05:08:21 PM PDT 24
Peak memory 200832 kb
Host smart-7fd4d551-d8f3-4b64-8b2b-371860a04c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610402203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1610402203
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.1393285082
Short name T481
Test name
Test status
Simulation time 23782179860 ps
CPU time 40.93 seconds
Started Aug 12 05:06:34 PM PDT 24
Finished Aug 12 05:07:15 PM PDT 24
Peak memory 200604 kb
Host smart-538e329f-8518-4ff0-83e9-93a0bd528999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393285082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1393285082
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1758837388
Short name T589
Test name
Test status
Simulation time 165765123725 ps
CPU time 20.4 seconds
Started Aug 12 05:06:35 PM PDT 24
Finished Aug 12 05:06:56 PM PDT 24
Peak memory 200720 kb
Host smart-7990a013-fa4c-41cc-8fcb-8f82c8fac479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758837388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1758837388
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.1588675326
Short name T1066
Test name
Test status
Simulation time 11978239 ps
CPU time 0.58 seconds
Started Aug 12 05:04:02 PM PDT 24
Finished Aug 12 05:04:03 PM PDT 24
Peak memory 196024 kb
Host smart-50cc421d-9658-4a37-83f0-1107aa272f90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588675326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1588675326
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.4140450316
Short name T129
Test name
Test status
Simulation time 103211483518 ps
CPU time 40.9 seconds
Started Aug 12 05:04:08 PM PDT 24
Finished Aug 12 05:04:49 PM PDT 24
Peak memory 200680 kb
Host smart-d351e8a4-8aec-4dca-a7c2-f54a11c5b13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140450316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.4140450316
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2577141625
Short name T545
Test name
Test status
Simulation time 154275204292 ps
CPU time 159.82 seconds
Started Aug 12 05:04:01 PM PDT 24
Finished Aug 12 05:06:41 PM PDT 24
Peak memory 200684 kb
Host smart-6c3105ed-7c42-4d24-9655-5f55e6159978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577141625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2577141625
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_intr.558356750
Short name T578
Test name
Test status
Simulation time 14752400836 ps
CPU time 25.95 seconds
Started Aug 12 05:04:00 PM PDT 24
Finished Aug 12 05:04:26 PM PDT 24
Peak memory 200616 kb
Host smart-2c743e94-a678-479f-bb1c-4d1bf17b9b9d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558356750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.558356750
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.137418252
Short name T1080
Test name
Test status
Simulation time 159206614905 ps
CPU time 172.17 seconds
Started Aug 12 05:04:01 PM PDT 24
Finished Aug 12 05:06:53 PM PDT 24
Peak memory 200744 kb
Host smart-ca5931a5-34ef-4dbf-be86-9f86c8f045d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=137418252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.137418252
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3850484831
Short name T981
Test name
Test status
Simulation time 3214508750 ps
CPU time 5.45 seconds
Started Aug 12 05:04:02 PM PDT 24
Finished Aug 12 05:04:08 PM PDT 24
Peak memory 197936 kb
Host smart-97e2c210-2c4d-4295-8152-4fd6939b99be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850484831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3850484831
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.262822903
Short name T730
Test name
Test status
Simulation time 9754168103 ps
CPU time 17.5 seconds
Started Aug 12 05:04:10 PM PDT 24
Finished Aug 12 05:04:27 PM PDT 24
Peak memory 200744 kb
Host smart-f0e7cd2f-12fc-4b95-9ea3-c56209bd5901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262822903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.262822903
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.1303779493
Short name T854
Test name
Test status
Simulation time 16472907417 ps
CPU time 135.68 seconds
Started Aug 12 05:04:08 PM PDT 24
Finished Aug 12 05:06:24 PM PDT 24
Peak memory 200680 kb
Host smart-ef9f4fa1-600a-48e4-8eab-441ae8d12e69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1303779493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1303779493
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.4182555997
Short name T1140
Test name
Test status
Simulation time 2240951966 ps
CPU time 4.14 seconds
Started Aug 12 05:04:05 PM PDT 24
Finished Aug 12 05:04:09 PM PDT 24
Peak memory 198056 kb
Host smart-0bafa46f-696d-48e7-b7e1-e17036f40f60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182555997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.4182555997
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2678948370
Short name T881
Test name
Test status
Simulation time 58408639882 ps
CPU time 31.77 seconds
Started Aug 12 05:04:12 PM PDT 24
Finished Aug 12 05:04:44 PM PDT 24
Peak memory 200712 kb
Host smart-52dcf1e1-d51b-46a5-8a08-fb99ad52c776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678948370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2678948370
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.517880246
Short name T898
Test name
Test status
Simulation time 4884320819 ps
CPU time 2.61 seconds
Started Aug 12 05:04:14 PM PDT 24
Finished Aug 12 05:04:17 PM PDT 24
Peak memory 197056 kb
Host smart-207e0eea-cf8d-4e1e-b1b6-063892aa2d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517880246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.517880246
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.459808878
Short name T663
Test name
Test status
Simulation time 293502949 ps
CPU time 1.07 seconds
Started Aug 12 05:04:11 PM PDT 24
Finished Aug 12 05:04:12 PM PDT 24
Peak memory 199028 kb
Host smart-e08b8532-69d3-4d10-a07c-8a6676395eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459808878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.459808878
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.2634215791
Short name T439
Test name
Test status
Simulation time 456385933038 ps
CPU time 824.28 seconds
Started Aug 12 05:04:13 PM PDT 24
Finished Aug 12 05:17:58 PM PDT 24
Peak memory 200684 kb
Host smart-a5ccd591-8e53-406f-af8c-94dc52ea872b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634215791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2634215791
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.2300679916
Short name T492
Test name
Test status
Simulation time 17725027828 ps
CPU time 46.31 seconds
Started Aug 12 05:04:19 PM PDT 24
Finished Aug 12 05:05:06 PM PDT 24
Peak memory 217324 kb
Host smart-55c4109f-4264-4107-9217-e985394f7bdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300679916 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.2300679916
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.3672715135
Short name T281
Test name
Test status
Simulation time 653412094 ps
CPU time 1.34 seconds
Started Aug 12 05:04:02 PM PDT 24
Finished Aug 12 05:04:04 PM PDT 24
Peak memory 199148 kb
Host smart-5a78a156-bc3e-4a88-b149-37a6650b9d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672715135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3672715135
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3047925731
Short name T294
Test name
Test status
Simulation time 42949811524 ps
CPU time 30.21 seconds
Started Aug 12 05:04:13 PM PDT 24
Finished Aug 12 05:04:44 PM PDT 24
Peak memory 200656 kb
Host smart-9670e48d-0ebe-428a-acd2-cbd469c7182e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047925731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3047925731
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3018090065
Short name T656
Test name
Test status
Simulation time 21981224681 ps
CPU time 29.72 seconds
Started Aug 12 05:06:36 PM PDT 24
Finished Aug 12 05:07:06 PM PDT 24
Peak memory 200744 kb
Host smart-8c31f6ac-e6c6-4134-a24d-aff951329f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018090065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3018090065
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2350698800
Short name T723
Test name
Test status
Simulation time 122651505687 ps
CPU time 132.47 seconds
Started Aug 12 05:06:46 PM PDT 24
Finished Aug 12 05:08:59 PM PDT 24
Peak memory 200856 kb
Host smart-7dd43700-b996-4a81-a6f1-99c7509731b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350698800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2350698800
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1704772687
Short name T170
Test name
Test status
Simulation time 156732514952 ps
CPU time 75.21 seconds
Started Aug 12 05:06:34 PM PDT 24
Finished Aug 12 05:07:50 PM PDT 24
Peak memory 200676 kb
Host smart-57129c23-4425-4e45-b7dd-87a991515eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704772687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1704772687
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.666985558
Short name T798
Test name
Test status
Simulation time 38922545662 ps
CPU time 62.57 seconds
Started Aug 12 05:06:37 PM PDT 24
Finished Aug 12 05:07:39 PM PDT 24
Peak memory 200696 kb
Host smart-0663e5bf-1f84-47c5-945d-845734f81a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666985558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.666985558
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2612104713
Short name T460
Test name
Test status
Simulation time 67924461602 ps
CPU time 23.62 seconds
Started Aug 12 05:06:36 PM PDT 24
Finished Aug 12 05:07:00 PM PDT 24
Peak memory 200672 kb
Host smart-fb3e1094-86b1-4696-9134-9b7cdc80be00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612104713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2612104713
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.2914369770
Short name T472
Test name
Test status
Simulation time 11858849098 ps
CPU time 11.42 seconds
Started Aug 12 05:06:34 PM PDT 24
Finished Aug 12 05:06:46 PM PDT 24
Peak memory 200604 kb
Host smart-a0badb04-1a91-4d21-9438-b8e28affb9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914369770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2914369770
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.990408039
Short name T949
Test name
Test status
Simulation time 114888535745 ps
CPU time 207.5 seconds
Started Aug 12 05:06:34 PM PDT 24
Finished Aug 12 05:10:02 PM PDT 24
Peak memory 200760 kb
Host smart-f16387ec-1357-44ee-b89e-39928d2a199b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990408039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.990408039
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1629164201
Short name T673
Test name
Test status
Simulation time 35316902 ps
CPU time 0.57 seconds
Started Aug 12 05:04:17 PM PDT 24
Finished Aug 12 05:04:18 PM PDT 24
Peak memory 196020 kb
Host smart-820e441f-7857-472a-967c-4d3fe2fe10a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629164201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1629164201
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.872765310
Short name T868
Test name
Test status
Simulation time 129963193762 ps
CPU time 62.36 seconds
Started Aug 12 05:04:19 PM PDT 24
Finished Aug 12 05:05:21 PM PDT 24
Peak memory 200740 kb
Host smart-0499b903-9eb3-46e4-99b9-24d5c5d9068c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872765310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.872765310
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2056677851
Short name T542
Test name
Test status
Simulation time 8057884517 ps
CPU time 14.94 seconds
Started Aug 12 05:04:09 PM PDT 24
Finished Aug 12 05:04:24 PM PDT 24
Peak memory 200632 kb
Host smart-bb7afecc-37de-4647-a730-db7a14e8cb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056677851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2056677851
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.415754033
Short name T262
Test name
Test status
Simulation time 41058310973 ps
CPU time 36.4 seconds
Started Aug 12 05:04:09 PM PDT 24
Finished Aug 12 05:04:45 PM PDT 24
Peak memory 200688 kb
Host smart-cf3ccfe2-e97b-4835-8d60-83e7a69019b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415754033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.415754033
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.1319407131
Short name T608
Test name
Test status
Simulation time 51234229982 ps
CPU time 80.76 seconds
Started Aug 12 05:04:08 PM PDT 24
Finished Aug 12 05:05:29 PM PDT 24
Peak memory 200744 kb
Host smart-1b379625-554f-42d4-a6b5-d9d7f48a9f2e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319407131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1319407131
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1726862866
Short name T774
Test name
Test status
Simulation time 172794270817 ps
CPU time 575.02 seconds
Started Aug 12 05:04:05 PM PDT 24
Finished Aug 12 05:13:40 PM PDT 24
Peak memory 200728 kb
Host smart-a68e2ae0-4f03-4afb-89d3-e022caadfe38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1726862866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1726862866
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.368540899
Short name T541
Test name
Test status
Simulation time 6339145176 ps
CPU time 7.63 seconds
Started Aug 12 05:04:05 PM PDT 24
Finished Aug 12 05:04:13 PM PDT 24
Peak memory 200744 kb
Host smart-c1a8098f-c556-4b33-9290-6cf1c4a5c7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368540899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.368540899
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1071580995
Short name T365
Test name
Test status
Simulation time 95086370670 ps
CPU time 36.45 seconds
Started Aug 12 05:04:04 PM PDT 24
Finished Aug 12 05:04:40 PM PDT 24
Peak memory 199564 kb
Host smart-00f86631-474e-4a06-9c93-ad4a0db3944a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071580995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1071580995
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2745947227
Short name T896
Test name
Test status
Simulation time 15660655650 ps
CPU time 452.26 seconds
Started Aug 12 05:04:09 PM PDT 24
Finished Aug 12 05:11:41 PM PDT 24
Peak memory 200760 kb
Host smart-a5c6cb56-9826-4af0-9666-beddd1393e23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2745947227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2745947227
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.814314577
Short name T957
Test name
Test status
Simulation time 7320743579 ps
CPU time 20.82 seconds
Started Aug 12 05:04:16 PM PDT 24
Finished Aug 12 05:04:37 PM PDT 24
Peak memory 198960 kb
Host smart-9c442e36-9037-4113-9843-0e48f8394205
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=814314577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.814314577
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1283737019
Short name T570
Test name
Test status
Simulation time 73199761960 ps
CPU time 169.45 seconds
Started Aug 12 05:04:07 PM PDT 24
Finished Aug 12 05:06:57 PM PDT 24
Peak memory 200488 kb
Host smart-24861820-18ea-4cc1-bb84-961683416d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283737019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1283737019
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.1864534123
Short name T606
Test name
Test status
Simulation time 6440548604 ps
CPU time 5.27 seconds
Started Aug 12 05:04:25 PM PDT 24
Finished Aug 12 05:04:30 PM PDT 24
Peak memory 196908 kb
Host smart-d87009d4-b92f-471f-9a42-cf1d772186f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864534123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.1864534123
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.3105157441
Short name T851
Test name
Test status
Simulation time 956462856 ps
CPU time 1.47 seconds
Started Aug 12 05:04:04 PM PDT 24
Finished Aug 12 05:04:06 PM PDT 24
Peak memory 200728 kb
Host smart-d28f70c1-5c21-4820-8521-7cc114eff5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105157441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3105157441
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.530727331
Short name T503
Test name
Test status
Simulation time 82723119720 ps
CPU time 133.87 seconds
Started Aug 12 05:04:09 PM PDT 24
Finished Aug 12 05:06:23 PM PDT 24
Peak memory 200600 kb
Host smart-6d44e976-0186-414c-9b71-f313bf1f74ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530727331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.530727331
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2855650874
Short name T523
Test name
Test status
Simulation time 3750805805 ps
CPU time 17.72 seconds
Started Aug 12 05:04:13 PM PDT 24
Finished Aug 12 05:04:31 PM PDT 24
Peak memory 216732 kb
Host smart-93d144d0-555c-4058-b212-ab0739fb9e7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855650874 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2855650874
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1582148543
Short name T273
Test name
Test status
Simulation time 1117038468 ps
CPU time 3.23 seconds
Started Aug 12 05:04:08 PM PDT 24
Finished Aug 12 05:04:12 PM PDT 24
Peak memory 200604 kb
Host smart-aafa3fda-352b-424c-b219-b15a4bef6c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582148543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1582148543
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.4093228646
Short name T1042
Test name
Test status
Simulation time 38326001399 ps
CPU time 72.02 seconds
Started Aug 12 05:04:14 PM PDT 24
Finished Aug 12 05:05:26 PM PDT 24
Peak memory 200772 kb
Host smart-feee263b-e7f5-4575-ab35-4791177db63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093228646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.4093228646
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.2455585476
Short name T182
Test name
Test status
Simulation time 70999926750 ps
CPU time 99.44 seconds
Started Aug 12 05:06:36 PM PDT 24
Finished Aug 12 05:08:15 PM PDT 24
Peak memory 200828 kb
Host smart-e59861c0-9f9e-4865-b296-33ec4c0fae95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455585476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2455585476
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.2839127546
Short name T1149
Test name
Test status
Simulation time 147259227025 ps
CPU time 39.11 seconds
Started Aug 12 05:06:36 PM PDT 24
Finished Aug 12 05:07:16 PM PDT 24
Peak memory 200676 kb
Host smart-8d7eca6f-1f0a-4867-a3f7-309ffe7b22b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839127546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2839127546
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.4100974560
Short name T1111
Test name
Test status
Simulation time 63477321609 ps
CPU time 89.21 seconds
Started Aug 12 05:06:35 PM PDT 24
Finished Aug 12 05:08:05 PM PDT 24
Peak memory 200640 kb
Host smart-f8b240ed-2648-44ac-836d-3586b30b2a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100974560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.4100974560
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3875253911
Short name T712
Test name
Test status
Simulation time 9203414524 ps
CPU time 13.52 seconds
Started Aug 12 05:06:36 PM PDT 24
Finished Aug 12 05:06:49 PM PDT 24
Peak memory 200684 kb
Host smart-df10b6fe-ff7a-4d1b-888d-021496df0f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875253911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3875253911
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.1606297488
Short name T453
Test name
Test status
Simulation time 21602851692 ps
CPU time 54.69 seconds
Started Aug 12 05:06:36 PM PDT 24
Finished Aug 12 05:07:31 PM PDT 24
Peak memory 200828 kb
Host smart-2f73a64d-22e7-4880-bd47-395d02de861a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606297488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.1606297488
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.4252341128
Short name T635
Test name
Test status
Simulation time 47152735469 ps
CPU time 13.59 seconds
Started Aug 12 05:06:35 PM PDT 24
Finished Aug 12 05:06:49 PM PDT 24
Peak memory 200768 kb
Host smart-804fb16f-45b9-4a60-91bd-d416a0e2ea21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252341128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.4252341128
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1198192716
Short name T325
Test name
Test status
Simulation time 518271395062 ps
CPU time 68.56 seconds
Started Aug 12 05:06:41 PM PDT 24
Finished Aug 12 05:07:50 PM PDT 24
Peak memory 200668 kb
Host smart-4f6f44be-bb8a-4871-9a45-c4a247782752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198192716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1198192716
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2020768883
Short name T1181
Test name
Test status
Simulation time 17706338439 ps
CPU time 15.39 seconds
Started Aug 12 05:06:43 PM PDT 24
Finished Aug 12 05:06:58 PM PDT 24
Peak memory 200828 kb
Host smart-0751aa4a-507b-47bf-b27f-2f33b94cdb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020768883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2020768883
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2137326819
Short name T519
Test name
Test status
Simulation time 45128562 ps
CPU time 0.56 seconds
Started Aug 12 05:04:21 PM PDT 24
Finished Aug 12 05:04:21 PM PDT 24
Peak memory 195972 kb
Host smart-7804996f-2254-439b-8303-afc0aa660a43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137326819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2137326819
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.962161079
Short name T1019
Test name
Test status
Simulation time 57076055755 ps
CPU time 18.85 seconds
Started Aug 12 05:04:16 PM PDT 24
Finished Aug 12 05:04:35 PM PDT 24
Peak memory 199904 kb
Host smart-d2a99a88-2ddb-449e-bf41-11328f47228a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962161079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.962161079
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1302571071
Short name T684
Test name
Test status
Simulation time 35966927311 ps
CPU time 39.71 seconds
Started Aug 12 05:04:13 PM PDT 24
Finished Aug 12 05:04:53 PM PDT 24
Peak memory 200660 kb
Host smart-e6c37e15-2594-4111-b680-b3337795e1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302571071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1302571071
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1781960522
Short name T324
Test name
Test status
Simulation time 28915248363 ps
CPU time 25.46 seconds
Started Aug 12 05:04:17 PM PDT 24
Finished Aug 12 05:04:43 PM PDT 24
Peak memory 200744 kb
Host smart-71dedcd1-f9b3-46d2-a9df-ecbf23820991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781960522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1781960522
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.3087525125
Short name T1162
Test name
Test status
Simulation time 76159608126 ps
CPU time 120.02 seconds
Started Aug 12 05:04:03 PM PDT 24
Finished Aug 12 05:06:03 PM PDT 24
Peak memory 200772 kb
Host smart-8dc51436-4a09-4112-9794-2453282fd319
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087525125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3087525125
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1872824634
Short name T406
Test name
Test status
Simulation time 110829884668 ps
CPU time 626.87 seconds
Started Aug 12 05:04:09 PM PDT 24
Finished Aug 12 05:14:36 PM PDT 24
Peak memory 200736 kb
Host smart-e11a992f-3704-416c-aec0-3ce8bf0d59d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1872824634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1872824634
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.4178090425
Short name T1173
Test name
Test status
Simulation time 1621929706 ps
CPU time 1.7 seconds
Started Aug 12 05:04:03 PM PDT 24
Finished Aug 12 05:04:05 PM PDT 24
Peak memory 199348 kb
Host smart-562a49b9-e9ba-486a-b75e-8cedad48668e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178090425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.4178090425
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.5346944
Short name T290
Test name
Test status
Simulation time 204573231756 ps
CPU time 85.3 seconds
Started Aug 12 05:04:14 PM PDT 24
Finished Aug 12 05:05:39 PM PDT 24
Peak memory 201052 kb
Host smart-b4a42f89-93f2-46af-8204-345e804a1561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5346944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.5346944
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.1057197515
Short name T711
Test name
Test status
Simulation time 22809225660 ps
CPU time 1318.75 seconds
Started Aug 12 05:04:06 PM PDT 24
Finished Aug 12 05:26:05 PM PDT 24
Peak memory 200740 kb
Host smart-fdf4424b-d425-43ac-934a-a05657769479
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1057197515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1057197515
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.342386034
Short name T349
Test name
Test status
Simulation time 4751238616 ps
CPU time 20.02 seconds
Started Aug 12 05:04:21 PM PDT 24
Finished Aug 12 05:04:41 PM PDT 24
Peak memory 198692 kb
Host smart-aa6bb1bd-23d1-47f9-ad1f-4c4256e6e84c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=342386034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.342386034
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.3810438623
Short name T699
Test name
Test status
Simulation time 39930060580 ps
CPU time 21.69 seconds
Started Aug 12 05:04:06 PM PDT 24
Finished Aug 12 05:04:28 PM PDT 24
Peak memory 200732 kb
Host smart-0819237f-8dd3-460c-8a8e-93bd094d34c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810438623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3810438623
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.894669496
Short name T1103
Test name
Test status
Simulation time 3169373169 ps
CPU time 1.87 seconds
Started Aug 12 05:04:09 PM PDT 24
Finished Aug 12 05:04:11 PM PDT 24
Peak memory 196672 kb
Host smart-32c363e3-80c7-4262-bed3-99e3181e30de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894669496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.894669496
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.472493312
Short name T782
Test name
Test status
Simulation time 467472798 ps
CPU time 1.73 seconds
Started Aug 12 05:04:08 PM PDT 24
Finished Aug 12 05:04:10 PM PDT 24
Peak memory 199068 kb
Host smart-e841b6bc-c180-44b2-b18e-0a6142702c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472493312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.472493312
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.3307613716
Short name T763
Test name
Test status
Simulation time 114745040038 ps
CPU time 184.82 seconds
Started Aug 12 05:04:20 PM PDT 24
Finished Aug 12 05:07:25 PM PDT 24
Peak memory 200872 kb
Host smart-b56387a1-d10f-48ba-96c8-8a7ca3019fa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307613716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3307613716
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.4162920114
Short name T886
Test name
Test status
Simulation time 295389027 ps
CPU time 1.51 seconds
Started Aug 12 05:04:08 PM PDT 24
Finished Aug 12 05:04:09 PM PDT 24
Peak memory 199156 kb
Host smart-0a36bfac-8fe1-477a-b349-4a71584bf051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162920114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.4162920114
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1699104500
Short name T973
Test name
Test status
Simulation time 60826824843 ps
CPU time 103.17 seconds
Started Aug 12 05:04:06 PM PDT 24
Finished Aug 12 05:05:49 PM PDT 24
Peak memory 200792 kb
Host smart-59d25a67-f8de-4309-9a21-e51039f60ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699104500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1699104500
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.4101150367
Short name T688
Test name
Test status
Simulation time 29847063438 ps
CPU time 28.26 seconds
Started Aug 12 05:06:42 PM PDT 24
Finished Aug 12 05:07:10 PM PDT 24
Peak memory 200796 kb
Host smart-39cd7e29-a81e-4ea5-a012-4738e26fe0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101150367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.4101150367
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.1153106432
Short name T12
Test name
Test status
Simulation time 158272699313 ps
CPU time 184.44 seconds
Started Aug 12 05:06:44 PM PDT 24
Finished Aug 12 05:09:48 PM PDT 24
Peak memory 200644 kb
Host smart-0b02498e-e4f3-47d1-8fb9-a6d4b8ccecea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153106432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.1153106432
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.3553165471
Short name T1096
Test name
Test status
Simulation time 120079625170 ps
CPU time 108.63 seconds
Started Aug 12 05:06:46 PM PDT 24
Finished Aug 12 05:08:35 PM PDT 24
Peak memory 200760 kb
Host smart-c087ad14-0093-47dd-9bff-65702af6fe84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553165471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3553165471
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3329097055
Short name T919
Test name
Test status
Simulation time 75132807021 ps
CPU time 64.65 seconds
Started Aug 12 05:06:46 PM PDT 24
Finished Aug 12 05:07:50 PM PDT 24
Peak memory 200820 kb
Host smart-79735720-9b67-4337-b29e-5f7b846fdf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329097055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3329097055
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.2935021629
Short name T647
Test name
Test status
Simulation time 105624549875 ps
CPU time 101.68 seconds
Started Aug 12 05:06:45 PM PDT 24
Finished Aug 12 05:08:26 PM PDT 24
Peak memory 200708 kb
Host smart-fa46feb9-8bda-4b02-9b0f-87c78d76b09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935021629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2935021629
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1023867512
Short name T171
Test name
Test status
Simulation time 49316054171 ps
CPU time 43.14 seconds
Started Aug 12 05:06:42 PM PDT 24
Finished Aug 12 05:07:25 PM PDT 24
Peak memory 200784 kb
Host smart-d8406562-bce6-476e-ab3a-1d4232a1619e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023867512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1023867512
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1552383764
Short name T612
Test name
Test status
Simulation time 120601183180 ps
CPU time 75.39 seconds
Started Aug 12 05:06:43 PM PDT 24
Finished Aug 12 05:07:59 PM PDT 24
Peak memory 200732 kb
Host smart-c5283ad2-1dfd-45b9-83c6-33702cdb086b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552383764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1552383764
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.3777462738
Short name T883
Test name
Test status
Simulation time 30043820553 ps
CPU time 84.96 seconds
Started Aug 12 05:06:46 PM PDT 24
Finished Aug 12 05:08:11 PM PDT 24
Peak memory 200760 kb
Host smart-71065833-15da-4ff3-9323-1f54c236e4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777462738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.3777462738
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.296365391
Short name T315
Test name
Test status
Simulation time 31558002274 ps
CPU time 24.06 seconds
Started Aug 12 05:06:43 PM PDT 24
Finished Aug 12 05:07:07 PM PDT 24
Peak memory 199540 kb
Host smart-783c6cf5-8eb8-467a-b7e6-33cdf3a2e890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296365391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.296365391
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1353392663
Short name T732
Test name
Test status
Simulation time 35801751 ps
CPU time 0.53 seconds
Started Aug 12 05:04:21 PM PDT 24
Finished Aug 12 05:04:21 PM PDT 24
Peak memory 196104 kb
Host smart-6d84635b-20aa-4b86-b889-e86d8880b5f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353392663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1353392663
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.16725925
Short name T1119
Test name
Test status
Simulation time 123775535960 ps
CPU time 66.65 seconds
Started Aug 12 05:04:08 PM PDT 24
Finished Aug 12 05:05:15 PM PDT 24
Peak memory 200736 kb
Host smart-e05fed54-2bf8-4e77-a610-60c102753860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16725925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.16725925
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2956389482
Short name T849
Test name
Test status
Simulation time 40360652857 ps
CPU time 65.11 seconds
Started Aug 12 05:04:08 PM PDT 24
Finished Aug 12 05:05:13 PM PDT 24
Peak memory 200644 kb
Host smart-d74adf89-753d-4d74-9e74-60f056c65f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956389482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2956389482
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.120490971
Short name T353
Test name
Test status
Simulation time 27460034274 ps
CPU time 11.5 seconds
Started Aug 12 05:04:12 PM PDT 24
Finished Aug 12 05:04:23 PM PDT 24
Peak memory 199164 kb
Host smart-d8c5865b-6cad-4624-81b0-6c63247c5e67
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120490971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.120490971
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.1789216382
Short name T1137
Test name
Test status
Simulation time 121353117687 ps
CPU time 450.45 seconds
Started Aug 12 05:04:19 PM PDT 24
Finished Aug 12 05:11:50 PM PDT 24
Peak memory 200768 kb
Host smart-adc538cd-5bfb-437d-9c30-5ca5897a88b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1789216382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1789216382
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.4056540801
Short name T512
Test name
Test status
Simulation time 12014473841 ps
CPU time 12.05 seconds
Started Aug 12 05:04:19 PM PDT 24
Finished Aug 12 05:04:31 PM PDT 24
Peak memory 200572 kb
Host smart-c2677cca-2300-40bc-94b5-0e681e59cac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056540801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.4056540801
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.3212329128
Short name T300
Test name
Test status
Simulation time 76471270467 ps
CPU time 138.34 seconds
Started Aug 12 05:04:17 PM PDT 24
Finished Aug 12 05:06:36 PM PDT 24
Peak memory 216640 kb
Host smart-1e79c345-1a53-4c28-a2d9-f7398d9f7fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212329128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3212329128
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.2627903543
Short name T977
Test name
Test status
Simulation time 14678004052 ps
CPU time 377.38 seconds
Started Aug 12 05:04:16 PM PDT 24
Finished Aug 12 05:10:34 PM PDT 24
Peak memory 200832 kb
Host smart-ca621908-bb58-4da1-8257-a62c5e2abd3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2627903543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2627903543
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2181882053
Short name T1100
Test name
Test status
Simulation time 6379491064 ps
CPU time 12.49 seconds
Started Aug 12 05:04:17 PM PDT 24
Finished Aug 12 05:04:30 PM PDT 24
Peak memory 198996 kb
Host smart-1eb186ac-b94d-4010-a47f-d59458abda66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2181882053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2181882053
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.2988986117
Short name T668
Test name
Test status
Simulation time 45989685266 ps
CPU time 39.3 seconds
Started Aug 12 05:04:12 PM PDT 24
Finished Aug 12 05:04:51 PM PDT 24
Peak memory 200760 kb
Host smart-f6208e14-191d-4d0b-b753-64c6671f46df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988986117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2988986117
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.1436027232
Short name T354
Test name
Test status
Simulation time 553797039 ps
CPU time 1.44 seconds
Started Aug 12 05:04:15 PM PDT 24
Finished Aug 12 05:04:16 PM PDT 24
Peak memory 196348 kb
Host smart-cfad0f34-5492-40a1-8fc6-3eada2167472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436027232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1436027232
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1852839083
Short name T835
Test name
Test status
Simulation time 105240754 ps
CPU time 0.88 seconds
Started Aug 12 05:04:06 PM PDT 24
Finished Aug 12 05:04:06 PM PDT 24
Peak memory 198564 kb
Host smart-64af37ad-6359-4ad5-a752-0c051634656b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852839083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1852839083
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.3450051532
Short name T154
Test name
Test status
Simulation time 278171995058 ps
CPU time 283.73 seconds
Started Aug 12 05:04:10 PM PDT 24
Finished Aug 12 05:08:54 PM PDT 24
Peak memory 200824 kb
Host smart-cf4e0905-54e9-4ef9-811b-907ca7292961
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450051532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3450051532
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2798328269
Short name T619
Test name
Test status
Simulation time 902078645 ps
CPU time 12.48 seconds
Started Aug 12 05:04:15 PM PDT 24
Finished Aug 12 05:04:27 PM PDT 24
Peak memory 200748 kb
Host smart-7fa92a65-bf63-40eb-8966-9b67c097e229
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798328269 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2798328269
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.624017952
Short name T468
Test name
Test status
Simulation time 1201508544 ps
CPU time 2.08 seconds
Started Aug 12 05:04:12 PM PDT 24
Finished Aug 12 05:04:14 PM PDT 24
Peak memory 199160 kb
Host smart-624b153d-7dde-43f8-9bff-7ab80f8fb212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624017952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.624017952
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.985826563
Short name T889
Test name
Test status
Simulation time 177485763592 ps
CPU time 73.73 seconds
Started Aug 12 05:04:13 PM PDT 24
Finished Aug 12 05:05:27 PM PDT 24
Peak memory 200796 kb
Host smart-b803a326-1b9a-4cdc-a94f-7d5872f5178d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985826563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.985826563
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.3074295221
Short name T838
Test name
Test status
Simulation time 18696767402 ps
CPU time 36.52 seconds
Started Aug 12 05:06:44 PM PDT 24
Finished Aug 12 05:07:21 PM PDT 24
Peak memory 200784 kb
Host smart-94993e66-56f8-45ee-89f3-3a4449c55b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074295221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3074295221
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.1831950378
Short name T197
Test name
Test status
Simulation time 15205312211 ps
CPU time 30.11 seconds
Started Aug 12 05:06:42 PM PDT 24
Finished Aug 12 05:07:12 PM PDT 24
Peak memory 200740 kb
Host smart-34ea4b63-c794-40f9-9185-95f990e034d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831950378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1831950378
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.465954212
Short name T685
Test name
Test status
Simulation time 131043156549 ps
CPU time 195.54 seconds
Started Aug 12 05:06:42 PM PDT 24
Finished Aug 12 05:09:58 PM PDT 24
Peak memory 200672 kb
Host smart-8080d568-1b66-4a9f-945f-a53b88a36457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465954212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.465954212
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.615865547
Short name T931
Test name
Test status
Simulation time 23789579507 ps
CPU time 14.99 seconds
Started Aug 12 05:06:44 PM PDT 24
Finished Aug 12 05:06:59 PM PDT 24
Peak memory 200664 kb
Host smart-80ce696d-6c78-4d15-93e3-df04081427f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615865547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.615865547
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3699209122
Short name T722
Test name
Test status
Simulation time 16422830114 ps
CPU time 9.62 seconds
Started Aug 12 05:06:41 PM PDT 24
Finished Aug 12 05:06:51 PM PDT 24
Peak memory 200804 kb
Host smart-c45c6f29-64bf-4b92-8ffb-6826bae876a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699209122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3699209122
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.3116765435
Short name T1031
Test name
Test status
Simulation time 12337767703 ps
CPU time 30.25 seconds
Started Aug 12 05:06:42 PM PDT 24
Finished Aug 12 05:07:12 PM PDT 24
Peak memory 200772 kb
Host smart-c62efd70-0700-4067-b5f7-c5f308e34cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116765435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3116765435
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.764653599
Short name T1081
Test name
Test status
Simulation time 20106940377 ps
CPU time 37.91 seconds
Started Aug 12 05:06:43 PM PDT 24
Finished Aug 12 05:07:21 PM PDT 24
Peak memory 200964 kb
Host smart-ee69ab08-a68b-49e7-a765-352f30843290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764653599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.764653599
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1018753473
Short name T1138
Test name
Test status
Simulation time 61357752761 ps
CPU time 80.05 seconds
Started Aug 12 05:06:43 PM PDT 24
Finished Aug 12 05:08:03 PM PDT 24
Peak memory 200784 kb
Host smart-2cc0595b-65f1-4fe2-9216-22d969504b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018753473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1018753473
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.405617451
Short name T951
Test name
Test status
Simulation time 225781532510 ps
CPU time 197.66 seconds
Started Aug 12 05:06:42 PM PDT 24
Finished Aug 12 05:10:00 PM PDT 24
Peak memory 200756 kb
Host smart-67d493ab-acd9-4a21-8da3-5f71b906c6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405617451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.405617451
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1121312130
Short name T1145
Test name
Test status
Simulation time 95636609824 ps
CPU time 148.96 seconds
Started Aug 12 05:06:43 PM PDT 24
Finished Aug 12 05:09:12 PM PDT 24
Peak memory 200736 kb
Host smart-6f30e28f-1e0e-4681-a833-94e6552de05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121312130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1121312130
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1444994474
Short name T336
Test name
Test status
Simulation time 16461980 ps
CPU time 0.56 seconds
Started Aug 12 05:04:22 PM PDT 24
Finished Aug 12 05:04:23 PM PDT 24
Peak memory 195096 kb
Host smart-2f72ffbf-11c7-4ebd-bcb0-d89600962571
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444994474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1444994474
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3730359527
Short name T756
Test name
Test status
Simulation time 90780196757 ps
CPU time 148.47 seconds
Started Aug 12 05:04:10 PM PDT 24
Finished Aug 12 05:06:38 PM PDT 24
Peak memory 200744 kb
Host smart-864c1dec-c8dc-4bf2-b219-cbcebbb76828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730359527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3730359527
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.4256652398
Short name T968
Test name
Test status
Simulation time 15021435054 ps
CPU time 11.89 seconds
Started Aug 12 05:04:12 PM PDT 24
Finished Aug 12 05:04:24 PM PDT 24
Peak memory 200812 kb
Host smart-4600cab6-3bab-452a-8437-a39c34e51966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256652398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.4256652398
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.2811434798
Short name T286
Test name
Test status
Simulation time 52033490055 ps
CPU time 45.24 seconds
Started Aug 12 05:04:19 PM PDT 24
Finished Aug 12 05:05:05 PM PDT 24
Peak memory 200760 kb
Host smart-445d0f7e-6f03-49b4-afc2-fd7cc1fa0e74
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811434798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2811434798
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.590183074
Short name T369
Test name
Test status
Simulation time 182204550668 ps
CPU time 1638.51 seconds
Started Aug 12 05:04:25 PM PDT 24
Finished Aug 12 05:31:43 PM PDT 24
Peak memory 200792 kb
Host smart-3ca3dd25-3a8f-4396-a585-f0a6584c3d82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=590183074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.590183074
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1472238697
Short name T736
Test name
Test status
Simulation time 7385796719 ps
CPU time 10.93 seconds
Started Aug 12 05:04:19 PM PDT 24
Finished Aug 12 05:04:30 PM PDT 24
Peak memory 199256 kb
Host smart-62bd248e-45af-40de-b5cc-e7a045b79648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472238697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1472238697
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.715533146
Short name T1188
Test name
Test status
Simulation time 199571057101 ps
CPU time 55.1 seconds
Started Aug 12 05:04:09 PM PDT 24
Finished Aug 12 05:05:04 PM PDT 24
Peak memory 210252 kb
Host smart-cc64cd95-f541-4154-a9f7-3ab9abb8ed1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715533146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.715533146
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.2796146862
Short name T1158
Test name
Test status
Simulation time 6019786857 ps
CPU time 290.5 seconds
Started Aug 12 05:04:15 PM PDT 24
Finished Aug 12 05:09:05 PM PDT 24
Peak memory 200748 kb
Host smart-d0ec0014-cb55-4d33-ac00-c7d426db2a0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2796146862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2796146862
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.1545938573
Short name T368
Test name
Test status
Simulation time 5401355970 ps
CPU time 23.14 seconds
Started Aug 12 05:04:09 PM PDT 24
Finished Aug 12 05:04:32 PM PDT 24
Peak memory 198860 kb
Host smart-633cb860-67c7-4e8b-8dd3-422203b2ae13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1545938573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1545938573
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.492589336
Short name T940
Test name
Test status
Simulation time 167176405255 ps
CPU time 12.53 seconds
Started Aug 12 05:04:10 PM PDT 24
Finished Aug 12 05:04:22 PM PDT 24
Peak memory 200296 kb
Host smart-688e3d6b-4a91-4e4a-b6f5-9de7fe6e0b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492589336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.492589336
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.3953960499
Short name T1085
Test name
Test status
Simulation time 1543851563 ps
CPU time 1.27 seconds
Started Aug 12 05:04:08 PM PDT 24
Finished Aug 12 05:04:10 PM PDT 24
Peak memory 196184 kb
Host smart-67d20ceb-216d-417e-b9a6-af80515af1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953960499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3953960499
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2917176705
Short name T491
Test name
Test status
Simulation time 6170054606 ps
CPU time 17.75 seconds
Started Aug 12 05:04:10 PM PDT 24
Finished Aug 12 05:04:27 PM PDT 24
Peak memory 199892 kb
Host smart-4569f2e2-4f06-40ab-84b3-a03665686098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917176705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2917176705
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.4226726766
Short name T448
Test name
Test status
Simulation time 507248726 ps
CPU time 8.33 seconds
Started Aug 12 05:04:09 PM PDT 24
Finished Aug 12 05:04:18 PM PDT 24
Peak memory 200888 kb
Host smart-ec9ff72c-40af-4fc1-972e-d69a403bfcb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226726766 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.4226726766
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3397579534
Short name T385
Test name
Test status
Simulation time 1260486885 ps
CPU time 2.56 seconds
Started Aug 12 05:04:22 PM PDT 24
Finished Aug 12 05:04:24 PM PDT 24
Peak memory 200676 kb
Host smart-01a5aa36-815c-424b-9c9d-fae9fa55978e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397579534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3397579534
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.4025396044
Short name T1130
Test name
Test status
Simulation time 51915851676 ps
CPU time 20.79 seconds
Started Aug 12 05:04:21 PM PDT 24
Finished Aug 12 05:04:42 PM PDT 24
Peak memory 200776 kb
Host smart-4e2d8922-fa72-4aa6-aa64-10d6cdc73899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025396044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.4025396044
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.1220400985
Short name T993
Test name
Test status
Simulation time 32328335319 ps
CPU time 59.52 seconds
Started Aug 12 05:06:43 PM PDT 24
Finished Aug 12 05:07:43 PM PDT 24
Peak memory 200744 kb
Host smart-991a83d9-040c-472e-a5b6-248cf2e1f6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220400985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1220400985
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1151330293
Short name T180
Test name
Test status
Simulation time 7312894510 ps
CPU time 3.84 seconds
Started Aug 12 05:06:42 PM PDT 24
Finished Aug 12 05:06:46 PM PDT 24
Peak memory 200808 kb
Host smart-e72deef4-ad56-4ba1-a39b-1066c86acfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151330293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1151330293
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.973566846
Short name T116
Test name
Test status
Simulation time 23967728672 ps
CPU time 17.74 seconds
Started Aug 12 05:06:41 PM PDT 24
Finished Aug 12 05:06:59 PM PDT 24
Peak memory 200820 kb
Host smart-8bd87aee-35f3-4624-a49e-64e6d121df7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973566846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.973566846
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1780528583
Short name T742
Test name
Test status
Simulation time 41673971209 ps
CPU time 36.27 seconds
Started Aug 12 05:06:43 PM PDT 24
Finished Aug 12 05:07:19 PM PDT 24
Peak memory 200740 kb
Host smart-b4edcaba-5d61-446e-b2c4-fed306eacc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780528583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1780528583
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.803030461
Short name T282
Test name
Test status
Simulation time 21626385241 ps
CPU time 26.81 seconds
Started Aug 12 05:06:47 PM PDT 24
Finished Aug 12 05:07:14 PM PDT 24
Peak memory 200792 kb
Host smart-75ec1b39-d38f-4359-9e3c-8471434c934b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803030461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.803030461
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.667676121
Short name T842
Test name
Test status
Simulation time 104155683860 ps
CPU time 79.43 seconds
Started Aug 12 05:06:47 PM PDT 24
Finished Aug 12 05:08:07 PM PDT 24
Peak memory 200756 kb
Host smart-021e942e-8813-4a02-a985-8932de7042fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667676121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.667676121
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.1470908784
Short name T121
Test name
Test status
Simulation time 24244101016 ps
CPU time 18.66 seconds
Started Aug 12 05:06:43 PM PDT 24
Finished Aug 12 05:07:02 PM PDT 24
Peak memory 200796 kb
Host smart-a5a0bab2-d816-4a71-892f-d952a8b5f9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470908784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1470908784
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.4108572968
Short name T1074
Test name
Test status
Simulation time 25406173948 ps
CPU time 16.23 seconds
Started Aug 12 05:06:47 PM PDT 24
Finished Aug 12 05:07:04 PM PDT 24
Peak memory 200756 kb
Host smart-8ecd0390-d0e6-4ae1-846e-2d4ce5921099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108572968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.4108572968
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.3406149328
Short name T330
Test name
Test status
Simulation time 28217432 ps
CPU time 0.61 seconds
Started Aug 12 05:04:26 PM PDT 24
Finished Aug 12 05:04:26 PM PDT 24
Peak memory 196444 kb
Host smart-5b385763-ba84-40d0-a5ef-dda4501882a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406149328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.3406149328
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.2345934818
Short name T502
Test name
Test status
Simulation time 60640458673 ps
CPU time 86.84 seconds
Started Aug 12 05:04:24 PM PDT 24
Finished Aug 12 05:05:51 PM PDT 24
Peak memory 200712 kb
Host smart-322116bd-728d-4ff7-a028-29a9fbb9f65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345934818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2345934818
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.2164697632
Short name T801
Test name
Test status
Simulation time 32069369239 ps
CPU time 56.11 seconds
Started Aug 12 05:04:27 PM PDT 24
Finished Aug 12 05:05:24 PM PDT 24
Peak memory 200692 kb
Host smart-c2bb0cc2-e801-4d15-9acb-1b52e5e4da68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164697632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2164697632
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.4245249885
Short name T100
Test name
Test status
Simulation time 14114980154 ps
CPU time 30.95 seconds
Started Aug 12 05:04:19 PM PDT 24
Finished Aug 12 05:04:50 PM PDT 24
Peak memory 200836 kb
Host smart-26fcf209-a9cb-40ff-beef-d4e2f14fbf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245249885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.4245249885
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.2935711018
Short name T709
Test name
Test status
Simulation time 52994554316 ps
CPU time 7.59 seconds
Started Aug 12 05:04:26 PM PDT 24
Finished Aug 12 05:04:34 PM PDT 24
Peak memory 200716 kb
Host smart-458a1f30-a5e8-4548-9436-8a22893a10d7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935711018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2935711018
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.2978500585
Short name T796
Test name
Test status
Simulation time 122161438351 ps
CPU time 652.6 seconds
Started Aug 12 05:04:21 PM PDT 24
Finished Aug 12 05:15:14 PM PDT 24
Peak memory 200716 kb
Host smart-78c8c9a0-8850-4984-9497-d338f2f58d36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2978500585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2978500585
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.3271090129
Short name T338
Test name
Test status
Simulation time 6452963890 ps
CPU time 15.32 seconds
Started Aug 12 05:04:24 PM PDT 24
Finished Aug 12 05:04:40 PM PDT 24
Peak memory 200288 kb
Host smart-6689ed6d-0e6f-4d5c-ac93-210c0ba0469f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271090129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3271090129
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.3232889497
Short name T655
Test name
Test status
Simulation time 31204051033 ps
CPU time 53.14 seconds
Started Aug 12 05:04:23 PM PDT 24
Finished Aug 12 05:05:16 PM PDT 24
Peak memory 201028 kb
Host smart-72bdca40-a42c-4773-94cc-23a374d75121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232889497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.3232889497
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.839845820
Short name T648
Test name
Test status
Simulation time 8743380490 ps
CPU time 84.92 seconds
Started Aug 12 05:04:24 PM PDT 24
Finished Aug 12 05:05:49 PM PDT 24
Peak memory 200784 kb
Host smart-a1cc7042-de16-407e-b8c1-779d9f3e7177
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=839845820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.839845820
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1839215196
Short name T1186
Test name
Test status
Simulation time 2101013860 ps
CPU time 6.12 seconds
Started Aug 12 05:04:22 PM PDT 24
Finished Aug 12 05:04:29 PM PDT 24
Peak memory 198680 kb
Host smart-5ef2674f-29c6-415c-94b9-cb2ff930e857
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1839215196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1839215196
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2177799877
Short name T1116
Test name
Test status
Simulation time 79671929867 ps
CPU time 32.23 seconds
Started Aug 12 05:04:17 PM PDT 24
Finished Aug 12 05:04:49 PM PDT 24
Peak memory 200740 kb
Host smart-c12dbc4f-f263-4517-b25f-ce066b8e5e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177799877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2177799877
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3329059029
Short name T410
Test name
Test status
Simulation time 6887289946 ps
CPU time 10.05 seconds
Started Aug 12 05:04:25 PM PDT 24
Finished Aug 12 05:04:35 PM PDT 24
Peak memory 197192 kb
Host smart-62c50d9e-b66a-4960-b92c-5dca1178dcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329059029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3329059029
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.3015435272
Short name T795
Test name
Test status
Simulation time 124475657 ps
CPU time 1.03 seconds
Started Aug 12 05:04:11 PM PDT 24
Finished Aug 12 05:04:12 PM PDT 24
Peak memory 197904 kb
Host smart-a3949dd7-7588-450e-912a-906ff7d0a838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015435272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3015435272
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1759586966
Short name T151
Test name
Test status
Simulation time 329177957828 ps
CPU time 192.66 seconds
Started Aug 12 05:04:28 PM PDT 24
Finished Aug 12 05:07:40 PM PDT 24
Peak memory 200748 kb
Host smart-829bc259-9c93-484c-96f9-7b961a6eb6ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759586966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1759586966
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.2924916187
Short name T906
Test name
Test status
Simulation time 6478680150 ps
CPU time 20.21 seconds
Started Aug 12 05:04:25 PM PDT 24
Finished Aug 12 05:04:46 PM PDT 24
Peak memory 217224 kb
Host smart-802a8b2f-432c-4c5b-a6a9-f0bd9cd17310
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924916187 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.2924916187
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1084043254
Short name T451
Test name
Test status
Simulation time 1371340427 ps
CPU time 4.33 seconds
Started Aug 12 05:04:25 PM PDT 24
Finished Aug 12 05:04:30 PM PDT 24
Peak memory 199112 kb
Host smart-d629109d-0fbf-4bec-a30f-9f6a56ad120e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084043254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1084043254
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.4212789018
Short name T251
Test name
Test status
Simulation time 70901402601 ps
CPU time 58.32 seconds
Started Aug 12 05:04:23 PM PDT 24
Finished Aug 12 05:05:21 PM PDT 24
Peak memory 200700 kb
Host smart-fe58c6d9-7866-4d33-91c1-2c7b18345c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212789018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.4212789018
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.4211643596
Short name T263
Test name
Test status
Simulation time 161701232251 ps
CPU time 25.02 seconds
Started Aug 12 05:06:43 PM PDT 24
Finished Aug 12 05:07:08 PM PDT 24
Peak memory 200748 kb
Host smart-e16521c3-ad99-4f09-ac89-008d59b11bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211643596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.4211643596
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3030284339
Short name T195
Test name
Test status
Simulation time 101114762566 ps
CPU time 151.72 seconds
Started Aug 12 05:06:43 PM PDT 24
Finished Aug 12 05:09:15 PM PDT 24
Peak memory 200732 kb
Host smart-83a2e4aa-e234-4d10-9317-6dfe189b88b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030284339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3030284339
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.250197216
Short name T1105
Test name
Test status
Simulation time 93638226291 ps
CPU time 77.27 seconds
Started Aug 12 05:06:43 PM PDT 24
Finished Aug 12 05:08:01 PM PDT 24
Peak memory 200868 kb
Host smart-4de0f2cf-9349-4b34-ad6b-a8534827fd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250197216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.250197216
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.222611831
Short name T834
Test name
Test status
Simulation time 51723703051 ps
CPU time 85.11 seconds
Started Aug 12 05:06:43 PM PDT 24
Finished Aug 12 05:08:08 PM PDT 24
Peak memory 200676 kb
Host smart-8145d83a-256f-4f23-a7f7-2cb1c15ec4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222611831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.222611831
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3930156081
Short name T989
Test name
Test status
Simulation time 71731713308 ps
CPU time 53.42 seconds
Started Aug 12 05:06:44 PM PDT 24
Finished Aug 12 05:07:38 PM PDT 24
Peak memory 200776 kb
Host smart-e305b0ae-c6ed-41d1-b464-2d5266788962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930156081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3930156081
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2679879827
Short name T758
Test name
Test status
Simulation time 132217395175 ps
CPU time 96 seconds
Started Aug 12 05:06:44 PM PDT 24
Finished Aug 12 05:08:20 PM PDT 24
Peak memory 200804 kb
Host smart-55141fc0-02f9-4735-a3cf-97931de7a9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679879827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2679879827
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1468990805
Short name T678
Test name
Test status
Simulation time 131459019931 ps
CPU time 285.88 seconds
Started Aug 12 05:06:50 PM PDT 24
Finished Aug 12 05:11:36 PM PDT 24
Peak memory 200832 kb
Host smart-dd31f6d0-46f4-43a1-afd2-5474ff955d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468990805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1468990805
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1408029239
Short name T696
Test name
Test status
Simulation time 14467889 ps
CPU time 0.57 seconds
Started Aug 12 05:03:41 PM PDT 24
Finished Aug 12 05:03:42 PM PDT 24
Peak memory 196036 kb
Host smart-6dc0417e-39ac-444a-9ea5-b35a24681eaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408029239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1408029239
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.860142881
Short name T420
Test name
Test status
Simulation time 73422940254 ps
CPU time 31.79 seconds
Started Aug 12 05:03:39 PM PDT 24
Finished Aug 12 05:04:11 PM PDT 24
Peak memory 200668 kb
Host smart-1070d374-4cc5-4aff-b74e-ef14d0b6ebd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860142881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.860142881
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1894822836
Short name T626
Test name
Test status
Simulation time 111623405246 ps
CPU time 24.23 seconds
Started Aug 12 05:03:42 PM PDT 24
Finished Aug 12 05:04:06 PM PDT 24
Peak memory 200732 kb
Host smart-b85407eb-6014-427d-b303-262af12fc1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894822836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1894822836
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2099997170
Short name T168
Test name
Test status
Simulation time 48797049183 ps
CPU time 42.88 seconds
Started Aug 12 05:03:36 PM PDT 24
Finished Aug 12 05:04:19 PM PDT 24
Peak memory 200612 kb
Host smart-f0c0c5f3-7991-4b4e-8550-cf683acda110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099997170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2099997170
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.1832840188
Short name T438
Test name
Test status
Simulation time 68693233308 ps
CPU time 28.56 seconds
Started Aug 12 05:03:34 PM PDT 24
Finished Aug 12 05:04:02 PM PDT 24
Peak memory 199764 kb
Host smart-a910e5dd-0b8d-4637-8f74-1a105f53ed8a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832840188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1832840188
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.1056171699
Short name T264
Test name
Test status
Simulation time 256664406379 ps
CPU time 188.38 seconds
Started Aug 12 05:03:34 PM PDT 24
Finished Aug 12 05:06:42 PM PDT 24
Peak memory 200036 kb
Host smart-5e13ee4a-4530-4cf4-b49a-0d47fca473a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1056171699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.1056171699
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1974375084
Short name T556
Test name
Test status
Simulation time 9087913721 ps
CPU time 10.14 seconds
Started Aug 12 05:03:34 PM PDT 24
Finished Aug 12 05:03:45 PM PDT 24
Peak memory 200532 kb
Host smart-b2e43bba-83df-4d1b-a72d-c7bcd3a1f3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974375084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1974375084
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.1992722773
Short name T1168
Test name
Test status
Simulation time 108727639644 ps
CPU time 87.76 seconds
Started Aug 12 05:03:34 PM PDT 24
Finished Aug 12 05:05:02 PM PDT 24
Peak memory 200912 kb
Host smart-a5e305ba-0991-44b9-9476-c5c2121bbf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992722773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1992722773
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3804011292
Short name T607
Test name
Test status
Simulation time 3603856253 ps
CPU time 216.7 seconds
Started Aug 12 05:03:37 PM PDT 24
Finished Aug 12 05:07:13 PM PDT 24
Peak memory 200792 kb
Host smart-49265372-8110-4226-a7ea-81ef1662e764
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3804011292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3804011292
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.2924965560
Short name T1037
Test name
Test status
Simulation time 5965803545 ps
CPU time 60.87 seconds
Started Aug 12 05:03:38 PM PDT 24
Finished Aug 12 05:04:39 PM PDT 24
Peak memory 198984 kb
Host smart-6fffc6d7-0eba-4db4-be29-f4a8d40f7cba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2924965560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2924965560
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3287128123
Short name T87
Test name
Test status
Simulation time 36489571615 ps
CPU time 17.54 seconds
Started Aug 12 05:03:46 PM PDT 24
Finished Aug 12 05:04:04 PM PDT 24
Peak memory 200696 kb
Host smart-6956221f-2338-4dd4-b904-000e3a6a440b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287128123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3287128123
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.1959904882
Short name T347
Test name
Test status
Simulation time 3009795760 ps
CPU time 4.85 seconds
Started Aug 12 05:03:43 PM PDT 24
Finished Aug 12 05:03:48 PM PDT 24
Peak memory 197264 kb
Host smart-dedbfbbf-4e4c-416e-b58f-7cf302df4750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959904882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1959904882
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3701513987
Short name T25
Test name
Test status
Simulation time 88615871 ps
CPU time 0.83 seconds
Started Aug 12 05:03:45 PM PDT 24
Finished Aug 12 05:03:45 PM PDT 24
Peak memory 218964 kb
Host smart-58ab5de9-cdf1-425e-abb1-6230546929a1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701513987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3701513987
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.367331275
Short name T674
Test name
Test status
Simulation time 470386988 ps
CPU time 2.2 seconds
Started Aug 12 05:03:28 PM PDT 24
Finished Aug 12 05:03:30 PM PDT 24
Peak memory 199608 kb
Host smart-83e964ba-ea79-4d5c-8498-4ae66d41d6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367331275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.367331275
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.4163484419
Short name T411
Test name
Test status
Simulation time 652971085335 ps
CPU time 184.59 seconds
Started Aug 12 05:03:53 PM PDT 24
Finished Aug 12 05:06:58 PM PDT 24
Peak memory 200652 kb
Host smart-7b6d78aa-e16e-4b34-bce4-7d2e7855cd82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163484419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.4163484419
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1618189484
Short name T799
Test name
Test status
Simulation time 7669763914 ps
CPU time 22.59 seconds
Started Aug 12 05:03:38 PM PDT 24
Finished Aug 12 05:04:01 PM PDT 24
Peak memory 209356 kb
Host smart-e6b8f108-d9dd-4db7-b70c-a60822f251fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618189484 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1618189484
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.2832963327
Short name T1093
Test name
Test status
Simulation time 517418347 ps
CPU time 1.86 seconds
Started Aug 12 05:03:30 PM PDT 24
Finished Aug 12 05:03:32 PM PDT 24
Peak memory 200652 kb
Host smart-1b8bee0c-2fea-4e44-8e94-9b1954c9b081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832963327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2832963327
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.2854202183
Short name T252
Test name
Test status
Simulation time 163990967248 ps
CPU time 102.42 seconds
Started Aug 12 05:03:43 PM PDT 24
Finished Aug 12 05:05:26 PM PDT 24
Peak memory 200804 kb
Host smart-4e321e88-02f4-4eb8-81f4-6ba5dae69ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854202183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2854202183
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.395249820
Short name T823
Test name
Test status
Simulation time 43073301 ps
CPU time 0.55 seconds
Started Aug 12 05:04:26 PM PDT 24
Finished Aug 12 05:04:27 PM PDT 24
Peak memory 195300 kb
Host smart-b3193d45-c895-4efc-9fbd-1fc04f524e43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395249820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.395249820
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3331925885
Short name T372
Test name
Test status
Simulation time 102993954910 ps
CPU time 154.5 seconds
Started Aug 12 05:04:26 PM PDT 24
Finished Aug 12 05:07:01 PM PDT 24
Peak memory 200736 kb
Host smart-5aa6563c-df2d-403c-8a83-913ed14563e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331925885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3331925885
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.1953588822
Short name T1004
Test name
Test status
Simulation time 71751691544 ps
CPU time 92.78 seconds
Started Aug 12 05:04:27 PM PDT 24
Finished Aug 12 05:06:00 PM PDT 24
Peak memory 200776 kb
Host smart-35414f1a-35ab-4daf-9d51-a2855cbe1cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953588822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1953588822
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_intr.2149941699
Short name T773
Test name
Test status
Simulation time 26950969841 ps
CPU time 16.83 seconds
Started Aug 12 05:04:15 PM PDT 24
Finished Aug 12 05:04:32 PM PDT 24
Peak memory 200744 kb
Host smart-3ed29bdf-e691-4e0a-a538-ee96b16685eb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149941699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2149941699
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.97653956
Short name T855
Test name
Test status
Simulation time 60927586019 ps
CPU time 260.45 seconds
Started Aug 12 05:04:27 PM PDT 24
Finished Aug 12 05:08:48 PM PDT 24
Peak memory 200772 kb
Host smart-dff631c2-2b2e-40d9-ac89-2473efe4f3e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=97653956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.97653956
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.3267049987
Short name T532
Test name
Test status
Simulation time 1711591992 ps
CPU time 3.77 seconds
Started Aug 12 05:04:19 PM PDT 24
Finished Aug 12 05:04:23 PM PDT 24
Peak memory 198944 kb
Host smart-8c84d388-511e-43ca-aa86-02cf4808b5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267049987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3267049987
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.1865466083
Short name T293
Test name
Test status
Simulation time 27018469462 ps
CPU time 43.01 seconds
Started Aug 12 05:04:22 PM PDT 24
Finished Aug 12 05:05:05 PM PDT 24
Peak memory 200548 kb
Host smart-222f7dd2-12b2-446f-bff3-b3a17cfe450f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865466083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.1865466083
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.77869571
Short name T485
Test name
Test status
Simulation time 32309154072 ps
CPU time 94.45 seconds
Started Aug 12 05:04:19 PM PDT 24
Finished Aug 12 05:05:53 PM PDT 24
Peak memory 200776 kb
Host smart-1805ffb4-d895-4277-b3a7-68c85010e0ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77869571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.77869571
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1459603381
Short name T1178
Test name
Test status
Simulation time 3587450598 ps
CPU time 28.33 seconds
Started Aug 12 05:04:24 PM PDT 24
Finished Aug 12 05:04:53 PM PDT 24
Peak memory 198908 kb
Host smart-1b42bca6-7dbb-4326-a700-450fec815238
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1459603381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1459603381
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.4127877715
Short name T444
Test name
Test status
Simulation time 30730112592 ps
CPU time 10.97 seconds
Started Aug 12 05:04:22 PM PDT 24
Finished Aug 12 05:04:33 PM PDT 24
Peak memory 200112 kb
Host smart-5011e825-98fa-4b99-bbdd-a9788e20f239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127877715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.4127877715
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.1578303484
Short name T528
Test name
Test status
Simulation time 84028446250 ps
CPU time 34.41 seconds
Started Aug 12 05:04:22 PM PDT 24
Finished Aug 12 05:04:56 PM PDT 24
Peak memory 197680 kb
Host smart-8eefa1cd-7e57-4d16-8bcd-6d7cfa788317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578303484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1578303484
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.4025743696
Short name T486
Test name
Test status
Simulation time 106210760 ps
CPU time 0.94 seconds
Started Aug 12 05:04:16 PM PDT 24
Finished Aug 12 05:04:17 PM PDT 24
Peak memory 198232 kb
Host smart-ef7986f8-3ec3-4c2c-b235-2e26ccf1201f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025743696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.4025743696
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.3508594924
Short name T846
Test name
Test status
Simulation time 2506627520 ps
CPU time 28.45 seconds
Started Aug 12 05:04:26 PM PDT 24
Finished Aug 12 05:04:54 PM PDT 24
Peak memory 209284 kb
Host smart-859a6954-6a3c-4aed-a3ac-fdad7afb298a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508594924 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.3508594924
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.1128832483
Short name T1047
Test name
Test status
Simulation time 635996505 ps
CPU time 2.02 seconds
Started Aug 12 05:04:24 PM PDT 24
Finished Aug 12 05:04:26 PM PDT 24
Peak memory 199140 kb
Host smart-4548d88a-0850-4833-909a-905a46b1e08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128832483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1128832483
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3412557145
Short name T972
Test name
Test status
Simulation time 40794789882 ps
CPU time 61.24 seconds
Started Aug 12 05:04:28 PM PDT 24
Finished Aug 12 05:05:29 PM PDT 24
Peak memory 200752 kb
Host smart-f1c5feb7-b3a8-4741-9feb-6abfaa63eee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412557145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3412557145
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.2996249844
Short name T970
Test name
Test status
Simulation time 13098662576 ps
CPU time 13.19 seconds
Started Aug 12 05:06:52 PM PDT 24
Finished Aug 12 05:07:05 PM PDT 24
Peak memory 200596 kb
Host smart-507bf54b-28eb-4f8e-b574-d9858098dde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996249844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2996249844
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.2468947861
Short name T905
Test name
Test status
Simulation time 49738335825 ps
CPU time 72.18 seconds
Started Aug 12 05:06:50 PM PDT 24
Finished Aug 12 05:08:03 PM PDT 24
Peak memory 200736 kb
Host smart-70a8c30a-828b-4f99-b1d2-902caf2fc43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468947861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.2468947861
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2745425861
Short name T654
Test name
Test status
Simulation time 126347382829 ps
CPU time 48.38 seconds
Started Aug 12 05:06:49 PM PDT 24
Finished Aug 12 05:07:37 PM PDT 24
Peak memory 200684 kb
Host smart-b2cd0ce3-7cac-479a-8de0-857aaaef3f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745425861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2745425861
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1242723617
Short name T1122
Test name
Test status
Simulation time 48109691476 ps
CPU time 20.86 seconds
Started Aug 12 05:06:51 PM PDT 24
Finished Aug 12 05:07:12 PM PDT 24
Peak memory 200760 kb
Host smart-f72682c6-aaea-457b-bdbf-6aeb335bdff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242723617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1242723617
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.2520202835
Short name T246
Test name
Test status
Simulation time 157278640534 ps
CPU time 57.48 seconds
Started Aug 12 05:06:52 PM PDT 24
Finished Aug 12 05:07:50 PM PDT 24
Peak memory 200776 kb
Host smart-596afba4-1dc6-420a-82c2-5f8282ee5739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520202835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2520202835
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.767147183
Short name T1185
Test name
Test status
Simulation time 36939330063 ps
CPU time 26.69 seconds
Started Aug 12 05:06:49 PM PDT 24
Finished Aug 12 05:07:16 PM PDT 24
Peak memory 200716 kb
Host smart-8f5c4d2d-2502-45d1-8b66-fec215ebab78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767147183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.767147183
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.2589817537
Short name T376
Test name
Test status
Simulation time 40113191211 ps
CPU time 21.65 seconds
Started Aug 12 05:06:51 PM PDT 24
Finished Aug 12 05:07:13 PM PDT 24
Peak memory 200772 kb
Host smart-7086d02f-bf56-4de9-9ead-da7e615de305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589817537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2589817537
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2312479626
Short name T150
Test name
Test status
Simulation time 8545219306 ps
CPU time 14.15 seconds
Started Aug 12 05:06:51 PM PDT 24
Finished Aug 12 05:07:06 PM PDT 24
Peak memory 200968 kb
Host smart-7b0fdbbe-b5c6-400b-b55b-c60c16cb0acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312479626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2312479626
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.236042491
Short name T328
Test name
Test status
Simulation time 19537496 ps
CPU time 0.56 seconds
Started Aug 12 05:04:28 PM PDT 24
Finished Aug 12 05:04:29 PM PDT 24
Peak memory 196128 kb
Host smart-a9c49554-4449-45e0-bf9d-676f35e2c425
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236042491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.236042491
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3017819636
Short name T904
Test name
Test status
Simulation time 123379651771 ps
CPU time 434.35 seconds
Started Aug 12 05:04:25 PM PDT 24
Finished Aug 12 05:11:40 PM PDT 24
Peak memory 200768 kb
Host smart-2efe64b9-ddcc-48bc-a9dc-7dd6518f19d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017819636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3017819636
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.106999926
Short name T897
Test name
Test status
Simulation time 29454243665 ps
CPU time 25.68 seconds
Started Aug 12 05:04:31 PM PDT 24
Finished Aug 12 05:04:57 PM PDT 24
Peak memory 200624 kb
Host smart-3869d549-7361-4fa7-8154-3419ad130842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106999926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.106999926
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.1117291039
Short name T1088
Test name
Test status
Simulation time 40400430864 ps
CPU time 182.1 seconds
Started Aug 12 05:04:18 PM PDT 24
Finished Aug 12 05:07:20 PM PDT 24
Peak memory 200424 kb
Host smart-f8dcd96c-a88c-4abe-bcc9-fa4a6a0a9f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117291039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1117291039
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.655982944
Short name T893
Test name
Test status
Simulation time 330629653482 ps
CPU time 60.65 seconds
Started Aug 12 05:04:19 PM PDT 24
Finished Aug 12 05:05:20 PM PDT 24
Peak memory 200620 kb
Host smart-492109a7-3643-44ab-b0d0-c045166a6c1a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655982944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.655982944
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.1762946731
Short name T1064
Test name
Test status
Simulation time 30807378839 ps
CPU time 225.59 seconds
Started Aug 12 05:04:32 PM PDT 24
Finished Aug 12 05:08:18 PM PDT 24
Peak memory 200740 kb
Host smart-7d904c0b-6173-4fbc-b9c5-c08dcc8ef9ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1762946731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1762946731
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1195009283
Short name T997
Test name
Test status
Simulation time 2467575570 ps
CPU time 2.14 seconds
Started Aug 12 05:04:29 PM PDT 24
Finished Aug 12 05:04:31 PM PDT 24
Peak memory 198244 kb
Host smart-0d09edc4-994d-4c97-b779-c36d5aab0f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195009283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1195009283
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.4092880829
Short name T505
Test name
Test status
Simulation time 26747306528 ps
CPU time 67.74 seconds
Started Aug 12 05:04:24 PM PDT 24
Finished Aug 12 05:05:31 PM PDT 24
Peak memory 200376 kb
Host smart-2c18236c-2564-4914-8d6c-5243f7688943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092880829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.4092880829
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.1241478517
Short name T1000
Test name
Test status
Simulation time 30287169525 ps
CPU time 101.18 seconds
Started Aug 12 05:04:26 PM PDT 24
Finished Aug 12 05:06:07 PM PDT 24
Peak memory 200808 kb
Host smart-c67fb29e-2964-4d10-96a4-6227b36d7f3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1241478517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1241478517
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.2947833791
Short name T70
Test name
Test status
Simulation time 4541592966 ps
CPU time 10.46 seconds
Started Aug 12 05:04:24 PM PDT 24
Finished Aug 12 05:04:34 PM PDT 24
Peak memory 199804 kb
Host smart-534dcceb-1216-4253-9a37-70ce4bcd8ad0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2947833791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2947833791
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2429303056
Short name T13
Test name
Test status
Simulation time 42503488305 ps
CPU time 8.55 seconds
Started Aug 12 05:04:25 PM PDT 24
Finished Aug 12 05:04:34 PM PDT 24
Peak memory 200272 kb
Host smart-bebe5bf8-bc02-4d80-a926-1c228677bcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429303056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2429303056
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1863870972
Short name T314
Test name
Test status
Simulation time 447847815 ps
CPU time 1.27 seconds
Started Aug 12 05:04:28 PM PDT 24
Finished Aug 12 05:04:30 PM PDT 24
Peak memory 196372 kb
Host smart-b0ebcae9-c30b-40d1-ad89-fca957b95434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863870972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1863870972
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.528405199
Short name T616
Test name
Test status
Simulation time 697995374 ps
CPU time 1.43 seconds
Started Aug 12 05:04:22 PM PDT 24
Finished Aug 12 05:04:24 PM PDT 24
Peak memory 199628 kb
Host smart-dfda07fd-12c4-4acd-963e-24e3022a60e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528405199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.528405199
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.811777061
Short name T547
Test name
Test status
Simulation time 614148055553 ps
CPU time 204.23 seconds
Started Aug 12 05:04:27 PM PDT 24
Finished Aug 12 05:07:52 PM PDT 24
Peak memory 200784 kb
Host smart-19559af9-cf00-4288-bc1d-09176ddad237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811777061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.811777061
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2025155970
Short name T506
Test name
Test status
Simulation time 1815912758 ps
CPU time 2.92 seconds
Started Aug 12 05:04:25 PM PDT 24
Finished Aug 12 05:04:28 PM PDT 24
Peak memory 200444 kb
Host smart-0c15a500-ff15-4ca6-8109-4eebd992df05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025155970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2025155970
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3608509468
Short name T878
Test name
Test status
Simulation time 48882883484 ps
CPU time 36.45 seconds
Started Aug 12 05:04:23 PM PDT 24
Finished Aug 12 05:04:59 PM PDT 24
Peak memory 200712 kb
Host smart-edda4528-c2dc-4ef1-9c85-67b357f4f160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608509468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3608509468
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3618914496
Short name T257
Test name
Test status
Simulation time 64652819008 ps
CPU time 14.84 seconds
Started Aug 12 05:06:51 PM PDT 24
Finished Aug 12 05:07:06 PM PDT 24
Peak memory 200580 kb
Host smart-1bc5b978-8e7e-41d7-9411-5440fcbf2b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618914496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3618914496
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.995309765
Short name T285
Test name
Test status
Simulation time 23567105505 ps
CPU time 12.3 seconds
Started Aug 12 05:06:49 PM PDT 24
Finished Aug 12 05:07:01 PM PDT 24
Peak memory 200596 kb
Host smart-4f6ca6fe-3869-4e99-9625-fd31fe395a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995309765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.995309765
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2250663256
Short name T638
Test name
Test status
Simulation time 53529256219 ps
CPU time 23.75 seconds
Started Aug 12 05:06:51 PM PDT 24
Finished Aug 12 05:07:15 PM PDT 24
Peak memory 200712 kb
Host smart-b0ac2504-1b8f-47d4-b736-ffc340d1af39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250663256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2250663256
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.726818699
Short name T932
Test name
Test status
Simulation time 29946850069 ps
CPU time 61.24 seconds
Started Aug 12 05:06:51 PM PDT 24
Finished Aug 12 05:07:52 PM PDT 24
Peak memory 200772 kb
Host smart-96f02c5a-bb9c-471e-a2f8-e6acc0d24d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726818699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.726818699
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2514253552
Short name T853
Test name
Test status
Simulation time 29048307596 ps
CPU time 55.29 seconds
Started Aug 12 05:06:50 PM PDT 24
Finished Aug 12 05:07:46 PM PDT 24
Peak memory 200740 kb
Host smart-5ebf86e9-3374-4d42-a597-303c2dba92cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514253552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2514253552
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.993123327
Short name T945
Test name
Test status
Simulation time 203761294958 ps
CPU time 80.16 seconds
Started Aug 12 05:06:49 PM PDT 24
Finished Aug 12 05:08:10 PM PDT 24
Peak memory 200800 kb
Host smart-543f1e5c-2e44-4e6f-a308-ad6c837095c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993123327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.993123327
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1510703885
Short name T194
Test name
Test status
Simulation time 71612060788 ps
CPU time 27.54 seconds
Started Aug 12 05:06:52 PM PDT 24
Finished Aug 12 05:07:20 PM PDT 24
Peak memory 200712 kb
Host smart-b419b3c0-5492-4681-8e36-bad65f1dbe5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510703885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1510703885
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2759728878
Short name T407
Test name
Test status
Simulation time 15693077930 ps
CPU time 25.92 seconds
Started Aug 12 05:06:49 PM PDT 24
Finished Aug 12 05:07:15 PM PDT 24
Peak memory 200780 kb
Host smart-e1e46a50-942c-4860-b117-7c693f9bdde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759728878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2759728878
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.3277343485
Short name T1157
Test name
Test status
Simulation time 73011654999 ps
CPU time 247.24 seconds
Started Aug 12 05:06:54 PM PDT 24
Finished Aug 12 05:11:02 PM PDT 24
Peak memory 200752 kb
Host smart-f5ed7441-36b0-4e8c-ab4a-e25234c6a6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277343485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.3277343485
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3939721937
Short name T7
Test name
Test status
Simulation time 25900070 ps
CPU time 0.59 seconds
Started Aug 12 05:04:29 PM PDT 24
Finished Aug 12 05:04:30 PM PDT 24
Peak memory 196124 kb
Host smart-aea1520e-9f4f-4bed-b4de-78005dd621df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939721937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3939721937
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3136061446
Short name T480
Test name
Test status
Simulation time 180687935524 ps
CPU time 148.93 seconds
Started Aug 12 05:04:27 PM PDT 24
Finished Aug 12 05:06:56 PM PDT 24
Peak memory 200768 kb
Host smart-fb8efdae-fa43-4cb8-9beb-68c64145be28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136061446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3136061446
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3272513772
Short name T144
Test name
Test status
Simulation time 157898649327 ps
CPU time 65.68 seconds
Started Aug 12 05:04:27 PM PDT 24
Finished Aug 12 05:05:32 PM PDT 24
Peak memory 200688 kb
Host smart-ae9bc6ac-f1e0-4439-b4bb-7e27a24c8aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272513772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3272513772
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.1799571294
Short name T1073
Test name
Test status
Simulation time 137808816410 ps
CPU time 342.25 seconds
Started Aug 12 05:04:29 PM PDT 24
Finished Aug 12 05:10:12 PM PDT 24
Peak memory 200732 kb
Host smart-9ada1e40-a032-4440-a093-737b8cf57e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799571294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1799571294
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.2033266523
Short name T592
Test name
Test status
Simulation time 23538300822 ps
CPU time 9.35 seconds
Started Aug 12 05:04:28 PM PDT 24
Finished Aug 12 05:04:38 PM PDT 24
Peak memory 200740 kb
Host smart-64ce0afe-8479-498e-a765-8b707ff59ee7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033266523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2033266523
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.52104748
Short name T803
Test name
Test status
Simulation time 141331265909 ps
CPU time 225.36 seconds
Started Aug 12 05:04:28 PM PDT 24
Finished Aug 12 05:08:13 PM PDT 24
Peak memory 200704 kb
Host smart-9de8e8e6-c13d-414d-8dc1-6750d47babb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=52104748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.52104748
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2820442487
Short name T982
Test name
Test status
Simulation time 5584037135 ps
CPU time 5.41 seconds
Started Aug 12 05:04:29 PM PDT 24
Finished Aug 12 05:04:35 PM PDT 24
Peak memory 200724 kb
Host smart-2a8589f2-de01-4f1b-8376-94fa612f0d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820442487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2820442487
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.2455658069
Short name T1187
Test name
Test status
Simulation time 217673972292 ps
CPU time 65.92 seconds
Started Aug 12 05:04:25 PM PDT 24
Finished Aug 12 05:05:31 PM PDT 24
Peak memory 201016 kb
Host smart-40d3113d-43f6-4dbd-9946-0a219aa921f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455658069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2455658069
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.1027156440
Short name T463
Test name
Test status
Simulation time 17015691763 ps
CPU time 908.88 seconds
Started Aug 12 05:04:29 PM PDT 24
Finished Aug 12 05:19:39 PM PDT 24
Peak memory 200708 kb
Host smart-257e583f-585f-40f5-b9a6-670d9d205b12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1027156440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1027156440
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.3024135436
Short name T871
Test name
Test status
Simulation time 4662338407 ps
CPU time 5.1 seconds
Started Aug 12 05:04:24 PM PDT 24
Finished Aug 12 05:04:29 PM PDT 24
Peak memory 199040 kb
Host smart-93aa2c11-d16e-473a-b450-1a0700f20397
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3024135436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3024135436
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.54045759
Short name T382
Test name
Test status
Simulation time 39929453010 ps
CPU time 11.43 seconds
Started Aug 12 05:04:28 PM PDT 24
Finished Aug 12 05:04:40 PM PDT 24
Peak memory 199252 kb
Host smart-a5a3f158-1187-4af4-b492-0382926fbb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54045759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.54045759
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2882363838
Short name T700
Test name
Test status
Simulation time 7814363909 ps
CPU time 3.36 seconds
Started Aug 12 05:04:23 PM PDT 24
Finished Aug 12 05:04:26 PM PDT 24
Peak memory 196956 kb
Host smart-3fdcf9a6-3de5-43c2-9fb0-0d12d540e448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882363838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2882363838
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1594726706
Short name T488
Test name
Test status
Simulation time 776854693 ps
CPU time 1.51 seconds
Started Aug 12 05:04:24 PM PDT 24
Finished Aug 12 05:04:25 PM PDT 24
Peak memory 199840 kb
Host smart-72d6f95d-dc30-4d70-8923-ae177bd3fd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594726706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1594726706
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.3213164499
Short name T876
Test name
Test status
Simulation time 91763153213 ps
CPU time 155.01 seconds
Started Aug 12 05:04:29 PM PDT 24
Finished Aug 12 05:07:04 PM PDT 24
Peak memory 200664 kb
Host smart-5650156d-9b4b-4664-8508-b9d2dbb026b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213164499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3213164499
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2768070454
Short name T454
Test name
Test status
Simulation time 561672857 ps
CPU time 1.94 seconds
Started Aug 12 05:04:26 PM PDT 24
Finished Aug 12 05:04:28 PM PDT 24
Peak memory 198944 kb
Host smart-f8e1c068-8998-4510-a9d6-3df6eecfcaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768070454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2768070454
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.2606626499
Short name T958
Test name
Test status
Simulation time 43165835642 ps
CPU time 36.62 seconds
Started Aug 12 05:04:27 PM PDT 24
Finished Aug 12 05:05:04 PM PDT 24
Peak memory 200780 kb
Host smart-809a7f4b-4ecd-4e76-a377-530fef4d3e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606626499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2606626499
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1182226072
Short name T214
Test name
Test status
Simulation time 37994123058 ps
CPU time 32.1 seconds
Started Aug 12 05:06:49 PM PDT 24
Finished Aug 12 05:07:21 PM PDT 24
Peak memory 200672 kb
Host smart-c4a175c7-d916-4f2b-ae3c-915690d5eef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182226072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1182226072
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.495130318
Short name T1132
Test name
Test status
Simulation time 138745354667 ps
CPU time 85 seconds
Started Aug 12 05:06:49 PM PDT 24
Finished Aug 12 05:08:15 PM PDT 24
Peak memory 200868 kb
Host smart-c622aeb6-cd50-4399-b70f-81b70815a8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495130318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.495130318
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2151154371
Short name T210
Test name
Test status
Simulation time 51285636080 ps
CPU time 43 seconds
Started Aug 12 05:06:51 PM PDT 24
Finished Aug 12 05:07:34 PM PDT 24
Peak memory 200636 kb
Host smart-875dcef9-bc9d-490f-9cc1-a58b4f948522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151154371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2151154371
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1581311489
Short name T434
Test name
Test status
Simulation time 153073417631 ps
CPU time 289.17 seconds
Started Aug 12 05:06:54 PM PDT 24
Finished Aug 12 05:11:44 PM PDT 24
Peak memory 200824 kb
Host smart-a294f368-a4cb-4b93-affb-6c2263e93e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581311489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1581311489
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3347046563
Short name T582
Test name
Test status
Simulation time 10816603770 ps
CPU time 13.58 seconds
Started Aug 12 05:06:51 PM PDT 24
Finished Aug 12 05:07:05 PM PDT 24
Peak memory 200712 kb
Host smart-6a3022c8-6ff6-4e41-8a7b-b24e0383dc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347046563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3347046563
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1503367468
Short name T573
Test name
Test status
Simulation time 19715302510 ps
CPU time 35.63 seconds
Started Aug 12 05:06:50 PM PDT 24
Finished Aug 12 05:07:26 PM PDT 24
Peak memory 200732 kb
Host smart-4af4b4f8-b892-41dc-a905-9e469a8a4bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503367468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1503367468
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2597151058
Short name T189
Test name
Test status
Simulation time 131480512836 ps
CPU time 105.63 seconds
Started Aug 12 05:06:54 PM PDT 24
Finished Aug 12 05:08:40 PM PDT 24
Peak memory 200696 kb
Host smart-5ca58681-c116-4631-940f-32e2c02a9e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597151058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2597151058
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.233019118
Short name T227
Test name
Test status
Simulation time 99426522671 ps
CPU time 18.59 seconds
Started Aug 12 05:06:52 PM PDT 24
Finished Aug 12 05:07:11 PM PDT 24
Peak memory 200880 kb
Host smart-75fe8968-f10f-4d08-96c3-d96ea7274f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233019118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.233019118
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2883141281
Short name T574
Test name
Test status
Simulation time 15569083233 ps
CPU time 23.72 seconds
Started Aug 12 05:06:56 PM PDT 24
Finished Aug 12 05:07:20 PM PDT 24
Peak memory 200828 kb
Host smart-8fca910f-0066-4853-b72f-9454f3390721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883141281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2883141281
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1811717733
Short name T925
Test name
Test status
Simulation time 25746520 ps
CPU time 0.54 seconds
Started Aug 12 05:04:29 PM PDT 24
Finished Aug 12 05:04:30 PM PDT 24
Peak memory 195596 kb
Host smart-1759fb31-44df-4617-8620-7f52751412cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811717733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1811717733
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2878085315
Short name T1050
Test name
Test status
Simulation time 113246418388 ps
CPU time 100.43 seconds
Started Aug 12 05:04:27 PM PDT 24
Finished Aug 12 05:06:07 PM PDT 24
Peak memory 200900 kb
Host smart-dda6b445-b30a-4e6c-8f55-004c0a5a277c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878085315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2878085315
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.2365748292
Short name T484
Test name
Test status
Simulation time 96296974714 ps
CPU time 25.03 seconds
Started Aug 12 05:04:29 PM PDT 24
Finished Aug 12 05:04:55 PM PDT 24
Peak memory 200468 kb
Host smart-2c2adb4b-c4ef-4526-bcff-a692a009f8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365748292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2365748292
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.4180235138
Short name T596
Test name
Test status
Simulation time 73014683801 ps
CPU time 128.54 seconds
Started Aug 12 05:04:29 PM PDT 24
Finished Aug 12 05:06:38 PM PDT 24
Peak memory 200672 kb
Host smart-0043def4-a95e-4eeb-bcb2-b89223149d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180235138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.4180235138
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.4006859406
Short name T1101
Test name
Test status
Simulation time 80039942668 ps
CPU time 62.15 seconds
Started Aug 12 05:04:38 PM PDT 24
Finished Aug 12 05:05:40 PM PDT 24
Peak memory 200700 kb
Host smart-1f5b3c4b-d0bc-4c2d-a621-690557b8123c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006859406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.4006859406
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.89087907
Short name T1155
Test name
Test status
Simulation time 89800727082 ps
CPU time 553.13 seconds
Started Aug 12 05:04:36 PM PDT 24
Finished Aug 12 05:13:49 PM PDT 24
Peak memory 200800 kb
Host smart-9503c535-3007-4905-8d07-87ba689e49b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=89087907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.89087907
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.246009387
Short name T1125
Test name
Test status
Simulation time 5991656531 ps
CPU time 8.76 seconds
Started Aug 12 05:04:39 PM PDT 24
Finished Aug 12 05:04:48 PM PDT 24
Peak memory 200716 kb
Host smart-ad72f995-5c31-4dcf-aa9b-59006694907a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246009387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.246009387
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.4035515039
Short name T705
Test name
Test status
Simulation time 81573734080 ps
CPU time 71.27 seconds
Started Aug 12 05:04:38 PM PDT 24
Finished Aug 12 05:05:50 PM PDT 24
Peak memory 201036 kb
Host smart-8b0a96fe-0c40-4758-917e-abe9c88efde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035515039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.4035515039
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.720867973
Short name T1024
Test name
Test status
Simulation time 20749771070 ps
CPU time 1119.86 seconds
Started Aug 12 05:04:35 PM PDT 24
Finished Aug 12 05:23:15 PM PDT 24
Peak memory 200692 kb
Host smart-22d66c20-abf7-416b-88eb-ed284be7175f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=720867973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.720867973
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.2223419944
Short name T728
Test name
Test status
Simulation time 7214046431 ps
CPU time 24.6 seconds
Started Aug 12 05:04:28 PM PDT 24
Finished Aug 12 05:04:53 PM PDT 24
Peak memory 199564 kb
Host smart-45353073-f0f0-4f5c-b60f-f815aab6b64a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2223419944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2223419944
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1280140974
Short name T1164
Test name
Test status
Simulation time 43275386485 ps
CPU time 59.13 seconds
Started Aug 12 05:04:30 PM PDT 24
Finished Aug 12 05:05:29 PM PDT 24
Peak memory 200756 kb
Host smart-0e159fb9-518e-4a02-b76e-64e6bce8f037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280140974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1280140974
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.1553157351
Short name T395
Test name
Test status
Simulation time 2579578354 ps
CPU time 4.93 seconds
Started Aug 12 05:04:39 PM PDT 24
Finished Aug 12 05:04:44 PM PDT 24
Peak memory 196784 kb
Host smart-4e52c48f-261e-48ec-91a0-cfb1112d9370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553157351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1553157351
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1546258099
Short name T631
Test name
Test status
Simulation time 893766008 ps
CPU time 1.72 seconds
Started Aug 12 05:04:28 PM PDT 24
Finished Aug 12 05:04:30 PM PDT 24
Peak memory 199776 kb
Host smart-ec9bd236-97fc-4de1-9e49-ffd00f5f6922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546258099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1546258099
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.4012537427
Short name T247
Test name
Test status
Simulation time 186943657143 ps
CPU time 90.03 seconds
Started Aug 12 05:04:35 PM PDT 24
Finished Aug 12 05:06:05 PM PDT 24
Peak memory 200636 kb
Host smart-174b09f7-03a9-450e-9694-b434957b2294
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012537427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.4012537427
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.801473762
Short name T927
Test name
Test status
Simulation time 574952297 ps
CPU time 8.17 seconds
Started Aug 12 05:04:36 PM PDT 24
Finished Aug 12 05:04:44 PM PDT 24
Peak memory 200844 kb
Host smart-3872f185-2c03-4018-baa9-22b2ac78f1fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801473762 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.801473762
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.3635177828
Short name T872
Test name
Test status
Simulation time 6815587940 ps
CPU time 17.47 seconds
Started Aug 12 05:04:39 PM PDT 24
Finished Aug 12 05:04:57 PM PDT 24
Peak memory 200664 kb
Host smart-a547ef2d-5731-4c75-ac25-4162efe31448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635177828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3635177828
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1298345690
Short name T890
Test name
Test status
Simulation time 59281771173 ps
CPU time 101.17 seconds
Started Aug 12 05:04:29 PM PDT 24
Finished Aug 12 05:06:10 PM PDT 24
Peak memory 200780 kb
Host smart-753099e4-7d19-43ce-b2d3-84e2935db018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298345690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1298345690
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3181683583
Short name T710
Test name
Test status
Simulation time 8440885963 ps
CPU time 12.87 seconds
Started Aug 12 05:06:59 PM PDT 24
Finished Aug 12 05:07:12 PM PDT 24
Peak memory 200516 kb
Host smart-3a7d1254-bfa6-45a4-80ef-facaaa574467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181683583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3181683583
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.932577562
Short name T1045
Test name
Test status
Simulation time 52120876083 ps
CPU time 26.19 seconds
Started Aug 12 05:06:58 PM PDT 24
Finished Aug 12 05:07:24 PM PDT 24
Peak memory 200760 kb
Host smart-5edb2431-9489-4fbd-bcf0-1001e34e85d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932577562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.932577562
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3763991124
Short name T163
Test name
Test status
Simulation time 64922169353 ps
CPU time 267.87 seconds
Started Aug 12 05:06:57 PM PDT 24
Finished Aug 12 05:11:25 PM PDT 24
Peak memory 200748 kb
Host smart-dc65c7cc-b3e1-4bcc-be13-3826976650e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763991124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3763991124
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.716121771
Short name T39
Test name
Test status
Simulation time 105582962741 ps
CPU time 42.35 seconds
Started Aug 12 05:06:58 PM PDT 24
Finished Aug 12 05:07:40 PM PDT 24
Peak memory 200724 kb
Host smart-d02a6940-3aca-4422-b3ae-a62d2e8920c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716121771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.716121771
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3751915135
Short name T755
Test name
Test status
Simulation time 20759974193 ps
CPU time 17.59 seconds
Started Aug 12 05:06:58 PM PDT 24
Finished Aug 12 05:07:15 PM PDT 24
Peak memory 199296 kb
Host smart-9dcd1d0e-d7a5-4159-9177-9544a82c3ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751915135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3751915135
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.3926132447
Short name T598
Test name
Test status
Simulation time 22053413358 ps
CPU time 38.91 seconds
Started Aug 12 05:06:58 PM PDT 24
Finished Aug 12 05:07:37 PM PDT 24
Peak memory 200716 kb
Host smart-3f198c78-0f81-40d7-89a0-7823f0414d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926132447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3926132447
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1743326506
Short name T1014
Test name
Test status
Simulation time 84623829859 ps
CPU time 122.68 seconds
Started Aug 12 05:06:57 PM PDT 24
Finished Aug 12 05:09:00 PM PDT 24
Peak memory 200808 kb
Host smart-b5fe7e96-6d22-4cdd-8044-0107adbf63b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743326506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1743326506
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.60700184
Short name T999
Test name
Test status
Simulation time 36028336059 ps
CPU time 25.77 seconds
Started Aug 12 05:06:56 PM PDT 24
Finished Aug 12 05:07:22 PM PDT 24
Peak memory 200712 kb
Host smart-a5b069d6-8fab-4886-bff6-05fee0cf214c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60700184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.60700184
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.3449749566
Short name T223
Test name
Test status
Simulation time 59052361937 ps
CPU time 76.14 seconds
Started Aug 12 05:06:58 PM PDT 24
Finished Aug 12 05:08:14 PM PDT 24
Peak memory 200796 kb
Host smart-304e4b31-1f99-4e2a-a104-849b7f37f518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449749566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3449749566
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.4090253487
Short name T1176
Test name
Test status
Simulation time 77044059 ps
CPU time 0.55 seconds
Started Aug 12 05:04:31 PM PDT 24
Finished Aug 12 05:04:32 PM PDT 24
Peak memory 196140 kb
Host smart-f3977b49-9166-42f1-827d-8832efaa838c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090253487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.4090253487
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3458240463
Short name T419
Test name
Test status
Simulation time 128072145018 ps
CPU time 43.34 seconds
Started Aug 12 05:04:36 PM PDT 24
Finished Aug 12 05:05:19 PM PDT 24
Peak memory 200740 kb
Host smart-e1b245ba-ba97-4e35-aaa9-280bef3a4fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458240463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3458240463
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2768454014
Short name T790
Test name
Test status
Simulation time 47733503464 ps
CPU time 21.69 seconds
Started Aug 12 05:04:31 PM PDT 24
Finished Aug 12 05:04:53 PM PDT 24
Peak memory 200700 kb
Host smart-f597775b-e0d8-41de-93ef-836b6a1a47e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768454014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2768454014
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_intr.1440001931
Short name T652
Test name
Test status
Simulation time 1159044012 ps
CPU time 1.12 seconds
Started Aug 12 05:04:35 PM PDT 24
Finished Aug 12 05:04:36 PM PDT 24
Peak memory 196464 kb
Host smart-67c87e1d-6fbe-45b3-baf1-b07df263bf76
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440001931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1440001931
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.2341774763
Short name T1038
Test name
Test status
Simulation time 187816618363 ps
CPU time 1423.92 seconds
Started Aug 12 05:04:31 PM PDT 24
Finished Aug 12 05:28:15 PM PDT 24
Peak memory 200568 kb
Host smart-bb268c84-e58f-4a83-8121-dbf1bd62d90f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2341774763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.2341774763
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.2586069897
Short name T339
Test name
Test status
Simulation time 169149283 ps
CPU time 0.88 seconds
Started Aug 12 05:04:29 PM PDT 24
Finished Aug 12 05:04:30 PM PDT 24
Peak memory 197924 kb
Host smart-b86d7ba9-8549-4f0f-9734-65a6325ead8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586069897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2586069897
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2598134049
Short name T995
Test name
Test status
Simulation time 102230566627 ps
CPU time 30.04 seconds
Started Aug 12 05:04:39 PM PDT 24
Finished Aug 12 05:05:09 PM PDT 24
Peak memory 200400 kb
Host smart-9c824915-3d8e-49ba-9e5b-d727b7679ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598134049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2598134049
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.1695797087
Short name T3
Test name
Test status
Simulation time 33521816107 ps
CPU time 1951.89 seconds
Started Aug 12 05:04:36 PM PDT 24
Finished Aug 12 05:37:08 PM PDT 24
Peak memory 200888 kb
Host smart-d24ea777-fdc4-40df-8fc8-b24d7d4964ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1695797087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.1695797087
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3254608217
Short name T1076
Test name
Test status
Simulation time 1484577418 ps
CPU time 3.02 seconds
Started Aug 12 05:04:31 PM PDT 24
Finished Aug 12 05:04:34 PM PDT 24
Peak memory 198892 kb
Host smart-fce2c70b-c1af-423d-8df9-94dfde1a757a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3254608217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3254608217
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1647408858
Short name T1082
Test name
Test status
Simulation time 21151221007 ps
CPU time 27.96 seconds
Started Aug 12 05:04:31 PM PDT 24
Finished Aug 12 05:04:59 PM PDT 24
Peak memory 199516 kb
Host smart-392aa272-3326-46f2-82ed-d3dc440ae0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647408858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1647408858
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2313246912
Short name T521
Test name
Test status
Simulation time 33678984861 ps
CPU time 51.73 seconds
Started Aug 12 05:04:38 PM PDT 24
Finished Aug 12 05:05:30 PM PDT 24
Peak memory 196532 kb
Host smart-0a1e2ab0-1ecc-4795-943d-3894ca78b2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313246912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2313246912
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1096096155
Short name T559
Test name
Test status
Simulation time 682760729 ps
CPU time 1.48 seconds
Started Aug 12 05:04:38 PM PDT 24
Finished Aug 12 05:04:40 PM PDT 24
Peak memory 200716 kb
Host smart-184eb0f0-8fa2-4db7-9e58-517e3ea829d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096096155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1096096155
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.2916443074
Short name T111
Test name
Test status
Simulation time 276544232846 ps
CPU time 120.83 seconds
Started Aug 12 05:04:38 PM PDT 24
Finished Aug 12 05:06:39 PM PDT 24
Peak memory 200684 kb
Host smart-7e82946a-64ef-468a-8b8c-a2f4d11e3338
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916443074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2916443074
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3170476175
Short name T924
Test name
Test status
Simulation time 4649135122 ps
CPU time 87.46 seconds
Started Aug 12 05:04:40 PM PDT 24
Finished Aug 12 05:06:08 PM PDT 24
Peak memory 216700 kb
Host smart-4059d22c-e766-48b9-a0d1-cc63931d2d2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170476175 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3170476175
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1309270853
Short name T421
Test name
Test status
Simulation time 6985754387 ps
CPU time 19.58 seconds
Started Aug 12 05:04:38 PM PDT 24
Finished Aug 12 05:04:58 PM PDT 24
Peak memory 200472 kb
Host smart-f5c460c6-ae3e-4bc0-bb15-93fdf82c47f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309270853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1309270853
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.3154542311
Short name T604
Test name
Test status
Simulation time 35160685651 ps
CPU time 53.11 seconds
Started Aug 12 05:04:33 PM PDT 24
Finished Aug 12 05:05:26 PM PDT 24
Peak memory 200776 kb
Host smart-6087c5ed-8ee4-44c8-8445-5dc897264cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154542311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3154542311
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.1460427842
Short name T707
Test name
Test status
Simulation time 79343601856 ps
CPU time 34.56 seconds
Started Aug 12 05:06:57 PM PDT 24
Finished Aug 12 05:07:32 PM PDT 24
Peak memory 200656 kb
Host smart-6cb109d8-d0dc-4133-98fc-bfffa6e14c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460427842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1460427842
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3690262093
Short name T190
Test name
Test status
Simulation time 15432126438 ps
CPU time 21.81 seconds
Started Aug 12 05:06:57 PM PDT 24
Finished Aug 12 05:07:19 PM PDT 24
Peak memory 200772 kb
Host smart-486fe178-6b9b-4278-baeb-091fe6ec2b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690262093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3690262093
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2934347641
Short name T204
Test name
Test status
Simulation time 94239049021 ps
CPU time 71.36 seconds
Started Aug 12 05:06:58 PM PDT 24
Finished Aug 12 05:08:10 PM PDT 24
Peak memory 200844 kb
Host smart-f4ca63d1-c5cf-4f41-a94e-eaf2202204f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934347641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2934347641
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2415552356
Short name T665
Test name
Test status
Simulation time 43884921644 ps
CPU time 37.47 seconds
Started Aug 12 05:06:57 PM PDT 24
Finished Aug 12 05:07:35 PM PDT 24
Peak memory 200776 kb
Host smart-180ad9cd-e27f-4a27-8ef3-70ba44d83a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415552356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2415552356
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.3865302696
Short name T1126
Test name
Test status
Simulation time 109758709891 ps
CPU time 171.66 seconds
Started Aug 12 05:06:57 PM PDT 24
Finished Aug 12 05:09:49 PM PDT 24
Peak memory 200828 kb
Host smart-0a283ee6-7c87-45e4-ae0c-aa61c0e65aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865302696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3865302696
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2238805900
Short name T807
Test name
Test status
Simulation time 24175471167 ps
CPU time 28.86 seconds
Started Aug 12 05:06:58 PM PDT 24
Finished Aug 12 05:07:27 PM PDT 24
Peak memory 200812 kb
Host smart-671418fa-14c0-44b0-af9a-e2c20718d6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238805900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2238805900
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2206502874
Short name T1003
Test name
Test status
Simulation time 168506559006 ps
CPU time 41.61 seconds
Started Aug 12 05:06:57 PM PDT 24
Finished Aug 12 05:07:38 PM PDT 24
Peak memory 200608 kb
Host smart-ed1134a8-d689-4683-b3e0-9f1c68ab15b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206502874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2206502874
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.1834396888
Short name T500
Test name
Test status
Simulation time 85572491038 ps
CPU time 73.77 seconds
Started Aug 12 05:06:59 PM PDT 24
Finished Aug 12 05:08:13 PM PDT 24
Peak memory 200732 kb
Host smart-afb73c8a-d8eb-450a-8306-bd71ca62a572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834396888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1834396888
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2458662205
Short name T159
Test name
Test status
Simulation time 10838414335 ps
CPU time 17.4 seconds
Started Aug 12 05:06:57 PM PDT 24
Finished Aug 12 05:07:14 PM PDT 24
Peak memory 200252 kb
Host smart-23b6cbd1-e459-41f5-8dec-e814532e747b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458662205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2458662205
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1721293350
Short name T862
Test name
Test status
Simulation time 218112697726 ps
CPU time 63.15 seconds
Started Aug 12 05:06:57 PM PDT 24
Finished Aug 12 05:08:00 PM PDT 24
Peak memory 200660 kb
Host smart-493911f7-62f3-420e-b3f0-9e318eca2cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721293350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1721293350
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2809242584
Short name T327
Test name
Test status
Simulation time 12074984 ps
CPU time 0.61 seconds
Started Aug 12 05:04:36 PM PDT 24
Finished Aug 12 05:04:37 PM PDT 24
Peak memory 196420 kb
Host smart-d2dbb216-da20-4019-a447-50531bb91201
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809242584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2809242584
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2892829308
Short name T1056
Test name
Test status
Simulation time 25092000416 ps
CPU time 34.33 seconds
Started Aug 12 05:04:39 PM PDT 24
Finished Aug 12 05:05:14 PM PDT 24
Peak memory 200804 kb
Host smart-a612c1fa-fd14-4a4f-a76b-792cc321f550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892829308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2892829308
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.1565287452
Short name T550
Test name
Test status
Simulation time 110428433607 ps
CPU time 82.2 seconds
Started Aug 12 05:04:39 PM PDT 24
Finished Aug 12 05:06:01 PM PDT 24
Peak memory 200468 kb
Host smart-8a282472-ae16-4870-aa30-82b3e7bfd6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565287452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1565287452
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.499894745
Short name T1148
Test name
Test status
Simulation time 142389693840 ps
CPU time 248.45 seconds
Started Aug 12 05:04:40 PM PDT 24
Finished Aug 12 05:08:48 PM PDT 24
Peak memory 200704 kb
Host smart-68bd3b8d-bce9-4402-b703-26f952e3f5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499894745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.499894745
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.536594494
Short name T71
Test name
Test status
Simulation time 54711348329 ps
CPU time 50.41 seconds
Started Aug 12 05:04:37 PM PDT 24
Finished Aug 12 05:05:27 PM PDT 24
Peak memory 200712 kb
Host smart-2fc8e8bf-d0cd-4cd4-ac19-85c1c521d92c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536594494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.536594494
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.1624747969
Short name T568
Test name
Test status
Simulation time 121868790694 ps
CPU time 866.54 seconds
Started Aug 12 05:04:37 PM PDT 24
Finished Aug 12 05:19:03 PM PDT 24
Peak memory 200708 kb
Host smart-f7d0784f-bad9-4627-85bf-5c6533bf16fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1624747969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.1624747969
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.1019013409
Short name T708
Test name
Test status
Simulation time 11371685623 ps
CPU time 24.25 seconds
Started Aug 12 05:04:37 PM PDT 24
Finished Aug 12 05:05:02 PM PDT 24
Peak memory 200484 kb
Host smart-3ce23d59-f610-4234-8f1e-aa0d736680c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019013409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1019013409
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.1057345246
Short name T653
Test name
Test status
Simulation time 199905498991 ps
CPU time 95.28 seconds
Started Aug 12 05:04:39 PM PDT 24
Finished Aug 12 05:06:15 PM PDT 24
Peak memory 201028 kb
Host smart-94d6cc83-5e06-4b80-945f-26c75a9919c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057345246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1057345246
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.1375137229
Short name T920
Test name
Test status
Simulation time 23291871101 ps
CPU time 1230.39 seconds
Started Aug 12 05:04:38 PM PDT 24
Finished Aug 12 05:25:09 PM PDT 24
Peak memory 200724 kb
Host smart-1eec3c62-89b0-4bfc-b9ea-e0f091a7614e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1375137229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1375137229
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1071607825
Short name T380
Test name
Test status
Simulation time 4636383761 ps
CPU time 8.54 seconds
Started Aug 12 05:04:38 PM PDT 24
Finished Aug 12 05:04:47 PM PDT 24
Peak memory 198912 kb
Host smart-53323186-4673-4720-a651-b4a1ff44dc4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1071607825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1071607825
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2771733506
Short name T1143
Test name
Test status
Simulation time 10107507756 ps
CPU time 17.35 seconds
Started Aug 12 05:04:39 PM PDT 24
Finished Aug 12 05:04:56 PM PDT 24
Peak memory 200552 kb
Host smart-f4d64a78-f389-421b-80b0-1bf1f2cba80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771733506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2771733506
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.495876828
Short name T1104
Test name
Test status
Simulation time 34151919933 ps
CPU time 12.83 seconds
Started Aug 12 05:04:39 PM PDT 24
Finished Aug 12 05:04:52 PM PDT 24
Peak memory 197532 kb
Host smart-98b53b53-c032-41ef-bbca-c49840093348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495876828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.495876828
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.2584738162
Short name T594
Test name
Test status
Simulation time 284506190 ps
CPU time 1.87 seconds
Started Aug 12 05:04:38 PM PDT 24
Finished Aug 12 05:04:40 PM PDT 24
Peak memory 199720 kb
Host smart-a21e6f03-1ff2-4b30-92b8-7c6e58f2718e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584738162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2584738162
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.3834006704
Short name T566
Test name
Test status
Simulation time 124711730010 ps
CPU time 192.24 seconds
Started Aug 12 05:04:39 PM PDT 24
Finished Aug 12 05:07:51 PM PDT 24
Peak memory 209192 kb
Host smart-3103991c-5618-485c-bd99-1a8471e1974e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834006704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3834006704
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.732910169
Short name T160
Test name
Test status
Simulation time 5777940244 ps
CPU time 32.54 seconds
Started Aug 12 05:04:38 PM PDT 24
Finished Aug 12 05:05:11 PM PDT 24
Peak memory 217276 kb
Host smart-eb863204-943b-4c37-b471-7b234c0778ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732910169 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.732910169
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2994845146
Short name T497
Test name
Test status
Simulation time 1984143127 ps
CPU time 2.24 seconds
Started Aug 12 05:04:39 PM PDT 24
Finished Aug 12 05:04:41 PM PDT 24
Peak memory 200640 kb
Host smart-b4d49b26-dcbe-412d-9f72-d7a24a2290a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994845146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2994845146
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2744530240
Short name T378
Test name
Test status
Simulation time 116531611571 ps
CPU time 59.91 seconds
Started Aug 12 05:04:39 PM PDT 24
Finished Aug 12 05:05:39 PM PDT 24
Peak memory 200808 kb
Host smart-ff1502c1-e45e-49bb-bdd7-71fbdc733bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744530240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2744530240
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.3161201327
Short name T562
Test name
Test status
Simulation time 69570237829 ps
CPU time 145.05 seconds
Started Aug 12 05:06:56 PM PDT 24
Finished Aug 12 05:09:21 PM PDT 24
Peak memory 200724 kb
Host smart-6c79fb5c-c462-4e27-82c4-1c8c88334b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161201327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3161201327
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3492306984
Short name T1114
Test name
Test status
Simulation time 132516899184 ps
CPU time 30.84 seconds
Started Aug 12 05:07:01 PM PDT 24
Finished Aug 12 05:07:32 PM PDT 24
Peak memory 200732 kb
Host smart-7f6f56cb-e427-40d1-831c-d6a1cf8bb7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492306984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3492306984
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2735120736
Short name T186
Test name
Test status
Simulation time 34499578806 ps
CPU time 14.99 seconds
Started Aug 12 05:06:57 PM PDT 24
Finished Aug 12 05:07:12 PM PDT 24
Peak memory 200716 kb
Host smart-6ae6b07a-8548-4bc5-93a4-0b93836fce0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735120736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2735120736
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1455181883
Short name T198
Test name
Test status
Simulation time 10255383421 ps
CPU time 10.94 seconds
Started Aug 12 05:06:57 PM PDT 24
Finished Aug 12 05:07:08 PM PDT 24
Peak memory 200844 kb
Host smart-45e96366-504f-495a-9ff4-1b5da5504ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455181883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1455181883
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.52985665
Short name T1078
Test name
Test status
Simulation time 12843992310 ps
CPU time 27.04 seconds
Started Aug 12 05:07:04 PM PDT 24
Finished Aug 12 05:07:31 PM PDT 24
Peak memory 200820 kb
Host smart-551a872f-2d20-4d4a-847b-06dfd77f3208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52985665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.52985665
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.4085227791
Short name T490
Test name
Test status
Simulation time 36283848388 ps
CPU time 19.02 seconds
Started Aug 12 05:06:56 PM PDT 24
Finished Aug 12 05:07:15 PM PDT 24
Peak memory 200720 kb
Host smart-d153c029-4422-4bd4-9bbb-4a2f824120be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085227791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.4085227791
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1578819820
Short name T222
Test name
Test status
Simulation time 69569469849 ps
CPU time 45.43 seconds
Started Aug 12 05:06:57 PM PDT 24
Finished Aug 12 05:07:43 PM PDT 24
Peak memory 200648 kb
Host smart-a6bd128f-da6f-47e1-a630-1a38fcbed3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578819820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1578819820
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.284353529
Short name T287
Test name
Test status
Simulation time 191915924347 ps
CPU time 74.25 seconds
Started Aug 12 05:07:00 PM PDT 24
Finished Aug 12 05:08:14 PM PDT 24
Peak memory 200728 kb
Host smart-bb0c686c-15ba-4e32-9945-82129aa396f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284353529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.284353529
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.4158561324
Short name T265
Test name
Test status
Simulation time 69900887452 ps
CPU time 8.5 seconds
Started Aug 12 05:07:05 PM PDT 24
Finished Aug 12 05:07:13 PM PDT 24
Peak memory 198804 kb
Host smart-ae135c66-9ad7-41e0-888a-0c42b67a1a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158561324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.4158561324
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.3977107534
Short name T1146
Test name
Test status
Simulation time 16711809995 ps
CPU time 25.68 seconds
Started Aug 12 05:07:03 PM PDT 24
Finished Aug 12 05:07:28 PM PDT 24
Peak memory 200644 kb
Host smart-8c2b907d-7cba-4bb0-82e3-1282163d7e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977107534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3977107534
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2419781877
Short name T843
Test name
Test status
Simulation time 11430951 ps
CPU time 0.57 seconds
Started Aug 12 05:04:46 PM PDT 24
Finished Aug 12 05:04:46 PM PDT 24
Peak memory 196116 kb
Host smart-ba4a1bb4-40ea-4241-b92f-264e43077e79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419781877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2419781877
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1134787622
Short name T813
Test name
Test status
Simulation time 106986612800 ps
CPU time 64.87 seconds
Started Aug 12 05:04:38 PM PDT 24
Finished Aug 12 05:05:43 PM PDT 24
Peak memory 200772 kb
Host smart-27a9a4a4-7f40-4644-836a-3b8b446ae2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134787622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1134787622
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.2022077853
Short name T1102
Test name
Test status
Simulation time 57227616794 ps
CPU time 22.61 seconds
Started Aug 12 05:04:39 PM PDT 24
Finished Aug 12 05:05:02 PM PDT 24
Peak memory 199624 kb
Host smart-16951978-9509-43da-8d0a-d25325cf9bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022077853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2022077853
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3877803794
Short name T659
Test name
Test status
Simulation time 86035206941 ps
CPU time 32.72 seconds
Started Aug 12 05:04:39 PM PDT 24
Finished Aug 12 05:05:12 PM PDT 24
Peak memory 200552 kb
Host smart-d3617a56-109a-4f70-9a30-3cd0406eae35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877803794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3877803794
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.3404310357
Short name T307
Test name
Test status
Simulation time 325300774469 ps
CPU time 147.66 seconds
Started Aug 12 05:04:38 PM PDT 24
Finished Aug 12 05:07:06 PM PDT 24
Peak memory 200748 kb
Host smart-54d6eb1c-b71a-4fb0-bc3b-4ebe660562d4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404310357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3404310357
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.671344084
Short name T243
Test name
Test status
Simulation time 121647461498 ps
CPU time 314.09 seconds
Started Aug 12 05:04:45 PM PDT 24
Finished Aug 12 05:10:00 PM PDT 24
Peak memory 200704 kb
Host smart-4b47fbdf-aca2-4b72-a6e7-a723f6172618
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=671344084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.671344084
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3643720183
Short name T1115
Test name
Test status
Simulation time 12773276040 ps
CPU time 11.88 seconds
Started Aug 12 05:04:48 PM PDT 24
Finished Aug 12 05:05:00 PM PDT 24
Peak memory 198960 kb
Host smart-11f3f597-6a72-4804-b579-9f0203d1def8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643720183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3643720183
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1102426773
Short name T1127
Test name
Test status
Simulation time 48192896458 ps
CPU time 92.92 seconds
Started Aug 12 05:04:36 PM PDT 24
Finished Aug 12 05:06:10 PM PDT 24
Peak memory 200908 kb
Host smart-40223189-cd69-412c-8864-3f4a33d40d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102426773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1102426773
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.4142203024
Short name T902
Test name
Test status
Simulation time 11354911713 ps
CPU time 101.99 seconds
Started Aug 12 05:04:46 PM PDT 24
Finished Aug 12 05:06:28 PM PDT 24
Peak memory 200700 kb
Host smart-51df4541-e102-4ff7-8b49-18967b675b6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4142203024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.4142203024
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.2451956554
Short name T687
Test name
Test status
Simulation time 3899667304 ps
CPU time 28.14 seconds
Started Aug 12 05:04:39 PM PDT 24
Finished Aug 12 05:05:07 PM PDT 24
Peak memory 198820 kb
Host smart-0ca7aecd-8cd5-4b74-bdbb-efe5ae55fa3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2451956554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2451956554
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1018482655
Short name T822
Test name
Test status
Simulation time 4611800797 ps
CPU time 7.9 seconds
Started Aug 12 05:04:38 PM PDT 24
Finished Aug 12 05:04:46 PM PDT 24
Peak memory 197040 kb
Host smart-e5b3cb1a-1a52-49f6-ab2a-62bb2c9b3e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018482655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1018482655
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.3344143603
Short name T308
Test name
Test status
Simulation time 5687908489 ps
CPU time 17.01 seconds
Started Aug 12 05:04:43 PM PDT 24
Finished Aug 12 05:05:00 PM PDT 24
Peak memory 200584 kb
Host smart-0fa78bdc-5397-4a5a-8c07-5cc3a9919975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344143603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3344143603
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.2055088649
Short name T1150
Test name
Test status
Simulation time 198329088474 ps
CPU time 47.49 seconds
Started Aug 12 05:04:45 PM PDT 24
Finished Aug 12 05:05:33 PM PDT 24
Peak memory 200840 kb
Host smart-9524eb1a-7810-4b08-ad2e-861847b9ffbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055088649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2055088649
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3499875862
Short name T108
Test name
Test status
Simulation time 12522324664 ps
CPU time 95.92 seconds
Started Aug 12 05:04:45 PM PDT 24
Finished Aug 12 05:06:21 PM PDT 24
Peak memory 209412 kb
Host smart-4eea08fb-ef8b-49ac-b791-f8da3e46eac7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499875862 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3499875862
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.428349277
Short name T639
Test name
Test status
Simulation time 398128291 ps
CPU time 2.17 seconds
Started Aug 12 05:04:37 PM PDT 24
Finished Aug 12 05:04:39 PM PDT 24
Peak memory 199396 kb
Host smart-e003f403-ef97-4f29-bdc4-cfcf5447ba91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428349277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.428349277
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1783572229
Short name T1107
Test name
Test status
Simulation time 19923849992 ps
CPU time 35.06 seconds
Started Aug 12 05:04:37 PM PDT 24
Finished Aug 12 05:05:12 PM PDT 24
Peak memory 200740 kb
Host smart-76de1edf-ab66-4e93-9cdb-b555cc8f93d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783572229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1783572229
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.4016634911
Short name T219
Test name
Test status
Simulation time 131354381975 ps
CPU time 133.68 seconds
Started Aug 12 05:07:04 PM PDT 24
Finished Aug 12 05:09:17 PM PDT 24
Peak memory 200708 kb
Host smart-ee643c28-0437-42e3-8a8f-bc144661339b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016634911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.4016634911
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1551482498
Short name T802
Test name
Test status
Simulation time 29169625110 ps
CPU time 17.1 seconds
Started Aug 12 05:07:10 PM PDT 24
Finished Aug 12 05:07:27 PM PDT 24
Peak memory 200664 kb
Host smart-515d2652-1052-4f58-a51f-68ea45639ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551482498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1551482498
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1742038009
Short name T174
Test name
Test status
Simulation time 8480882898 ps
CPU time 10.22 seconds
Started Aug 12 05:07:01 PM PDT 24
Finished Aug 12 05:07:12 PM PDT 24
Peak memory 200808 kb
Host smart-61ff9c0d-77de-4faf-adfe-d4e1a4fa611c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742038009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1742038009
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1020195535
Short name T322
Test name
Test status
Simulation time 15058053262 ps
CPU time 28.03 seconds
Started Aug 12 05:07:03 PM PDT 24
Finished Aug 12 05:07:32 PM PDT 24
Peak memory 200728 kb
Host smart-523bbb8d-b5d4-459f-b107-973b1c9631b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020195535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1020195535
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2188097630
Short name T588
Test name
Test status
Simulation time 38361779179 ps
CPU time 9.09 seconds
Started Aug 12 05:07:03 PM PDT 24
Finished Aug 12 05:07:12 PM PDT 24
Peak memory 200364 kb
Host smart-a340a05a-936c-4e5d-a452-ce8739592018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188097630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2188097630
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.761762157
Short name T162
Test name
Test status
Simulation time 84346414924 ps
CPU time 25.47 seconds
Started Aug 12 05:07:02 PM PDT 24
Finished Aug 12 05:07:27 PM PDT 24
Peak memory 200672 kb
Host smart-f040ef28-3b2c-4b5d-8e76-b0fe19e9b209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761762157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.761762157
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.1991060349
Short name T187
Test name
Test status
Simulation time 90614340389 ps
CPU time 132.49 seconds
Started Aug 12 05:07:02 PM PDT 24
Finished Aug 12 05:09:14 PM PDT 24
Peak memory 200664 kb
Host smart-b0887cc6-6d9e-4133-8a9d-03fe14c66af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991060349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.1991060349
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.2388647185
Short name T667
Test name
Test status
Simulation time 32232341372 ps
CPU time 47.26 seconds
Started Aug 12 05:07:04 PM PDT 24
Finished Aug 12 05:07:51 PM PDT 24
Peak memory 200828 kb
Host smart-52e46dee-d015-411a-b543-2b97b1423101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388647185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2388647185
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.90619714
Short name T994
Test name
Test status
Simulation time 51245668806 ps
CPU time 22.26 seconds
Started Aug 12 05:07:10 PM PDT 24
Finished Aug 12 05:07:32 PM PDT 24
Peak memory 200124 kb
Host smart-8e1d8576-4607-4222-8198-205174a06d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90619714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.90619714
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2386357002
Short name T147
Test name
Test status
Simulation time 23373861683 ps
CPU time 40.82 seconds
Started Aug 12 05:07:12 PM PDT 24
Finished Aug 12 05:07:52 PM PDT 24
Peak memory 200664 kb
Host smart-b407e2f3-0db2-46d3-8e38-93a38c61a087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386357002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2386357002
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.682052181
Short name T824
Test name
Test status
Simulation time 12646755 ps
CPU time 0.59 seconds
Started Aug 12 05:04:46 PM PDT 24
Finished Aug 12 05:04:46 PM PDT 24
Peak memory 195460 kb
Host smart-1920482f-e790-432d-b5a1-4de6c81dc5ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682052181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.682052181
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.1075421419
Short name T392
Test name
Test status
Simulation time 88768188878 ps
CPU time 77.41 seconds
Started Aug 12 05:04:47 PM PDT 24
Finished Aug 12 05:06:05 PM PDT 24
Peak memory 200808 kb
Host smart-5ff28ef9-c1f8-4e3d-89eb-a100405a4151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075421419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1075421419
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.2656276149
Short name T239
Test name
Test status
Simulation time 224115574697 ps
CPU time 76.81 seconds
Started Aug 12 05:04:45 PM PDT 24
Finished Aug 12 05:06:02 PM PDT 24
Peak memory 200724 kb
Host smart-7701497e-8952-436a-8b47-34f278fafd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656276149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2656276149
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.2725057616
Short name T137
Test name
Test status
Simulation time 36196022182 ps
CPU time 13.95 seconds
Started Aug 12 05:04:47 PM PDT 24
Finished Aug 12 05:05:01 PM PDT 24
Peak memory 200844 kb
Host smart-e282a176-c033-45e3-9e44-511f94faab9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725057616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2725057616
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.16767587
Short name T913
Test name
Test status
Simulation time 145904786148 ps
CPU time 144.68 seconds
Started Aug 12 05:04:44 PM PDT 24
Finished Aug 12 05:07:09 PM PDT 24
Peak memory 200500 kb
Host smart-e00c06f9-97b3-41d0-9403-408b4ff6c5dd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16767587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.16767587
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.350539329
Short name T811
Test name
Test status
Simulation time 87208245095 ps
CPU time 379.83 seconds
Started Aug 12 05:04:46 PM PDT 24
Finished Aug 12 05:11:06 PM PDT 24
Peak memory 200684 kb
Host smart-5ee46e14-6614-4d9d-9c98-90a707af1e2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=350539329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.350539329
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2117626627
Short name T682
Test name
Test status
Simulation time 7308694762 ps
CPU time 11.61 seconds
Started Aug 12 05:04:46 PM PDT 24
Finished Aug 12 05:04:58 PM PDT 24
Peak memory 199820 kb
Host smart-a932d878-0607-4205-b9a7-61a7d1e70697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117626627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2117626627
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.211129646
Short name T303
Test name
Test status
Simulation time 157924652078 ps
CPU time 118.23 seconds
Started Aug 12 05:04:46 PM PDT 24
Finished Aug 12 05:06:45 PM PDT 24
Peak memory 200576 kb
Host smart-243173ba-d110-41c8-8b03-582302ce205a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211129646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.211129646
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.3739687339
Short name T507
Test name
Test status
Simulation time 16122824247 ps
CPU time 199.71 seconds
Started Aug 12 05:04:45 PM PDT 24
Finished Aug 12 05:08:05 PM PDT 24
Peak memory 200804 kb
Host smart-ad270acc-b4ef-46f5-a2aa-31b72303c785
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3739687339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3739687339
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1350161955
Short name T346
Test name
Test status
Simulation time 4719190540 ps
CPU time 4.71 seconds
Started Aug 12 05:04:45 PM PDT 24
Finished Aug 12 05:04:50 PM PDT 24
Peak memory 198940 kb
Host smart-3a826a71-b90c-4915-bdae-32ef34564355
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1350161955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1350161955
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.835312778
Short name T238
Test name
Test status
Simulation time 22574488218 ps
CPU time 33.16 seconds
Started Aug 12 05:04:48 PM PDT 24
Finished Aug 12 05:05:21 PM PDT 24
Peak memory 200852 kb
Host smart-6c1e265a-ea8e-4a2d-9afc-44e077819dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835312778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.835312778
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3165234885
Short name T442
Test name
Test status
Simulation time 5639657911 ps
CPU time 2.63 seconds
Started Aug 12 05:04:44 PM PDT 24
Finished Aug 12 05:04:47 PM PDT 24
Peak memory 196976 kb
Host smart-7dbbef14-568e-48f1-b996-f5ad27c5c970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165234885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3165234885
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.505555904
Short name T844
Test name
Test status
Simulation time 309569407 ps
CPU time 1.15 seconds
Started Aug 12 05:04:47 PM PDT 24
Finished Aug 12 05:04:49 PM PDT 24
Peak memory 199260 kb
Host smart-5a559ee1-f9b3-49dd-92c0-ac88a84bd46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505555904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.505555904
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1555578026
Short name T518
Test name
Test status
Simulation time 183218433818 ps
CPU time 686.13 seconds
Started Aug 12 05:04:47 PM PDT 24
Finished Aug 12 05:16:14 PM PDT 24
Peak memory 200744 kb
Host smart-4c39b64f-3a50-4c0d-a614-761216c0f0cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555578026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1555578026
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.95944276
Short name T875
Test name
Test status
Simulation time 3313457052 ps
CPU time 38.64 seconds
Started Aug 12 05:04:44 PM PDT 24
Finished Aug 12 05:05:23 PM PDT 24
Peak memory 217136 kb
Host smart-b79d2444-c102-425d-ab68-8e708d939d7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95944276 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.95944276
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1191351827
Short name T586
Test name
Test status
Simulation time 1888074291 ps
CPU time 2.7 seconds
Started Aug 12 05:04:45 PM PDT 24
Finished Aug 12 05:04:48 PM PDT 24
Peak memory 199188 kb
Host smart-22cb1b09-f8a0-493f-819a-105a79adabd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191351827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1191351827
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.3671069836
Short name T470
Test name
Test status
Simulation time 14550454073 ps
CPU time 25.85 seconds
Started Aug 12 05:04:48 PM PDT 24
Finished Aug 12 05:05:14 PM PDT 24
Peak memory 200836 kb
Host smart-b0ebe47b-6de7-4f6c-a78f-c0157fa34e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671069836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3671069836
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1712893449
Short name T1124
Test name
Test status
Simulation time 147088522472 ps
CPU time 151.27 seconds
Started Aug 12 05:07:02 PM PDT 24
Finished Aug 12 05:09:33 PM PDT 24
Peak memory 200800 kb
Host smart-caabeea7-4e07-45a2-843e-720f3a0f7039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712893449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1712893449
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.785374550
Short name T125
Test name
Test status
Simulation time 25920891686 ps
CPU time 22.17 seconds
Started Aug 12 05:07:11 PM PDT 24
Finished Aug 12 05:07:33 PM PDT 24
Peak memory 200612 kb
Host smart-d73a5a45-385c-47a8-9ae1-b2a005ab294b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785374550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.785374550
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3383777436
Short name T193
Test name
Test status
Simulation time 162919690130 ps
CPU time 254.92 seconds
Started Aug 12 05:07:04 PM PDT 24
Finished Aug 12 05:11:19 PM PDT 24
Peak memory 200696 kb
Host smart-a29cf470-24e7-4e47-90d6-3f9e20f4625a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383777436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3383777436
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3871174863
Short name T864
Test name
Test status
Simulation time 20089460194 ps
CPU time 26.53 seconds
Started Aug 12 05:07:12 PM PDT 24
Finished Aug 12 05:07:38 PM PDT 24
Peak memory 200792 kb
Host smart-f1e9ce13-e52e-4ff0-a97b-1220bba2e6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871174863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3871174863
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1059474117
Short name T233
Test name
Test status
Simulation time 21769708568 ps
CPU time 21.74 seconds
Started Aug 12 05:07:13 PM PDT 24
Finished Aug 12 05:07:35 PM PDT 24
Peak memory 200756 kb
Host smart-3bee0022-a1e4-41da-8574-fe68b154e4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059474117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1059474117
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1748937869
Short name T1090
Test name
Test status
Simulation time 33775440779 ps
CPU time 15.95 seconds
Started Aug 12 05:07:11 PM PDT 24
Finished Aug 12 05:07:27 PM PDT 24
Peak memory 200816 kb
Host smart-18fd9b45-b765-411a-a3ff-ef98888ccb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748937869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1748937869
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.1513221913
Short name T683
Test name
Test status
Simulation time 34856855805 ps
CPU time 39.09 seconds
Started Aug 12 05:07:11 PM PDT 24
Finished Aug 12 05:07:50 PM PDT 24
Peak memory 200736 kb
Host smart-04c68fb4-334e-4339-9118-31583d9694ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513221913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1513221913
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2955079486
Short name T873
Test name
Test status
Simulation time 9843118728 ps
CPU time 12.18 seconds
Started Aug 12 05:07:12 PM PDT 24
Finished Aug 12 05:07:25 PM PDT 24
Peak memory 200756 kb
Host smart-03bd696b-9686-4f08-b374-fe96c089db33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955079486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2955079486
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.650964976
Short name T140
Test name
Test status
Simulation time 51657701787 ps
CPU time 78.17 seconds
Started Aug 12 05:07:12 PM PDT 24
Finished Aug 12 05:08:30 PM PDT 24
Peak memory 200732 kb
Host smart-3ad9f543-c7f6-4347-ba9b-f1fff4ec1394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650964976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.650964976
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.1750038962
Short name T1184
Test name
Test status
Simulation time 137748427096 ps
CPU time 78.03 seconds
Started Aug 12 05:07:14 PM PDT 24
Finished Aug 12 05:08:32 PM PDT 24
Peak memory 200812 kb
Host smart-0f543238-3603-401e-ad75-bf74eef8b670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750038962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1750038962
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3083234684
Short name T335
Test name
Test status
Simulation time 19347789 ps
CPU time 0.56 seconds
Started Aug 12 05:04:56 PM PDT 24
Finished Aug 12 05:04:56 PM PDT 24
Peak memory 196096 kb
Host smart-021ab4bf-61ce-47d0-bc3f-5a4b2b1c2da7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083234684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3083234684
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3096116903
Short name T643
Test name
Test status
Simulation time 58405081893 ps
CPU time 12.01 seconds
Started Aug 12 05:04:48 PM PDT 24
Finished Aug 12 05:05:00 PM PDT 24
Peak memory 200752 kb
Host smart-54abd06f-8c5c-414c-b254-69adbb83b10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096116903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3096116903
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.3595367953
Short name T143
Test name
Test status
Simulation time 17427658628 ps
CPU time 13.95 seconds
Started Aug 12 05:04:46 PM PDT 24
Finished Aug 12 05:05:00 PM PDT 24
Peak memory 200672 kb
Host smart-95668750-7d07-4732-a989-f6181533ab7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595367953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3595367953
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.4087596398
Short name T614
Test name
Test status
Simulation time 56818415439 ps
CPU time 41.82 seconds
Started Aug 12 05:04:47 PM PDT 24
Finished Aug 12 05:05:29 PM PDT 24
Peak memory 200744 kb
Host smart-6a7d264f-b9c8-4bdd-94cc-5037dfb27672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087596398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.4087596398
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.706374171
Short name T426
Test name
Test status
Simulation time 63843260521 ps
CPU time 93.64 seconds
Started Aug 12 05:04:46 PM PDT 24
Finished Aug 12 05:06:19 PM PDT 24
Peak memory 198528 kb
Host smart-c16ad264-f674-4417-a86c-235592d9bca1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706374171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.706374171
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.3612092611
Short name T537
Test name
Test status
Simulation time 135322609632 ps
CPU time 422.22 seconds
Started Aug 12 05:04:53 PM PDT 24
Finished Aug 12 05:11:55 PM PDT 24
Peak memory 200716 kb
Host smart-2c9560a7-603f-45f9-ad6d-f75201bd575f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3612092611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3612092611
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1076294031
Short name T357
Test name
Test status
Simulation time 2864956320 ps
CPU time 3.94 seconds
Started Aug 12 05:04:50 PM PDT 24
Finished Aug 12 05:04:54 PM PDT 24
Peak memory 198108 kb
Host smart-80cd7a15-7a34-4b9f-945a-8883a033e678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076294031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1076294031
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.2934952428
Short name T975
Test name
Test status
Simulation time 303982847321 ps
CPU time 58.69 seconds
Started Aug 12 05:04:45 PM PDT 24
Finished Aug 12 05:05:44 PM PDT 24
Peak memory 209048 kb
Host smart-ac56e88e-abda-4512-baab-ad65a62b1f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934952428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2934952428
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.4036652162
Short name T255
Test name
Test status
Simulation time 9707004121 ps
CPU time 122.78 seconds
Started Aug 12 05:04:49 PM PDT 24
Finished Aug 12 05:06:52 PM PDT 24
Peak memory 200684 kb
Host smart-41776545-6513-4e1a-b6d9-d0f560e8f6b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4036652162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.4036652162
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.726090041
Short name T821
Test name
Test status
Simulation time 5847018858 ps
CPU time 48.61 seconds
Started Aug 12 05:04:47 PM PDT 24
Finished Aug 12 05:05:36 PM PDT 24
Peak memory 200748 kb
Host smart-4795c6d8-6126-4cfc-b584-58415a402144
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=726090041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.726090041
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.864579340
Short name T367
Test name
Test status
Simulation time 21503849381 ps
CPU time 11.88 seconds
Started Aug 12 05:04:53 PM PDT 24
Finished Aug 12 05:05:06 PM PDT 24
Peak memory 200676 kb
Host smart-93d1b801-3c44-4e85-9d29-d57e7a96d076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864579340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.864579340
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1525547613
Short name T1134
Test name
Test status
Simulation time 3254533310 ps
CPU time 1.83 seconds
Started Aug 12 05:04:47 PM PDT 24
Finished Aug 12 05:04:48 PM PDT 24
Peak memory 197244 kb
Host smart-9e856d40-368a-48f8-bae4-3eda27f20a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525547613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1525547613
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.697459178
Short name T4
Test name
Test status
Simulation time 6295984962 ps
CPU time 17.73 seconds
Started Aug 12 05:04:45 PM PDT 24
Finished Aug 12 05:05:03 PM PDT 24
Peak memory 200504 kb
Host smart-49e972da-a959-4df5-8447-28b28329ef3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697459178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.697459178
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.2409835699
Short name T404
Test name
Test status
Simulation time 2540005414 ps
CPU time 32.14 seconds
Started Aug 12 05:04:53 PM PDT 24
Finished Aug 12 05:05:26 PM PDT 24
Peak memory 209164 kb
Host smart-3728bbd5-6f21-4fa9-9ed4-64388e63edc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409835699 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2409835699
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.3806996701
Short name T1018
Test name
Test status
Simulation time 456521925 ps
CPU time 1.78 seconds
Started Aug 12 05:04:50 PM PDT 24
Finished Aug 12 05:04:52 PM PDT 24
Peak memory 199548 kb
Host smart-8686c65e-290d-4044-ab1c-7f9f1480dfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806996701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3806996701
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3884651889
Short name T1023
Test name
Test status
Simulation time 45295202710 ps
CPU time 36.96 seconds
Started Aug 12 05:04:44 PM PDT 24
Finished Aug 12 05:05:21 PM PDT 24
Peak memory 200744 kb
Host smart-ced82f7e-698d-49ff-9b14-b9883861a889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884651889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3884651889
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2491262330
Short name T591
Test name
Test status
Simulation time 9599084518 ps
CPU time 14.41 seconds
Started Aug 12 05:07:11 PM PDT 24
Finished Aug 12 05:07:26 PM PDT 24
Peak memory 200604 kb
Host smart-03064727-9b7b-4c7b-ab0b-48480b65fb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491262330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2491262330
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3652328926
Short name T901
Test name
Test status
Simulation time 169929040681 ps
CPU time 125.53 seconds
Started Aug 12 05:07:11 PM PDT 24
Finished Aug 12 05:09:16 PM PDT 24
Peak memory 200684 kb
Host smart-6f49e16a-c40a-455a-ad20-ff2d5953ee1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652328926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3652328926
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1367567872
Short name T267
Test name
Test status
Simulation time 87060989020 ps
CPU time 73.07 seconds
Started Aug 12 05:07:14 PM PDT 24
Finished Aug 12 05:08:27 PM PDT 24
Peak memory 200812 kb
Host smart-f9f4bb5a-87f2-4e76-9b07-d664e092e73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367567872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1367567872
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2886657593
Short name T691
Test name
Test status
Simulation time 80865701073 ps
CPU time 84.66 seconds
Started Aug 12 05:07:11 PM PDT 24
Finished Aug 12 05:08:36 PM PDT 24
Peak memory 200796 kb
Host smart-faab43c5-ff39-40ee-9431-1ea703ce08e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886657593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2886657593
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1095226710
Short name T965
Test name
Test status
Simulation time 18316919544 ps
CPU time 17.1 seconds
Started Aug 12 05:07:11 PM PDT 24
Finished Aug 12 05:07:28 PM PDT 24
Peak memory 200760 kb
Host smart-a0b57818-6021-4344-9292-f4be74e6ea23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095226710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1095226710
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.1549752792
Short name T249
Test name
Test status
Simulation time 58405354162 ps
CPU time 247.56 seconds
Started Aug 12 05:07:12 PM PDT 24
Finished Aug 12 05:11:20 PM PDT 24
Peak memory 200728 kb
Host smart-8c82b183-6e9c-46f2-8ab5-e439fe72ee62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549752792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1549752792
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3705328828
Short name T212
Test name
Test status
Simulation time 95063301405 ps
CPU time 40.6 seconds
Started Aug 12 05:07:12 PM PDT 24
Finished Aug 12 05:07:53 PM PDT 24
Peak memory 200800 kb
Host smart-a4875c32-f65b-4efd-8e92-4471b5dbd6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705328828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3705328828
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3434962945
Short name T405
Test name
Test status
Simulation time 14047551 ps
CPU time 0.55 seconds
Started Aug 12 05:04:54 PM PDT 24
Finished Aug 12 05:04:55 PM PDT 24
Peak memory 195124 kb
Host smart-3db901e9-7391-41bb-954a-0135599c2ff1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434962945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3434962945
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3099388918
Short name T272
Test name
Test status
Simulation time 51931026623 ps
CPU time 40.3 seconds
Started Aug 12 05:04:52 PM PDT 24
Finished Aug 12 05:05:32 PM PDT 24
Peak memory 200664 kb
Host smart-7a08dcb0-a92d-4670-bfb3-4eeb5c9772e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099388918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3099388918
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.902061815
Short name T595
Test name
Test status
Simulation time 62067169098 ps
CPU time 92.87 seconds
Started Aug 12 05:04:55 PM PDT 24
Finished Aug 12 05:06:28 PM PDT 24
Peak memory 200752 kb
Host smart-7eae0de3-a499-4efd-bc03-3bb2502574bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902061815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.902061815
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3179425798
Short name T177
Test name
Test status
Simulation time 20550548191 ps
CPU time 39.17 seconds
Started Aug 12 05:04:52 PM PDT 24
Finished Aug 12 05:05:31 PM PDT 24
Peak memory 200804 kb
Host smart-b66316ce-b825-469b-ba44-daa99ba4d089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179425798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3179425798
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2816938292
Short name T634
Test name
Test status
Simulation time 41969598905 ps
CPU time 57.81 seconds
Started Aug 12 05:04:49 PM PDT 24
Finished Aug 12 05:05:47 PM PDT 24
Peak memory 198736 kb
Host smart-393454de-8e42-4471-b092-5e6087efc0a3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816938292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2816938292
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.4079257123
Short name T355
Test name
Test status
Simulation time 96309262802 ps
CPU time 207.89 seconds
Started Aug 12 05:04:53 PM PDT 24
Finished Aug 12 05:08:22 PM PDT 24
Peak memory 200668 kb
Host smart-17bb9401-a79c-464b-ac60-470149233d09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4079257123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.4079257123
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.2625899676
Short name T753
Test name
Test status
Simulation time 9115626853 ps
CPU time 12.17 seconds
Started Aug 12 05:04:56 PM PDT 24
Finished Aug 12 05:05:09 PM PDT 24
Peak memory 200688 kb
Host smart-80d00986-061e-4626-9bd4-2ca03313c967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625899676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2625899676
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.3338757018
Short name T915
Test name
Test status
Simulation time 283316379842 ps
CPU time 61.72 seconds
Started Aug 12 05:04:53 PM PDT 24
Finished Aug 12 05:05:55 PM PDT 24
Peak memory 200528 kb
Host smart-27ec7ea3-92fa-4e60-bc82-b1e045b3ba60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338757018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3338757018
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.185497325
Short name T1083
Test name
Test status
Simulation time 5261726074 ps
CPU time 3.29 seconds
Started Aug 12 05:04:50 PM PDT 24
Finished Aug 12 05:04:53 PM PDT 24
Peak memory 198988 kb
Host smart-b47ee77a-d245-47cc-93e0-aa35359891c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=185497325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.185497325
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2779474392
Short name T259
Test name
Test status
Simulation time 31118417145 ps
CPU time 59.37 seconds
Started Aug 12 05:04:53 PM PDT 24
Finished Aug 12 05:05:52 PM PDT 24
Peak memory 200740 kb
Host smart-1182ac01-3c23-4d84-8e5c-95127942bc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779474392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2779474392
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2851266020
Short name T780
Test name
Test status
Simulation time 5903710303 ps
CPU time 10.17 seconds
Started Aug 12 05:04:51 PM PDT 24
Finished Aug 12 05:05:01 PM PDT 24
Peak memory 197056 kb
Host smart-2c9f78c6-6ae8-4a4d-82a6-e48568e310f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851266020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2851266020
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.2479419245
Short name T720
Test name
Test status
Simulation time 429533869 ps
CPU time 1.64 seconds
Started Aug 12 05:04:52 PM PDT 24
Finished Aug 12 05:04:54 PM PDT 24
Peak memory 199144 kb
Host smart-f076c264-d9f5-4054-b297-d811559ef164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479419245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2479419245
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.3413682627
Short name T689
Test name
Test status
Simulation time 446068256 ps
CPU time 4.27 seconds
Started Aug 12 05:04:55 PM PDT 24
Finished Aug 12 05:04:59 PM PDT 24
Peak memory 200768 kb
Host smart-7ec69d8f-223f-4003-9b36-873109669aa4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413682627 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.3413682627
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.2696564206
Short name T1012
Test name
Test status
Simulation time 8838324885 ps
CPU time 13.65 seconds
Started Aug 12 05:04:51 PM PDT 24
Finished Aug 12 05:05:05 PM PDT 24
Peak memory 200588 kb
Host smart-98f9e692-e34d-46db-9156-141b99b7f4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696564206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2696564206
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.820369391
Short name T630
Test name
Test status
Simulation time 50640468073 ps
CPU time 98.83 seconds
Started Aug 12 05:04:55 PM PDT 24
Finished Aug 12 05:06:34 PM PDT 24
Peak memory 200768 kb
Host smart-70f43c7a-0c82-47b5-b200-2ba15834db42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820369391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.820369391
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.3160169252
Short name T126
Test name
Test status
Simulation time 46375089192 ps
CPU time 108.18 seconds
Started Aug 12 05:07:13 PM PDT 24
Finished Aug 12 05:09:02 PM PDT 24
Peak memory 200688 kb
Host smart-c96b5112-b021-4a5e-9e2e-861729f9866a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160169252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.3160169252
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1589758269
Short name T971
Test name
Test status
Simulation time 96698602794 ps
CPU time 212.12 seconds
Started Aug 12 05:07:14 PM PDT 24
Finished Aug 12 05:10:46 PM PDT 24
Peak memory 200644 kb
Host smart-36e15ae3-1b4a-4558-82fc-c3649a0e3236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589758269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1589758269
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1730796582
Short name T366
Test name
Test status
Simulation time 41223072287 ps
CPU time 33.56 seconds
Started Aug 12 05:07:13 PM PDT 24
Finished Aug 12 05:07:46 PM PDT 24
Peak memory 200664 kb
Host smart-3cf52aaf-398b-4c0e-bab5-53d5eae803f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730796582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1730796582
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3507653025
Short name T66
Test name
Test status
Simulation time 25126914831 ps
CPU time 36.73 seconds
Started Aug 12 05:07:12 PM PDT 24
Finished Aug 12 05:07:49 PM PDT 24
Peak memory 200712 kb
Host smart-6f4ce8bc-1e8b-4023-8b4e-fce47f4e9146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507653025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3507653025
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.324094737
Short name T211
Test name
Test status
Simulation time 76994170272 ps
CPU time 60.01 seconds
Started Aug 12 05:07:12 PM PDT 24
Finished Aug 12 05:08:12 PM PDT 24
Peak memory 200580 kb
Host smart-f2ffe896-e287-4c48-8c08-7e8092595cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324094737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.324094737
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2397945171
Short name T628
Test name
Test status
Simulation time 8036631091 ps
CPU time 12.55 seconds
Started Aug 12 05:07:10 PM PDT 24
Finished Aug 12 05:07:23 PM PDT 24
Peak memory 200624 kb
Host smart-094d84cf-b508-402e-aac9-9a020ec6469e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397945171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2397945171
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.2511248100
Short name T462
Test name
Test status
Simulation time 45422295691 ps
CPU time 19.16 seconds
Started Aug 12 05:07:13 PM PDT 24
Finished Aug 12 05:07:32 PM PDT 24
Peak memory 200744 kb
Host smart-db292c74-818c-4180-b475-215559b57286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511248100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2511248100
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3748393566
Short name T735
Test name
Test status
Simulation time 116543366922 ps
CPU time 172.98 seconds
Started Aug 12 05:07:13 PM PDT 24
Finished Aug 12 05:10:06 PM PDT 24
Peak memory 200748 kb
Host smart-deea0ee0-5b83-4ccc-b0f0-fbf50dc113a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748393566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3748393566
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1789477472
Short name T615
Test name
Test status
Simulation time 39174025266 ps
CPU time 16.07 seconds
Started Aug 12 05:07:13 PM PDT 24
Finished Aug 12 05:07:29 PM PDT 24
Peak memory 200832 kb
Host smart-526f58f2-0aee-4760-b504-037515061258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789477472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1789477472
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3519481761
Short name T743
Test name
Test status
Simulation time 43534037678 ps
CPU time 19.89 seconds
Started Aug 12 05:07:11 PM PDT 24
Finished Aug 12 05:07:31 PM PDT 24
Peak memory 200772 kb
Host smart-82ccad89-a80a-4889-8c1b-906e9311d605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519481761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3519481761
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1644739497
Short name T422
Test name
Test status
Simulation time 54678020 ps
CPU time 0.59 seconds
Started Aug 12 05:03:28 PM PDT 24
Finished Aug 12 05:03:29 PM PDT 24
Peak memory 196072 kb
Host smart-f32d8f76-fe3d-49dc-aac0-85938615853c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644739497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1644739497
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1683393089
Short name T1089
Test name
Test status
Simulation time 62737966901 ps
CPU time 46.94 seconds
Started Aug 12 05:03:38 PM PDT 24
Finished Aug 12 05:04:25 PM PDT 24
Peak memory 200760 kb
Host smart-f2e9ba2a-4987-49fd-b2c9-04704ac1d440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683393089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1683393089
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3313030790
Short name T155
Test name
Test status
Simulation time 174363886684 ps
CPU time 211.49 seconds
Started Aug 12 05:03:46 PM PDT 24
Finished Aug 12 05:07:18 PM PDT 24
Peak memory 200736 kb
Host smart-fe508f3e-4bd5-45ca-9e50-d2e09ce270d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313030790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3313030790
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_intr.1023951185
Short name T517
Test name
Test status
Simulation time 17407596765 ps
CPU time 6.6 seconds
Started Aug 12 05:03:48 PM PDT 24
Finished Aug 12 05:03:55 PM PDT 24
Peak memory 200204 kb
Host smart-1d65bc90-36ba-451a-82d2-6b08112031de
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023951185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1023951185
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3327902046
Short name T593
Test name
Test status
Simulation time 67976637632 ps
CPU time 692.81 seconds
Started Aug 12 05:03:50 PM PDT 24
Finished Aug 12 05:15:23 PM PDT 24
Peak memory 200644 kb
Host smart-2855400c-9961-447e-83bf-379cd67f8be9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3327902046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3327902046
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2967164300
Short name T908
Test name
Test status
Simulation time 432442029 ps
CPU time 0.74 seconds
Started Aug 12 05:03:38 PM PDT 24
Finished Aug 12 05:03:39 PM PDT 24
Peak memory 196324 kb
Host smart-cc17845d-2d88-42b2-b27b-b38be4f153f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967164300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2967164300
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.459753488
Short name T483
Test name
Test status
Simulation time 74141479476 ps
CPU time 124.43 seconds
Started Aug 12 05:03:33 PM PDT 24
Finished Aug 12 05:05:38 PM PDT 24
Peak memory 200788 kb
Host smart-c34593e3-0023-4eab-a48f-124128885401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459753488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.459753488
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.2876615399
Short name T955
Test name
Test status
Simulation time 12003232720 ps
CPU time 632.38 seconds
Started Aug 12 05:03:37 PM PDT 24
Finished Aug 12 05:14:10 PM PDT 24
Peak memory 200756 kb
Host smart-3fc249dd-eb25-4dab-8fdb-5b5f2ff8b653
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2876615399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2876615399
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3034176821
Short name T1144
Test name
Test status
Simulation time 5149025007 ps
CPU time 48.17 seconds
Started Aug 12 05:03:34 PM PDT 24
Finished Aug 12 05:04:23 PM PDT 24
Peak memory 198880 kb
Host smart-da96cd2f-9a6b-44eb-9f7b-2eb4b5d22f21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3034176821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3034176821
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3052855415
Short name T446
Test name
Test status
Simulation time 61816779751 ps
CPU time 24.85 seconds
Started Aug 12 05:03:55 PM PDT 24
Finished Aug 12 05:04:20 PM PDT 24
Peak memory 200564 kb
Host smart-af01f2e3-ebab-461e-83fc-c242e68ec871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052855415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3052855415
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.825662240
Short name T671
Test name
Test status
Simulation time 4792323069 ps
CPU time 2.26 seconds
Started Aug 12 05:03:48 PM PDT 24
Finished Aug 12 05:03:51 PM PDT 24
Peak memory 196984 kb
Host smart-2b993123-033e-47cd-ba4c-9d3baabc034d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825662240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.825662240
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1155706973
Short name T26
Test name
Test status
Simulation time 64160892 ps
CPU time 0.93 seconds
Started Aug 12 05:03:31 PM PDT 24
Finished Aug 12 05:03:32 PM PDT 24
Peak memory 218996 kb
Host smart-02528305-f0a7-464f-926e-45a66199da1f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155706973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1155706973
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.1082500310
Short name T280
Test name
Test status
Simulation time 548602876 ps
CPU time 1.84 seconds
Started Aug 12 05:03:37 PM PDT 24
Finished Aug 12 05:03:39 PM PDT 24
Peak memory 199500 kb
Host smart-96a0e385-e01a-4994-81c0-6abacf25f4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082500310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1082500310
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2741307133
Short name T1069
Test name
Test status
Simulation time 58298982169 ps
CPU time 109.33 seconds
Started Aug 12 05:03:38 PM PDT 24
Finished Aug 12 05:05:28 PM PDT 24
Peak memory 200680 kb
Host smart-9996bd71-26f4-421a-b635-8f85da3cd23a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741307133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2741307133
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.141300919
Short name T812
Test name
Test status
Simulation time 1553160144 ps
CPU time 18.34 seconds
Started Aug 12 05:03:45 PM PDT 24
Finished Aug 12 05:04:04 PM PDT 24
Peak memory 200732 kb
Host smart-9b494c2f-22c4-4391-8477-f8edb3977781
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141300919 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.141300919
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2469517608
Short name T658
Test name
Test status
Simulation time 6708493924 ps
CPU time 18.83 seconds
Started Aug 12 05:03:32 PM PDT 24
Finished Aug 12 05:03:51 PM PDT 24
Peak memory 200748 kb
Host smart-5213d409-9310-48d8-a30b-e0c36ca887b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469517608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2469517608
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.1697304532
Short name T311
Test name
Test status
Simulation time 114425035856 ps
CPU time 45.37 seconds
Started Aug 12 05:03:35 PM PDT 24
Finished Aug 12 05:04:21 PM PDT 24
Peak memory 200808 kb
Host smart-4cd56b7c-da65-490f-a41c-289b9430e4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697304532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1697304532
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.2910629982
Short name T341
Test name
Test status
Simulation time 33407353 ps
CPU time 0.55 seconds
Started Aug 12 05:05:00 PM PDT 24
Finished Aug 12 05:05:01 PM PDT 24
Peak memory 196284 kb
Host smart-b9a970d6-eab3-4f75-81bd-239915d71184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910629982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2910629982
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.462547182
Short name T1032
Test name
Test status
Simulation time 56788102892 ps
CPU time 43.25 seconds
Started Aug 12 05:04:54 PM PDT 24
Finished Aug 12 05:05:38 PM PDT 24
Peak memory 200676 kb
Host smart-8a17823b-2123-42ae-8f37-5a83e2e635c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462547182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.462547182
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3983007700
Short name T1065
Test name
Test status
Simulation time 41761002735 ps
CPU time 16.52 seconds
Started Aug 12 05:04:51 PM PDT 24
Finished Aug 12 05:05:08 PM PDT 24
Peak memory 200544 kb
Host smart-6bcd7a83-e5db-416d-ad4b-6abd8a491e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983007700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3983007700
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2391549002
Short name T623
Test name
Test status
Simulation time 8726472565 ps
CPU time 13.3 seconds
Started Aug 12 05:04:52 PM PDT 24
Finished Aug 12 05:05:06 PM PDT 24
Peak memory 200680 kb
Host smart-4353fdd9-cf07-4434-a8e5-0790b4460119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391549002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2391549002
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.1388252807
Short name T9
Test name
Test status
Simulation time 107816839788 ps
CPU time 205.4 seconds
Started Aug 12 05:04:50 PM PDT 24
Finished Aug 12 05:08:16 PM PDT 24
Peak memory 200828 kb
Host smart-67ef95b8-948d-4cd8-bea2-21da015b7ca9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388252807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1388252807
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3616986239
Short name T1092
Test name
Test status
Simulation time 162842894825 ps
CPU time 178.85 seconds
Started Aug 12 05:04:51 PM PDT 24
Finished Aug 12 05:07:50 PM PDT 24
Peak memory 200828 kb
Host smart-911aca5b-55ad-461c-9544-165be10eae80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3616986239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3616986239
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3404761248
Short name T1040
Test name
Test status
Simulation time 9846554974 ps
CPU time 16.42 seconds
Started Aug 12 05:04:56 PM PDT 24
Finished Aug 12 05:05:12 PM PDT 24
Peak memory 200260 kb
Host smart-274678aa-d577-4fcf-8ba0-85e5a65473fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404761248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3404761248
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.1015490814
Short name T383
Test name
Test status
Simulation time 91828299264 ps
CPU time 52.84 seconds
Started Aug 12 05:04:53 PM PDT 24
Finished Aug 12 05:05:46 PM PDT 24
Peak memory 198976 kb
Host smart-086d8fa2-9270-4f2d-9599-fa0a6f5a7520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015490814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1015490814
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.1991768559
Short name T548
Test name
Test status
Simulation time 10940167529 ps
CPU time 595.76 seconds
Started Aug 12 05:04:54 PM PDT 24
Finished Aug 12 05:14:50 PM PDT 24
Peak memory 200776 kb
Host smart-17bd3e69-3b8a-4026-b66f-0221ef7ad749
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1991768559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1991768559
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.4263783479
Short name T934
Test name
Test status
Simulation time 6760810892 ps
CPU time 14.85 seconds
Started Aug 12 05:04:55 PM PDT 24
Finished Aug 12 05:05:10 PM PDT 24
Peak memory 199996 kb
Host smart-8baa8da0-2928-46ec-8f25-02c507c84cda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4263783479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.4263783479
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.496120569
Short name T676
Test name
Test status
Simulation time 42605896148 ps
CPU time 29.27 seconds
Started Aug 12 05:04:51 PM PDT 24
Finished Aug 12 05:05:20 PM PDT 24
Peak memory 200528 kb
Host smart-d9062013-a517-4b49-86e8-2652c219df32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496120569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.496120569
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.3079671446
Short name T437
Test name
Test status
Simulation time 1483144343 ps
CPU time 2.95 seconds
Started Aug 12 05:04:51 PM PDT 24
Finished Aug 12 05:04:54 PM PDT 24
Peak memory 196440 kb
Host smart-ecc91c39-68e0-433c-8b9b-7ecadac319a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079671446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3079671446
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3416074862
Short name T701
Test name
Test status
Simulation time 685818040 ps
CPU time 1.84 seconds
Started Aug 12 05:04:49 PM PDT 24
Finished Aug 12 05:04:51 PM PDT 24
Peak memory 199440 kb
Host smart-ca19586d-e581-4d70-b8bb-3f6eda3b7805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416074862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3416074862
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.3985970236
Short name T885
Test name
Test status
Simulation time 219595277916 ps
CPU time 76.33 seconds
Started Aug 12 05:04:58 PM PDT 24
Finished Aug 12 05:06:14 PM PDT 24
Peak memory 200772 kb
Host smart-d32a114a-16a3-4ce6-9346-07156572feb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985970236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3985970236
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.90790130
Short name T926
Test name
Test status
Simulation time 7773323971 ps
CPU time 121.07 seconds
Started Aug 12 05:04:58 PM PDT 24
Finished Aug 12 05:07:00 PM PDT 24
Peak memory 217284 kb
Host smart-c72e0410-da2c-43c9-976a-835fd0c6331f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90790130 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.90790130
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2424053005
Short name T590
Test name
Test status
Simulation time 1404089023 ps
CPU time 2.64 seconds
Started Aug 12 05:04:51 PM PDT 24
Finished Aug 12 05:04:54 PM PDT 24
Peak memory 199224 kb
Host smart-50a48bbf-203c-4083-9f86-420c43710a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424053005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2424053005
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.228076947
Short name T952
Test name
Test status
Simulation time 156145124095 ps
CPU time 53.74 seconds
Started Aug 12 05:04:50 PM PDT 24
Finished Aug 12 05:05:43 PM PDT 24
Peak memory 200720 kb
Host smart-bf45d53b-4bdd-4785-b0dc-0b7704ce6d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228076947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.228076947
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3818482181
Short name T358
Test name
Test status
Simulation time 104498980 ps
CPU time 0.53 seconds
Started Aug 12 05:04:56 PM PDT 24
Finished Aug 12 05:04:57 PM PDT 24
Peak memory 195760 kb
Host smart-92f1ce93-79f2-4825-ab4b-e9930da7cb8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818482181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3818482181
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1970868134
Short name T524
Test name
Test status
Simulation time 66100848756 ps
CPU time 27.55 seconds
Started Aug 12 05:04:57 PM PDT 24
Finished Aug 12 05:05:25 PM PDT 24
Peak memory 200740 kb
Host smart-51ac47fa-8f08-4aa9-b425-9fb7d6abd470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970868134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1970868134
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1399205762
Short name T1182
Test name
Test status
Simulation time 16518011194 ps
CPU time 12.83 seconds
Started Aug 12 05:04:58 PM PDT 24
Finished Aug 12 05:05:11 PM PDT 24
Peak memory 200156 kb
Host smart-f004b1bd-6e05-4160-b664-91f499a96dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399205762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1399205762
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1161219019
Short name T571
Test name
Test status
Simulation time 33646701324 ps
CPU time 43.57 seconds
Started Aug 12 05:04:57 PM PDT 24
Finished Aug 12 05:05:40 PM PDT 24
Peak memory 200756 kb
Host smart-1951c102-e338-4a27-9eeb-75b9afa81309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161219019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1161219019
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.812557179
Short name T540
Test name
Test status
Simulation time 61900547534 ps
CPU time 46.31 seconds
Started Aug 12 05:04:59 PM PDT 24
Finished Aug 12 05:05:46 PM PDT 24
Peak memory 200424 kb
Host smart-3d3fa2ce-6056-49a3-ba6a-2cd9b82c20df
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812557179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.812557179
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.377767042
Short name T549
Test name
Test status
Simulation time 51330827498 ps
CPU time 399.66 seconds
Started Aug 12 05:04:56 PM PDT 24
Finished Aug 12 05:11:36 PM PDT 24
Peak memory 200784 kb
Host smart-c128d43b-a706-4d65-9f33-95d80338e5ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=377767042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.377767042
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2879040187
Short name T348
Test name
Test status
Simulation time 3954045004 ps
CPU time 6.06 seconds
Started Aug 12 05:05:03 PM PDT 24
Finished Aug 12 05:05:09 PM PDT 24
Peak memory 200032 kb
Host smart-91c8002d-0c1c-47f4-b47f-084e8210265e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879040187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2879040187
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_perf.2439678833
Short name T41
Test name
Test status
Simulation time 13530522402 ps
CPU time 804.69 seconds
Started Aug 12 05:04:57 PM PDT 24
Finished Aug 12 05:18:22 PM PDT 24
Peak memory 200792 kb
Host smart-968d177f-2a30-4bb5-8acf-d7431773c439
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2439678833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2439678833
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1784403553
Short name T399
Test name
Test status
Simulation time 7393866351 ps
CPU time 11.31 seconds
Started Aug 12 05:05:02 PM PDT 24
Finished Aug 12 05:05:14 PM PDT 24
Peak memory 199544 kb
Host smart-d7f38790-6c1d-45c5-994d-8fa0947948f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1784403553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1784403553
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.2440497565
Short name T457
Test name
Test status
Simulation time 38930217547 ps
CPU time 24.12 seconds
Started Aug 12 05:04:54 PM PDT 24
Finished Aug 12 05:05:18 PM PDT 24
Peak memory 200656 kb
Host smart-0aeeb611-d9af-4f4e-b378-742f22220708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440497565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.2440497565
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.4035358137
Short name T1046
Test name
Test status
Simulation time 6296796404 ps
CPU time 1.47 seconds
Started Aug 12 05:04:56 PM PDT 24
Finished Aug 12 05:04:58 PM PDT 24
Peak memory 196912 kb
Host smart-065841b5-bd07-4853-a284-f5318b6f2f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035358137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.4035358137
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2135450911
Short name T962
Test name
Test status
Simulation time 513132644 ps
CPU time 1.91 seconds
Started Aug 12 05:05:03 PM PDT 24
Finished Aug 12 05:05:05 PM PDT 24
Peak memory 199756 kb
Host smart-33ae8cc9-81cf-4ab6-b80b-85def2f67447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135450911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2135450911
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2358744175
Short name T30
Test name
Test status
Simulation time 1263685436 ps
CPU time 15.05 seconds
Started Aug 12 05:04:57 PM PDT 24
Finished Aug 12 05:05:13 PM PDT 24
Peak memory 200800 kb
Host smart-c8879263-caf8-45a0-bf63-999006b550d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358744175 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2358744175
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3506504122
Short name T312
Test name
Test status
Simulation time 6935567620 ps
CPU time 9.15 seconds
Started Aug 12 05:04:58 PM PDT 24
Finished Aug 12 05:05:07 PM PDT 24
Peak memory 200728 kb
Host smart-cf388eae-9f0b-4f74-a2d5-8b27b4baa215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506504122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3506504122
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.162280178
Short name T389
Test name
Test status
Simulation time 29129457754 ps
CPU time 10.84 seconds
Started Aug 12 05:04:58 PM PDT 24
Finished Aug 12 05:05:09 PM PDT 24
Peak memory 198780 kb
Host smart-1eec73eb-2caa-4ab6-a297-3047becad1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162280178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.162280178
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1030082831
Short name T1039
Test name
Test status
Simulation time 64467085 ps
CPU time 0.56 seconds
Started Aug 12 05:05:06 PM PDT 24
Finished Aug 12 05:05:06 PM PDT 24
Peak memory 196388 kb
Host smart-4765126d-fb1a-4b06-89bb-61cf2e6ae2ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030082831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1030082831
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3998588688
Short name T254
Test name
Test status
Simulation time 46000158091 ps
CPU time 27.73 seconds
Started Aug 12 05:04:58 PM PDT 24
Finished Aug 12 05:05:26 PM PDT 24
Peak memory 200828 kb
Host smart-4e4e605c-b817-4fc2-8619-2b5cc69c3e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998588688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3998588688
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2865418168
Short name T1011
Test name
Test status
Simulation time 100047344142 ps
CPU time 72.16 seconds
Started Aug 12 05:04:58 PM PDT 24
Finished Aug 12 05:06:11 PM PDT 24
Peak memory 200680 kb
Host smart-a8c4c10f-8cf5-4804-9a33-c5b7a380dd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865418168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2865418168
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3653429971
Short name T432
Test name
Test status
Simulation time 48325285071 ps
CPU time 81.33 seconds
Started Aug 12 05:04:57 PM PDT 24
Finished Aug 12 05:06:19 PM PDT 24
Peak memory 200792 kb
Host smart-3e309637-2819-4aa9-854e-c972e5642c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653429971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3653429971
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2100574156
Short name T1154
Test name
Test status
Simulation time 40497050167 ps
CPU time 26.43 seconds
Started Aug 12 05:05:07 PM PDT 24
Finished Aug 12 05:05:33 PM PDT 24
Peak memory 200668 kb
Host smart-19166dd9-62a9-47b5-9945-a49f3637e3ae
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100574156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2100574156
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.3920381597
Short name T436
Test name
Test status
Simulation time 127180419406 ps
CPU time 423.88 seconds
Started Aug 12 05:05:03 PM PDT 24
Finished Aug 12 05:12:07 PM PDT 24
Peak memory 200768 kb
Host smart-91a2a7a6-e180-451f-a5e7-6971a3fa6bcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3920381597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3920381597
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1613265944
Short name T867
Test name
Test status
Simulation time 3931931838 ps
CPU time 2.35 seconds
Started Aug 12 05:05:08 PM PDT 24
Finished Aug 12 05:05:11 PM PDT 24
Peak memory 196688 kb
Host smart-0de8ddef-b94e-46d6-9b30-25b2974d8895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613265944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1613265944
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1043835101
Short name T817
Test name
Test status
Simulation time 27043973511 ps
CPU time 24.71 seconds
Started Aug 12 05:05:05 PM PDT 24
Finished Aug 12 05:05:30 PM PDT 24
Peak memory 200960 kb
Host smart-24e6ec83-3502-4c86-bfcf-530aad41e5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043835101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1043835101
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.458506361
Short name T985
Test name
Test status
Simulation time 7125302386 ps
CPU time 34.53 seconds
Started Aug 12 05:05:08 PM PDT 24
Finished Aug 12 05:05:43 PM PDT 24
Peak memory 200808 kb
Host smart-a5754d63-3b1f-4e5d-8959-dc9b9662bc17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=458506361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.458506361
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.1647666747
Short name T990
Test name
Test status
Simulation time 7029295789 ps
CPU time 24.67 seconds
Started Aug 12 05:04:59 PM PDT 24
Finished Aug 12 05:05:24 PM PDT 24
Peak memory 200024 kb
Host smart-4670ae70-c850-4615-87c6-9fadc1dd38ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1647666747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1647666747
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.2871578103
Short name T645
Test name
Test status
Simulation time 31067106810 ps
CPU time 25.15 seconds
Started Aug 12 05:05:08 PM PDT 24
Finished Aug 12 05:05:33 PM PDT 24
Peak memory 200764 kb
Host smart-73eaffca-6b22-40ca-85e0-f376cc46aa56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871578103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2871578103
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2591869044
Short name T784
Test name
Test status
Simulation time 4085121401 ps
CPU time 1.39 seconds
Started Aug 12 05:05:06 PM PDT 24
Finished Aug 12 05:05:08 PM PDT 24
Peak memory 197328 kb
Host smart-15979b1f-42fb-4908-b24c-874333ae4b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591869044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2591869044
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.393242447
Short name T954
Test name
Test status
Simulation time 265788397 ps
CPU time 2.4 seconds
Started Aug 12 05:04:58 PM PDT 24
Finished Aug 12 05:05:00 PM PDT 24
Peak memory 199444 kb
Host smart-82502ebb-b3e8-440d-b8f3-406104b398ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393242447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.393242447
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.3545235657
Short name T749
Test name
Test status
Simulation time 544968222862 ps
CPU time 862.03 seconds
Started Aug 12 05:05:06 PM PDT 24
Finished Aug 12 05:19:29 PM PDT 24
Peak memory 200804 kb
Host smart-5fce06d5-302c-459e-b419-317350d10fcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545235657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3545235657
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.2357336500
Short name T563
Test name
Test status
Simulation time 767809622 ps
CPU time 9.32 seconds
Started Aug 12 05:05:06 PM PDT 24
Finished Aug 12 05:05:16 PM PDT 24
Peak memory 216544 kb
Host smart-323704a2-6a22-431e-afaf-17df8adfc001
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357336500 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.2357336500
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3317795455
Short name T299
Test name
Test status
Simulation time 7024028252 ps
CPU time 17.15 seconds
Started Aug 12 05:05:04 PM PDT 24
Finished Aug 12 05:05:21 PM PDT 24
Peak memory 200112 kb
Host smart-35c1d4c8-2651-437c-b0ab-b0087cb671c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317795455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3317795455
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.734995257
Short name T401
Test name
Test status
Simulation time 30400716250 ps
CPU time 33.87 seconds
Started Aug 12 05:04:58 PM PDT 24
Finished Aug 12 05:05:32 PM PDT 24
Peak memory 200736 kb
Host smart-37460b6d-cb5d-4cea-b8b1-5bb0d0343646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734995257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.734995257
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.2347055940
Short name T819
Test name
Test status
Simulation time 21631757 ps
CPU time 0.55 seconds
Started Aug 12 05:05:07 PM PDT 24
Finished Aug 12 05:05:07 PM PDT 24
Peak memory 196088 kb
Host smart-bd59afe1-011b-4582-96c2-efef75122c57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347055940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2347055940
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.976884846
Short name T425
Test name
Test status
Simulation time 66672880492 ps
CPU time 120.64 seconds
Started Aug 12 05:05:06 PM PDT 24
Finished Aug 12 05:07:07 PM PDT 24
Peak memory 200784 kb
Host smart-897a21ce-279c-48ce-a760-165466a68999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976884846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.976884846
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.4002472960
Short name T1123
Test name
Test status
Simulation time 131231687422 ps
CPU time 68.41 seconds
Started Aug 12 05:05:05 PM PDT 24
Finished Aug 12 05:06:13 PM PDT 24
Peak memory 200744 kb
Host smart-97c9cbb2-5860-4e22-9d0d-bc1ce5a124a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002472960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.4002472960
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3739703371
Short name T309
Test name
Test status
Simulation time 125322044671 ps
CPU time 206.01 seconds
Started Aug 12 05:05:06 PM PDT 24
Finished Aug 12 05:08:32 PM PDT 24
Peak memory 200612 kb
Host smart-d112291d-d3ec-4796-a1e3-bc308ca2621b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739703371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3739703371
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3097354329
Short name T394
Test name
Test status
Simulation time 16977615440 ps
CPU time 29.51 seconds
Started Aug 12 05:05:07 PM PDT 24
Finished Aug 12 05:05:37 PM PDT 24
Peak memory 200456 kb
Host smart-9ec83dee-0cf5-4eef-b4ff-4d2985393285
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097354329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3097354329
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1545663593
Short name T515
Test name
Test status
Simulation time 70432050940 ps
CPU time 279.58 seconds
Started Aug 12 05:05:07 PM PDT 24
Finished Aug 12 05:09:47 PM PDT 24
Peak memory 200812 kb
Host smart-d7e321aa-4cd9-4222-bd57-56d088cb606e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1545663593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1545663593
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3716111709
Short name T731
Test name
Test status
Simulation time 10071268246 ps
CPU time 9.39 seconds
Started Aug 12 05:05:05 PM PDT 24
Finished Aug 12 05:05:15 PM PDT 24
Peak memory 200640 kb
Host smart-c5c28670-6345-4762-a33b-add65067cd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716111709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3716111709
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.271857401
Short name T942
Test name
Test status
Simulation time 64290624040 ps
CPU time 100.47 seconds
Started Aug 12 05:05:10 PM PDT 24
Finished Aug 12 05:06:50 PM PDT 24
Peak memory 200912 kb
Host smart-7b396f27-ed27-4c26-b14f-8590f6d116ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271857401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.271857401
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.3876624441
Short name T776
Test name
Test status
Simulation time 8924237456 ps
CPU time 130.73 seconds
Started Aug 12 05:05:05 PM PDT 24
Finished Aug 12 05:07:16 PM PDT 24
Peak memory 200832 kb
Host smart-45a2c8ae-77f5-43b7-9f44-a9a736a06989
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3876624441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3876624441
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.1788224936
Short name T694
Test name
Test status
Simulation time 4649150189 ps
CPU time 11.57 seconds
Started Aug 12 05:05:05 PM PDT 24
Finished Aug 12 05:05:17 PM PDT 24
Peak memory 198864 kb
Host smart-6f11ee0f-9cfc-4c3d-97f8-0b8fa35c3570
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1788224936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1788224936
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.1793132596
Short name T498
Test name
Test status
Simulation time 118502254219 ps
CPU time 79.83 seconds
Started Aug 12 05:05:03 PM PDT 24
Finished Aug 12 05:06:23 PM PDT 24
Peak memory 200796 kb
Host smart-16e79eff-876c-4e84-a857-02d9f13d7e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793132596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1793132596
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.312319863
Short name T429
Test name
Test status
Simulation time 2958760007 ps
CPU time 3.08 seconds
Started Aug 12 05:05:05 PM PDT 24
Finished Aug 12 05:05:08 PM PDT 24
Peak memory 197628 kb
Host smart-e154b088-2e3f-4507-9d91-e51efd2b0cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312319863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.312319863
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1262556953
Short name T966
Test name
Test status
Simulation time 695327985 ps
CPU time 3.47 seconds
Started Aug 12 05:05:06 PM PDT 24
Finished Aug 12 05:05:10 PM PDT 24
Peak memory 199604 kb
Host smart-fd7291c0-0046-41cd-9888-3f9bcc65ebf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262556953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1262556953
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.882621935
Short name T22
Test name
Test status
Simulation time 2744880711 ps
CPU time 16.23 seconds
Started Aug 12 05:05:03 PM PDT 24
Finished Aug 12 05:05:19 PM PDT 24
Peak memory 209328 kb
Host smart-42e4feda-ada9-4df8-8fbd-a017396a9922
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882621935 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.882621935
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2924691549
Short name T340
Test name
Test status
Simulation time 826276032 ps
CPU time 2.88 seconds
Started Aug 12 05:05:06 PM PDT 24
Finished Aug 12 05:05:09 PM PDT 24
Peak memory 199744 kb
Host smart-86235fe4-f9bb-4423-bf07-27a6d2e2744d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924691549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2924691549
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.3529008348
Short name T613
Test name
Test status
Simulation time 29169128039 ps
CPU time 44.23 seconds
Started Aug 12 05:05:04 PM PDT 24
Finished Aug 12 05:05:48 PM PDT 24
Peak memory 200816 kb
Host smart-5100b0e3-8e88-4c74-bb3b-a3eb32c33060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529008348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.3529008348
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3545330126
Short name T718
Test name
Test status
Simulation time 11476320 ps
CPU time 0.57 seconds
Started Aug 12 05:05:10 PM PDT 24
Finished Aug 12 05:05:11 PM PDT 24
Peak memory 196292 kb
Host smart-9142bff0-af9b-41fd-bc4f-e027167affed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545330126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3545330126
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.4243787417
Short name T1057
Test name
Test status
Simulation time 156088707432 ps
CPU time 53.57 seconds
Started Aug 12 05:05:07 PM PDT 24
Finished Aug 12 05:06:00 PM PDT 24
Peak memory 200808 kb
Host smart-2ba10c41-5445-49cd-85fe-3bfb577f71d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243787417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.4243787417
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.1480989488
Short name T858
Test name
Test status
Simulation time 59722197738 ps
CPU time 24.44 seconds
Started Aug 12 05:05:08 PM PDT 24
Finished Aug 12 05:05:33 PM PDT 24
Peak memory 200756 kb
Host smart-0c6e62b9-dfda-4a37-b03c-508c8cbdda4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480989488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1480989488
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2273926061
Short name T455
Test name
Test status
Simulation time 159834289606 ps
CPU time 51.97 seconds
Started Aug 12 05:05:06 PM PDT 24
Finished Aug 12 05:05:58 PM PDT 24
Peak memory 200716 kb
Host smart-6d318572-6686-495f-89b4-1a471bb20fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273926061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2273926061
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.1286704677
Short name T471
Test name
Test status
Simulation time 45013273927 ps
CPU time 45.39 seconds
Started Aug 12 05:05:08 PM PDT 24
Finished Aug 12 05:05:54 PM PDT 24
Peak memory 199392 kb
Host smart-ae9f91dc-da0e-4dfa-823f-adce3084a0fd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286704677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1286704677
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3732008741
Short name T242
Test name
Test status
Simulation time 59804395373 ps
CPU time 441.09 seconds
Started Aug 12 05:05:14 PM PDT 24
Finished Aug 12 05:12:35 PM PDT 24
Peak memory 200672 kb
Host smart-e98730c9-f376-4f5e-81fc-1e493b6d6654
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3732008741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3732008741
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.539769089
Short name T1120
Test name
Test status
Simulation time 5806728013 ps
CPU time 10.25 seconds
Started Aug 12 05:05:14 PM PDT 24
Finished Aug 12 05:05:24 PM PDT 24
Peak memory 200232 kb
Host smart-dd92a773-7403-4268-9068-76b296e819e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539769089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.539769089
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.229604615
Short name T114
Test name
Test status
Simulation time 109537858718 ps
CPU time 38.13 seconds
Started Aug 12 05:05:09 PM PDT 24
Finished Aug 12 05:05:48 PM PDT 24
Peak memory 200932 kb
Host smart-6ae95499-1606-480e-b0ca-4ac012b2f96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229604615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.229604615
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1710812740
Short name T1172
Test name
Test status
Simulation time 2118539854 ps
CPU time 40.67 seconds
Started Aug 12 05:05:11 PM PDT 24
Finished Aug 12 05:05:52 PM PDT 24
Peak memory 200768 kb
Host smart-0ac19c25-c7d5-4fe8-8eb9-9847cfa8e09d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1710812740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1710812740
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1421941661
Short name T14
Test name
Test status
Simulation time 2850593881 ps
CPU time 20.45 seconds
Started Aug 12 05:05:04 PM PDT 24
Finished Aug 12 05:05:24 PM PDT 24
Peak memory 199352 kb
Host smart-7e4b1463-e644-4eab-b68b-2c249be8c93f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1421941661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1421941661
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.863185378
Short name T938
Test name
Test status
Simulation time 34492219587 ps
CPU time 21.32 seconds
Started Aug 12 05:05:10 PM PDT 24
Finished Aug 12 05:05:31 PM PDT 24
Peak memory 200724 kb
Host smart-f8ba0e96-bce7-44f1-8728-4d9d22963553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863185378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.863185378
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.236581324
Short name T298
Test name
Test status
Simulation time 3323583012 ps
CPU time 5.53 seconds
Started Aug 12 05:05:17 PM PDT 24
Finished Aug 12 05:05:23 PM PDT 24
Peak memory 196764 kb
Host smart-bf39c251-e556-4d4f-a89f-71dec9e2e83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236581324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.236581324
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.2905226850
Short name T276
Test name
Test status
Simulation time 6264620029 ps
CPU time 6.21 seconds
Started Aug 12 05:05:06 PM PDT 24
Finished Aug 12 05:05:12 PM PDT 24
Peak memory 200728 kb
Host smart-608dd750-cf89-4690-9cf5-d9f0d3e77e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905226850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2905226850
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.3969264701
Short name T158
Test name
Test status
Simulation time 309526581388 ps
CPU time 507.06 seconds
Started Aug 12 05:05:11 PM PDT 24
Finished Aug 12 05:13:39 PM PDT 24
Peak memory 200664 kb
Host smart-8a817e36-b41f-4dae-95aa-670d6a7989b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969264701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.3969264701
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1035909666
Short name T1051
Test name
Test status
Simulation time 4644120116 ps
CPU time 24.78 seconds
Started Aug 12 05:05:11 PM PDT 24
Finished Aug 12 05:05:36 PM PDT 24
Peak memory 209216 kb
Host smart-1c29055b-808b-43c9-8eba-80ce751cbaa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035909666 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1035909666
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.2710111499
Short name T391
Test name
Test status
Simulation time 1034899853 ps
CPU time 3.17 seconds
Started Aug 12 05:05:10 PM PDT 24
Finished Aug 12 05:05:13 PM PDT 24
Peak memory 199752 kb
Host smart-dcc651fa-1124-4688-9359-9181a3a426cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710111499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2710111499
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3457981068
Short name T746
Test name
Test status
Simulation time 74720205393 ps
CPU time 140.65 seconds
Started Aug 12 05:05:02 PM PDT 24
Finished Aug 12 05:07:23 PM PDT 24
Peak memory 200832 kb
Host smart-b77c134a-bbe1-407e-91b2-30bcf7a14e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457981068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3457981068
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2439617629
Short name T767
Test name
Test status
Simulation time 57268838 ps
CPU time 0.55 seconds
Started Aug 12 05:05:12 PM PDT 24
Finished Aug 12 05:05:13 PM PDT 24
Peak memory 196416 kb
Host smart-6fb90f70-1364-479d-bb1b-b3c84ba5ffba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439617629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2439617629
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.316539909
Short name T921
Test name
Test status
Simulation time 144249300938 ps
CPU time 87.59 seconds
Started Aug 12 05:05:10 PM PDT 24
Finished Aug 12 05:06:38 PM PDT 24
Peak memory 200912 kb
Host smart-5b53ca69-f3fd-470c-910d-d175f7755f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316539909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.316539909
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.3488276460
Short name T754
Test name
Test status
Simulation time 181578069593 ps
CPU time 38.64 seconds
Started Aug 12 05:05:10 PM PDT 24
Finished Aug 12 05:05:49 PM PDT 24
Peak memory 200696 kb
Host smart-35c4b6b7-a63f-405d-b2e2-b3d57ca9657b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488276460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3488276460
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.800618411
Short name T845
Test name
Test status
Simulation time 18616216562 ps
CPU time 28.09 seconds
Started Aug 12 05:05:17 PM PDT 24
Finished Aug 12 05:05:46 PM PDT 24
Peak memory 200688 kb
Host smart-fec4d08c-937d-4bd1-926a-afb84d35ca1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800618411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.800618411
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.2912216095
Short name T887
Test name
Test status
Simulation time 45464164878 ps
CPU time 46.9 seconds
Started Aug 12 05:05:14 PM PDT 24
Finished Aug 12 05:06:01 PM PDT 24
Peak memory 200776 kb
Host smart-feac818b-0d46-477b-8bea-a220d34cd8b3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912216095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2912216095
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.175921670
Short name T585
Test name
Test status
Simulation time 131234739388 ps
CPU time 976.25 seconds
Started Aug 12 05:05:10 PM PDT 24
Finished Aug 12 05:21:26 PM PDT 24
Peak memory 200768 kb
Host smart-af94c06f-cc35-4574-9023-6155ad678531
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=175921670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.175921670
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1309841693
Short name T820
Test name
Test status
Simulation time 1482601010 ps
CPU time 1.96 seconds
Started Aug 12 05:05:10 PM PDT 24
Finished Aug 12 05:05:12 PM PDT 24
Peak memory 197932 kb
Host smart-e0a0ea08-5634-4650-90d1-351f314839c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309841693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1309841693
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.884542470
Short name T1044
Test name
Test status
Simulation time 151334890992 ps
CPU time 35.91 seconds
Started Aug 12 05:05:11 PM PDT 24
Finished Aug 12 05:05:47 PM PDT 24
Peak memory 200936 kb
Host smart-857b3e9e-f73f-4c49-9f98-c0e2b5e14e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884542470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.884542470
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.4121287072
Short name T603
Test name
Test status
Simulation time 9554748573 ps
CPU time 562.04 seconds
Started Aug 12 05:05:10 PM PDT 24
Finished Aug 12 05:14:33 PM PDT 24
Peak memory 200744 kb
Host smart-ea476304-102b-40a8-a59b-f6e00a031057
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4121287072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.4121287072
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.637717417
Short name T771
Test name
Test status
Simulation time 5586487088 ps
CPU time 25.21 seconds
Started Aug 12 05:05:14 PM PDT 24
Finished Aug 12 05:05:39 PM PDT 24
Peak memory 198948 kb
Host smart-53b8cad2-07e4-462d-a0d3-bb9200f1d9f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=637717417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.637717417
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2365552107
Short name T244
Test name
Test status
Simulation time 87736862503 ps
CPU time 138.02 seconds
Started Aug 12 05:05:09 PM PDT 24
Finished Aug 12 05:07:27 PM PDT 24
Peak memory 200496 kb
Host smart-98b893c7-aebb-4767-83fa-0d3737c9aaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365552107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2365552107
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.4260541872
Short name T555
Test name
Test status
Simulation time 5329411664 ps
CPU time 7.92 seconds
Started Aug 12 05:05:13 PM PDT 24
Finished Aug 12 05:05:21 PM PDT 24
Peak memory 197012 kb
Host smart-ae746d24-721b-47f8-9fb2-ff1727846036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260541872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.4260541872
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2924990289
Short name T386
Test name
Test status
Simulation time 121313552 ps
CPU time 0.83 seconds
Started Aug 12 05:05:15 PM PDT 24
Finished Aug 12 05:05:16 PM PDT 24
Peak memory 198024 kb
Host smart-30849d1b-358f-4b19-84ab-dec58e2b5cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924990289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2924990289
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.1044264226
Short name T741
Test name
Test status
Simulation time 326485331636 ps
CPU time 1697.92 seconds
Started Aug 12 05:05:15 PM PDT 24
Finished Aug 12 05:33:34 PM PDT 24
Peak memory 200720 kb
Host smart-771a48b5-b37d-4057-a7a9-1e49e899482e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044264226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1044264226
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.428509494
Short name T452
Test name
Test status
Simulation time 437051295 ps
CPU time 1.41 seconds
Started Aug 12 05:05:17 PM PDT 24
Finished Aug 12 05:05:19 PM PDT 24
Peak memory 199428 kb
Host smart-ea0f5345-edb3-4032-9500-ad5314d228d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428509494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.428509494
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2143478353
Short name T772
Test name
Test status
Simulation time 2537234986 ps
CPU time 1.6 seconds
Started Aug 12 05:05:11 PM PDT 24
Finished Aug 12 05:05:13 PM PDT 24
Peak memory 198404 kb
Host smart-114b7dce-9af7-45ad-80af-d11bb2028743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143478353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2143478353
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3433107132
Short name T1009
Test name
Test status
Simulation time 36345969 ps
CPU time 0.59 seconds
Started Aug 12 05:05:20 PM PDT 24
Finished Aug 12 05:05:21 PM PDT 24
Peak memory 196124 kb
Host smart-a1bb98c7-6d61-455c-b5d7-46e929c4a434
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433107132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3433107132
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.3612012325
Short name T130
Test name
Test status
Simulation time 151124887027 ps
CPU time 82.5 seconds
Started Aug 12 05:05:16 PM PDT 24
Finished Aug 12 05:06:39 PM PDT 24
Peak memory 200704 kb
Host smart-8cc5f933-ee27-4974-ad59-eeb6a5c27ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612012325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3612012325
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2675118209
Short name T880
Test name
Test status
Simulation time 214487361293 ps
CPU time 42.79 seconds
Started Aug 12 05:05:11 PM PDT 24
Finished Aug 12 05:05:54 PM PDT 24
Peak memory 200676 kb
Host smart-453c6afa-af05-4c9d-a813-e1b94990c0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675118209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2675118209
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.1803995269
Short name T119
Test name
Test status
Simulation time 94481936277 ps
CPU time 159.61 seconds
Started Aug 12 05:05:12 PM PDT 24
Finished Aug 12 05:07:51 PM PDT 24
Peak memory 200660 kb
Host smart-70e46cce-a939-463f-8fe0-75cda6943064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803995269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1803995269
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.1704233148
Short name T860
Test name
Test status
Simulation time 16377359068 ps
CPU time 8.11 seconds
Started Aug 12 05:05:11 PM PDT 24
Finished Aug 12 05:05:20 PM PDT 24
Peak memory 197764 kb
Host smart-43955956-5cc7-4707-8936-f43ba4fe5d93
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704233148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1704233148
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.3257955489
Short name T297
Test name
Test status
Simulation time 54177391508 ps
CPU time 303.25 seconds
Started Aug 12 05:05:11 PM PDT 24
Finished Aug 12 05:10:14 PM PDT 24
Peak memory 200612 kb
Host smart-8f19e2d4-5427-42af-b3f6-06198accabb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3257955489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3257955489
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.2648964316
Short name T991
Test name
Test status
Simulation time 5821914641 ps
CPU time 6.58 seconds
Started Aug 12 05:05:11 PM PDT 24
Finished Aug 12 05:05:18 PM PDT 24
Peak memory 199800 kb
Host smart-e148212d-3754-45d3-91ec-97b5e9b6021b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648964316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2648964316
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.4071238457
Short name T1013
Test name
Test status
Simulation time 28760878664 ps
CPU time 23.08 seconds
Started Aug 12 05:05:12 PM PDT 24
Finished Aug 12 05:05:35 PM PDT 24
Peak memory 199448 kb
Host smart-9e0e5cf1-b72f-4e88-9db0-b3642e712250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071238457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.4071238457
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.1931522160
Short name T1183
Test name
Test status
Simulation time 23590583372 ps
CPU time 282.48 seconds
Started Aug 12 05:05:11 PM PDT 24
Finished Aug 12 05:09:54 PM PDT 24
Peak memory 200604 kb
Host smart-ca5ef220-1905-4fa4-8733-80083cc4aa8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1931522160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1931522160
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.2882589750
Short name T1070
Test name
Test status
Simulation time 5601796740 ps
CPU time 23.84 seconds
Started Aug 12 05:05:14 PM PDT 24
Finished Aug 12 05:05:38 PM PDT 24
Peak memory 198708 kb
Host smart-1c3cb3cf-9dd3-46d1-80d5-3ce2b1c4487f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2882589750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.2882589750
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3078295203
Short name T274
Test name
Test status
Simulation time 4343064955 ps
CPU time 6.92 seconds
Started Aug 12 05:05:14 PM PDT 24
Finished Aug 12 05:05:21 PM PDT 24
Peak memory 197020 kb
Host smart-5acf4537-998c-4c4e-ae69-0361202670a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078295203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3078295203
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1170944755
Short name T716
Test name
Test status
Simulation time 132811513 ps
CPU time 0.97 seconds
Started Aug 12 05:05:12 PM PDT 24
Finished Aug 12 05:05:13 PM PDT 24
Peak memory 198968 kb
Host smart-a3d93b61-129c-4c0e-a495-edc61d3c7f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170944755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1170944755
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.4128719973
Short name T601
Test name
Test status
Simulation time 210976069256 ps
CPU time 68.14 seconds
Started Aug 12 05:05:18 PM PDT 24
Finished Aug 12 05:06:26 PM PDT 24
Peak memory 200684 kb
Host smart-aea454f7-929f-4663-9620-fdc7f3d95804
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128719973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.4128719973
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3599983899
Short name T1035
Test name
Test status
Simulation time 3015389054 ps
CPU time 18.67 seconds
Started Aug 12 05:05:18 PM PDT 24
Finished Aug 12 05:05:37 PM PDT 24
Peak memory 209336 kb
Host smart-496e3696-f197-4cc2-8337-66b0756b9519
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599983899 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3599983899
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3243336891
Short name T1108
Test name
Test status
Simulation time 556903963 ps
CPU time 1.15 seconds
Started Aug 12 05:05:11 PM PDT 24
Finished Aug 12 05:05:13 PM PDT 24
Peak memory 197844 kb
Host smart-c44ae762-84d9-4e03-aa88-7912c31a017e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243336891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3243336891
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.575742572
Short name T750
Test name
Test status
Simulation time 18129986636 ps
CPU time 18.82 seconds
Started Aug 12 05:05:16 PM PDT 24
Finished Aug 12 05:05:35 PM PDT 24
Peak memory 198480 kb
Host smart-036365b2-da0e-4a92-bde2-bdcf971d6e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575742572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.575742572
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.543110326
Short name T326
Test name
Test status
Simulation time 32599555 ps
CPU time 0.54 seconds
Started Aug 12 05:05:18 PM PDT 24
Finished Aug 12 05:05:19 PM PDT 24
Peak memory 195160 kb
Host smart-2f61db3f-8295-44c5-8d39-405b84b8e5da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543110326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.543110326
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2899095408
Short name T1030
Test name
Test status
Simulation time 51460588932 ps
CPU time 41.03 seconds
Started Aug 12 05:05:19 PM PDT 24
Finished Aug 12 05:06:01 PM PDT 24
Peak memory 200676 kb
Host smart-f191cf40-5881-46ac-99cb-85f79214d424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899095408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2899095408
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.277081175
Short name T127
Test name
Test status
Simulation time 122918019868 ps
CPU time 69.34 seconds
Started Aug 12 05:05:18 PM PDT 24
Finished Aug 12 05:06:27 PM PDT 24
Peak memory 200740 kb
Host smart-1eb9e354-aa32-4a6a-b8da-4b2e7f50f6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277081175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.277081175
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.2828561993
Short name T544
Test name
Test status
Simulation time 5959210643 ps
CPU time 10.16 seconds
Started Aug 12 05:05:19 PM PDT 24
Finished Aug 12 05:05:29 PM PDT 24
Peak memory 200568 kb
Host smart-31197fff-38ef-425a-9510-3ef3eac174bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828561993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2828561993
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2499035488
Short name T493
Test name
Test status
Simulation time 24076341113 ps
CPU time 33.08 seconds
Started Aug 12 05:05:26 PM PDT 24
Finished Aug 12 05:06:00 PM PDT 24
Peak memory 197008 kb
Host smart-4f9b1bb0-302f-403e-afbc-b1b87e73f1d1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499035488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2499035488
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2019600854
Short name T702
Test name
Test status
Simulation time 117630924239 ps
CPU time 314.52 seconds
Started Aug 12 05:05:20 PM PDT 24
Finished Aug 12 05:10:34 PM PDT 24
Peak memory 200640 kb
Host smart-0e7a3e19-e0dd-449c-927d-f7cc49b3d5ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2019600854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2019600854
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.185084953
Short name T646
Test name
Test status
Simulation time 6244251860 ps
CPU time 5.12 seconds
Started Aug 12 05:05:18 PM PDT 24
Finished Aug 12 05:05:23 PM PDT 24
Peak memory 198572 kb
Host smart-920f3185-067d-440a-a6e7-a7d3f6472b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185084953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.185084953
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.3863135356
Short name T351
Test name
Test status
Simulation time 38694834893 ps
CPU time 13.99 seconds
Started Aug 12 05:05:21 PM PDT 24
Finished Aug 12 05:05:35 PM PDT 24
Peak memory 200772 kb
Host smart-00a80ba4-d3b7-4034-905c-d4b44c4db672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863135356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3863135356
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.2424379583
Short name T278
Test name
Test status
Simulation time 18544597512 ps
CPU time 820.49 seconds
Started Aug 12 05:05:20 PM PDT 24
Finished Aug 12 05:19:01 PM PDT 24
Peak memory 200644 kb
Host smart-8be1a1f3-e949-4d62-9f5a-01cdd6638f82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2424379583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2424379583
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.562609257
Short name T650
Test name
Test status
Simulation time 4699186504 ps
CPU time 42.97 seconds
Started Aug 12 05:05:27 PM PDT 24
Finished Aug 12 05:06:10 PM PDT 24
Peak memory 199068 kb
Host smart-1910cd2d-068a-4064-ad6c-dab1abb6d468
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=562609257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.562609257
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.2288898171
Short name T288
Test name
Test status
Simulation time 24756883818 ps
CPU time 27.76 seconds
Started Aug 12 05:05:18 PM PDT 24
Finished Aug 12 05:05:46 PM PDT 24
Peak memory 200632 kb
Host smart-9d0e55af-b2a1-4a18-a089-f55f96d84c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288898171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2288898171
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3270172724
Short name T884
Test name
Test status
Simulation time 3643790644 ps
CPU time 5.83 seconds
Started Aug 12 05:05:19 PM PDT 24
Finished Aug 12 05:05:25 PM PDT 24
Peak memory 196748 kb
Host smart-7b01f7b9-9001-4d9f-ac73-8b07c6e03f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270172724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3270172724
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1693720634
Short name T946
Test name
Test status
Simulation time 6243366011 ps
CPU time 23.79 seconds
Started Aug 12 05:05:20 PM PDT 24
Finished Aug 12 05:05:44 PM PDT 24
Peak memory 200116 kb
Host smart-69a6c476-4991-4a2a-a0de-d2dbd67d6aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693720634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1693720634
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.1280836227
Short name T449
Test name
Test status
Simulation time 268639174291 ps
CPU time 358.21 seconds
Started Aug 12 05:05:16 PM PDT 24
Finished Aug 12 05:11:15 PM PDT 24
Peak memory 200756 kb
Host smart-d03f12a3-eb98-409b-a037-631cef3672f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280836227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1280836227
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.903378928
Short name T941
Test name
Test status
Simulation time 17290579781 ps
CPU time 49.34 seconds
Started Aug 12 05:05:19 PM PDT 24
Finished Aug 12 05:06:08 PM PDT 24
Peak memory 216280 kb
Host smart-718778ee-c3b3-48f4-b317-7e1ba1e366fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903378928 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.903378928
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3335857930
Short name T714
Test name
Test status
Simulation time 2753027783 ps
CPU time 1.87 seconds
Started Aug 12 05:05:21 PM PDT 24
Finished Aug 12 05:05:23 PM PDT 24
Peak memory 199532 kb
Host smart-3391a7c0-1da7-41b4-8868-18214f7d47c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335857930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3335857930
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.767589173
Short name T1010
Test name
Test status
Simulation time 121050887001 ps
CPU time 75.45 seconds
Started Aug 12 05:05:18 PM PDT 24
Finished Aug 12 05:06:34 PM PDT 24
Peak memory 200712 kb
Host smart-760e2e0d-4ed1-4066-a0dc-acda8d0e40e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767589173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.767589173
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.4073003530
Short name T1099
Test name
Test status
Simulation time 26594365 ps
CPU time 0.56 seconds
Started Aug 12 05:05:25 PM PDT 24
Finished Aug 12 05:05:26 PM PDT 24
Peak memory 196320 kb
Host smart-cacbf50e-26dc-40b5-8d54-770c991d2a01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073003530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.4073003530
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.1016742954
Short name T427
Test name
Test status
Simulation time 35282040038 ps
CPU time 17.78 seconds
Started Aug 12 05:05:19 PM PDT 24
Finished Aug 12 05:05:37 PM PDT 24
Peak memory 200672 kb
Host smart-203183bf-a873-4c9e-8a69-6c3e368fb654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016742954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1016742954
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_intr.1070055931
Short name T725
Test name
Test status
Simulation time 14180668216 ps
CPU time 21.84 seconds
Started Aug 12 05:05:19 PM PDT 24
Finished Aug 12 05:05:41 PM PDT 24
Peak memory 199276 kb
Host smart-ae0b9209-7b9c-4858-9de1-b98d25333dcd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070055931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.1070055931
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.3175436504
Short name T967
Test name
Test status
Simulation time 101163324790 ps
CPU time 914.1 seconds
Started Aug 12 05:05:31 PM PDT 24
Finished Aug 12 05:20:45 PM PDT 24
Peak memory 200868 kb
Host smart-16db302f-6b84-4301-b6c5-2d73e0c50570
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3175436504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3175436504
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.2414563688
Short name T510
Test name
Test status
Simulation time 7974100557 ps
CPU time 4.97 seconds
Started Aug 12 05:05:19 PM PDT 24
Finished Aug 12 05:05:24 PM PDT 24
Peak memory 200340 kb
Host smart-05529bfb-02f8-4877-82d6-3c5163afbb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414563688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2414563688
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.3897631272
Short name T1068
Test name
Test status
Simulation time 102019076151 ps
CPU time 165.08 seconds
Started Aug 12 05:05:18 PM PDT 24
Finished Aug 12 05:08:04 PM PDT 24
Peak memory 200620 kb
Host smart-bc789b1e-7787-4f78-9c4c-fe5c21edb420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897631272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3897631272
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.1248729289
Short name T911
Test name
Test status
Simulation time 42660116681 ps
CPU time 207.77 seconds
Started Aug 12 05:05:17 PM PDT 24
Finished Aug 12 05:08:45 PM PDT 24
Peak memory 200740 kb
Host smart-5a3e68d2-c73c-4591-be0a-62a94b8b8057
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1248729289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1248729289
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.3272354372
Short name T5
Test name
Test status
Simulation time 3378152972 ps
CPU time 21.33 seconds
Started Aug 12 05:05:24 PM PDT 24
Finished Aug 12 05:05:46 PM PDT 24
Peak memory 199156 kb
Host smart-180d1ece-020d-4a97-8247-5521c0ea1d10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3272354372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.3272354372
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2889868852
Short name T745
Test name
Test status
Simulation time 165798310010 ps
CPU time 130.79 seconds
Started Aug 12 05:05:28 PM PDT 24
Finished Aug 12 05:07:39 PM PDT 24
Peak memory 200800 kb
Host smart-5bdf49af-3cac-4f95-a2b9-ef375a6edc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889868852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2889868852
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2408485177
Short name T681
Test name
Test status
Simulation time 1551582669 ps
CPU time 2.92 seconds
Started Aug 12 05:05:28 PM PDT 24
Finished Aug 12 05:05:31 PM PDT 24
Peak memory 196556 kb
Host smart-934a8f3b-30c8-4bca-b464-727e75bcec38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408485177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2408485177
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.1021855772
Short name T575
Test name
Test status
Simulation time 741751029 ps
CPU time 3.19 seconds
Started Aug 12 05:05:18 PM PDT 24
Finished Aug 12 05:05:21 PM PDT 24
Peak memory 199584 kb
Host smart-d524dc0d-17b4-4f73-b721-d6f708a04492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021855772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1021855772
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.1736168929
Short name T840
Test name
Test status
Simulation time 153219005107 ps
CPU time 590.87 seconds
Started Aug 12 05:05:25 PM PDT 24
Finished Aug 12 05:15:16 PM PDT 24
Peak memory 201012 kb
Host smart-8aeb1bbd-2651-40d6-859f-be72a5822631
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736168929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1736168929
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.3974648992
Short name T28
Test name
Test status
Simulation time 7954543210 ps
CPU time 29.38 seconds
Started Aug 12 05:05:26 PM PDT 24
Finished Aug 12 05:05:56 PM PDT 24
Peak memory 210312 kb
Host smart-872b4a9a-657c-46ba-883c-f1a83b97c20f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974648992 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3974648992
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.415967667
Short name T778
Test name
Test status
Simulation time 6700023504 ps
CPU time 13.19 seconds
Started Aug 12 05:05:19 PM PDT 24
Finished Aug 12 05:05:32 PM PDT 24
Peak memory 200592 kb
Host smart-7580db77-c55d-48a9-a24b-a05020304431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415967667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.415967667
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.1842614819
Short name T695
Test name
Test status
Simulation time 45043424807 ps
CPU time 41.92 seconds
Started Aug 12 05:05:28 PM PDT 24
Finished Aug 12 05:06:10 PM PDT 24
Peak memory 200784 kb
Host smart-0cc1a27d-fb43-4bd0-8fb8-a5281ece4638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842614819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1842614819
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2333329559
Short name T1001
Test name
Test status
Simulation time 15087825 ps
CPU time 0.54 seconds
Started Aug 12 05:05:24 PM PDT 24
Finished Aug 12 05:05:25 PM PDT 24
Peak memory 195704 kb
Host smart-f8ef24f0-ddf6-4c50-8a27-2b37e8e62da9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333329559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2333329559
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.1114751135
Short name T375
Test name
Test status
Simulation time 21381831596 ps
CPU time 33.4 seconds
Started Aug 12 05:05:26 PM PDT 24
Finished Aug 12 05:06:00 PM PDT 24
Peak memory 200668 kb
Host smart-e6342d73-39cd-4731-9016-b2afa9d1c9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114751135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1114751135
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.1005218257
Short name T808
Test name
Test status
Simulation time 123051437873 ps
CPU time 166.73 seconds
Started Aug 12 05:05:25 PM PDT 24
Finished Aug 12 05:08:12 PM PDT 24
Peak memory 200764 kb
Host smart-26c38e09-ccf8-4720-9bb8-e9e2c36bcd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005218257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1005218257
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1783139574
Short name T852
Test name
Test status
Simulation time 36920090934 ps
CPU time 15.88 seconds
Started Aug 12 05:05:25 PM PDT 24
Finished Aug 12 05:05:41 PM PDT 24
Peak memory 200836 kb
Host smart-d17736fa-82d0-48ce-8ae1-f3c5313e655e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783139574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1783139574
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.2835820848
Short name T105
Test name
Test status
Simulation time 39683629973 ps
CPU time 7.71 seconds
Started Aug 12 05:05:26 PM PDT 24
Finished Aug 12 05:05:34 PM PDT 24
Peak memory 200736 kb
Host smart-4fc1124f-ebd2-498d-987e-8a92bdd81668
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835820848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2835820848
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.4168822045
Short name T38
Test name
Test status
Simulation time 313852071617 ps
CPU time 164.99 seconds
Started Aug 12 05:05:24 PM PDT 24
Finished Aug 12 05:08:09 PM PDT 24
Peak memory 200740 kb
Host smart-e228ded5-06c3-4311-ad5f-eef7af2d0c02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4168822045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.4168822045
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.4099359343
Short name T976
Test name
Test status
Simulation time 3655126901 ps
CPU time 4.18 seconds
Started Aug 12 05:05:25 PM PDT 24
Finished Aug 12 05:05:29 PM PDT 24
Peak memory 199500 kb
Host smart-9f77a005-a823-4eef-8060-25c60a10830e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099359343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.4099359343
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3344249231
Short name T974
Test name
Test status
Simulation time 228528602852 ps
CPU time 106.23 seconds
Started Aug 12 05:05:28 PM PDT 24
Finished Aug 12 05:07:14 PM PDT 24
Peak memory 209164 kb
Host smart-70a8d256-b077-4e0f-8bf6-b9b39d759d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344249231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3344249231
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.3947957633
Short name T85
Test name
Test status
Simulation time 5129295181 ps
CPU time 271.27 seconds
Started Aug 12 05:05:25 PM PDT 24
Finished Aug 12 05:09:57 PM PDT 24
Peak memory 200768 kb
Host smart-baa50301-7df2-4215-8619-2214ea98a47a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3947957633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3947957633
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.347743506
Short name T522
Test name
Test status
Simulation time 7702235981 ps
CPU time 17.56 seconds
Started Aug 12 05:05:26 PM PDT 24
Finished Aug 12 05:05:44 PM PDT 24
Peak memory 199796 kb
Host smart-f7a66dac-6fee-404c-83ec-949982af2318
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=347743506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.347743506
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.926120432
Short name T1179
Test name
Test status
Simulation time 113959073169 ps
CPU time 225.55 seconds
Started Aug 12 05:05:26 PM PDT 24
Finished Aug 12 05:09:11 PM PDT 24
Peak memory 200736 kb
Host smart-9e63d0db-c9e2-46fc-addc-eff317a2e523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926120432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.926120432
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.2568410043
Short name T625
Test name
Test status
Simulation time 38731433987 ps
CPU time 31.19 seconds
Started Aug 12 05:05:30 PM PDT 24
Finished Aug 12 05:06:01 PM PDT 24
Peak memory 196868 kb
Host smart-68ac5d3d-74a1-45f0-8979-958d905c75e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568410043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2568410043
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.2438895674
Short name T863
Test name
Test status
Simulation time 698704729 ps
CPU time 1.62 seconds
Started Aug 12 05:05:26 PM PDT 24
Finished Aug 12 05:05:28 PM PDT 24
Peak memory 198876 kb
Host smart-1728cf7b-c680-4b7a-a366-90a3daa470a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438895674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2438895674
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.3173899679
Short name T733
Test name
Test status
Simulation time 314743929626 ps
CPU time 214.25 seconds
Started Aug 12 05:05:27 PM PDT 24
Finished Aug 12 05:09:01 PM PDT 24
Peak memory 200892 kb
Host smart-9eec9126-df73-41c5-a8b2-befab4c1e4db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173899679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3173899679
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1526806976
Short name T1166
Test name
Test status
Simulation time 19102574428 ps
CPU time 60.85 seconds
Started Aug 12 05:05:30 PM PDT 24
Finished Aug 12 05:06:31 PM PDT 24
Peak memory 216556 kb
Host smart-30e494c3-1759-4889-b76e-02276da5ee00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526806976 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1526806976
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1635046218
Short name T903
Test name
Test status
Simulation time 1924737650 ps
CPU time 2.29 seconds
Started Aug 12 05:05:25 PM PDT 24
Finished Aug 12 05:05:27 PM PDT 24
Peak memory 199120 kb
Host smart-7fafd732-6f00-4800-bafb-d40674a76e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635046218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1635046218
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1707120534
Short name T992
Test name
Test status
Simulation time 115144541477 ps
CPU time 52.49 seconds
Started Aug 12 05:05:26 PM PDT 24
Finished Aug 12 05:06:19 PM PDT 24
Peak memory 200836 kb
Host smart-aa3c3cb2-e5f1-4f22-b85f-3bf825698982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707120534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1707120534
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.2242719896
Short name T916
Test name
Test status
Simulation time 137294242 ps
CPU time 0.55 seconds
Started Aug 12 05:03:44 PM PDT 24
Finished Aug 12 05:03:45 PM PDT 24
Peak memory 195584 kb
Host smart-e4225c0c-29f8-4a20-95df-f4b37fa1eed6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242719896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2242719896
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.883160439
Short name T408
Test name
Test status
Simulation time 53629125775 ps
CPU time 58.59 seconds
Started Aug 12 05:03:37 PM PDT 24
Finished Aug 12 05:04:36 PM PDT 24
Peak memory 200792 kb
Host smart-b5672d26-8e38-4363-a75d-532462c38b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883160439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.883160439
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.184202893
Short name T67
Test name
Test status
Simulation time 82528224448 ps
CPU time 28.91 seconds
Started Aug 12 05:03:33 PM PDT 24
Finished Aug 12 05:04:03 PM PDT 24
Peak memory 200484 kb
Host smart-a51f8967-0d35-48df-ab27-91f145c74810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184202893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.184202893
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.85604359
Short name T175
Test name
Test status
Simulation time 22108627216 ps
CPU time 46.51 seconds
Started Aug 12 05:03:54 PM PDT 24
Finished Aug 12 05:04:41 PM PDT 24
Peak memory 200720 kb
Host smart-9d06820f-7fbd-462b-a26b-f06f117e13f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85604359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.85604359
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.3237007649
Short name T789
Test name
Test status
Simulation time 60640783273 ps
CPU time 93.3 seconds
Started Aug 12 05:03:52 PM PDT 24
Finished Aug 12 05:05:26 PM PDT 24
Peak memory 200744 kb
Host smart-997494f9-a46e-4e68-8cba-060f25e122aa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237007649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3237007649
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.726252650
Short name T1021
Test name
Test status
Simulation time 84929273048 ps
CPU time 145.5 seconds
Started Aug 12 05:03:43 PM PDT 24
Finished Aug 12 05:06:09 PM PDT 24
Peak memory 200740 kb
Host smart-b4fb9c2d-261e-4e1a-9cea-615a905744a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=726252650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.726252650
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.4126115597
Short name T744
Test name
Test status
Simulation time 2197793361 ps
CPU time 4.52 seconds
Started Aug 12 05:03:49 PM PDT 24
Finished Aug 12 05:03:54 PM PDT 24
Peak memory 199620 kb
Host smart-b49b873d-1e77-462d-8ab4-5f77e75c890a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126115597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.4126115597
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.2531626569
Short name T677
Test name
Test status
Simulation time 140357731377 ps
CPU time 263.65 seconds
Started Aug 12 05:03:51 PM PDT 24
Finished Aug 12 05:08:14 PM PDT 24
Peak memory 208908 kb
Host smart-3f82e09c-e766-47d9-9118-13a0d7de879b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531626569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2531626569
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.1755351684
Short name T384
Test name
Test status
Simulation time 2562925941 ps
CPU time 80.21 seconds
Started Aug 12 05:03:47 PM PDT 24
Finished Aug 12 05:05:07 PM PDT 24
Peak memory 200712 kb
Host smart-2e9eb3bc-55ec-46d3-9ac0-bf00902abeb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1755351684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1755351684
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2854791881
Short name T579
Test name
Test status
Simulation time 5275865361 ps
CPU time 18.83 seconds
Started Aug 12 05:03:49 PM PDT 24
Finished Aug 12 05:04:08 PM PDT 24
Peak memory 200044 kb
Host smart-2f9fb7fc-2dd7-4a9e-97c7-82f2b6c4794d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2854791881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2854791881
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2148836804
Short name T907
Test name
Test status
Simulation time 84771103060 ps
CPU time 36.97 seconds
Started Aug 12 05:03:54 PM PDT 24
Finished Aug 12 05:04:32 PM PDT 24
Peak memory 200796 kb
Host smart-851f4f17-7403-412d-9e6a-aaa9480b7979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148836804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2148836804
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.584685163
Short name T414
Test name
Test status
Simulation time 3175457588 ps
CPU time 1.51 seconds
Started Aug 12 05:03:39 PM PDT 24
Finished Aug 12 05:03:41 PM PDT 24
Peak memory 196992 kb
Host smart-0afec9ad-73c5-4e13-8072-a17555800639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584685163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.584685163
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2829966138
Short name T27
Test name
Test status
Simulation time 35847555 ps
CPU time 0.76 seconds
Started Aug 12 05:03:54 PM PDT 24
Finished Aug 12 05:03:55 PM PDT 24
Peak memory 218944 kb
Host smart-9e1b8c8d-18a3-4aca-8cd3-042f9f7fdb51
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829966138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2829966138
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.3759570941
Short name T1152
Test name
Test status
Simulation time 431394197 ps
CPU time 1.27 seconds
Started Aug 12 05:03:41 PM PDT 24
Finished Aug 12 05:03:43 PM PDT 24
Peak memory 199488 kb
Host smart-693490b5-4f64-41f5-8d96-a515dace07a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759570941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3759570941
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.184937223
Short name T431
Test name
Test status
Simulation time 4879583730 ps
CPU time 9.68 seconds
Started Aug 12 05:03:53 PM PDT 24
Finished Aug 12 05:04:03 PM PDT 24
Peak memory 200688 kb
Host smart-a8707bd2-b16d-4848-8266-de293bf32780
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184937223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.184937223
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.1894709307
Short name T1136
Test name
Test status
Simulation time 7233037607 ps
CPU time 24.39 seconds
Started Aug 12 05:03:47 PM PDT 24
Finished Aug 12 05:04:12 PM PDT 24
Peak memory 216352 kb
Host smart-a60d721f-72bc-4d1a-81c1-4975d078d2bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894709307 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1894709307
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.146413783
Short name T1027
Test name
Test status
Simulation time 2096421065 ps
CPU time 1.7 seconds
Started Aug 12 05:03:37 PM PDT 24
Finished Aug 12 05:03:39 PM PDT 24
Peak memory 200680 kb
Host smart-e0b11303-2018-4cc5-b561-847e319ea70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146413783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.146413783
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.307664828
Short name T1016
Test name
Test status
Simulation time 68978693283 ps
CPU time 57.37 seconds
Started Aug 12 05:03:38 PM PDT 24
Finished Aug 12 05:04:36 PM PDT 24
Peak memory 200644 kb
Host smart-087c3df8-64d8-4867-a7d3-02d32412e897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307664828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.307664828
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.1984085957
Short name T334
Test name
Test status
Simulation time 15084315 ps
CPU time 0.57 seconds
Started Aug 12 05:05:37 PM PDT 24
Finished Aug 12 05:05:38 PM PDT 24
Peak memory 196064 kb
Host smart-ea36ef5d-378d-4113-84dd-b0e9dcab0c38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984085957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1984085957
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2145122603
Short name T482
Test name
Test status
Simulation time 46043334477 ps
CPU time 19.33 seconds
Started Aug 12 05:05:24 PM PDT 24
Finished Aug 12 05:05:44 PM PDT 24
Peak memory 199944 kb
Host smart-ef6e5b07-8c10-40bc-84b0-a06eb00c987e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145122603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2145122603
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.338901728
Short name T899
Test name
Test status
Simulation time 24823703765 ps
CPU time 37.77 seconds
Started Aug 12 05:05:26 PM PDT 24
Finished Aug 12 05:06:04 PM PDT 24
Peak memory 200680 kb
Host smart-615ef84f-0a19-41a3-9a02-cf305fa7cbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338901728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.338901728
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.1126590588
Short name T229
Test name
Test status
Simulation time 12687707805 ps
CPU time 12.67 seconds
Started Aug 12 05:05:25 PM PDT 24
Finished Aug 12 05:05:37 PM PDT 24
Peak memory 200672 kb
Host smart-326760c1-e409-49c3-ab38-b86fcad1a9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126590588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1126590588
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.383748592
Short name T320
Test name
Test status
Simulation time 7085997366 ps
CPU time 3.66 seconds
Started Aug 12 05:05:25 PM PDT 24
Finished Aug 12 05:05:29 PM PDT 24
Peak memory 197860 kb
Host smart-c3a484ed-e1f5-4c38-8468-5ede403d8167
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383748592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.383748592
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.1899630953
Short name T543
Test name
Test status
Simulation time 65653819050 ps
CPU time 138.16 seconds
Started Aug 12 05:05:36 PM PDT 24
Finished Aug 12 05:07:54 PM PDT 24
Peak memory 200812 kb
Host smart-bb55ffcf-9794-4ddd-9aca-6feae0d8bc61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1899630953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.1899630953
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.244192864
Short name T469
Test name
Test status
Simulation time 6417993546 ps
CPU time 10.94 seconds
Started Aug 12 05:05:25 PM PDT 24
Finished Aug 12 05:05:36 PM PDT 24
Peak memory 198636 kb
Host smart-d60deb7e-697c-4e9c-b770-5f811d3364de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244192864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.244192864
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.718238253
Short name T1106
Test name
Test status
Simulation time 27325624302 ps
CPU time 47.37 seconds
Started Aug 12 05:05:25 PM PDT 24
Finished Aug 12 05:06:13 PM PDT 24
Peak memory 199924 kb
Host smart-b8101ed0-883f-44c6-af96-91ef037f7cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718238253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.718238253
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.1896994559
Short name T511
Test name
Test status
Simulation time 25770926221 ps
CPU time 295.59 seconds
Started Aug 12 05:05:27 PM PDT 24
Finished Aug 12 05:10:22 PM PDT 24
Peak memory 200772 kb
Host smart-f773efd3-1a75-462a-8b9c-ef8dda2b62e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1896994559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1896994559
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.468379716
Short name T1109
Test name
Test status
Simulation time 4459268037 ps
CPU time 39.94 seconds
Started Aug 12 05:05:28 PM PDT 24
Finished Aug 12 05:06:08 PM PDT 24
Peak memory 199588 kb
Host smart-f08be541-589b-4458-b5a1-64cf73db4797
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=468379716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.468379716
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.600139616
Short name T88
Test name
Test status
Simulation time 20699849761 ps
CPU time 36.37 seconds
Started Aug 12 05:05:25 PM PDT 24
Finished Aug 12 05:06:01 PM PDT 24
Peak memory 200628 kb
Host smart-fc164cdb-2005-433e-8dbf-558e504ac8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600139616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.600139616
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.116215801
Short name T777
Test name
Test status
Simulation time 2136855554 ps
CPU time 3.75 seconds
Started Aug 12 05:05:25 PM PDT 24
Finished Aug 12 05:05:29 PM PDT 24
Peak memory 196296 kb
Host smart-a3a65047-8710-4fe7-a6eb-a7b9752f40e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116215801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.116215801
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2588965390
Short name T538
Test name
Test status
Simulation time 652806265 ps
CPU time 2.5 seconds
Started Aug 12 05:05:27 PM PDT 24
Finished Aug 12 05:05:30 PM PDT 24
Peak memory 198996 kb
Host smart-1de4c88b-79f5-48d5-ab2d-5457b1cc4fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588965390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2588965390
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.383493745
Short name T704
Test name
Test status
Simulation time 65728626654 ps
CPU time 103.02 seconds
Started Aug 12 05:05:35 PM PDT 24
Finished Aug 12 05:07:18 PM PDT 24
Peak memory 200748 kb
Host smart-48396275-5284-406c-8c95-849a13a2a6bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383493745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.383493745
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.1006139183
Short name T950
Test name
Test status
Simulation time 5974869943 ps
CPU time 23.09 seconds
Started Aug 12 05:05:33 PM PDT 24
Finished Aug 12 05:05:56 PM PDT 24
Peak memory 209304 kb
Host smart-71783514-e5f0-4c10-aadd-d6b1ea1c2c08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006139183 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.1006139183
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.977588173
Short name T1026
Test name
Test status
Simulation time 770746284 ps
CPU time 2.42 seconds
Started Aug 12 05:05:25 PM PDT 24
Finished Aug 12 05:05:28 PM PDT 24
Peak memory 199520 kb
Host smart-75bc26b5-753b-4204-86fd-c6459ef01048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977588173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.977588173
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.3774541767
Short name T456
Test name
Test status
Simulation time 59753220870 ps
CPU time 86.72 seconds
Started Aug 12 05:05:25 PM PDT 24
Finished Aug 12 05:06:52 PM PDT 24
Peak memory 200656 kb
Host smart-8b7ff46e-3a62-4cf0-999c-504d59d3afd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774541767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3774541767
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.3839565637
Short name T775
Test name
Test status
Simulation time 31002285 ps
CPU time 0.58 seconds
Started Aug 12 05:05:34 PM PDT 24
Finished Aug 12 05:05:35 PM PDT 24
Peak memory 194948 kb
Host smart-8a4c1ab7-7df9-4e64-9d21-7f7f042cabac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839565637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.3839565637
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.1134607515
Short name T762
Test name
Test status
Simulation time 91827649119 ps
CPU time 195.39 seconds
Started Aug 12 05:05:33 PM PDT 24
Finished Aug 12 05:08:48 PM PDT 24
Peak memory 200816 kb
Host smart-9aa17a2f-3f0f-4025-898c-879c0cbd1422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134607515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1134607515
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_intr.4146623855
Short name T1063
Test name
Test status
Simulation time 246270420227 ps
CPU time 99.28 seconds
Started Aug 12 05:05:33 PM PDT 24
Finished Aug 12 05:07:12 PM PDT 24
Peak memory 198568 kb
Host smart-e1c8d020-6f1b-466c-be0f-04d93ca63e41
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146623855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.4146623855
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.4239749583
Short name T996
Test name
Test status
Simulation time 87028573199 ps
CPU time 516.51 seconds
Started Aug 12 05:05:33 PM PDT 24
Finished Aug 12 05:14:10 PM PDT 24
Peak memory 200704 kb
Host smart-ddef8043-21a8-422e-902c-a1ef03775ec8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4239749583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.4239749583
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.459249689
Short name T765
Test name
Test status
Simulation time 13582918947 ps
CPU time 12.63 seconds
Started Aug 12 05:05:37 PM PDT 24
Finished Aug 12 05:05:50 PM PDT 24
Peak memory 200748 kb
Host smart-2da91dbd-5801-4102-931c-441e98e1abcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459249689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.459249689
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.3637762700
Short name T1147
Test name
Test status
Simulation time 104249355312 ps
CPU time 48.77 seconds
Started Aug 12 05:05:33 PM PDT 24
Finished Aug 12 05:06:22 PM PDT 24
Peak memory 209176 kb
Host smart-50c1030a-accf-413c-984c-28a458a1ce3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637762700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3637762700
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.419832098
Short name T417
Test name
Test status
Simulation time 14000459690 ps
CPU time 201.74 seconds
Started Aug 12 05:05:32 PM PDT 24
Finished Aug 12 05:08:54 PM PDT 24
Peak memory 200648 kb
Host smart-3b90c6e0-85b9-495f-95a7-84af39887918
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=419832098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.419832098
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.2234495340
Short name T1002
Test name
Test status
Simulation time 3491259723 ps
CPU time 26.76 seconds
Started Aug 12 05:05:33 PM PDT 24
Finished Aug 12 05:06:00 PM PDT 24
Peak memory 198736 kb
Host smart-de4c17dd-a6a9-49f2-bdd8-a4813d673888
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2234495340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2234495340
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.1614113157
Short name T552
Test name
Test status
Simulation time 184969168741 ps
CPU time 243.71 seconds
Started Aug 12 05:05:36 PM PDT 24
Finished Aug 12 05:09:40 PM PDT 24
Peak memory 200792 kb
Host smart-6686897c-f72b-4980-bc78-07a469c11f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614113157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1614113157
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2477349298
Short name T1060
Test name
Test status
Simulation time 752696602 ps
CPU time 1.39 seconds
Started Aug 12 05:05:32 PM PDT 24
Finished Aug 12 05:05:34 PM PDT 24
Peak memory 196232 kb
Host smart-1e71fd67-263b-4534-9e9d-6021d62ab4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477349298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2477349298
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.589153383
Short name T581
Test name
Test status
Simulation time 5729330547 ps
CPU time 9.07 seconds
Started Aug 12 05:05:32 PM PDT 24
Finished Aug 12 05:05:41 PM PDT 24
Peak memory 200536 kb
Host smart-65ec03b1-e96d-4227-a3d2-f6cf045f2c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589153383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.589153383
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2509723415
Short name T569
Test name
Test status
Simulation time 1467966769 ps
CPU time 3.56 seconds
Started Aug 12 05:05:38 PM PDT 24
Finished Aug 12 05:05:42 PM PDT 24
Peak memory 199772 kb
Host smart-e5b5b501-a6c9-4906-b35c-9a5ec2c7fe97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509723415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2509723415
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2657000871
Short name T266
Test name
Test status
Simulation time 142721409394 ps
CPU time 81.3 seconds
Started Aug 12 05:05:32 PM PDT 24
Finished Aug 12 05:06:54 PM PDT 24
Peak memory 200808 kb
Host smart-2da7eaa7-80c6-4c48-9f2a-de5993a5559a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657000871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2657000871
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1830225857
Short name T1052
Test name
Test status
Simulation time 14464807 ps
CPU time 0.56 seconds
Started Aug 12 05:05:38 PM PDT 24
Finished Aug 12 05:05:38 PM PDT 24
Peak memory 195328 kb
Host smart-bb0053ff-004d-4ad2-9440-ed389f6b3b26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830225857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1830225857
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.3404483267
Short name T148
Test name
Test status
Simulation time 133963620213 ps
CPU time 98.44 seconds
Started Aug 12 05:05:35 PM PDT 24
Finished Aug 12 05:07:13 PM PDT 24
Peak memory 200700 kb
Host smart-28b76203-1c14-4f18-8751-787ac81b3788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404483267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3404483267
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3799144569
Short name T865
Test name
Test status
Simulation time 134428661593 ps
CPU time 256.26 seconds
Started Aug 12 05:05:34 PM PDT 24
Finished Aug 12 05:09:50 PM PDT 24
Peak memory 200748 kb
Host smart-ecb0acc3-d438-44f1-86a7-c55d154beb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799144569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3799144569
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3935073479
Short name T666
Test name
Test status
Simulation time 33416609435 ps
CPU time 22.6 seconds
Started Aug 12 05:05:37 PM PDT 24
Finished Aug 12 05:05:59 PM PDT 24
Peak memory 200716 kb
Host smart-2ae27358-d742-469a-8439-5a38e1904601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935073479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3935073479
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2754232177
Short name T546
Test name
Test status
Simulation time 16670039372 ps
CPU time 28.81 seconds
Started Aug 12 05:05:40 PM PDT 24
Finished Aug 12 05:06:09 PM PDT 24
Peak memory 200708 kb
Host smart-25312db9-4bc0-4ead-8a78-5043a21e2c17
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754232177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2754232177
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2995654793
Short name T751
Test name
Test status
Simulation time 71585925177 ps
CPU time 499.89 seconds
Started Aug 12 05:05:42 PM PDT 24
Finished Aug 12 05:14:02 PM PDT 24
Peak memory 200844 kb
Host smart-baada311-3c35-407f-90c1-10ad54c3dae0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2995654793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2995654793
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.2471495848
Short name T344
Test name
Test status
Simulation time 9553015166 ps
CPU time 7.12 seconds
Started Aug 12 05:05:38 PM PDT 24
Finished Aug 12 05:05:45 PM PDT 24
Peak memory 200536 kb
Host smart-2827ace1-4dcd-4df5-80b9-da12c9fa01df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471495848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.2471495848
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.2137687641
Short name T734
Test name
Test status
Simulation time 50147052113 ps
CPU time 23.54 seconds
Started Aug 12 05:05:39 PM PDT 24
Finished Aug 12 05:06:03 PM PDT 24
Peak memory 209340 kb
Host smart-f727f9cc-b9ff-454c-b0c1-7afd50637972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137687641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2137687641
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.2573733074
Short name T814
Test name
Test status
Simulation time 17377670416 ps
CPU time 471.94 seconds
Started Aug 12 05:05:42 PM PDT 24
Finished Aug 12 05:13:34 PM PDT 24
Peak memory 200704 kb
Host smart-b0f8afb1-4a81-4679-8c85-2762fcf9a89b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2573733074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2573733074
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.2937949960
Short name T830
Test name
Test status
Simulation time 7572400469 ps
CPU time 64.32 seconds
Started Aug 12 05:05:44 PM PDT 24
Finished Aug 12 05:06:48 PM PDT 24
Peak memory 198912 kb
Host smart-bc6e00cd-d648-4ad4-b12a-f774e0c15705
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2937949960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2937949960
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.4160752573
Short name T584
Test name
Test status
Simulation time 26648106115 ps
CPU time 21.99 seconds
Started Aug 12 05:05:40 PM PDT 24
Finished Aug 12 05:06:02 PM PDT 24
Peak memory 200744 kb
Host smart-47fea017-d329-4ae1-b658-735ad867c841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160752573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.4160752573
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3422373170
Short name T1128
Test name
Test status
Simulation time 4118568767 ps
CPU time 6.93 seconds
Started Aug 12 05:05:41 PM PDT 24
Finished Aug 12 05:05:48 PM PDT 24
Peak memory 197044 kb
Host smart-5f560104-33b6-4cd6-8106-855f0b13d992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422373170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3422373170
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2295584598
Short name T345
Test name
Test status
Simulation time 331786237 ps
CPU time 1.21 seconds
Started Aug 12 05:05:34 PM PDT 24
Finished Aug 12 05:05:35 PM PDT 24
Peak memory 199432 kb
Host smart-b17b792d-e6b9-47fa-b68d-79116bd60565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295584598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2295584598
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.773282709
Short name T888
Test name
Test status
Simulation time 3492364074 ps
CPU time 16.91 seconds
Started Aug 12 05:05:39 PM PDT 24
Finished Aug 12 05:05:56 PM PDT 24
Peak memory 200944 kb
Host smart-2057074b-c36e-4bd6-b94c-0be11e328b32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773282709 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.773282709
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3743866159
Short name T850
Test name
Test status
Simulation time 1497905065 ps
CPU time 1.96 seconds
Started Aug 12 05:05:39 PM PDT 24
Finished Aug 12 05:05:41 PM PDT 24
Peak memory 200488 kb
Host smart-c01cb0ea-f828-4fc9-96de-0f994d7c02a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743866159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3743866159
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2765474051
Short name T530
Test name
Test status
Simulation time 57474468956 ps
CPU time 27.98 seconds
Started Aug 12 05:05:39 PM PDT 24
Finished Aug 12 05:06:07 PM PDT 24
Peak memory 200704 kb
Host smart-56a114d7-0be9-4f8a-b6bf-f584cf5eb1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765474051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2765474051
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1918232073
Short name T350
Test name
Test status
Simulation time 14980942 ps
CPU time 0.57 seconds
Started Aug 12 05:05:40 PM PDT 24
Finished Aug 12 05:05:40 PM PDT 24
Peak memory 196404 kb
Host smart-7481d815-cb4f-43b2-89b2-8b1ca022c811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918232073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1918232073
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1423699268
Short name T117
Test name
Test status
Simulation time 57024770378 ps
CPU time 34.08 seconds
Started Aug 12 05:05:41 PM PDT 24
Finished Aug 12 05:06:15 PM PDT 24
Peak memory 200712 kb
Host smart-1c6076ed-76d9-485c-a6ab-db0c8c8d3751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423699268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1423699268
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1341288946
Short name T1020
Test name
Test status
Simulation time 23048759127 ps
CPU time 38.25 seconds
Started Aug 12 05:05:40 PM PDT 24
Finished Aug 12 05:06:18 PM PDT 24
Peak memory 200748 kb
Host smart-546fe17c-8b29-4e0a-a470-454550ee2f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341288946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1341288946
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3659141377
Short name T124
Test name
Test status
Simulation time 97450707802 ps
CPU time 142.83 seconds
Started Aug 12 05:05:38 PM PDT 24
Finished Aug 12 05:08:01 PM PDT 24
Peak memory 200632 kb
Host smart-14e273aa-7c05-426a-b777-53df278218aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659141377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3659141377
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.135122204
Short name T275
Test name
Test status
Simulation time 115922425683 ps
CPU time 99.36 seconds
Started Aug 12 05:05:42 PM PDT 24
Finished Aug 12 05:07:21 PM PDT 24
Peak memory 200812 kb
Host smart-9d9aa99b-e1ec-4fbf-bdde-346b7e9e2ba1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135122204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.135122204
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.201611963
Short name T874
Test name
Test status
Simulation time 70105781239 ps
CPU time 797.42 seconds
Started Aug 12 05:05:40 PM PDT 24
Finished Aug 12 05:18:57 PM PDT 24
Peak memory 200736 kb
Host smart-8d0b07b3-4396-47a4-b55b-651e736707a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=201611963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.201611963
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.930555923
Short name T894
Test name
Test status
Simulation time 7332911636 ps
CPU time 9.1 seconds
Started Aug 12 05:05:42 PM PDT 24
Finished Aug 12 05:05:51 PM PDT 24
Peak memory 200336 kb
Host smart-098f738b-ff21-4849-b177-8f9536027e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930555923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.930555923
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.1646308059
Short name T424
Test name
Test status
Simulation time 34278762470 ps
CPU time 51.31 seconds
Started Aug 12 05:05:42 PM PDT 24
Finished Aug 12 05:06:33 PM PDT 24
Peak memory 199652 kb
Host smart-43ffb759-d606-4a2c-9cae-50e46d01eb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646308059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1646308059
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.2825397154
Short name T531
Test name
Test status
Simulation time 13420096387 ps
CPU time 276.85 seconds
Started Aug 12 05:05:37 PM PDT 24
Finished Aug 12 05:10:14 PM PDT 24
Peak memory 200764 kb
Host smart-52f32ea7-f644-4914-b487-e40642453792
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2825397154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2825397154
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2477948790
Short name T373
Test name
Test status
Simulation time 3239088504 ps
CPU time 11.71 seconds
Started Aug 12 05:05:39 PM PDT 24
Finished Aug 12 05:05:51 PM PDT 24
Peak memory 199716 kb
Host smart-4d22a9a4-9aa9-4aab-a5a0-b86ed1f75faa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2477948790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2477948790
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.2906006898
Short name T1059
Test name
Test status
Simulation time 16299747545 ps
CPU time 12.91 seconds
Started Aug 12 05:05:41 PM PDT 24
Finished Aug 12 05:05:54 PM PDT 24
Peak memory 199716 kb
Host smart-ddd0d068-6b77-418e-ba81-801826185a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906006898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2906006898
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.2752495491
Short name T430
Test name
Test status
Simulation time 2081978397 ps
CPU time 1.39 seconds
Started Aug 12 05:05:38 PM PDT 24
Finished Aug 12 05:05:40 PM PDT 24
Peak memory 196284 kb
Host smart-915ee8ab-65a1-464b-9477-b6b5be61112d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752495491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2752495491
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1614594395
Short name T313
Test name
Test status
Simulation time 474752344 ps
CPU time 1.29 seconds
Started Aug 12 05:05:37 PM PDT 24
Finished Aug 12 05:05:39 PM PDT 24
Peak memory 200696 kb
Host smart-03b818d4-64e3-4b6c-9201-623bb9bac321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614594395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1614594395
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.178201493
Short name T156
Test name
Test status
Simulation time 183093927003 ps
CPU time 113.06 seconds
Started Aug 12 05:05:40 PM PDT 24
Finished Aug 12 05:07:33 PM PDT 24
Peak memory 200708 kb
Host smart-8b3ab327-cbfc-4568-bb63-a3cd8fef2073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178201493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.178201493
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2603384980
Short name T29
Test name
Test status
Simulation time 1648153490 ps
CPU time 21.35 seconds
Started Aug 12 05:05:40 PM PDT 24
Finished Aug 12 05:06:02 PM PDT 24
Peak memory 209028 kb
Host smart-b2af43f2-7dcf-43b3-9041-2bf8de81a0ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603384980 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2603384980
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.2743345991
Short name T317
Test name
Test status
Simulation time 7902034126 ps
CPU time 8.41 seconds
Started Aug 12 05:05:40 PM PDT 24
Finished Aug 12 05:05:49 PM PDT 24
Peak memory 200392 kb
Host smart-f19d5217-0329-49cb-b8a7-d921e65ff604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743345991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2743345991
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.2536072787
Short name T473
Test name
Test status
Simulation time 97279484721 ps
CPU time 12.91 seconds
Started Aug 12 05:05:38 PM PDT 24
Finished Aug 12 05:05:51 PM PDT 24
Peak memory 200736 kb
Host smart-0b8fe222-887f-4079-b017-2ce74a2078d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536072787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2536072787
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.3967757600
Short name T825
Test name
Test status
Simulation time 48472525 ps
CPU time 0.56 seconds
Started Aug 12 05:05:48 PM PDT 24
Finished Aug 12 05:05:49 PM PDT 24
Peak memory 196284 kb
Host smart-324767f2-e2a0-457d-8334-451b05e11f4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967757600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3967757600
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1787239156
Short name T402
Test name
Test status
Simulation time 79125310722 ps
CPU time 31.84 seconds
Started Aug 12 05:05:37 PM PDT 24
Finished Aug 12 05:06:09 PM PDT 24
Peak memory 200724 kb
Host smart-a825d8b3-41ad-4437-869e-43dd5f9b1ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787239156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1787239156
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.2342829384
Short name T377
Test name
Test status
Simulation time 41191335883 ps
CPU time 15.68 seconds
Started Aug 12 05:05:38 PM PDT 24
Finished Aug 12 05:05:54 PM PDT 24
Peak memory 200748 kb
Host smart-927b2af8-9fb0-4029-9655-e4e1eedc57c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342829384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.2342829384
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3055926834
Short name T217
Test name
Test status
Simulation time 33758596365 ps
CPU time 85.14 seconds
Started Aug 12 05:05:46 PM PDT 24
Finished Aug 12 05:07:12 PM PDT 24
Peak memory 200804 kb
Host smart-57c6c1f2-d9d1-442a-8295-5d16173721bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055926834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3055926834
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.3816767122
Short name T567
Test name
Test status
Simulation time 44986494706 ps
CPU time 85.57 seconds
Started Aug 12 05:05:46 PM PDT 24
Finished Aug 12 05:07:12 PM PDT 24
Peak memory 200548 kb
Host smart-e0570635-6b8a-425f-93b7-49e0d83dec2d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816767122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3816767122
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.4138731613
Short name T508
Test name
Test status
Simulation time 124367645945 ps
CPU time 1103.64 seconds
Started Aug 12 05:05:45 PM PDT 24
Finished Aug 12 05:24:09 PM PDT 24
Peak memory 200768 kb
Host smart-2f2ccf16-a116-48e6-a2ef-287e89e06249
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4138731613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.4138731613
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.774698493
Short name T713
Test name
Test status
Simulation time 2626674181 ps
CPU time 2 seconds
Started Aug 12 05:05:48 PM PDT 24
Finished Aug 12 05:05:50 PM PDT 24
Peak memory 197052 kb
Host smart-ebe12056-1246-4811-a05e-2ac076ca7ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774698493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.774698493
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.1546777262
Short name T621
Test name
Test status
Simulation time 95545116502 ps
CPU time 163.08 seconds
Started Aug 12 05:05:47 PM PDT 24
Finished Aug 12 05:08:31 PM PDT 24
Peak memory 209124 kb
Host smart-f05bb422-91f7-424c-89ce-1c10904a944a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546777262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1546777262
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.2599231607
Short name T600
Test name
Test status
Simulation time 18780779320 ps
CPU time 487.88 seconds
Started Aug 12 05:05:46 PM PDT 24
Finished Aug 12 05:13:54 PM PDT 24
Peak memory 200964 kb
Host smart-f51c95a7-8d33-429c-b0b6-ce6eb3695863
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2599231607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2599231607
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3565837242
Short name T1048
Test name
Test status
Simulation time 4396668226 ps
CPU time 32.4 seconds
Started Aug 12 05:05:45 PM PDT 24
Finished Aug 12 05:06:17 PM PDT 24
Peak memory 198916 kb
Host smart-058fb87d-559d-4d60-b8fc-0f8f945300d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3565837242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3565837242
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.4018160679
Short name T487
Test name
Test status
Simulation time 73454932051 ps
CPU time 111.92 seconds
Started Aug 12 05:05:45 PM PDT 24
Finished Aug 12 05:07:37 PM PDT 24
Peak memory 200724 kb
Host smart-ca82fdcc-74c4-428f-a2ca-8fd327fa8867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018160679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.4018160679
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.4056179435
Short name T363
Test name
Test status
Simulation time 2067526072 ps
CPU time 1.13 seconds
Started Aug 12 05:05:45 PM PDT 24
Finished Aug 12 05:05:46 PM PDT 24
Peak memory 196204 kb
Host smart-b32042f8-25dc-4f4d-a5ac-c9d0f43d8c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056179435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.4056179435
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3957229719
Short name T599
Test name
Test status
Simulation time 565373806 ps
CPU time 1.27 seconds
Started Aug 12 05:05:41 PM PDT 24
Finished Aug 12 05:05:42 PM PDT 24
Peak memory 200384 kb
Host smart-40a07e58-6bc3-4888-809b-11b79c8e4e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957229719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3957229719
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.326381729
Short name T1005
Test name
Test status
Simulation time 45339685262 ps
CPU time 292.53 seconds
Started Aug 12 05:05:46 PM PDT 24
Finished Aug 12 05:10:39 PM PDT 24
Peak memory 200752 kb
Host smart-c2bb3fb1-cd34-4277-b7b9-4724cae24e0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326381729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.326381729
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.1565863245
Short name T1087
Test name
Test status
Simulation time 9408336878 ps
CPU time 28.76 seconds
Started Aug 12 05:05:48 PM PDT 24
Finished Aug 12 05:06:17 PM PDT 24
Peak memory 216744 kb
Host smart-9e53767a-8be1-45db-a2da-e0c1fb3ef33c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565863245 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.1565863245
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2491791201
Short name T797
Test name
Test status
Simulation time 890513677 ps
CPU time 2.56 seconds
Started Aug 12 05:05:46 PM PDT 24
Finished Aug 12 05:05:49 PM PDT 24
Peak memory 199780 kb
Host smart-76708b84-f6ec-4a61-ba6e-0c764207497d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491791201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2491791201
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.2278675168
Short name T478
Test name
Test status
Simulation time 71125232707 ps
CPU time 140.11 seconds
Started Aug 12 05:05:39 PM PDT 24
Finished Aug 12 05:07:59 PM PDT 24
Peak memory 200800 kb
Host smart-7a2d7fa5-83ec-49ac-8eb3-35c606a35479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278675168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2278675168
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2278383301
Short name T917
Test name
Test status
Simulation time 30766170 ps
CPU time 0.54 seconds
Started Aug 12 05:05:53 PM PDT 24
Finished Aug 12 05:05:54 PM PDT 24
Peak memory 194948 kb
Host smart-23e5287f-e191-4855-be48-6f58808de9aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278383301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2278383301
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.1990119537
Short name T149
Test name
Test status
Simulation time 155939732231 ps
CPU time 209.4 seconds
Started Aug 12 05:05:45 PM PDT 24
Finished Aug 12 05:09:14 PM PDT 24
Peak memory 200788 kb
Host smart-28d29648-7481-4332-ac96-534cb3614965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990119537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1990119537
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.857037834
Short name T1170
Test name
Test status
Simulation time 121088574295 ps
CPU time 202.49 seconds
Started Aug 12 05:05:46 PM PDT 24
Finished Aug 12 05:09:09 PM PDT 24
Peak memory 200764 kb
Host smart-7187f080-fa02-4cd6-a64a-07518fd02bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857037834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.857037834
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2007766249
Short name T230
Test name
Test status
Simulation time 58617121430 ps
CPU time 21.74 seconds
Started Aug 12 05:05:45 PM PDT 24
Finished Aug 12 05:06:06 PM PDT 24
Peak memory 199320 kb
Host smart-59d0edf2-c7ff-42a9-a6fa-374b464b6a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007766249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2007766249
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3489223345
Short name T316
Test name
Test status
Simulation time 24182038551 ps
CPU time 40.12 seconds
Started Aug 12 05:05:45 PM PDT 24
Finished Aug 12 05:06:25 PM PDT 24
Peak memory 199844 kb
Host smart-504c1bdf-9c24-4a83-a5bb-1427affcb0a7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489223345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3489223345
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.309009944
Short name T475
Test name
Test status
Simulation time 56506766111 ps
CPU time 415.63 seconds
Started Aug 12 05:05:46 PM PDT 24
Finished Aug 12 05:12:42 PM PDT 24
Peak memory 200692 kb
Host smart-7951acd3-1a53-48e9-b9d0-074cdbf0834d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=309009944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.309009944
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1458141480
Short name T580
Test name
Test status
Simulation time 5012641493 ps
CPU time 3.41 seconds
Started Aug 12 05:05:48 PM PDT 24
Finished Aug 12 05:05:51 PM PDT 24
Peak memory 198712 kb
Host smart-a9382c67-e144-40d6-9520-479df2ee46cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458141480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1458141480
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1873647506
Short name T390
Test name
Test status
Simulation time 74164310844 ps
CPU time 33.79 seconds
Started Aug 12 05:05:46 PM PDT 24
Finished Aug 12 05:06:20 PM PDT 24
Peak memory 201156 kb
Host smart-43295a8b-cba8-4b98-b98e-60aad5cffef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873647506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1873647506
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.2309635614
Short name T284
Test name
Test status
Simulation time 11616164454 ps
CPU time 62.29 seconds
Started Aug 12 05:05:47 PM PDT 24
Finished Aug 12 05:06:49 PM PDT 24
Peak memory 200772 kb
Host smart-1f4214f7-70f5-4b1a-89b0-4cc4951b5288
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2309635614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2309635614
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2033751970
Short name T331
Test name
Test status
Simulation time 3897388443 ps
CPU time 28.69 seconds
Started Aug 12 05:05:46 PM PDT 24
Finished Aug 12 05:06:15 PM PDT 24
Peak memory 199096 kb
Host smart-f27d136d-1c16-43e4-8a41-a74946aa0902
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2033751970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2033751970
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2384671863
Short name T525
Test name
Test status
Simulation time 65786940190 ps
CPU time 25.58 seconds
Started Aug 12 05:05:46 PM PDT 24
Finished Aug 12 05:06:11 PM PDT 24
Peak memory 200552 kb
Host smart-921df641-307c-4795-b0fe-b38fd7e23810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384671863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2384671863
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3307225150
Short name T423
Test name
Test status
Simulation time 4432026522 ps
CPU time 2.19 seconds
Started Aug 12 05:05:48 PM PDT 24
Finished Aug 12 05:05:50 PM PDT 24
Peak memory 196932 kb
Host smart-50fce19d-c628-4a1e-a2b4-db871f010f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307225150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3307225150
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2532644450
Short name T770
Test name
Test status
Simulation time 699130395 ps
CPU time 2.83 seconds
Started Aug 12 05:05:46 PM PDT 24
Finished Aug 12 05:05:49 PM PDT 24
Peak memory 199028 kb
Host smart-f92d8629-985a-4ae4-a4f1-682654a09e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532644450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2532644450
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.1566407407
Short name T1091
Test name
Test status
Simulation time 377394662211 ps
CPU time 931.54 seconds
Started Aug 12 05:05:53 PM PDT 24
Finished Aug 12 05:21:24 PM PDT 24
Peak memory 200908 kb
Host smart-5e78c58e-aafa-40ec-8d5b-f4c3157792a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566407407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1566407407
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1668401280
Short name T107
Test name
Test status
Simulation time 10419661282 ps
CPU time 42.53 seconds
Started Aug 12 05:05:53 PM PDT 24
Finished Aug 12 05:06:36 PM PDT 24
Peak memory 209188 kb
Host smart-9ba527c8-063c-4008-bac1-bf8a46f922bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668401280 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1668401280
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2667214470
Short name T19
Test name
Test status
Simulation time 1317719718 ps
CPU time 1.56 seconds
Started Aug 12 05:05:45 PM PDT 24
Finished Aug 12 05:05:47 PM PDT 24
Peak memory 200588 kb
Host smart-3e7f127f-8a19-4476-89b4-4b49b03816c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667214470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2667214470
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.479415241
Short name T564
Test name
Test status
Simulation time 122274260815 ps
CPU time 197.36 seconds
Started Aug 12 05:05:46 PM PDT 24
Finished Aug 12 05:09:03 PM PDT 24
Peak memory 200720 kb
Host smart-b4daef9c-b1de-4aa1-ab8b-c294236a5d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479415241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.479415241
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.3430520852
Short name T370
Test name
Test status
Simulation time 12090004 ps
CPU time 0.55 seconds
Started Aug 12 05:05:51 PM PDT 24
Finished Aug 12 05:05:52 PM PDT 24
Peak memory 196172 kb
Host smart-52bd2c0a-b917-4474-ae2e-5369ef0f61d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430520852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3430520852
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2777222367
Short name T1153
Test name
Test status
Simulation time 119984027398 ps
CPU time 48.61 seconds
Started Aug 12 05:05:53 PM PDT 24
Finished Aug 12 05:06:42 PM PDT 24
Peak memory 200620 kb
Host smart-cf6bdcf5-2f29-4fcd-8619-1ce94586fb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777222367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2777222367
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.2798121685
Short name T978
Test name
Test status
Simulation time 154488473196 ps
CPU time 212.18 seconds
Started Aug 12 05:05:53 PM PDT 24
Finished Aug 12 05:09:25 PM PDT 24
Peak memory 200812 kb
Host smart-380095df-147e-43cc-855e-cd9f42f04ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798121685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2798121685
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.1667469800
Short name T205
Test name
Test status
Simulation time 100299721825 ps
CPU time 252.75 seconds
Started Aug 12 05:05:52 PM PDT 24
Finished Aug 12 05:10:05 PM PDT 24
Peak memory 200748 kb
Host smart-c3688ffe-bcbf-473e-a923-ed9a4d0ea1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667469800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1667469800
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.494529839
Short name T17
Test name
Test status
Simulation time 33745266580 ps
CPU time 15.12 seconds
Started Aug 12 05:05:55 PM PDT 24
Finished Aug 12 05:06:10 PM PDT 24
Peak memory 200688 kb
Host smart-2d531245-7bce-4017-91a5-d4bd0e92da99
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494529839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.494529839
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.1952791166
Short name T447
Test name
Test status
Simulation time 131373478954 ps
CPU time 197.65 seconds
Started Aug 12 05:05:52 PM PDT 24
Finished Aug 12 05:09:10 PM PDT 24
Peak memory 200680 kb
Host smart-bd1ece93-4444-489f-8541-5c33e23e3681
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1952791166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1952791166
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.3882612514
Short name T520
Test name
Test status
Simulation time 2749031234 ps
CPU time 2.77 seconds
Started Aug 12 05:05:53 PM PDT 24
Finished Aug 12 05:05:56 PM PDT 24
Peak memory 200024 kb
Host smart-f170c2d6-c360-41b6-aaf4-696332f331eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882612514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3882612514
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3010044922
Short name T998
Test name
Test status
Simulation time 113720731857 ps
CPU time 185.37 seconds
Started Aug 12 05:05:51 PM PDT 24
Finished Aug 12 05:08:57 PM PDT 24
Peak memory 216656 kb
Host smart-d1479a91-6c9d-4523-b32b-646f688f68f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010044922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3010044922
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.3111275537
Short name T1061
Test name
Test status
Simulation time 5451030613 ps
CPU time 263.48 seconds
Started Aug 12 05:05:53 PM PDT 24
Finished Aug 12 05:10:17 PM PDT 24
Peak memory 200812 kb
Host smart-9abf8ca7-2c7b-4af0-a78b-f520f0e32fbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3111275537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3111275537
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3907714790
Short name T332
Test name
Test status
Simulation time 6905812732 ps
CPU time 16.29 seconds
Started Aug 12 05:05:54 PM PDT 24
Finished Aug 12 05:06:10 PM PDT 24
Peak memory 199080 kb
Host smart-705c5a3b-fff4-41b8-b465-2874124c29de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3907714790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3907714790
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2010176392
Short name T166
Test name
Test status
Simulation time 13729093499 ps
CPU time 12.86 seconds
Started Aug 12 05:05:52 PM PDT 24
Finished Aug 12 05:06:05 PM PDT 24
Peak memory 200804 kb
Host smart-45f7b5e8-f9b7-44ec-a4d6-e2dacb4e5e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010176392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2010176392
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.2743016773
Short name T672
Test name
Test status
Simulation time 5065419516 ps
CPU time 8.82 seconds
Started Aug 12 05:05:51 PM PDT 24
Finished Aug 12 05:06:00 PM PDT 24
Peak memory 196972 kb
Host smart-a19e9832-d32e-4aad-b1f1-9891ea3e2810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743016773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2743016773
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.769096310
Short name T895
Test name
Test status
Simulation time 693230669 ps
CPU time 2.05 seconds
Started Aug 12 05:05:54 PM PDT 24
Finished Aug 12 05:05:56 PM PDT 24
Peak memory 199704 kb
Host smart-526704f2-e1fb-42db-a64b-5488a35d1356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769096310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.769096310
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.3295976512
Short name T179
Test name
Test status
Simulation time 214001041734 ps
CPU time 100.41 seconds
Started Aug 12 05:05:54 PM PDT 24
Finished Aug 12 05:07:34 PM PDT 24
Peak memory 200828 kb
Host smart-470dbc20-03ad-4d1f-a3ea-1fb847961b9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295976512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3295976512
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1782974084
Short name T1139
Test name
Test status
Simulation time 5992330666 ps
CPU time 70.16 seconds
Started Aug 12 05:05:53 PM PDT 24
Finished Aug 12 05:07:04 PM PDT 24
Peak memory 217212 kb
Host smart-f6f5946f-cde3-4c88-be35-62725fee597b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782974084 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1782974084
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3831448096
Short name T870
Test name
Test status
Simulation time 5292625366 ps
CPU time 2.11 seconds
Started Aug 12 05:05:55 PM PDT 24
Finished Aug 12 05:05:57 PM PDT 24
Peak memory 200012 kb
Host smart-238331b8-2629-44fc-b25d-f88a16bdd13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831448096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3831448096
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3636670186
Short name T1008
Test name
Test status
Simulation time 58993331472 ps
CPU time 24.16 seconds
Started Aug 12 05:05:53 PM PDT 24
Finished Aug 12 05:06:17 PM PDT 24
Peak memory 200824 kb
Host smart-21328bd8-0873-456a-bd36-106ba5e6e012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636670186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3636670186
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3886044479
Short name T337
Test name
Test status
Simulation time 10807412 ps
CPU time 0.54 seconds
Started Aug 12 05:06:00 PM PDT 24
Finished Aug 12 05:06:01 PM PDT 24
Peak memory 196028 kb
Host smart-5ae2f34e-50a1-4aad-b53c-7fe902a3aa17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886044479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3886044479
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1814432213
Short name T617
Test name
Test status
Simulation time 31133352944 ps
CPU time 56.13 seconds
Started Aug 12 05:05:55 PM PDT 24
Finished Aug 12 05:06:51 PM PDT 24
Peak memory 200672 kb
Host smart-1ffb3d62-242f-4993-8144-e15b58af9e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814432213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1814432213
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.496019712
Short name T576
Test name
Test status
Simulation time 145282888167 ps
CPU time 115.98 seconds
Started Aug 12 05:05:57 PM PDT 24
Finished Aug 12 05:07:53 PM PDT 24
Peak memory 200776 kb
Host smart-6cc0081d-f383-4228-8052-9039d531261b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496019712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.496019712
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.605568789
Short name T248
Test name
Test status
Simulation time 10026115565 ps
CPU time 20.2 seconds
Started Aug 12 05:05:54 PM PDT 24
Finished Aug 12 05:06:14 PM PDT 24
Peak memory 200552 kb
Host smart-e2b6d073-6e39-4001-88c7-b49f00e1447b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605568789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.605568789
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.1138138495
Short name T1098
Test name
Test status
Simulation time 165619689806 ps
CPU time 272.72 seconds
Started Aug 12 05:05:59 PM PDT 24
Finished Aug 12 05:10:32 PM PDT 24
Peak memory 200676 kb
Host smart-42006309-fec2-42ad-a7ce-69cbd7706015
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1138138495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.1138138495
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.905553058
Short name T779
Test name
Test status
Simulation time 2205122329 ps
CPU time 1.72 seconds
Started Aug 12 05:06:02 PM PDT 24
Finished Aug 12 05:06:04 PM PDT 24
Peak memory 198332 kb
Host smart-f535f5f8-a1b4-4b1a-9cb7-e3c42114c482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905553058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.905553058
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3820332883
Short name T310
Test name
Test status
Simulation time 410063964847 ps
CPU time 45.3 seconds
Started Aug 12 05:05:53 PM PDT 24
Finished Aug 12 05:06:39 PM PDT 24
Peak memory 201004 kb
Host smart-6acce205-dfde-42f4-af92-04529f9c2d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820332883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3820332883
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1515499145
Short name T618
Test name
Test status
Simulation time 17996689170 ps
CPU time 828.22 seconds
Started Aug 12 05:05:59 PM PDT 24
Finished Aug 12 05:19:48 PM PDT 24
Peak memory 200704 kb
Host smart-7411050b-6cb0-48a4-9b52-4d6a91414e1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1515499145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1515499145
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1354762245
Short name T333
Test name
Test status
Simulation time 3459804554 ps
CPU time 9.63 seconds
Started Aug 12 05:05:54 PM PDT 24
Finished Aug 12 05:06:04 PM PDT 24
Peak memory 198648 kb
Host smart-b43adb64-433e-4bef-844e-963e8aa4834e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1354762245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1354762245
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.99788735
Short name T856
Test name
Test status
Simulation time 9267836442 ps
CPU time 4.52 seconds
Started Aug 12 05:05:54 PM PDT 24
Finished Aug 12 05:05:58 PM PDT 24
Peak memory 200652 kb
Host smart-0f8bc5f7-86d5-4bcd-830d-2feda33976af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99788735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.99788735
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1598299282
Short name T833
Test name
Test status
Simulation time 2525492980 ps
CPU time 3.53 seconds
Started Aug 12 05:05:57 PM PDT 24
Finished Aug 12 05:06:01 PM PDT 24
Peak memory 196612 kb
Host smart-924a20f6-7138-45ce-accb-e669b0244acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598299282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1598299282
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.4288202684
Short name T787
Test name
Test status
Simulation time 883088385 ps
CPU time 3.9 seconds
Started Aug 12 05:05:54 PM PDT 24
Finished Aug 12 05:05:58 PM PDT 24
Peak memory 200680 kb
Host smart-a7d3cb27-a97a-4a71-ad22-4ea2ff3a0b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288202684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.4288202684
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.4139179700
Short name T769
Test name
Test status
Simulation time 141045506039 ps
CPU time 129.01 seconds
Started Aug 12 05:06:00 PM PDT 24
Finished Aug 12 05:08:10 PM PDT 24
Peak memory 200724 kb
Host smart-94339033-f3d6-4884-9825-f56377ef9ae0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139179700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.4139179700
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.821537842
Short name T1141
Test name
Test status
Simulation time 1729800399 ps
CPU time 19.08 seconds
Started Aug 12 05:05:58 PM PDT 24
Finished Aug 12 05:06:17 PM PDT 24
Peak memory 200836 kb
Host smart-10296cef-1aa0-4c08-ae1e-28ca9898b07d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821537842 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.821537842
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.3983158865
Short name T783
Test name
Test status
Simulation time 845910326 ps
CPU time 1.46 seconds
Started Aug 12 05:05:57 PM PDT 24
Finished Aug 12 05:05:59 PM PDT 24
Peak memory 200036 kb
Host smart-1c5d1e9d-872c-4cb1-9433-5cb84536e76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983158865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3983158865
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1576723169
Short name T253
Test name
Test status
Simulation time 121982799602 ps
CPU time 67.5 seconds
Started Aug 12 05:05:53 PM PDT 24
Finished Aug 12 05:07:01 PM PDT 24
Peak memory 200668 kb
Host smart-2055cfa5-966c-4f69-a349-f9d99e8e8f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576723169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1576723169
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2246124063
Short name T466
Test name
Test status
Simulation time 14819409 ps
CPU time 0.58 seconds
Started Aug 12 05:06:02 PM PDT 24
Finished Aug 12 05:06:03 PM PDT 24
Peak memory 196116 kb
Host smart-738d11d1-9320-4d51-9ffd-ed32a21c6810
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246124063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2246124063
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.3934109302
Short name T831
Test name
Test status
Simulation time 21057592957 ps
CPU time 35.35 seconds
Started Aug 12 05:05:59 PM PDT 24
Finished Aug 12 05:06:34 PM PDT 24
Peak memory 200804 kb
Host smart-5ca62451-1196-4bad-ac8f-4412edfbe0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934109302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3934109302
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.57051546
Short name T440
Test name
Test status
Simulation time 50825944019 ps
CPU time 39.73 seconds
Started Aug 12 05:06:01 PM PDT 24
Finished Aug 12 05:06:41 PM PDT 24
Peak memory 200868 kb
Host smart-a1d469b9-b30e-4e5a-af93-422482b960bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57051546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.57051546
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1079009121
Short name T577
Test name
Test status
Simulation time 97598179779 ps
CPU time 37.73 seconds
Started Aug 12 05:05:59 PM PDT 24
Finished Aug 12 05:06:37 PM PDT 24
Peak memory 200696 kb
Host smart-a2e5d23e-7140-487a-8b71-74647fa80266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079009121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1079009121
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.773144143
Short name T611
Test name
Test status
Simulation time 47080337637 ps
CPU time 55.16 seconds
Started Aug 12 05:05:59 PM PDT 24
Finished Aug 12 05:06:54 PM PDT 24
Peak memory 200352 kb
Host smart-aba7b221-c080-4199-b11b-3d3ff5799c2e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773144143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.773144143
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_loopback.4131399812
Short name T364
Test name
Test status
Simulation time 5582643683 ps
CPU time 6.32 seconds
Started Aug 12 05:06:01 PM PDT 24
Finished Aug 12 05:06:07 PM PDT 24
Peak memory 200680 kb
Host smart-63f5da2f-7964-4f7f-b933-2fb3cec451e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131399812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.4131399812
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.1694608333
Short name T944
Test name
Test status
Simulation time 197374980444 ps
CPU time 77.87 seconds
Started Aug 12 05:06:00 PM PDT 24
Finished Aug 12 05:07:19 PM PDT 24
Peak memory 200824 kb
Host smart-12d6b844-18bd-4d81-97e6-decc3e3d3cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694608333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1694608333
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.3353180400
Short name T848
Test name
Test status
Simulation time 11282396810 ps
CPU time 139.12 seconds
Started Aug 12 05:05:57 PM PDT 24
Finished Aug 12 05:08:17 PM PDT 24
Peak memory 200808 kb
Host smart-bbe4e282-0cc3-405f-ad21-2f21de89c5b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3353180400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3353180400
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.3903458853
Short name T1160
Test name
Test status
Simulation time 2527962774 ps
CPU time 13.99 seconds
Started Aug 12 05:05:58 PM PDT 24
Finished Aug 12 05:06:12 PM PDT 24
Peak memory 199036 kb
Host smart-f7e7f179-b374-42e1-aa8f-489d885fc0dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3903458853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3903458853
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.3775523975
Short name T82
Test name
Test status
Simulation time 96713832200 ps
CPU time 104.03 seconds
Started Aug 12 05:06:01 PM PDT 24
Finished Aug 12 05:07:45 PM PDT 24
Peak memory 200744 kb
Host smart-b2f7a9c9-e6de-4a86-9c3c-bb4f125031c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775523975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3775523975
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.556097719
Short name T964
Test name
Test status
Simulation time 606961844 ps
CPU time 1.49 seconds
Started Aug 12 05:05:59 PM PDT 24
Finished Aug 12 05:06:01 PM PDT 24
Peak memory 196440 kb
Host smart-1ac42a7a-b963-4713-b6df-11f1ed3ebeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556097719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.556097719
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.131924706
Short name T679
Test name
Test status
Simulation time 307047729 ps
CPU time 1.6 seconds
Started Aug 12 05:06:00 PM PDT 24
Finished Aug 12 05:06:02 PM PDT 24
Peak memory 199688 kb
Host smart-9d636cdb-f055-41e1-80e7-5671ff7d8fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131924706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.131924706
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.4149636226
Short name T792
Test name
Test status
Simulation time 119058727335 ps
CPU time 97.13 seconds
Started Aug 12 05:06:01 PM PDT 24
Finished Aug 12 05:07:38 PM PDT 24
Peak memory 200780 kb
Host smart-223fa621-9479-4b0f-ac96-7509f16285be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149636226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.4149636226
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.2073024247
Short name T416
Test name
Test status
Simulation time 28131994995 ps
CPU time 34.55 seconds
Started Aug 12 05:06:00 PM PDT 24
Finished Aug 12 05:06:34 PM PDT 24
Peak memory 216508 kb
Host smart-6824476e-f21b-41ca-a33a-d6d2ec7ff481
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073024247 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2073024247
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.2877350050
Short name T605
Test name
Test status
Simulation time 15747355589 ps
CPU time 12.21 seconds
Started Aug 12 05:06:00 PM PDT 24
Finished Aug 12 05:06:13 PM PDT 24
Peak memory 200732 kb
Host smart-b7a6dd69-c117-409a-9e25-2b21a802efb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877350050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2877350050
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2334249630
Short name T479
Test name
Test status
Simulation time 73471710720 ps
CPU time 137.9 seconds
Started Aug 12 05:06:00 PM PDT 24
Finished Aug 12 05:08:18 PM PDT 24
Peak memory 200800 kb
Host smart-5d44314c-9d54-4e38-8a44-c4d44beea58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334249630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2334249630
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.3149812316
Short name T499
Test name
Test status
Simulation time 50172593 ps
CPU time 0.56 seconds
Started Aug 12 05:06:06 PM PDT 24
Finished Aug 12 05:06:06 PM PDT 24
Peak memory 196116 kb
Host smart-ec3a36fb-d078-4c87-a833-f67ef9b6bcaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149812316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.3149812316
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3658762343
Short name T692
Test name
Test status
Simulation time 40449951629 ps
CPU time 29.2 seconds
Started Aug 12 05:06:03 PM PDT 24
Finished Aug 12 05:06:32 PM PDT 24
Peak memory 200728 kb
Host smart-85c3f8e5-d4ce-47dd-ae02-abd779bcede5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658762343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3658762343
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.248703145
Short name T936
Test name
Test status
Simulation time 76674232627 ps
CPU time 30.44 seconds
Started Aug 12 05:05:58 PM PDT 24
Finished Aug 12 05:06:28 PM PDT 24
Peak memory 200816 kb
Host smart-e0084029-64f1-4491-a834-d3a9f6ed5843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248703145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.248703145
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.661957472
Short name T891
Test name
Test status
Simulation time 35021597448 ps
CPU time 97.68 seconds
Started Aug 12 05:05:59 PM PDT 24
Finished Aug 12 05:07:37 PM PDT 24
Peak memory 200828 kb
Host smart-7d18642a-d846-4a60-8025-bbcf4e7f5a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661957472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.661957472
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3304254662
Short name T717
Test name
Test status
Simulation time 19008964888 ps
CPU time 4.36 seconds
Started Aug 12 05:05:59 PM PDT 24
Finished Aug 12 05:06:04 PM PDT 24
Peak memory 198308 kb
Host smart-8c8be8a7-bf12-427c-80f9-8c26c057577e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304254662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3304254662
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.541228319
Short name T879
Test name
Test status
Simulation time 83304524379 ps
CPU time 295.13 seconds
Started Aug 12 05:05:59 PM PDT 24
Finished Aug 12 05:10:55 PM PDT 24
Peak memory 200676 kb
Host smart-68c75854-ce8e-4b59-8bf7-16edcc11a6d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=541228319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.541228319
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.2670127329
Short name T535
Test name
Test status
Simulation time 313890968 ps
CPU time 0.72 seconds
Started Aug 12 05:06:02 PM PDT 24
Finished Aug 12 05:06:03 PM PDT 24
Peak memory 196204 kb
Host smart-4a52c8c9-2422-4c35-907f-876a4f834220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670127329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2670127329
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2132058097
Short name T793
Test name
Test status
Simulation time 73716215526 ps
CPU time 39.28 seconds
Started Aug 12 05:05:59 PM PDT 24
Finished Aug 12 05:06:39 PM PDT 24
Peak memory 199964 kb
Host smart-9a794b7e-8236-4624-b4b4-6f6640bc460f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132058097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2132058097
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3093485306
Short name T983
Test name
Test status
Simulation time 2700796937 ps
CPU time 116.22 seconds
Started Aug 12 05:06:01 PM PDT 24
Finished Aug 12 05:07:57 PM PDT 24
Peak memory 200808 kb
Host smart-334a4257-ca1b-4719-9096-8ec1a27ba6ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3093485306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3093485306
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.2779572538
Short name T930
Test name
Test status
Simulation time 1395382471 ps
CPU time 2.08 seconds
Started Aug 12 05:06:00 PM PDT 24
Finished Aug 12 05:06:03 PM PDT 24
Peak memory 199000 kb
Host smart-17c6f261-8a15-4d8c-9cf5-885296a48413
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2779572538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.2779572538
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2790540489
Short name T818
Test name
Test status
Simulation time 80995951403 ps
CPU time 21.38 seconds
Started Aug 12 05:06:01 PM PDT 24
Finished Aug 12 05:06:23 PM PDT 24
Peak memory 200508 kb
Host smart-eadbfbe5-5f5d-473e-806e-d8db40eac2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790540489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2790540489
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1084438329
Short name T815
Test name
Test status
Simulation time 5151004869 ps
CPU time 1.16 seconds
Started Aug 12 05:05:57 PM PDT 24
Finished Aug 12 05:05:59 PM PDT 24
Peak memory 196872 kb
Host smart-a692ecff-78c0-48fd-b700-87b5e54bcd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084438329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1084438329
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.1897347230
Short name T302
Test name
Test status
Simulation time 6060775728 ps
CPU time 13.91 seconds
Started Aug 12 05:06:02 PM PDT 24
Finished Aug 12 05:06:16 PM PDT 24
Peak memory 200724 kb
Host smart-0c38b27f-008b-47c9-8285-6910fcb33353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897347230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1897347230
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.3026908231
Short name T31
Test name
Test status
Simulation time 15861299418 ps
CPU time 59.12 seconds
Started Aug 12 05:06:01 PM PDT 24
Finished Aug 12 05:07:00 PM PDT 24
Peak memory 209156 kb
Host smart-416450bb-abaf-45c3-a28d-bb5a03bf7003
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026908231 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.3026908231
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2508381339
Short name T669
Test name
Test status
Simulation time 13775556722 ps
CPU time 14.61 seconds
Started Aug 12 05:06:02 PM PDT 24
Finished Aug 12 05:06:17 PM PDT 24
Peak memory 200652 kb
Host smart-ac42d6cf-dec8-4eff-94ae-3fb2b4fbb635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508381339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2508381339
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.686560190
Short name T1165
Test name
Test status
Simulation time 49032237152 ps
CPU time 68.82 seconds
Started Aug 12 05:06:01 PM PDT 24
Finished Aug 12 05:07:10 PM PDT 24
Peak memory 200692 kb
Host smart-291aeccc-4f4e-45f5-a396-bfef9d07a183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686560190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.686560190
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.196537810
Short name T747
Test name
Test status
Simulation time 21291795 ps
CPU time 0.57 seconds
Started Aug 12 05:03:54 PM PDT 24
Finished Aug 12 05:03:55 PM PDT 24
Peak memory 196012 kb
Host smart-f3b19a37-2f36-433b-a2b3-3b2a222d170b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196537810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.196537810
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1387225879
Short name T809
Test name
Test status
Simulation time 45297121648 ps
CPU time 71.71 seconds
Started Aug 12 05:03:52 PM PDT 24
Finished Aug 12 05:05:04 PM PDT 24
Peak memory 200752 kb
Host smart-bee9fdb1-74dc-4c1b-9d5c-bbc291d31029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387225879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1387225879
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.4008558028
Short name T1072
Test name
Test status
Simulation time 60060850310 ps
CPU time 102.32 seconds
Started Aug 12 05:03:40 PM PDT 24
Finished Aug 12 05:05:23 PM PDT 24
Peak memory 200040 kb
Host smart-ed74142e-2781-4253-8ce0-6f31fcb56d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008558028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.4008558028
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.943930496
Short name T760
Test name
Test status
Simulation time 57151737300 ps
CPU time 24.43 seconds
Started Aug 12 05:04:01 PM PDT 24
Finished Aug 12 05:04:25 PM PDT 24
Peak memory 200660 kb
Host smart-994149c8-1ddb-432f-a5ef-a91424429bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943930496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.943930496
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.498080796
Short name T450
Test name
Test status
Simulation time 22716797572 ps
CPU time 17.44 seconds
Started Aug 12 05:03:48 PM PDT 24
Finished Aug 12 05:04:06 PM PDT 24
Peak memory 200828 kb
Host smart-e969149c-de36-4bf9-a205-907ea77a0822
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498080796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.498080796
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.3040540556
Short name T477
Test name
Test status
Simulation time 84299187199 ps
CPU time 319.28 seconds
Started Aug 12 05:03:47 PM PDT 24
Finished Aug 12 05:09:06 PM PDT 24
Peak memory 200728 kb
Host smart-95f7e08e-0412-416d-8443-ca2cc3b5af72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3040540556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3040540556
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.995899764
Short name T509
Test name
Test status
Simulation time 19159185 ps
CPU time 0.6 seconds
Started Aug 12 05:03:50 PM PDT 24
Finished Aug 12 05:03:50 PM PDT 24
Peak memory 196440 kb
Host smart-4276df2b-693d-44d5-9f46-a82e65394b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995899764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.995899764
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.355247155
Short name T1043
Test name
Test status
Simulation time 44113334413 ps
CPU time 21.52 seconds
Started Aug 12 05:03:53 PM PDT 24
Finished Aug 12 05:04:15 PM PDT 24
Peak memory 199504 kb
Host smart-3323fa8e-0200-4eb6-aefd-20e4284c2760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355247155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.355247155
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.4275594262
Short name T1180
Test name
Test status
Simulation time 11264734149 ps
CPU time 167.96 seconds
Started Aug 12 05:03:45 PM PDT 24
Finished Aug 12 05:06:33 PM PDT 24
Peak memory 200748 kb
Host smart-43e67247-96cc-4a59-a01b-a4220c61cce4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4275594262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.4275594262
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1482415488
Short name T342
Test name
Test status
Simulation time 7835453378 ps
CPU time 62.66 seconds
Started Aug 12 05:03:54 PM PDT 24
Finished Aug 12 05:04:57 PM PDT 24
Peak memory 198556 kb
Host smart-decb7719-81a1-4ac1-bb8d-ba4bf2a5b078
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1482415488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1482415488
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.4189828499
Short name T433
Test name
Test status
Simulation time 54424637552 ps
CPU time 24.17 seconds
Started Aug 12 05:03:46 PM PDT 24
Finished Aug 12 05:04:11 PM PDT 24
Peak memory 200272 kb
Host smart-12e55bab-ec06-4ecd-ae2a-d771347162ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189828499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.4189828499
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1631250979
Short name T398
Test name
Test status
Simulation time 3506944825 ps
CPU time 2.08 seconds
Started Aug 12 05:03:35 PM PDT 24
Finished Aug 12 05:03:37 PM PDT 24
Peak memory 197388 kb
Host smart-4ad6ac51-5453-4b03-af7d-3d8cd391c94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631250979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1631250979
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2031747769
Short name T724
Test name
Test status
Simulation time 742832772 ps
CPU time 2.58 seconds
Started Aug 12 05:03:47 PM PDT 24
Finished Aug 12 05:03:50 PM PDT 24
Peak memory 199832 kb
Host smart-d5ec4910-84ee-4725-94b9-06ad45733525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031747769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2031747769
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.2766527360
Short name T706
Test name
Test status
Simulation time 221631182353 ps
CPU time 1006.63 seconds
Started Aug 12 05:03:50 PM PDT 24
Finished Aug 12 05:20:37 PM PDT 24
Peak memory 209220 kb
Host smart-7f665d8e-76b5-4172-9269-6a355ae4e2d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766527360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2766527360
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.3578445493
Short name T96
Test name
Test status
Simulation time 9102173833 ps
CPU time 58.59 seconds
Started Aug 12 05:03:42 PM PDT 24
Finished Aug 12 05:04:41 PM PDT 24
Peak memory 217032 kb
Host smart-0faf7390-44e5-4097-a95c-e593eba9018c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578445493 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.3578445493
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.559125299
Short name T445
Test name
Test status
Simulation time 1489923996 ps
CPU time 2.18 seconds
Started Aug 12 05:03:34 PM PDT 24
Finished Aug 12 05:03:37 PM PDT 24
Peak memory 199372 kb
Host smart-c7f77703-021c-416a-ada7-1430ee07b4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559125299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.559125299
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1801617304
Short name T458
Test name
Test status
Simulation time 8351291763 ps
CPU time 8.51 seconds
Started Aug 12 05:03:43 PM PDT 24
Finished Aug 12 05:03:51 PM PDT 24
Peak memory 200808 kb
Host smart-872b836c-f744-4baf-b147-926062aabbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801617304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1801617304
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.195369590
Short name T583
Test name
Test status
Simulation time 32281985906 ps
CPU time 56.39 seconds
Started Aug 12 05:06:07 PM PDT 24
Finished Aug 12 05:07:03 PM PDT 24
Peak memory 200776 kb
Host smart-c0ba2f94-cc14-4b5e-9377-614b53074fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195369590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.195369590
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.338109222
Short name T1129
Test name
Test status
Simulation time 53282364041 ps
CPU time 90.49 seconds
Started Aug 12 05:06:09 PM PDT 24
Finished Aug 12 05:07:40 PM PDT 24
Peak memory 216524 kb
Host smart-2e2aff40-f901-4f4b-a613-d22759f95d35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338109222 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.338109222
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.4079975979
Short name T1117
Test name
Test status
Simulation time 54011476995 ps
CPU time 47.16 seconds
Started Aug 12 05:06:06 PM PDT 24
Finished Aug 12 05:06:53 PM PDT 24
Peak memory 200804 kb
Host smart-1c488b83-7216-4dc3-aac9-b2753e04b709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079975979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.4079975979
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.933407797
Short name T914
Test name
Test status
Simulation time 5298392234 ps
CPU time 58.7 seconds
Started Aug 12 05:06:07 PM PDT 24
Finished Aug 12 05:07:06 PM PDT 24
Peak memory 209256 kb
Host smart-5d465787-cd00-45b4-8b90-558b1bc960d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933407797 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.933407797
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2263984953
Short name T1067
Test name
Test status
Simulation time 161528141142 ps
CPU time 22.4 seconds
Started Aug 12 05:06:07 PM PDT 24
Finished Aug 12 05:06:29 PM PDT 24
Peak memory 199348 kb
Host smart-c79dc222-1a63-40ff-9cb0-04d1f5a00fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263984953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2263984953
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.820566244
Short name T939
Test name
Test status
Simulation time 2964401661 ps
CPU time 8.69 seconds
Started Aug 12 05:06:09 PM PDT 24
Finished Aug 12 05:06:18 PM PDT 24
Peak memory 200916 kb
Host smart-f6687141-a67c-4c6c-a81f-68a2249dc821
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820566244 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.820566244
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.2252321989
Short name T929
Test name
Test status
Simulation time 60110150732 ps
CPU time 44.04 seconds
Started Aug 12 05:06:10 PM PDT 24
Finished Aug 12 05:06:54 PM PDT 24
Peak memory 200768 kb
Host smart-e7e8fa23-b045-4952-b7fe-3bf94d691900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252321989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2252321989
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.304570593
Short name T476
Test name
Test status
Simulation time 3220896859 ps
CPU time 11.25 seconds
Started Aug 12 05:06:08 PM PDT 24
Finished Aug 12 05:06:19 PM PDT 24
Peak memory 216828 kb
Host smart-f36f454d-d28a-458b-9327-75d3582b53e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304570593 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.304570593
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3692749766
Short name T829
Test name
Test status
Simulation time 42180627397 ps
CPU time 17.1 seconds
Started Aug 12 05:06:07 PM PDT 24
Finished Aug 12 05:06:24 PM PDT 24
Peak memory 200748 kb
Host smart-4c1ce723-85f7-437e-b3d6-554ed2e55a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692749766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3692749766
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1647316298
Short name T632
Test name
Test status
Simulation time 63226186532 ps
CPU time 55.53 seconds
Started Aug 12 05:06:07 PM PDT 24
Finished Aug 12 05:07:03 PM PDT 24
Peak memory 209304 kb
Host smart-ad01ae0b-1791-4d2d-abfd-931e84aebee7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647316298 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1647316298
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.2101476448
Short name T496
Test name
Test status
Simulation time 18583251607 ps
CPU time 43.06 seconds
Started Aug 12 05:06:06 PM PDT 24
Finished Aug 12 05:06:49 PM PDT 24
Peak memory 200844 kb
Host smart-253794c4-1bac-460b-9e0a-73bf09763901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101476448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2101476448
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2278775580
Short name T526
Test name
Test status
Simulation time 4051097050 ps
CPU time 51.96 seconds
Started Aug 12 05:06:07 PM PDT 24
Finished Aug 12 05:06:59 PM PDT 24
Peak memory 209328 kb
Host smart-da69e2df-0499-43c8-adcb-9857245970ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278775580 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2278775580
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1310455829
Short name T118
Test name
Test status
Simulation time 34295403660 ps
CPU time 78.22 seconds
Started Aug 12 05:06:07 PM PDT 24
Finished Aug 12 05:07:26 PM PDT 24
Peak memory 200776 kb
Host smart-08a3ad4e-4c28-4d61-9d22-00f7dddad25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310455829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1310455829
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.1220124433
Short name T922
Test name
Test status
Simulation time 10738196967 ps
CPU time 37.21 seconds
Started Aug 12 05:06:08 PM PDT 24
Finished Aug 12 05:06:46 PM PDT 24
Peak memory 210276 kb
Host smart-1189d58e-dcae-4a2e-939f-a5b946448383
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220124433 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.1220124433
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3857074901
Short name T947
Test name
Test status
Simulation time 68406323453 ps
CPU time 14.3 seconds
Started Aug 12 05:06:05 PM PDT 24
Finished Aug 12 05:06:20 PM PDT 24
Peak memory 200640 kb
Host smart-dcbc2330-cad2-4c34-9d41-746d26e8a206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857074901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3857074901
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2079385520
Short name T323
Test name
Test status
Simulation time 5162271422 ps
CPU time 19.47 seconds
Started Aug 12 05:06:11 PM PDT 24
Finished Aug 12 05:06:30 PM PDT 24
Peak memory 209004 kb
Host smart-1d560b51-1db6-4483-8078-7901070cff99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079385520 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2079385520
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3876632431
Short name T409
Test name
Test status
Simulation time 28103057343 ps
CPU time 28.65 seconds
Started Aug 12 05:06:08 PM PDT 24
Finished Aug 12 05:06:37 PM PDT 24
Peak memory 200652 kb
Host smart-c9a23ae1-d6b9-486f-bbd8-b4f01d096e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876632431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3876632431
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.2735188497
Short name T923
Test name
Test status
Simulation time 101668774 ps
CPU time 2.02 seconds
Started Aug 12 05:06:06 PM PDT 24
Finished Aug 12 05:06:08 PM PDT 24
Peak memory 200672 kb
Host smart-49abdd61-e268-4355-b0d2-d4b8e8a98c83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735188497 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.2735188497
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1810920777
Short name T95
Test name
Test status
Simulation time 13371278040 ps
CPU time 55.95 seconds
Started Aug 12 05:06:08 PM PDT 24
Finished Aug 12 05:07:04 PM PDT 24
Peak memory 217524 kb
Host smart-60afc157-edc9-4d08-8d75-6eed1d88028c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810920777 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1810920777
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.2262070051
Short name T943
Test name
Test status
Simulation time 27809512 ps
CPU time 0.56 seconds
Started Aug 12 05:03:50 PM PDT 24
Finished Aug 12 05:03:51 PM PDT 24
Peak memory 195556 kb
Host smart-4ff3dbf1-35a9-4875-a467-143b7ae2051d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262070051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2262070051
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3741605621
Short name T910
Test name
Test status
Simulation time 90735185167 ps
CPU time 40.57 seconds
Started Aug 12 05:03:56 PM PDT 24
Finished Aug 12 05:04:37 PM PDT 24
Peak memory 200796 kb
Host smart-362b65b4-244e-46ba-9de2-710678d7513d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741605621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3741605621
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2039173361
Short name T759
Test name
Test status
Simulation time 167373279628 ps
CPU time 47.48 seconds
Started Aug 12 05:03:47 PM PDT 24
Finished Aug 12 05:04:35 PM PDT 24
Peak memory 200604 kb
Host smart-8a37033c-6ccc-4ff4-b54e-432e632c0136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039173361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2039173361
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1675689728
Short name T271
Test name
Test status
Simulation time 265134566483 ps
CPU time 50.69 seconds
Started Aug 12 05:03:52 PM PDT 24
Finished Aug 12 05:04:43 PM PDT 24
Peak memory 200804 kb
Host smart-35a82a16-e0da-4d3c-aa93-70cf4d02dd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675689728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1675689728
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.2535991221
Short name T514
Test name
Test status
Simulation time 27544463899 ps
CPU time 21.54 seconds
Started Aug 12 05:03:51 PM PDT 24
Finished Aug 12 05:04:12 PM PDT 24
Peak memory 199796 kb
Host smart-b5c8c340-4ca5-41cc-ac96-2088fae71da6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535991221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2535991221
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.785764486
Short name T969
Test name
Test status
Simulation time 162530308608 ps
CPU time 276.25 seconds
Started Aug 12 05:03:54 PM PDT 24
Finished Aug 12 05:08:30 PM PDT 24
Peak memory 200824 kb
Host smart-aed0f24e-420b-48d9-8cbc-e44af554f875
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=785764486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.785764486
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.2535581180
Short name T388
Test name
Test status
Simulation time 5111897284 ps
CPU time 3.35 seconds
Started Aug 12 05:03:55 PM PDT 24
Finished Aug 12 05:03:58 PM PDT 24
Peak memory 198792 kb
Host smart-c75b35c3-a93c-4592-9c69-12a198e93e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535581180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2535581180
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1560534567
Short name T1055
Test name
Test status
Simulation time 149531856240 ps
CPU time 57.96 seconds
Started Aug 12 05:03:49 PM PDT 24
Finished Aug 12 05:04:47 PM PDT 24
Peak memory 209032 kb
Host smart-f4277955-1b52-4935-b29f-f7ae76196636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560534567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1560534567
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.656845992
Short name T397
Test name
Test status
Simulation time 6096223940 ps
CPU time 182.08 seconds
Started Aug 12 05:03:49 PM PDT 24
Finished Aug 12 05:06:51 PM PDT 24
Peak memory 200716 kb
Host smart-d1c2de7c-70cf-4f62-99fd-2dc84624ed7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=656845992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.656845992
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.2325154989
Short name T988
Test name
Test status
Simulation time 6332594980 ps
CPU time 49.88 seconds
Started Aug 12 05:03:55 PM PDT 24
Finished Aug 12 05:04:45 PM PDT 24
Peak memory 200352 kb
Host smart-e7fa9c8f-2b39-43c1-ae54-4063cd21824a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2325154989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2325154989
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.431117329
Short name T633
Test name
Test status
Simulation time 39926543487 ps
CPU time 17.09 seconds
Started Aug 12 05:03:42 PM PDT 24
Finished Aug 12 05:04:00 PM PDT 24
Peak memory 200720 kb
Host smart-635789e4-e288-451f-8db9-76368dc55017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431117329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.431117329
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.3344168017
Short name T764
Test name
Test status
Simulation time 6929447907 ps
CPU time 1.49 seconds
Started Aug 12 05:03:39 PM PDT 24
Finished Aug 12 05:03:41 PM PDT 24
Peak memory 196856 kb
Host smart-362d1aae-c7f7-4a2d-aded-76dc6bae8be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344168017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3344168017
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.1849256041
Short name T602
Test name
Test status
Simulation time 1059261029 ps
CPU time 1.32 seconds
Started Aug 12 05:03:53 PM PDT 24
Finished Aug 12 05:03:55 PM PDT 24
Peak memory 199584 kb
Host smart-bb9d38b9-02a0-44ac-ba7c-61c352e4fd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849256041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1849256041
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2616699411
Short name T651
Test name
Test status
Simulation time 2022137082 ps
CPU time 24.17 seconds
Started Aug 12 05:03:48 PM PDT 24
Finished Aug 12 05:04:13 PM PDT 24
Peak memory 216716 kb
Host smart-5d55f7af-5bb8-450d-a8a7-3446754215db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616699411 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2616699411
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.1104438517
Short name T721
Test name
Test status
Simulation time 1637305525 ps
CPU time 2.3 seconds
Started Aug 12 05:03:43 PM PDT 24
Finished Aug 12 05:03:46 PM PDT 24
Peak memory 199736 kb
Host smart-2fd3b83f-91a9-4e3c-bb63-6024380676e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104438517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1104438517
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.3764461262
Short name T1169
Test name
Test status
Simulation time 45069919302 ps
CPU time 46.32 seconds
Started Aug 12 05:03:49 PM PDT 24
Finished Aug 12 05:04:35 PM PDT 24
Peak memory 200932 kb
Host smart-4654cc96-eb5d-4dad-ad67-861f4fa0be8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764461262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3764461262
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.2734537471
Short name T167
Test name
Test status
Simulation time 54407111627 ps
CPU time 21.9 seconds
Started Aug 12 05:06:09 PM PDT 24
Finished Aug 12 05:06:31 PM PDT 24
Peak memory 200712 kb
Host smart-bccf80fb-8ebc-4e9f-8621-50bef265ded9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734537471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2734537471
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.3715186848
Short name T110
Test name
Test status
Simulation time 17604407323 ps
CPU time 37.2 seconds
Started Aug 12 05:06:07 PM PDT 24
Finished Aug 12 05:06:44 PM PDT 24
Peak memory 217228 kb
Host smart-eda2f1f3-c7a5-4fb3-999d-0473b6a07a1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715186848 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3715186848
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.3311463893
Short name T841
Test name
Test status
Simulation time 5256475892 ps
CPU time 24.81 seconds
Started Aug 12 05:06:05 PM PDT 24
Finished Aug 12 05:06:30 PM PDT 24
Peak memory 209256 kb
Host smart-64376e32-4b8a-45cb-9582-117d93837e6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311463893 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.3311463893
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.1273823307
Short name T933
Test name
Test status
Simulation time 272874307143 ps
CPU time 45.73 seconds
Started Aug 12 05:06:06 PM PDT 24
Finished Aug 12 05:06:52 PM PDT 24
Peak memory 200728 kb
Host smart-73edecba-f287-423c-b99c-c2017cfb33c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273823307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1273823307
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1911692305
Short name T98
Test name
Test status
Simulation time 4377331483 ps
CPU time 22.38 seconds
Started Aug 12 05:06:07 PM PDT 24
Finished Aug 12 05:06:30 PM PDT 24
Peak memory 216400 kb
Host smart-808c4727-49f1-45a9-876d-c39a669bc68d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911692305 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1911692305
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.147707263
Short name T565
Test name
Test status
Simulation time 290477899366 ps
CPU time 404.47 seconds
Started Aug 12 05:06:08 PM PDT 24
Finished Aug 12 05:12:53 PM PDT 24
Peak memory 200828 kb
Host smart-ddef303c-54e2-48e3-84ca-9cf816183526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147707263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.147707263
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.1764629518
Short name T319
Test name
Test status
Simulation time 11694324164 ps
CPU time 33.07 seconds
Started Aug 12 05:06:08 PM PDT 24
Finished Aug 12 05:06:42 PM PDT 24
Peak memory 217280 kb
Host smart-4f3eaf8e-1fc3-4c65-b9a6-3781676131cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764629518 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.1764629518
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.3549263696
Short name T1015
Test name
Test status
Simulation time 4194293069 ps
CPU time 25.96 seconds
Started Aug 12 05:06:07 PM PDT 24
Finished Aug 12 05:06:33 PM PDT 24
Peak memory 209244 kb
Host smart-b29f77a5-5664-4884-a60f-367e60fb0522
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549263696 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.3549263696
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2837913602
Short name T161
Test name
Test status
Simulation time 15098116478 ps
CPU time 23.61 seconds
Started Aug 12 05:06:08 PM PDT 24
Finished Aug 12 05:06:31 PM PDT 24
Peak memory 200784 kb
Host smart-e16db3f2-3383-4b2e-a024-6d168ab5a599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837913602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2837913602
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.4209530169
Short name T572
Test name
Test status
Simulation time 388067318 ps
CPU time 10.48 seconds
Started Aug 12 05:06:22 PM PDT 24
Finished Aug 12 05:06:32 PM PDT 24
Peak memory 200732 kb
Host smart-d2df1570-8016-48dd-ad78-9e4def21fb56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209530169 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.4209530169
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.2183630659
Short name T215
Test name
Test status
Simulation time 28565162496 ps
CPU time 43.84 seconds
Started Aug 12 05:06:23 PM PDT 24
Finished Aug 12 05:07:07 PM PDT 24
Peak memory 200704 kb
Host smart-70c0ab2f-d26b-4038-b9dc-ea1d2df73bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183630659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2183630659
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.266466064
Short name T859
Test name
Test status
Simulation time 15243790792 ps
CPU time 38.04 seconds
Started Aug 12 05:06:20 PM PDT 24
Finished Aug 12 05:06:58 PM PDT 24
Peak memory 216628 kb
Host smart-26a8769b-f1f8-4a59-8bec-0e75f192e4e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266466064 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.266466064
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.2132561407
Short name T644
Test name
Test status
Simulation time 30189457375 ps
CPU time 56.61 seconds
Started Aug 12 05:06:21 PM PDT 24
Finished Aug 12 05:07:18 PM PDT 24
Peak memory 200708 kb
Host smart-b5dd9207-a228-4aaa-8c20-11e24ec0c8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132561407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2132561407
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.161247503
Short name T800
Test name
Test status
Simulation time 2600496986 ps
CPU time 74.51 seconds
Started Aug 12 05:06:20 PM PDT 24
Finished Aug 12 05:07:35 PM PDT 24
Peak memory 216452 kb
Host smart-1184544e-a511-4de2-8a94-4f6c883fdd9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161247503 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.161247503
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2096314796
Short name T146
Test name
Test status
Simulation time 125874170164 ps
CPU time 149.69 seconds
Started Aug 12 05:06:21 PM PDT 24
Finished Aug 12 05:08:51 PM PDT 24
Peak memory 200568 kb
Host smart-62bc2d53-bf2a-43bf-bff4-5d7493ae33fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096314796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2096314796
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2554402110
Short name T109
Test name
Test status
Simulation time 6636296189 ps
CPU time 21.45 seconds
Started Aug 12 05:06:20 PM PDT 24
Finished Aug 12 05:06:42 PM PDT 24
Peak memory 209244 kb
Host smart-8dd7aa6b-c43c-4732-9dfe-1ae2567518df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554402110 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2554402110
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.1062696188
Short name T1054
Test name
Test status
Simulation time 3335287214 ps
CPU time 9.74 seconds
Started Aug 12 05:06:23 PM PDT 24
Finished Aug 12 05:06:33 PM PDT 24
Peak memory 209268 kb
Host smart-6a15687b-6101-4648-b19f-3a63defaf8ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062696188 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.1062696188
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2267297052
Short name T690
Test name
Test status
Simulation time 14062397 ps
CPU time 0.54 seconds
Started Aug 12 05:03:49 PM PDT 24
Finished Aug 12 05:03:50 PM PDT 24
Peak memory 195272 kb
Host smart-0f54d239-23a8-40d3-80c8-932fba0878df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267297052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2267297052
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2214319211
Short name T83
Test name
Test status
Simulation time 25736058190 ps
CPU time 35.11 seconds
Started Aug 12 05:03:54 PM PDT 24
Finished Aug 12 05:04:29 PM PDT 24
Peak memory 200832 kb
Host smart-7d07e81e-4965-4e56-a2aa-060613fbb770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214319211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2214319211
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2730169421
Short name T489
Test name
Test status
Simulation time 22846570402 ps
CPU time 37.09 seconds
Started Aug 12 05:03:54 PM PDT 24
Finished Aug 12 05:04:31 PM PDT 24
Peak memory 200724 kb
Host smart-50da6ae3-bf27-45c8-b7fe-131b49e361e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730169421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2730169421
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1335985905
Short name T1077
Test name
Test status
Simulation time 16533293116 ps
CPU time 12.72 seconds
Started Aug 12 05:03:48 PM PDT 24
Finished Aug 12 05:04:01 PM PDT 24
Peak memory 200772 kb
Host smart-9c13f17b-6ed9-4763-a0d3-42d72de83945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335985905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1335985905
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.242282285
Short name T412
Test name
Test status
Simulation time 44267045386 ps
CPU time 39.53 seconds
Started Aug 12 05:03:53 PM PDT 24
Finished Aug 12 05:04:37 PM PDT 24
Peak memory 200780 kb
Host smart-74654ae4-f5e2-4265-9299-5730614bf3bc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242282285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.242282285
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.120725785
Short name T984
Test name
Test status
Simulation time 82202565876 ps
CPU time 557.08 seconds
Started Aug 12 05:03:52 PM PDT 24
Finished Aug 12 05:13:09 PM PDT 24
Peak memory 200840 kb
Host smart-92d95e23-fac3-480f-bd9c-ade1f09be339
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=120725785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.120725785
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2220636436
Short name T624
Test name
Test status
Simulation time 6726498126 ps
CPU time 20.24 seconds
Started Aug 12 05:03:50 PM PDT 24
Finished Aug 12 05:04:10 PM PDT 24
Peak memory 200416 kb
Host smart-5d66f87d-be7a-456d-a751-fe31c315d0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220636436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2220636436
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.1374216416
Short name T362
Test name
Test status
Simulation time 17084807708 ps
CPU time 13.85 seconds
Started Aug 12 05:03:50 PM PDT 24
Finished Aug 12 05:04:04 PM PDT 24
Peak memory 200752 kb
Host smart-d98774af-a2fd-4c39-a78b-d9dac6e4499e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374216416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1374216416
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.2575753744
Short name T403
Test name
Test status
Simulation time 24034111992 ps
CPU time 306.44 seconds
Started Aug 12 05:03:55 PM PDT 24
Finished Aug 12 05:09:02 PM PDT 24
Peak memory 200660 kb
Host smart-a0209451-0510-43bf-9d00-fc3f14c1db60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2575753744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2575753744
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1660199210
Short name T343
Test name
Test status
Simulation time 3252576404 ps
CPU time 20.8 seconds
Started Aug 12 05:03:49 PM PDT 24
Finished Aug 12 05:04:10 PM PDT 24
Peak memory 199344 kb
Host smart-2584c6d0-28b7-4720-8152-090c4f506c61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1660199210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1660199210
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.2474630477
Short name T786
Test name
Test status
Simulation time 202315602812 ps
CPU time 161.92 seconds
Started Aug 12 05:03:56 PM PDT 24
Finished Aug 12 05:06:38 PM PDT 24
Peak memory 200752 kb
Host smart-b45279d6-643b-4890-8d95-ff34eeed2808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474630477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2474630477
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.710696804
Short name T794
Test name
Test status
Simulation time 26711439338 ps
CPU time 4.3 seconds
Started Aug 12 05:03:48 PM PDT 24
Finished Aug 12 05:03:52 PM PDT 24
Peak memory 196816 kb
Host smart-d9601f6d-e357-4977-a7f6-576d7ecc870c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710696804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.710696804
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2678903855
Short name T810
Test name
Test status
Simulation time 5908276519 ps
CPU time 16.23 seconds
Started Aug 12 05:03:45 PM PDT 24
Finished Aug 12 05:04:01 PM PDT 24
Peak memory 200060 kb
Host smart-b67f4379-1438-4725-ac66-c10e28b4bded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678903855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2678903855
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.3034303951
Short name T1151
Test name
Test status
Simulation time 36593549125 ps
CPU time 65.33 seconds
Started Aug 12 05:03:47 PM PDT 24
Finished Aug 12 05:04:52 PM PDT 24
Peak memory 200764 kb
Host smart-6db15bf1-6583-4707-b8ad-5550584783ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034303951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3034303951
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.1197251972
Short name T387
Test name
Test status
Simulation time 3507890359 ps
CPU time 42.43 seconds
Started Aug 12 05:03:46 PM PDT 24
Finished Aug 12 05:04:29 PM PDT 24
Peak memory 210544 kb
Host smart-c8eb4410-6f6d-47af-8ee2-b8f8ad491b9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197251972 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.1197251972
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.186865729
Short name T791
Test name
Test status
Simulation time 2281817674 ps
CPU time 1.93 seconds
Started Aug 12 05:03:52 PM PDT 24
Finished Aug 12 05:03:54 PM PDT 24
Peak memory 198720 kb
Host smart-27891ebc-1100-469a-8d4e-a1642b9bd7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186865729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.186865729
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2117898052
Short name T1175
Test name
Test status
Simulation time 10174964300 ps
CPU time 16.79 seconds
Started Aug 12 05:03:53 PM PDT 24
Finished Aug 12 05:04:10 PM PDT 24
Peak memory 199388 kb
Host smart-04a6138c-d3d2-4e73-b4b1-9012f884b84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117898052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2117898052
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.3113306107
Short name T516
Test name
Test status
Simulation time 8891528018 ps
CPU time 18.92 seconds
Started Aug 12 05:06:19 PM PDT 24
Finished Aug 12 05:06:38 PM PDT 24
Peak memory 200672 kb
Host smart-6cf2cc53-d52b-4bda-b93a-6d1c3ad224c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113306107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3113306107
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1011623918
Short name T698
Test name
Test status
Simulation time 2506320234 ps
CPU time 15.73 seconds
Started Aug 12 05:06:20 PM PDT 24
Finished Aug 12 05:06:36 PM PDT 24
Peak memory 209240 kb
Host smart-63953140-6808-45bb-a043-caf549d82631
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011623918 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1011623918
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1590365633
Short name T781
Test name
Test status
Simulation time 157285546115 ps
CPU time 224.39 seconds
Started Aug 12 05:06:22 PM PDT 24
Finished Aug 12 05:10:07 PM PDT 24
Peak memory 200804 kb
Host smart-0173ace6-6444-4ac5-8173-8ae60694164d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590365633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1590365633
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.1483930471
Short name T92
Test name
Test status
Simulation time 1067764044 ps
CPU time 13.39 seconds
Started Aug 12 05:06:19 PM PDT 24
Finished Aug 12 05:06:32 PM PDT 24
Peak memory 209228 kb
Host smart-1d367c79-01be-4d42-982d-f07a7c9e6ab6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483930471 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.1483930471
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.1619333887
Short name T461
Test name
Test status
Simulation time 59159136004 ps
CPU time 25.67 seconds
Started Aug 12 05:06:23 PM PDT 24
Finished Aug 12 05:06:48 PM PDT 24
Peak memory 200820 kb
Host smart-3bab2f59-efb3-4aff-be59-6e819854f086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619333887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1619333887
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.917158925
Short name T94
Test name
Test status
Simulation time 12200948308 ps
CPU time 42 seconds
Started Aug 12 05:06:20 PM PDT 24
Finished Aug 12 05:07:03 PM PDT 24
Peak memory 217516 kb
Host smart-f5d71078-7b6d-4169-91bd-402062e635d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917158925 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.917158925
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.1440564800
Short name T816
Test name
Test status
Simulation time 21149113295 ps
CPU time 39.5 seconds
Started Aug 12 05:06:20 PM PDT 24
Finished Aug 12 05:07:00 PM PDT 24
Peak memory 200708 kb
Host smart-35337bde-dcee-4875-b314-9abf6284c4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440564800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1440564800
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.1079519995
Short name T726
Test name
Test status
Simulation time 5160446507 ps
CPU time 38.44 seconds
Started Aug 12 05:06:20 PM PDT 24
Finished Aug 12 05:06:59 PM PDT 24
Peak memory 217328 kb
Host smart-af2307d2-23b1-4087-b3dc-09d0ad3a938c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079519995 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.1079519995
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.699895895
Short name T837
Test name
Test status
Simulation time 110225997318 ps
CPU time 164.91 seconds
Started Aug 12 05:06:20 PM PDT 24
Finished Aug 12 05:09:05 PM PDT 24
Peak memory 200420 kb
Host smart-c6cf3d38-e49e-4301-8ab3-6f46d13b7767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699895895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.699895895
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.2007878715
Short name T642
Test name
Test status
Simulation time 4250272545 ps
CPU time 51.26 seconds
Started Aug 12 05:06:23 PM PDT 24
Finished Aug 12 05:07:14 PM PDT 24
Peak memory 217184 kb
Host smart-fcdb9674-7aeb-4e5b-8f65-46801bcf29c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007878715 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.2007878715
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1052912390
Short name T610
Test name
Test status
Simulation time 2597195324 ps
CPU time 12.5 seconds
Started Aug 12 05:06:20 PM PDT 24
Finished Aug 12 05:06:33 PM PDT 24
Peak memory 200972 kb
Host smart-c25109f5-e715-44e9-ac7f-651458e40bfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052912390 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1052912390
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2679681128
Short name T184
Test name
Test status
Simulation time 186690054369 ps
CPU time 55.98 seconds
Started Aug 12 05:06:21 PM PDT 24
Finished Aug 12 05:07:18 PM PDT 24
Peak memory 200608 kb
Host smart-45940aa1-412f-4845-a940-eed0d4b124e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679681128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2679681128
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.3551060584
Short name T866
Test name
Test status
Simulation time 18068984140 ps
CPU time 29.55 seconds
Started Aug 12 05:06:22 PM PDT 24
Finished Aug 12 05:06:52 PM PDT 24
Peak memory 200820 kb
Host smart-b9541e4e-1497-4904-8b58-e8f07ad9bd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551060584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3551060584
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.921510318
Short name T441
Test name
Test status
Simulation time 12383795579 ps
CPU time 46.45 seconds
Started Aug 12 05:06:20 PM PDT 24
Finished Aug 12 05:07:07 PM PDT 24
Peak memory 216700 kb
Host smart-4b0e1fb4-89c6-423e-a093-6d0cb56a51b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921510318 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.921510318
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.140371013
Short name T191
Test name
Test status
Simulation time 14768580905 ps
CPU time 21.32 seconds
Started Aug 12 05:06:18 PM PDT 24
Finished Aug 12 05:06:39 PM PDT 24
Peak memory 200744 kb
Host smart-86fcfcd9-249f-460e-aaf2-d00e5c2d63f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140371013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.140371013
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1658316222
Short name T1025
Test name
Test status
Simulation time 10368663539 ps
CPU time 37.05 seconds
Started Aug 12 05:06:20 PM PDT 24
Finished Aug 12 05:06:57 PM PDT 24
Peak memory 216224 kb
Host smart-e2bea5b3-7acb-4e56-aac4-5612baa6104b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658316222 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1658316222
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1996036673
Short name T188
Test name
Test status
Simulation time 16106227217 ps
CPU time 25.28 seconds
Started Aug 12 05:06:19 PM PDT 24
Finished Aug 12 05:06:44 PM PDT 24
Peak memory 200744 kb
Host smart-f775f6f2-5613-4ac1-ba78-e503f527b3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996036673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1996036673
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.3048741628
Short name T1058
Test name
Test status
Simulation time 3264138651 ps
CPU time 100.21 seconds
Started Aug 12 05:06:20 PM PDT 24
Finished Aug 12 05:08:00 PM PDT 24
Peak memory 209080 kb
Host smart-a7781186-64eb-4a63-9cc5-e555b92d6fb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048741628 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.3048741628
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.3946013078
Short name T24
Test name
Test status
Simulation time 92331330 ps
CPU time 0.53 seconds
Started Aug 12 05:03:56 PM PDT 24
Finished Aug 12 05:03:56 PM PDT 24
Peak memory 195088 kb
Host smart-f2182152-73ec-4c4d-b6b5-db4d9a1fe20e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946013078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3946013078
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.1986899055
Short name T465
Test name
Test status
Simulation time 27196508280 ps
CPU time 60.1 seconds
Started Aug 12 05:03:52 PM PDT 24
Finished Aug 12 05:04:57 PM PDT 24
Peak memory 200716 kb
Host smart-737555fb-48d9-482a-a286-ce858b5e4252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986899055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1986899055
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1533257785
Short name T670
Test name
Test status
Simulation time 71753700496 ps
CPU time 31.11 seconds
Started Aug 12 05:03:50 PM PDT 24
Finished Aug 12 05:04:21 PM PDT 24
Peak memory 200816 kb
Host smart-34c7a9ba-b0cc-4d19-80e0-90f925d713c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533257785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1533257785
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2039268167
Short name T1036
Test name
Test status
Simulation time 19273603787 ps
CPU time 28.49 seconds
Started Aug 12 05:03:48 PM PDT 24
Finished Aug 12 05:04:16 PM PDT 24
Peak memory 200816 kb
Host smart-6365b4da-d42c-4bc5-985f-5268232887fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039268167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2039268167
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.4010096275
Short name T1161
Test name
Test status
Simulation time 44947930748 ps
CPU time 98.25 seconds
Started Aug 12 05:03:55 PM PDT 24
Finished Aug 12 05:05:33 PM PDT 24
Peak memory 200612 kb
Host smart-33c3bb16-82ef-4873-bf80-5c35dbf57e6b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010096275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.4010096275
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.563056674
Short name T752
Test name
Test status
Simulation time 47524748178 ps
CPU time 248.67 seconds
Started Aug 12 05:03:58 PM PDT 24
Finished Aug 12 05:08:06 PM PDT 24
Peak memory 200716 kb
Host smart-6fa42d41-3cd8-49b4-b6a9-7a658c18b5de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=563056674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.563056674
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1282246399
Short name T533
Test name
Test status
Simulation time 6823752126 ps
CPU time 12.5 seconds
Started Aug 12 05:03:57 PM PDT 24
Finished Aug 12 05:04:10 PM PDT 24
Peak memory 200712 kb
Host smart-5eafb998-5b73-4350-b10e-9cfca892d9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282246399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1282246399
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.473438630
Short name T295
Test name
Test status
Simulation time 97526895386 ps
CPU time 84.98 seconds
Started Aug 12 05:03:56 PM PDT 24
Finished Aug 12 05:05:21 PM PDT 24
Peak memory 209004 kb
Host smart-12b95183-196e-4c33-a5f1-09ed282e1058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473438630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.473438630
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.1821715927
Short name T609
Test name
Test status
Simulation time 5151742347 ps
CPU time 52.8 seconds
Started Aug 12 05:04:00 PM PDT 24
Finished Aug 12 05:04:53 PM PDT 24
Peak memory 200760 kb
Host smart-936e049a-2342-4dcf-b8f5-e4c82ccb6ab4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1821715927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1821715927
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.172467127
Short name T352
Test name
Test status
Simulation time 3853382674 ps
CPU time 20.31 seconds
Started Aug 12 05:03:49 PM PDT 24
Finished Aug 12 05:04:09 PM PDT 24
Peak memory 198788 kb
Host smart-ffc98154-5c4a-4347-9369-c940cc11804f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=172467127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.172467127
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3258257884
Short name T396
Test name
Test status
Simulation time 36588071141 ps
CPU time 53.42 seconds
Started Aug 12 05:03:51 PM PDT 24
Finished Aug 12 05:04:44 PM PDT 24
Peak memory 200708 kb
Host smart-10406c6b-c8d7-4612-861f-a62ec5664d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258257884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3258257884
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3378432220
Short name T291
Test name
Test status
Simulation time 78651948394 ps
CPU time 25.03 seconds
Started Aug 12 05:03:54 PM PDT 24
Finished Aug 12 05:04:19 PM PDT 24
Peak memory 196568 kb
Host smart-843a47aa-f9c3-4c04-918a-621cb7452f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378432220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3378432220
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.2049037488
Short name T748
Test name
Test status
Simulation time 5680057122 ps
CPU time 12.09 seconds
Started Aug 12 05:03:49 PM PDT 24
Finished Aug 12 05:04:01 PM PDT 24
Peak memory 200176 kb
Host smart-5ed1c0e2-140f-430d-bbe9-6e1bc3e45f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049037488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2049037488
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.2536215938
Short name T629
Test name
Test status
Simulation time 68734905316 ps
CPU time 74.53 seconds
Started Aug 12 05:03:58 PM PDT 24
Finished Aug 12 05:05:13 PM PDT 24
Peak memory 200740 kb
Host smart-5d71287c-8366-4c45-a39d-a3ef842a8f81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536215938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2536215938
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.3863288450
Short name T534
Test name
Test status
Simulation time 8730307321 ps
CPU time 23.12 seconds
Started Aug 12 05:03:57 PM PDT 24
Finished Aug 12 05:04:20 PM PDT 24
Peak memory 217256 kb
Host smart-6bdc0e60-55ec-4a62-83e2-dcfff3697bb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863288450 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.3863288450
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.2408428208
Short name T18
Test name
Test status
Simulation time 770345520 ps
CPU time 2.63 seconds
Started Aug 12 05:03:48 PM PDT 24
Finished Aug 12 05:03:51 PM PDT 24
Peak memory 199264 kb
Host smart-6c537b50-c19f-41f3-840f-cf2e9cebc85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408428208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2408428208
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2013487262
Short name T561
Test name
Test status
Simulation time 46522369063 ps
CPU time 91.61 seconds
Started Aug 12 05:03:46 PM PDT 24
Finished Aug 12 05:05:18 PM PDT 24
Peak memory 200716 kb
Host smart-c10e05b4-ba40-4f61-bf34-4a934643666d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013487262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2013487262
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.3521802196
Short name T501
Test name
Test status
Simulation time 53339906319 ps
CPU time 39.72 seconds
Started Aug 12 05:06:20 PM PDT 24
Finished Aug 12 05:07:00 PM PDT 24
Peak memory 200832 kb
Host smart-bfd1279a-24cb-447d-9aad-968b4cb9de82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521802196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3521802196
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3127348842
Short name T686
Test name
Test status
Simulation time 3784516439 ps
CPU time 36.59 seconds
Started Aug 12 05:06:23 PM PDT 24
Finished Aug 12 05:07:00 PM PDT 24
Peak memory 217212 kb
Host smart-804c9c87-e161-4982-9c7e-3d3ada285fe1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127348842 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3127348842
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1645940940
Short name T928
Test name
Test status
Simulation time 85610249733 ps
CPU time 114.4 seconds
Started Aug 12 05:06:22 PM PDT 24
Finished Aug 12 05:08:17 PM PDT 24
Peak memory 200840 kb
Host smart-6eb74334-05c5-400c-aa9c-a19f596d04c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645940940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1645940940
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2678477869
Short name T93
Test name
Test status
Simulation time 4192120328 ps
CPU time 19.94 seconds
Started Aug 12 05:06:22 PM PDT 24
Finished Aug 12 05:06:42 PM PDT 24
Peak memory 201236 kb
Host smart-f46fad63-4f21-48bc-8b0d-d5e6e3e6b9a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678477869 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2678477869
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3472013397
Short name T106
Test name
Test status
Simulation time 88983873032 ps
CPU time 82.9 seconds
Started Aug 12 05:06:29 PM PDT 24
Finished Aug 12 05:07:52 PM PDT 24
Peak memory 200836 kb
Host smart-2ca5325f-0373-4d6d-81d5-548cb0b7587f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472013397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3472013397
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.803613233
Short name T869
Test name
Test status
Simulation time 3107124719 ps
CPU time 34.5 seconds
Started Aug 12 05:06:21 PM PDT 24
Finished Aug 12 05:06:56 PM PDT 24
Peak memory 216456 kb
Host smart-0a520d06-374e-4a72-8482-c45eddd502de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803613233 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.803613233
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.519949503
Short name T103
Test name
Test status
Simulation time 74241394690 ps
CPU time 26.06 seconds
Started Aug 12 05:06:26 PM PDT 24
Finished Aug 12 05:06:52 PM PDT 24
Peak memory 200660 kb
Host smart-7e81b5a0-8285-4dc8-8f21-f596e83b1ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519949503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.519949503
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.4179019527
Short name T68
Test name
Test status
Simulation time 5093085292 ps
CPU time 25.95 seconds
Started Aug 12 05:06:22 PM PDT 24
Finished Aug 12 05:06:48 PM PDT 24
Peak memory 209092 kb
Host smart-85416c16-0167-424c-bd9a-8b04fcab8de4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179019527 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.4179019527
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.4072501386
Short name T11
Test name
Test status
Simulation time 9755343555 ps
CPU time 14.07 seconds
Started Aug 12 05:06:21 PM PDT 24
Finished Aug 12 05:06:36 PM PDT 24
Peak memory 200728 kb
Host smart-3daf32b0-21ed-4aa7-9587-cf84b4218054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072501386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.4072501386
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.1053019085
Short name T554
Test name
Test status
Simulation time 1866815568 ps
CPU time 39.57 seconds
Started Aug 12 05:06:22 PM PDT 24
Finished Aug 12 05:07:02 PM PDT 24
Peak memory 209088 kb
Host smart-d119730e-06b6-4d79-91a8-08c5c92e6f9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053019085 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.1053019085
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3339641497
Short name T1156
Test name
Test status
Simulation time 43453488124 ps
CPU time 66.5 seconds
Started Aug 12 05:06:28 PM PDT 24
Finished Aug 12 05:07:34 PM PDT 24
Peak memory 200772 kb
Host smart-1b51674c-36e3-4599-911b-050b328afc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339641497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3339641497
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.3441512159
Short name T208
Test name
Test status
Simulation time 4218266926 ps
CPU time 29.24 seconds
Started Aug 12 05:06:22 PM PDT 24
Finished Aug 12 05:06:52 PM PDT 24
Peak memory 217292 kb
Host smart-1ad9ea92-487c-4afe-8659-bea3372b3bc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441512159 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.3441512159
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2414554951
Short name T86
Test name
Test status
Simulation time 138678292955 ps
CPU time 30.04 seconds
Started Aug 12 05:06:21 PM PDT 24
Finished Aug 12 05:06:51 PM PDT 24
Peak memory 200576 kb
Host smart-ccc2c0e7-065c-4bfe-93f8-baae7ee7b584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414554951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2414554951
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.1622599408
Short name T1062
Test name
Test status
Simulation time 3620713624 ps
CPU time 9.62 seconds
Started Aug 12 05:06:26 PM PDT 24
Finished Aug 12 05:06:35 PM PDT 24
Peak memory 209024 kb
Host smart-80bfc12f-8c95-44c3-90e5-dcd593c48027
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622599408 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1622599408
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2955920746
Short name T1133
Test name
Test status
Simulation time 75648339712 ps
CPU time 165.08 seconds
Started Aug 12 05:06:22 PM PDT 24
Finished Aug 12 05:09:07 PM PDT 24
Peak memory 200784 kb
Host smart-8b2a2def-46ac-4f68-8303-efae1d1d8259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955920746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2955920746
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2911457903
Short name T766
Test name
Test status
Simulation time 20210458463 ps
CPU time 19.01 seconds
Started Aug 12 05:06:28 PM PDT 24
Finished Aug 12 05:06:47 PM PDT 24
Peak memory 200832 kb
Host smart-5f3e9f55-1484-4c87-a60d-bd44fa0e0333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911457903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2911457903
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3331603749
Short name T112
Test name
Test status
Simulation time 5196891692 ps
CPU time 104.86 seconds
Started Aug 12 05:06:28 PM PDT 24
Finished Aug 12 05:08:13 PM PDT 24
Peak memory 217152 kb
Host smart-9d0e8f23-53ed-45f8-ac1d-88a11ab5ab05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331603749 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3331603749
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.2229863201
Short name T200
Test name
Test status
Simulation time 19762236065 ps
CPU time 33.34 seconds
Started Aug 12 05:06:31 PM PDT 24
Finished Aug 12 05:07:04 PM PDT 24
Peak memory 200664 kb
Host smart-c619eb17-1d35-41f1-87ad-02ef8ca931eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229863201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2229863201
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2426504993
Short name T539
Test name
Test status
Simulation time 3217208939 ps
CPU time 20.44 seconds
Started Aug 12 05:06:22 PM PDT 24
Finished Aug 12 05:06:43 PM PDT 24
Peak memory 217344 kb
Host smart-88ff635e-a67a-4bb0-aff3-09f0f29460e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426504993 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2426504993
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.531520261
Short name T329
Test name
Test status
Simulation time 14002836 ps
CPU time 0.57 seconds
Started Aug 12 05:03:59 PM PDT 24
Finished Aug 12 05:04:00 PM PDT 24
Peak memory 196040 kb
Host smart-fbd4fdf8-bd17-44db-9887-ac023ea3dbac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531520261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.531520261
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.4226297650
Short name T120
Test name
Test status
Simulation time 133463299966 ps
CPU time 104.94 seconds
Started Aug 12 05:04:02 PM PDT 24
Finished Aug 12 05:05:47 PM PDT 24
Peak memory 200816 kb
Host smart-e895771f-0c96-4ef6-90e0-c8cb349eb537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226297650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.4226297650
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2275164238
Short name T371
Test name
Test status
Simulation time 18918072240 ps
CPU time 29.7 seconds
Started Aug 12 05:03:54 PM PDT 24
Finished Aug 12 05:04:24 PM PDT 24
Peak memory 200604 kb
Host smart-6d1a96ab-d7a1-48f9-bbe5-0e75cfd1c4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275164238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2275164238
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.4130282014
Short name T826
Test name
Test status
Simulation time 2791072472 ps
CPU time 5.31 seconds
Started Aug 12 05:03:55 PM PDT 24
Finished Aug 12 05:04:00 PM PDT 24
Peak memory 200596 kb
Host smart-0ca366f6-cba5-4691-84e7-1898579ef7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130282014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.4130282014
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.1290369357
Short name T467
Test name
Test status
Simulation time 33349976291 ps
CPU time 50.3 seconds
Started Aug 12 05:03:56 PM PDT 24
Finished Aug 12 05:04:46 PM PDT 24
Peak memory 196840 kb
Host smart-19caad2b-0cbb-4769-b61e-3c441a3a72a0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290369357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1290369357
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.3706336926
Short name T1041
Test name
Test status
Simulation time 127956217394 ps
CPU time 915.14 seconds
Started Aug 12 05:03:56 PM PDT 24
Finished Aug 12 05:19:12 PM PDT 24
Peak memory 200676 kb
Host smart-3643283e-5820-4535-93df-de1a96315a5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3706336926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3706336926
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1615839144
Short name T1095
Test name
Test status
Simulation time 2764585781 ps
CPU time 6.06 seconds
Started Aug 12 05:03:47 PM PDT 24
Finished Aug 12 05:03:54 PM PDT 24
Peak memory 200448 kb
Host smart-63f5904b-acce-4b2f-a7e1-6f76494e6eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615839144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1615839144
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.4280493759
Short name T657
Test name
Test status
Simulation time 58685842155 ps
CPU time 83.48 seconds
Started Aug 12 05:03:52 PM PDT 24
Finished Aug 12 05:05:15 PM PDT 24
Peak memory 200164 kb
Host smart-feacb957-7883-4ac5-ad8e-3f7919d2d0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280493759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.4280493759
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1994387873
Short name T1097
Test name
Test status
Simulation time 25603148401 ps
CPU time 1085.63 seconds
Started Aug 12 05:03:45 PM PDT 24
Finished Aug 12 05:21:51 PM PDT 24
Peak memory 200800 kb
Host smart-89835b42-76a3-48dd-986d-32cf037dea9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1994387873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1994387873
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.2926392917
Short name T960
Test name
Test status
Simulation time 2826573991 ps
CPU time 18.18 seconds
Started Aug 12 05:03:55 PM PDT 24
Finished Aug 12 05:04:13 PM PDT 24
Peak memory 198768 kb
Host smart-352b69b6-1090-43c1-933b-4572b666af4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2926392917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2926392917
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2798341076
Short name T961
Test name
Test status
Simulation time 105473910812 ps
CPU time 143.89 seconds
Started Aug 12 05:03:59 PM PDT 24
Finished Aug 12 05:06:23 PM PDT 24
Peak memory 200592 kb
Host smart-f8ea4f85-82b4-4309-9138-1180afbf6b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798341076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2798341076
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1743879707
Short name T361
Test name
Test status
Simulation time 43550968769 ps
CPU time 10.82 seconds
Started Aug 12 05:03:47 PM PDT 24
Finished Aug 12 05:03:58 PM PDT 24
Peak memory 196616 kb
Host smart-c2587946-b591-4bd8-932c-c972d4ce3d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743879707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1743879707
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.114313147
Short name T739
Test name
Test status
Simulation time 273498336 ps
CPU time 1.43 seconds
Started Aug 12 05:03:52 PM PDT 24
Finished Aug 12 05:03:54 PM PDT 24
Peak memory 200328 kb
Host smart-defec91a-16e8-4f83-825f-30b5563e3aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114313147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.114313147
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3425739352
Short name T199
Test name
Test status
Simulation time 276920457276 ps
CPU time 251.85 seconds
Started Aug 12 05:03:59 PM PDT 24
Finished Aug 12 05:08:11 PM PDT 24
Peak memory 200740 kb
Host smart-62454b88-a329-411c-9c3f-c73f98e602a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425739352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3425739352
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.2222267053
Short name T935
Test name
Test status
Simulation time 18021768397 ps
CPU time 52.14 seconds
Started Aug 12 05:03:55 PM PDT 24
Finished Aug 12 05:04:47 PM PDT 24
Peak memory 210384 kb
Host smart-d3d88add-5749-441c-8116-6c7bf499bd2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222267053 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2222267053
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2500520136
Short name T305
Test name
Test status
Simulation time 6641397716 ps
CPU time 22.04 seconds
Started Aug 12 05:03:57 PM PDT 24
Finished Aug 12 05:04:19 PM PDT 24
Peak memory 200584 kb
Host smart-e96e4847-b934-478a-81d8-1e09a743c5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500520136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2500520136
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2482253736
Short name T269
Test name
Test status
Simulation time 164986925364 ps
CPU time 77.18 seconds
Started Aug 12 05:03:43 PM PDT 24
Finished Aug 12 05:05:00 PM PDT 24
Peak memory 200904 kb
Host smart-ae7a3922-5c39-4fa3-bcb6-cea0ba904880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482253736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2482253736
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3004470147
Short name T1118
Test name
Test status
Simulation time 137973049234 ps
CPU time 205.05 seconds
Started Aug 12 05:06:22 PM PDT 24
Finished Aug 12 05:09:47 PM PDT 24
Peak memory 200704 kb
Host smart-ba62f79d-4300-40eb-99dc-db5dd451276d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004470147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3004470147
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1711631186
Short name T91
Test name
Test status
Simulation time 2870519905 ps
CPU time 14.46 seconds
Started Aug 12 05:06:31 PM PDT 24
Finished Aug 12 05:06:45 PM PDT 24
Peak memory 217180 kb
Host smart-7f0bb180-cf6c-499e-9457-dd7f9f411b56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711631186 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1711631186
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3981941476
Short name T277
Test name
Test status
Simulation time 69839116644 ps
CPU time 19.22 seconds
Started Aug 12 05:06:24 PM PDT 24
Finished Aug 12 05:06:43 PM PDT 24
Peak memory 200792 kb
Host smart-7c375fef-97d8-435b-8a4a-85acebbe0333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981941476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3981941476
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.1776565926
Short name T836
Test name
Test status
Simulation time 2363496119 ps
CPU time 11.87 seconds
Started Aug 12 05:06:23 PM PDT 24
Finished Aug 12 05:06:35 PM PDT 24
Peak memory 200884 kb
Host smart-771f31d8-34ff-4482-9f57-ed7966eac41c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776565926 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1776565926
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.14163168
Short name T1113
Test name
Test status
Simulation time 165683809769 ps
CPU time 40.35 seconds
Started Aug 12 05:06:23 PM PDT 24
Finished Aug 12 05:07:04 PM PDT 24
Peak memory 200612 kb
Host smart-1aeba3be-aa9c-499a-a8ba-fd4a01dca07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14163168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.14163168
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.839238325
Short name T1131
Test name
Test status
Simulation time 9293761023 ps
CPU time 28.63 seconds
Started Aug 12 05:06:23 PM PDT 24
Finished Aug 12 05:06:52 PM PDT 24
Peak memory 209236 kb
Host smart-a0bdde2b-2dcd-424e-8c60-f9d971e8acd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839238325 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.839238325
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3941390281
Short name T861
Test name
Test status
Simulation time 183965867731 ps
CPU time 44.72 seconds
Started Aug 12 05:06:31 PM PDT 24
Finished Aug 12 05:07:16 PM PDT 24
Peak memory 200752 kb
Host smart-3af2044b-4486-4d62-b4a5-84dad121d68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941390281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3941390281
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.753557611
Short name T857
Test name
Test status
Simulation time 4752075072 ps
CPU time 59.84 seconds
Started Aug 12 05:06:31 PM PDT 24
Finished Aug 12 05:07:31 PM PDT 24
Peak memory 209060 kb
Host smart-2c5e2746-d2c9-4a0b-92b5-8a88b3ed4f82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753557611 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.753557611
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2575945974
Short name T135
Test name
Test status
Simulation time 73589039909 ps
CPU time 31.41 seconds
Started Aug 12 05:06:28 PM PDT 24
Finished Aug 12 05:07:00 PM PDT 24
Peak memory 200832 kb
Host smart-9f902d0d-1379-48d1-90cf-605e921f3d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575945974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2575945974
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1336508053
Short name T113
Test name
Test status
Simulation time 3160862843 ps
CPU time 41.14 seconds
Started Aug 12 05:06:24 PM PDT 24
Finished Aug 12 05:07:05 PM PDT 24
Peak memory 216920 kb
Host smart-2d57e0cc-42ac-41f8-836d-fd320109c641
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336508053 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1336508053
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.465090711
Short name T260
Test name
Test status
Simulation time 210026855716 ps
CPU time 26.71 seconds
Started Aug 12 05:06:25 PM PDT 24
Finished Aug 12 05:06:52 PM PDT 24
Peak memory 200728 kb
Host smart-b6664b56-cbf5-4301-a98a-49ca02db73db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465090711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.465090711
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.1959051152
Short name T649
Test name
Test status
Simulation time 6225623189 ps
CPU time 35.28 seconds
Started Aug 12 05:06:21 PM PDT 24
Finished Aug 12 05:06:57 PM PDT 24
Peak memory 209292 kb
Host smart-5a4851dc-1955-48b0-b3f3-634a8d291ad8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959051152 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.1959051152
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.121987935
Short name T435
Test name
Test status
Simulation time 81192518177 ps
CPU time 48.56 seconds
Started Aug 12 05:06:22 PM PDT 24
Finished Aug 12 05:07:11 PM PDT 24
Peak memory 200672 kb
Host smart-96c7cab6-ef23-4b1c-83d4-0188fa50ab95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121987935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.121987935
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3552592565
Short name T381
Test name
Test status
Simulation time 4515052209 ps
CPU time 48.09 seconds
Started Aug 12 05:06:29 PM PDT 24
Finished Aug 12 05:07:17 PM PDT 24
Peak memory 216864 kb
Host smart-5564d39e-f503-4f9d-9f0c-2ff4b54a0234
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552592565 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3552592565
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.4156762125
Short name T123
Test name
Test status
Simulation time 35176459799 ps
CPU time 15.86 seconds
Started Aug 12 05:06:31 PM PDT 24
Finished Aug 12 05:06:47 PM PDT 24
Peak memory 200748 kb
Host smart-d195dbf3-52c5-4bd5-abf1-5cf8cc8ccc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156762125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.4156762125
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3062726024
Short name T428
Test name
Test status
Simulation time 14218764802 ps
CPU time 75.3 seconds
Started Aug 12 05:06:21 PM PDT 24
Finished Aug 12 05:07:36 PM PDT 24
Peak memory 217284 kb
Host smart-09606a3a-0227-46e6-91ca-408a990b66eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062726024 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3062726024
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.2003451371
Short name T715
Test name
Test status
Simulation time 291944002786 ps
CPU time 328.11 seconds
Started Aug 12 05:06:22 PM PDT 24
Finished Aug 12 05:11:51 PM PDT 24
Peak memory 200612 kb
Host smart-f21f8b13-7a8d-48f9-9f11-cb752e8d69eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003451371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2003451371
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.3854651486
Short name T703
Test name
Test status
Simulation time 3141132125 ps
CPU time 13.52 seconds
Started Aug 12 05:06:21 PM PDT 24
Finished Aug 12 05:06:35 PM PDT 24
Peak memory 209128 kb
Host smart-2650fa44-3b89-4132-8761-863180b44eb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854651486 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3854651486
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.2148150394
Short name T529
Test name
Test status
Simulation time 114092962075 ps
CPU time 50.44 seconds
Started Aug 12 05:06:23 PM PDT 24
Finished Aug 12 05:07:14 PM PDT 24
Peak memory 200784 kb
Host smart-65a9f91c-f8f4-44db-a842-cbfde8809bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148150394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2148150394
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1146001976
Short name T20
Test name
Test status
Simulation time 4699510135 ps
CPU time 97.5 seconds
Started Aug 12 05:06:28 PM PDT 24
Finished Aug 12 05:08:06 PM PDT 24
Peak memory 209832 kb
Host smart-3fe38699-f7f0-4897-b9d3-45947b2a0113
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146001976 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1146001976
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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