Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	83586	1			T1	3		T2	37		T3	2
all_values[1]	83586	1			T1	3		T2	37		T3	2
all_values[2]	83586	1			T1	3		T2	37		T3	2
all_values[3]	83586	1			T1	3		T2	37		T3	2
all_values[4]	83586	1			T1	3		T2	37		T3	2
all_values[5]	83586	1			T1	3		T2	37		T3	2
all_values[6]	83586	1			T1	3		T2	37		T3	2
all_values[7]	83586	1			T1	3		T2	37		T3	2
all_values[8]	83586	1			T1	3		T2	37		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

380192

1

T1

15

T2

156

T3

18

auto[1]

372082

1

T1

12

T2

177

T4

3393

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

680864

1

T1

20

T2

299

T3

13

auto[1]

71410

1

T1

7

T2

34

T3

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	20667	1			T2	25		T4	168		T8	4
all_values[0]	auto[0]	auto[1]	18677	1			T2	2		T3	2		T4	37
all_values[0]	auto[1]	auto[0]	27958	1			T4	525		T8	2		T9	13
all_values[0]	auto[1]	auto[1]	16284	1			T1	3		T2	10		T4	44
all_values[1]	auto[0]	auto[0]	38812	1			T3	2		T4	166		T5	1
all_values[1]	auto[0]	auto[1]	1201	1			T12	29		T33	1		T38	2
all_values[1]	auto[1]	auto[0]	42219	1			T1	3		T2	37		T4	608
all_values[1]	auto[1]	auto[1]	1354	1			T35	1		T14	9		T39	3
all_values[2]	auto[0]	auto[0]	42399	1			T2	6		T3	1		T4	609
all_values[2]	auto[0]	auto[1]	2165	1			T2	3		T3	1		T4	6
all_values[2]	auto[1]	auto[0]	36848	1			T1	2		T2	21		T4	151
all_values[2]	auto[1]	auto[1]	2174	1			T1	1		T2	7		T4	8
all_values[3]	auto[0]	auto[0]	42758	1			T1	3		T2	32		T3	2
all_values[3]	auto[0]	auto[1]	294	1			T6	1		T12	2		T13	6
all_values[3]	auto[1]	auto[0]	40288	1			T2	5		T4	76		T6	14
all_values[3]	auto[1]	auto[1]	246	1			T12	1		T20	2		T41	2
all_values[4]	auto[0]	auto[0]	44345	1			T2	28		T3	2		T4	475
all_values[4]	auto[0]	auto[1]	350	1			T12	4		T20	3		T65	2
all_values[4]	auto[1]	auto[0]	38671	1			T1	3		T2	9		T4	299
all_values[4]	auto[1]	auto[1]	220	1			T12	1		T14	6		T15	2
all_values[5]	auto[0]	auto[0]	43820	1			T1	3		T2	28		T3	2
all_values[5]	auto[0]	auto[1]	149	1			T28	4		T65	2		T30	3
all_values[5]	auto[1]	auto[0]	39464	1			T2	9		T4	647		T6	2
all_values[5]	auto[1]	auto[1]	153	1			T28	1		T30	1		T31	1
all_values[6]	auto[0]	auto[0]	39844	1			T1	3		T2	11		T3	2
all_values[6]	auto[0]	auto[1]	179	1			T15	1		T28	5		T65	1
all_values[6]	auto[1]	auto[0]	43428	1			T2	26		T4	333		T5	1
all_values[6]	auto[1]	auto[1]	135	1			T15	3		T65	3		T30	1
all_values[7]	auto[0]	auto[0]	43804	1			T1	3		T2	19		T3	2
all_values[7]	auto[0]	auto[1]	257	1			T4	5		T20	2		T15	1
all_values[7]	auto[1]	auto[0]	39294	1			T2	18		T4	297		T6	21
all_values[7]	auto[1]	auto[1]	231	1			T12	1		T20	1		T14	2
all_values[8]	auto[0]	auto[0]	26567	1			T4	315		T8	4		T9	113
all_values[8]	auto[0]	auto[1]	13904	1			T1	3		T2	2		T3	2
all_values[8]	auto[1]	auto[0]	29678	1			T2	25		T4	391		T8	2
all_values[8]	auto[1]	auto[1]	13437	1			T2	10		T4	14		T5	1