Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1808	1			T4	3		T5	18		T7	15
auto[BaudRate115200]	1459	1			T1	1		T4	2		T9	3
auto[BaudRate230400]	1522	1			T1	2		T4	5		T6	2
auto[BaudRate128Kbps]	1431	1			T4	2		T6	2		T9	3
auto[BaudRate256Kbps]	1748	1			T1	1		T2	10		T3	1
auto[BaudRate1Mbps]	1478	1			T1	2		T3	1		T4	5
auto[BaudRate1p5Mbps]	1049	1			T4	3		T6	1		T8	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1031	1			T1	6		T34	7		T40	3
freqs[25]	926	1			T294	2		T116	5		T252	9
freqs[48]	389	1			T6	7		T9	14		T273	2
freqs[50]	516	1			T12	3		T251	7		T16	1
freqs[100]	1024	1			T10	6		T146	7		T118	5

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	188	1			T34	2		T40	3		T95	2
auto[BaudRate9600]	freqs[25]	126	1			T294	1		T116	2		T97	1
auto[BaudRate9600]	freqs[48]	63	1			T9	2		T87	7		T254	9
auto[BaudRate9600]	freqs[50]	109	1			T251	2		T303	1		T213	1
auto[BaudRate9600]	freqs[100]	137	1			T10	1		T118	2		T117	1
auto[BaudRate115200]	freqs[24]	143	1			T1	1		T34	2		T28	4
auto[BaudRate115200]	freqs[25]	140	1			T294	1		T252	2		T96	1
auto[BaudRate115200]	freqs[48]	54	1			T9	3		T87	3		T302	2
auto[BaudRate115200]	freqs[50]	59	1			T12	1		T251	2		T303	2
auto[BaudRate115200]	freqs[100]	143	1			T10	1		T146	1		T333	1
auto[BaudRate230400]	freqs[24]	131	1			T1	2		T28	1		T95	2
auto[BaudRate230400]	freqs[25]	141	1			T252	1		T96	1		T97	3
auto[BaudRate230400]	freqs[48]	53	1			T6	2		T9	3		T87	3
auto[BaudRate230400]	freqs[50]	44	1			T12	2		T123	1		T213	1
auto[BaudRate230400]	freqs[100]	147	1			T10	1		T146	1		T117	2
auto[BaudRate128Kbps]	freqs[24]	146	1			T34	1		T28	2		T95	1
auto[BaudRate128Kbps]	freqs[25]	115	1			T97	1		T280	2		T193	1
auto[BaudRate128Kbps]	freqs[48]	46	1			T6	2		T9	3		T87	4
auto[BaudRate128Kbps]	freqs[50]	64	1			T16	1		T123	2		T303	1
auto[BaudRate128Kbps]	freqs[100]	142	1			T10	1		T118	1		T117	2
auto[BaudRate256Kbps]	freqs[24]	152	1			T1	1		T34	1		T28	4
auto[BaudRate256Kbps]	freqs[25]	151	1			T116	1		T252	4		T97	1
auto[BaudRate256Kbps]	freqs[48]	43	1			T9	2		T273	1		T87	1
auto[BaudRate256Kbps]	freqs[50]	75	1			T123	2		T303	2		T353	1
auto[BaudRate256Kbps]	freqs[100]	157	1			T146	1		T118	1		T117	2
auto[BaudRate1Mbps]	freqs[24]	190	1			T1	2		T34	1		T28	3
auto[BaudRate1Mbps]	freqs[25]	168	1			T116	2		T252	2		T349	2
auto[BaudRate1Mbps]	freqs[48]	57	1			T6	2		T9	1		T341	1
auto[BaudRate1Mbps]	freqs[50]	94	1			T251	1		T123	1		T303	2
auto[BaudRate1Mbps]	freqs[100]	148	1			T10	1		T146	1		T333	1
auto[BaudRate1p5Mbps]	freqs[25]	85	1			T349	1		T193	2		T321	2
auto[BaudRate1p5Mbps]	freqs[48]	73	1			T6	1		T273	1		T87	9
auto[BaudRate1p5Mbps]	freqs[50]	71	1			T251	2		T123	1		T213	2
auto[BaudRate1p5Mbps]	freqs[100]	150	1			T10	1		T146	3		T118	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded