Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	8	122	93.85

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	8	122	93.85	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	23496784	1			T1	11		T2	62184		T4	204600
all_levels[1]	155692	1			T2	3436		T4	1839		T9	1
all_levels[2]	2148	1			T4	1		T10	3		T13	1
all_levels[3]	848	1			T4	1		T10	3		T13	1
all_levels[4]	602	1			T1	3		T10	3		T13	2
all_levels[5]	468	1			T1	1		T10	1		T13	1
all_levels[6]	351	1			T4	1		T8	1		T13	2
all_levels[7]	320	1			T8	3		T13	2		T37	1
all_levels[8]	233	1			T8	1		T13	1		T34	1
all_levels[9]	214	1			T6	1		T8	1		T13	1
all_levels[10]	164	1			T4	1		T13	1		T42	1
all_levels[11]	180	1			T13	4		T39	2		T106	2
all_levels[12]	156	1			T10	1		T13	1		T34	1
all_levels[13]	123	1			T37	1		T39	1		T107	1
all_levels[14]	103	1			T10	1		T97	1		T108	1
all_levels[15]	116	1			T4	1		T6	1		T13	1
all_levels[16]	84	1			T8	1		T13	1		T109	1
all_levels[17]	84	1			T8	1		T110	1		T98	1
all_levels[18]	76	1			T95	1		T111	1		T112	1
all_levels[19]	59	1			T113	1		T114	1		T115	1
all_levels[20]	60	1			T8	1		T10	1		T116	2
all_levels[21]	65	1			T116	1		T117	1		T97	1
all_levels[22]	49	1			T1	1		T4	1		T116	1
all_levels[23]	53	1			T1	1		T116	1		T31	2
all_levels[24]	53	1			T118	1		T119	1		T120	11
all_levels[25]	43	1			T98	1		T121	2		T122	1
all_levels[26]	38	1			T116	1		T109	1		T123	2
all_levels[27]	29	1			T1	1		T41	1		T118	1
all_levels[28]	41	1			T6	2		T65	1		T95	1
all_levels[29]	34	1			T33	1		T117	1		T124	2
all_levels[30]	50	1			T117	1		T125	1		T126	1
all_levels[31]	34	1			T116	1		T109	1		T93	1
all_levels[32]	26	1			T116	1		T113	2		T110	2
all_levels[33]	22	1			T1	1		T27	1		T109	1
all_levels[34]	21	1			T10	1		T127	1		T115	2
all_levels[35]	13	1			T116	1		T65	1		T128	1
all_levels[36]	14	1			T13	1		T129	1		T130	1
all_levels[37]	12	1			T110	1		T131	1		T132	2
all_levels[38]	19	1			T116	1		T133	1		T134	1
all_levels[39]	14	1			T133	1		T135	1		T136	2
all_levels[40]	17	1			T137	1		T121	1		T138	1
all_levels[41]	13	1			T113	1		T139	1		T140	2
all_levels[42]	24	1			T141	1		T142	2		T143	1
all_levels[43]	23	1			T126	1		T144	1		T145	2
all_levels[44]	21	1			T113	1		T146	1		T147	1
all_levels[45]	10	1			T148	1		T149	1		T150	1
all_levels[46]	11	1			T8	1		T151	1		T152	1
all_levels[47]	15	1			T6	1		T153	1		T149	1
all_levels[48]	9	1			T127	1		T133	1		T154	1
all_levels[49]	10	1			T155	1		T133	1		T141	1
all_levels[50]	13	1			T156	1		T157	1		T158	1
all_levels[51]	9	1			T112	1		T154	1		T159	1
all_levels[52]	7	1			T149	2		T160	1		T161	1
all_levels[53]	10	1			T162	2		T163	1		T164	2
all_levels[54]	14	1			T8	1		T41	1		T119	2
all_levels[55]	12	1			T165	1		T166	2		T167	1
all_levels[56]	17	1			T108	2		T154	1		T168	1
all_levels[57]	7	1			T115	3		T169	1		T170	2
all_levels[58]	9	1			T144	1		T171	2		T172	1
all_levels[59]	10	1			T173	2		T167	1		T147	2
all_levels[60]	7	1			T174	1		T166	1		T175	1
all_levels[61]	9	1			T126	1		T176	1		T138	1
all_levels[62]	6	1			T138	1		T160	2		T177	1
all_levels[63]	6	1			T178	1		T179	1		T180	1
all_levels[64]	92	1			T6	1		T13	1		T41	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23656037

1

T1

15

T2

65620

T4

206445

auto[1]

3839

1

T1

4

T5

1

T7

1

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	8	122	93.85	8

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[37] , all_levels[38]]	[auto[1]]	--	--	2
[all_levels[45]]	[auto[1]]	0	1	1
[all_levels[48]]	[auto[1]]	0	1	1
[all_levels[51]]	[auto[1]]	0	1	1
[all_levels[60]]	[auto[1]]	0	1	1
[all_levels[62] , all_levels[63]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	23493363	1			T1	9		T2	62184		T4	204600
all_levels[0]	auto[1]	3421	1			T1	2		T5	1		T7	1
all_levels[1]	auto[0]	155628	1			T2	3436		T4	1839		T9	1
all_levels[1]	auto[1]	64	1			T165	1		T95	1		T118	3
all_levels[2]	auto[0]	2121	1			T4	1		T10	3		T13	1
all_levels[2]	auto[1]	27	1			T37	1		T39	2		T137	1
all_levels[3]	auto[0]	826	1			T4	1		T10	3		T13	1
all_levels[3]	auto[1]	22	1			T36	1		T181	1		T113	2
all_levels[4]	auto[0]	583	1			T1	1		T10	2		T13	2
all_levels[4]	auto[1]	19	1			T1	2		T10	1		T37	1
all_levels[5]	auto[0]	451	1			T1	1		T10	1		T13	1
all_levels[5]	auto[1]	17	1			T108	2		T182	1		T115	1
all_levels[6]	auto[0]	338	1			T4	1		T8	1		T13	2
all_levels[6]	auto[1]	13	1			T167	1		T164	1		T183	1
all_levels[7]	auto[0]	296	1			T8	2		T13	2		T37	1
all_levels[7]	auto[1]	24	1			T8	1		T184	1		T185	3
all_levels[8]	auto[0]	221	1			T8	1		T13	1		T34	1
all_levels[8]	auto[1]	12	1			T109	1		T186	1		T153	1
all_levels[9]	auto[0]	201	1			T6	1		T8	1		T13	1
all_levels[9]	auto[1]	13	1			T112	1		T187	1		T188	1
all_levels[10]	auto[0]	158	1			T4	1		T13	1		T42	1
all_levels[10]	auto[1]	6	1			T110	1		T142	1		T189	2
all_levels[11]	auto[0]	165	1			T13	4		T39	2		T106	2
all_levels[11]	auto[1]	15	1			T137	1		T190	1		T191	2
all_levels[12]	auto[0]	141	1			T10	1		T13	1		T34	1
all_levels[12]	auto[1]	15	1			T37	2		T192	1		T173	1
all_levels[13]	auto[0]	118	1			T37	1		T39	1		T107	1
all_levels[13]	auto[1]	5	1			T112	1		T193	1		T194	1
all_levels[14]	auto[0]	97	1			T10	1		T97	1		T108	1
all_levels[14]	auto[1]	6	1			T162	1		T195	3		T196	1
all_levels[15]	auto[0]	103	1			T4	1		T6	1		T13	1
all_levels[15]	auto[1]	13	1			T114	2		T197	1		T82	1
all_levels[16]	auto[0]	69	1			T8	1		T13	1		T109	1
all_levels[16]	auto[1]	15	1			T198	1		T199	1		T200	1
all_levels[17]	auto[0]	81	1			T8	1		T110	1		T98	1
all_levels[17]	auto[1]	3	1			T201	1		T168	1		T202	1
all_levels[18]	auto[0]	72	1			T95	1		T111	1		T112	1
all_levels[18]	auto[1]	4	1			T203	1		T204	2		T205	1
all_levels[19]	auto[0]	52	1			T113	1		T114	1		T115	1
all_levels[19]	auto[1]	7	1			T206	1		T207	1		T208	2
all_levels[20]	auto[0]	52	1			T8	1		T10	1		T116	2
all_levels[20]	auto[1]	8	1			T209	1		T210	5		T204	1
all_levels[21]	auto[0]	58	1			T116	1		T117	1		T97	1
all_levels[21]	auto[1]	7	1			T98	1		T211	1		T212	1
all_levels[22]	auto[0]	45	1			T1	1		T4	1		T116	1
all_levels[22]	auto[1]	4	1			T213	1		T206	1		T214	1
all_levels[23]	auto[0]	51	1			T1	1		T116	1		T31	2
all_levels[23]	auto[1]	2	1			T215	1		T216	1		-	-
all_levels[24]	auto[0]	52	1			T118	1		T119	1		T120	10
all_levels[24]	auto[1]	1	1			T120	1		-	-		-	-
all_levels[25]	auto[0]	40	1			T98	1		T121	1		T122	1
all_levels[25]	auto[1]	3	1			T121	1		T158	1		T217	1
all_levels[26]	auto[0]	34	1			T116	1		T109	1		T123	1
all_levels[26]	auto[1]	4	1			T123	1		T118	1		T218	2
all_levels[27]	auto[0]	28	1			T1	1		T41	1		T118	1
all_levels[27]	auto[1]	1	1			T219	1		-	-		-	-
all_levels[28]	auto[0]	39	1			T6	2		T65	1		T95	1
all_levels[28]	auto[1]	2	1			T220	1		T221	1		-	-
all_levels[29]	auto[0]	28	1			T33	1		T117	1		T124	1
all_levels[29]	auto[1]	6	1			T124	1		T194	1		T222	2
all_levels[30]	auto[0]	44	1			T117	1		T125	1		T126	1
all_levels[30]	auto[1]	6	1			T223	1		T224	3		T225	2
all_levels[31]	auto[0]	28	1			T116	1		T109	1		T93	1
all_levels[31]	auto[1]	6	1			T138	2		T101	3		T226	1
all_levels[32]	auto[0]	23	1			T116	1		T113	1		T110	1
all_levels[32]	auto[1]	3	1			T113	1		T110	1		T227	1
all_levels[33]	auto[0]	20	1			T1	1		T27	1		T109	1
all_levels[33]	auto[1]	2	1			T156	1		T228	1		-	-
all_levels[34]	auto[0]	19	1			T10	1		T127	1		T115	1
all_levels[34]	auto[1]	2	1			T115	1		T229	1		-	-
all_levels[35]	auto[0]	12	1			T116	1		T65	1		T128	1
all_levels[35]	auto[1]	1	1			T230	1		-	-		-	-
all_levels[36]	auto[0]	13	1			T13	1		T129	1		T130	1
all_levels[36]	auto[1]	1	1			T231	1		-	-		-	-
all_levels[37]	auto[0]	12	1			T110	1		T131	1		T132	2
all_levels[38]	auto[0]	19	1			T116	1		T133	1		T134	1
all_levels[39]	auto[0]	11	1			T133	1		T135	1		T136	2
all_levels[39]	auto[1]	3	1			T232	1		T233	2		-	-
all_levels[40]	auto[0]	14	1			T137	1		T121	1		T138	1
all_levels[40]	auto[1]	3	1			T201	2		T234	1		-	-
all_levels[41]	auto[0]	10	1			T113	1		T139	1		T140	1
all_levels[41]	auto[1]	3	1			T140	1		T235	2		-	-
all_levels[42]	auto[0]	21	1			T141	1		T142	1		T143	1
all_levels[42]	auto[1]	3	1			T142	1		T236	1		T237	1
all_levels[43]	auto[0]	21	1			T126	1		T144	1		T145	1
all_levels[43]	auto[1]	2	1			T145	1		T238	1		-	-
all_levels[44]	auto[0]	18	1			T113	1		T146	1		T147	1
all_levels[44]	auto[1]	3	1			T229	1		T217	2		-	-
all_levels[45]	auto[0]	10	1			T148	1		T149	1		T150	1
all_levels[46]	auto[0]	9	1			T8	1		T151	1		T152	1
all_levels[46]	auto[1]	2	1			T205	2		-	-		-	-
all_levels[47]	auto[0]	10	1			T6	1		T153	1		T149	1
all_levels[47]	auto[1]	5	1			T239	1		T240	4		-	-
all_levels[48]	auto[0]	9	1			T127	1		T133	1		T154	1
all_levels[49]	auto[0]	9	1			T155	1		T133	1		T141	1
all_levels[49]	auto[1]	1	1			T241	1		-	-		-	-
all_levels[50]	auto[0]	12	1			T156	1		T157	1		T158	1
all_levels[50]	auto[1]	1	1			T242	1		-	-		-	-
all_levels[51]	auto[0]	9	1			T112	1		T154	1		T159	1
all_levels[52]	auto[0]	6	1			T149	2		T160	1		T161	1
all_levels[52]	auto[1]	1	1			T243	1		-	-		-	-
all_levels[53]	auto[0]	7	1			T162	1		T163	1		T164	1
all_levels[53]	auto[1]	3	1			T162	1		T164	1		T244	1
all_levels[54]	auto[0]	13	1			T8	1		T41	1		T119	1
all_levels[54]	auto[1]	1	1			T119	1		-	-		-	-
all_levels[55]	auto[0]	10	1			T165	1		T166	2		T167	1
all_levels[55]	auto[1]	2	1			T228	1		T245	1		-	-
all_levels[56]	auto[0]	13	1			T108	1		T154	1		T168	1
all_levels[56]	auto[1]	4	1			T108	1		T246	1		T247	2
all_levels[57]	auto[0]	4	1			T115	1		T169	1		T170	1
all_levels[57]	auto[1]	3	1			T115	2		T170	1		-	-
all_levels[58]	auto[0]	7	1			T144	1		T171	1		T172	1
all_levels[58]	auto[1]	2	1			T171	1		T248	1		-	-
all_levels[59]	auto[0]	8	1			T173	1		T167	1		T147	1
all_levels[59]	auto[1]	2	1			T173	1		T147	1		-	-
all_levels[60]	auto[0]	7	1			T174	1		T166	1		T175	1
all_levels[61]	auto[0]	7	1			T126	1		T176	1		T138	1
all_levels[61]	auto[1]	2	1			T168	2		-	-		-	-
all_levels[62]	auto[0]	6	1			T138	1		T160	2		T177	1
all_levels[63]	auto[0]	6	1			T178	1		T179	1		T180	1
all_levels[64]	auto[0]	79	1			T6	1		T13	1		T41	1
all_levels[64]	auto[1]	13	1			T141	1		T249	2		T250	1