Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	83586	1			T1	3		T2	37		T3	2
all_pins[1]	83586	1			T1	3		T2	37		T3	2
all_pins[2]	83586	1			T1	3		T2	37		T3	2
all_pins[3]	83586	1			T1	3		T2	37		T3	2
all_pins[4]	83586	1			T1	3		T2	37		T3	2
all_pins[5]	83586	1			T1	3		T2	37		T3	2
all_pins[6]	83586	1			T1	3		T2	37		T3	2
all_pins[7]	83586	1			T1	3		T2	37		T3	2
all_pins[8]	83586	1			T1	3		T2	37		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	717243	1			T1	23		T2	306		T3	18
values[0x1]	35031	1			T1	4		T2	27		T4	66
transitions[0x0=>0x1]	28212	1			T1	4		T2	18		T4	66
transitions[0x1=>0x0]	28025	1			T1	3		T2	17		T4	66

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	67247	1			T2	27		T3	2		T4	730
all_pins[0]	values[0x1]	16339	1			T1	3		T2	10		T4	44
all_pins[0]	transitions[0x0=>0x1]	15935	1			T1	3		T2	10		T4	44
all_pins[0]	transitions[0x1=>0x0]	945	1			T35	1		T14	9		T39	3
all_pins[1]	values[0x0]	82237	1			T1	3		T2	37		T3	2
all_pins[1]	values[0x1]	1349	1			T35	1		T14	9		T39	3
all_pins[1]	transitions[0x0=>0x1]	1240	1			T35	1		T14	9		T39	3
all_pins[1]	transitions[0x1=>0x0]	2114	1			T1	1		T2	7		T4	8
all_pins[2]	values[0x0]	81363	1			T1	2		T2	30		T3	2
all_pins[2]	values[0x1]	2223	1			T1	1		T2	7		T4	8
all_pins[2]	transitions[0x0=>0x1]	2164	1			T1	1		T2	7		T4	8
all_pins[2]	transitions[0x1=>0x0]	187	1			T12	1		T41	1		T15	1
all_pins[3]	values[0x0]	83340	1			T1	3		T2	37		T3	2
all_pins[3]	values[0x1]	246	1			T12	1		T20	2		T41	2
all_pins[3]	transitions[0x0=>0x1]	217	1			T12	1		T20	2		T41	2
all_pins[3]	transitions[0x1=>0x0]	191	1			T12	1		T14	6		T15	2
all_pins[4]	values[0x0]	83366	1			T1	3		T2	37		T3	2
all_pins[4]	values[0x1]	220	1			T12	1		T14	6		T15	2
all_pins[4]	transitions[0x0=>0x1]	183	1			T12	1		T14	6		T15	2
all_pins[4]	transitions[0x1=>0x0]	140	1			T28	1		T30	1		T31	1
all_pins[5]	values[0x0]	83409	1			T1	3		T2	37		T3	2
all_pins[5]	values[0x1]	177	1			T28	1		T16	1		T30	1
all_pins[5]	transitions[0x0=>0x1]	143	1			T28	1		T16	1		T30	1
all_pins[5]	transitions[0x1=>0x0]	721	1			T6	1		T34	3		T36	3
all_pins[6]	values[0x0]	82831	1			T1	3		T2	37		T3	2
all_pins[6]	values[0x1]	755	1			T6	1		T34	3		T36	3
all_pins[6]	transitions[0x0=>0x1]	721	1			T6	1		T34	3		T36	3
all_pins[6]	transitions[0x1=>0x0]	197	1			T12	1		T20	1		T14	2
all_pins[7]	values[0x0]	83355	1			T1	3		T2	37		T3	2
all_pins[7]	values[0x1]	231	1			T12	1		T20	1		T14	2
all_pins[7]	transitions[0x0=>0x1]	126	1			T12	1		T14	2		T251	2
all_pins[7]	transitions[0x1=>0x0]	13386	1			T2	10		T4	14		T5	1
all_pins[8]	values[0x0]	70095	1			T1	3		T2	27		T3	2
all_pins[8]	values[0x1]	13491	1			T2	10		T4	14		T5	1
all_pins[8]	transitions[0x0=>0x1]	7483	1			T2	1		T4	14		T6	1
all_pins[8]	transitions[0x1=>0x0]	10144	1			T1	2		T4	44		T6	14