Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6026413	1			T1	2		T2	18778		T4	2313
all_levels[1]	817763	1			T2	50		T4	662		T8	1
all_levels[2]	291965	1			T1	1		T2	51		T4	681
all_levels[3]	152167	1			T2	52		T4	984		T9	398
all_levels[4]	694479	1			T2	53		T4	964		T6	2
all_levels[5]	225083	1			T1	1		T2	45		T4	958
all_levels[6]	153055	1			T2	48		T4	980		T6	1
all_levels[7]	199190	1			T2	46		T4	958		T6	1
all_levels[8]	170392	1			T2	49		T4	995		T9	512
all_levels[9]	143330	1			T2	53		T4	962		T9	576
all_levels[10]	143258	1			T2	66		T4	944		T6	1
all_levels[11]	217397	1			T2	46		T4	977		T6	1
all_levels[12]	423276	1			T2	36		T4	28424		T6	3
all_levels[13]	190387	1			T1	1		T2	55		T4	982
all_levels[14]	132459	1			T1	2		T2	59		T4	1123
all_levels[15]	228299	1			T2	56		T4	957		T6	2
all_levels[16]	152399	1			T2	48		T4	950		T9	144
all_levels[17]	135216	1			T1	7		T2	49		T4	950
all_levels[18]	160661	1			T2	53		T4	1265		T6	2
all_levels[19]	144355	1			T2	48		T4	1240		T11	381
all_levels[20]	353472	1			T2	54		T4	1223		T9	1
all_levels[21]	424897	1			T2	40		T4	1201		T11	383
all_levels[22]	364458	1			T2	57		T4	1236		T11	369
all_levels[23]	126472	1			T2	45		T4	1261		T11	383
all_levels[24]	144498	1			T2	58		T4	1246		T9	1
all_levels[25]	150415	1			T2	58		T4	1265		T9	1
all_levels[26]	190231	1			T2	49		T4	1245		T9	1
all_levels[27]	139347	1			T2	40		T4	1271		T11	383
all_levels[28]	458165	1			T2	53		T4	1253		T11	383
all_levels[29]	122534	1			T2	46		T4	1250		T6	2
all_levels[30]	172091	1			T2	49		T4	1278		T11	383
all_levels[31]	610477	1			T2	1200		T4	5451		T11	571
all_levels[32]	9601092	1			T1	6		T2	44130		T4	138999

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23656037

1

T1

15

T2

65620

T4

206445

auto[1]

3656

1

T1

5

T4

3

T6

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6024290	1			T1	1		T2	18778		T4	2313
all_levels[0]	auto[1]	2123	1			T1	1		T7	1		T8	2
all_levels[1]	auto[0]	817482	1			T2	50		T4	662		T8	1
all_levels[1]	auto[1]	281	1			T10	2		T285	1		T282	1
all_levels[2]	auto[0]	291925	1			T1	1		T2	51		T4	681
all_levels[2]	auto[1]	40	1			T10	1		T253	1		T94	1
all_levels[3]	auto[0]	152055	1			T2	52		T4	984		T9	398
all_levels[3]	auto[1]	112	1			T95	2		T96	1		T186	2
all_levels[4]	auto[0]	694461	1			T2	53		T4	964		T6	2
all_levels[4]	auto[1]	18	1			T34	3		T113	1		T274	1
all_levels[5]	auto[0]	225061	1			T1	1		T2	45		T4	958
all_levels[5]	auto[1]	22	1			T33	1		T94	1		T123	1
all_levels[6]	auto[0]	153028	1			T2	48		T4	980		T6	1
all_levels[6]	auto[1]	27	1			T265	1		T193	1		T115	1
all_levels[7]	auto[0]	199122	1			T2	46		T4	958		T6	1
all_levels[7]	auto[1]	68	1			T165	1		T280	8		T108	1
all_levels[8]	auto[0]	170361	1			T2	49		T4	995		T9	512
all_levels[8]	auto[1]	31	1			T37	1		T94	1		T118	1
all_levels[9]	auto[0]	143307	1			T2	53		T4	962		T9	576
all_levels[9]	auto[1]	23	1			T278	1		T285	1		T137	1
all_levels[10]	auto[0]	143243	1			T2	66		T4	944		T6	1
all_levels[10]	auto[1]	15	1			T33	1		T27	1		T153	1
all_levels[11]	auto[0]	217380	1			T2	46		T4	977		T6	1
all_levels[11]	auto[1]	17	1			T41	1		T251	1		T137	1
all_levels[12]	auto[0]	423259	1			T2	36		T4	28424		T6	3
all_levels[12]	auto[1]	17	1			T182	1		T162	2		T129	2
all_levels[13]	auto[0]	190359	1			T1	1		T2	55		T4	982
all_levels[13]	auto[1]	28	1			T190	1		T176	2		T345	2
all_levels[14]	auto[0]	132448	1			T1	2		T2	59		T4	1122
all_levels[14]	auto[1]	11	1			T4	1		T121	1		T115	1
all_levels[15]	auto[0]	228214	1			T2	56		T4	957		T6	2
all_levels[15]	auto[1]	85	1			T8	2		T137	1		T277	1
all_levels[16]	auto[0]	152378	1			T2	48		T4	950		T9	144
all_levels[16]	auto[1]	21	1			T265	1		T339	1		T209	1
all_levels[17]	auto[0]	135194	1			T1	5		T2	49		T4	950
all_levels[17]	auto[1]	22	1			T1	2		T6	1		T278	1
all_levels[18]	auto[0]	160638	1			T2	53		T4	1265		T6	2
all_levels[18]	auto[1]	23	1			T97	1		T304	1		T187	1
all_levels[19]	auto[0]	144328	1			T2	48		T4	1240		T11	381
all_levels[19]	auto[1]	27	1			T33	1		T258	1		T106	1
all_levels[20]	auto[0]	353463	1			T2	54		T4	1223		T9	1
all_levels[20]	auto[1]	9	1			T10	1		T193	1		T139	1
all_levels[21]	auto[0]	424885	1			T2	40		T4	1201		T11	383
all_levels[21]	auto[1]	12	1			T34	1		T153	1		T358	1
all_levels[22]	auto[0]	364440	1			T2	57		T4	1236		T11	369
all_levels[22]	auto[1]	18	1			T94	1		T192	1		T316	1
all_levels[23]	auto[0]	126454	1			T2	45		T4	1261		T11	383
all_levels[23]	auto[1]	18	1			T190	2		T265	2		T162	2
all_levels[24]	auto[0]	144487	1			T2	58		T4	1246		T9	1
all_levels[24]	auto[1]	11	1			T121	1		T359	1		T327	1
all_levels[25]	auto[0]	150389	1			T2	58		T4	1265		T9	1
all_levels[25]	auto[1]	26	1			T258	1		T348	1		T349	1
all_levels[26]	auto[0]	190217	1			T2	49		T4	1245		T9	1
all_levels[26]	auto[1]	14	1			T33	2		T37	3		T360	2
all_levels[27]	auto[0]	139321	1			T2	40		T4	1271		T11	383
all_levels[27]	auto[1]	26	1			T65	1		T213	1		T191	2
all_levels[28]	auto[0]	458142	1			T2	53		T4	1253		T11	383
all_levels[28]	auto[1]	23	1			T181	3		T361	1		T173	1
all_levels[29]	auto[0]	122520	1			T2	46		T4	1250		T6	2
all_levels[29]	auto[1]	14	1			T33	2		T181	1		T95	2
all_levels[30]	auto[0]	172084	1			T2	49		T4	1278		T11	383
all_levels[30]	auto[1]	7	1			T126	1		T362	1		T363	1
all_levels[31]	auto[0]	610449	1			T2	1200		T4	5451		T11	571
all_levels[31]	auto[1]	28	1			T184	1		T120	2		T308	1
all_levels[32]	auto[0]	9600653	1			T1	4		T2	44130		T4	138997
all_levels[32]	auto[1]	439	1			T1	2		T4	2		T8	2