Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	648	1			T20	4		T15	7		T28	7
all_values[1]	648	1			T20	4		T15	7		T28	7
all_values[2]	648	1			T20	4		T15	7		T28	7
all_values[3]	648	1			T20	4		T15	7		T28	7
all_values[4]	648	1			T20	4		T15	7		T28	7
all_values[5]	648	1			T20	4		T15	7		T28	7
all_values[6]	648	1			T20	4		T15	7		T28	7
all_values[7]	648	1			T20	4		T15	7		T28	7
all_values[8]	648	1			T20	4		T15	7		T28	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3232

1

T20

18

T15

31

T28

36

auto[1]

2600

1

T20

18

T15

32

T28

27

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1880

1

T20

12

T15

23

T28

26

auto[1]

3952

1

T20

24

T15

40

T28

37

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3416

1

T20

22

T15

35

T28

39

auto[1]

2416

1

T20

14

T15

28

T28

24

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	203	1			T15	1		T28	3		T65	2
all_values[0]	auto[0]	auto[1]	auto[1]	168	1			T20	3		T15	3		T28	2
all_values[0]	auto[1]	auto[0]	auto[1]	158	1			T15	2		T65	1		T30	3
all_values[0]	auto[1]	auto[1]	auto[1]	119	1			T20	1		T15	1		T28	2
all_values[1]	auto[0]	auto[0]	auto[0]	203	1			T20	1		T15	3		T28	4
all_values[1]	auto[0]	auto[1]	auto[0]	176	1			T20	1		T28	1		T65	2
all_values[1]	auto[1]	auto[0]	auto[1]	156	1			T20	1		T15	2		T28	2
all_values[1]	auto[1]	auto[1]	auto[1]	113	1			T20	1		T15	2		T30	4
all_values[2]	auto[0]	auto[0]	auto[0]	128	1			T20	1		T28	2		T65	1
all_values[2]	auto[0]	auto[0]	auto[1]	55	1			T65	1		T30	4		T32	1
all_values[2]	auto[0]	auto[1]	auto[0]	112	1			T15	2		T28	2		T65	1
all_values[2]	auto[0]	auto[1]	auto[1]	74	1			T20	1		T15	1		T28	1
all_values[2]	auto[1]	auto[0]	auto[1]	165	1			T20	1		T15	2		T28	1
all_values[2]	auto[1]	auto[1]	auto[1]	114	1			T20	1		T15	2		T28	1
all_values[3]	auto[0]	auto[0]	auto[0]	135	1			T20	1		T15	1		T28	1
all_values[3]	auto[0]	auto[0]	auto[1]	65	1			T65	2		T31	1		T32	3
all_values[3]	auto[0]	auto[1]	auto[0]	118	1			T15	3		T28	3		T31	1
all_values[3]	auto[0]	auto[1]	auto[1]	57	1			T20	1		T30	1		T31	1
all_values[3]	auto[1]	auto[0]	auto[1]	151	1			T20	1		T28	1		T65	1
all_values[3]	auto[1]	auto[1]	auto[1]	122	1			T20	1		T15	3		T28	2
all_values[4]	auto[0]	auto[0]	auto[0]	148	1			T15	3		T28	5		T30	2
all_values[4]	auto[0]	auto[0]	auto[1]	78	1			T20	2		T30	2		T32	1
all_values[4]	auto[0]	auto[1]	auto[0]	121	1			T15	1		T28	1		T30	5
all_values[4]	auto[0]	auto[1]	auto[1]	68	1			T15	1		T65	1		T31	2
all_values[4]	auto[1]	auto[0]	auto[1]	133	1			T20	2		T15	1		T65	2
all_values[4]	auto[1]	auto[1]	auto[1]	100	1			T15	1		T28	1		T65	1
all_values[5]	auto[0]	auto[0]	auto[0]	136	1			T20	2		T15	2		T65	2
all_values[5]	auto[0]	auto[0]	auto[1]	60	1			T28	1		T30	1		T32	1
all_values[5]	auto[0]	auto[1]	auto[0]	103	1			T20	2		T15	3		T28	1
all_values[5]	auto[0]	auto[1]	auto[1]	75	1			T30	1		T105	3		T89	1
all_values[5]	auto[1]	auto[0]	auto[1]	165	1			T28	4		T65	2		T30	3
all_values[5]	auto[1]	auto[1]	auto[1]	109	1			T15	2		T28	1		T30	2
all_values[6]	auto[0]	auto[0]	auto[0]	132	1			T20	4		T15	1		T28	1
all_values[6]	auto[0]	auto[0]	auto[1]	71	1			T15	1		T28	1		T30	1
all_values[6]	auto[0]	auto[1]	auto[0]	100	1			T15	1		T30	6		T32	4
all_values[6]	auto[0]	auto[1]	auto[1]	60	1			T15	1		T65	2		T31	1
all_values[6]	auto[1]	auto[0]	auto[1]	168	1			T15	2		T28	5		T65	1
all_values[6]	auto[1]	auto[1]	auto[1]	117	1			T15	1		T65	1		T31	1
all_values[7]	auto[0]	auto[0]	auto[0]	152	1			T15	1		T28	2		T30	7
all_values[7]	auto[0]	auto[0]	auto[1]	63	1			T15	1		T28	1		T65	1
all_values[7]	auto[0]	auto[1]	auto[0]	116	1			T15	2		T28	3		T65	1
all_values[7]	auto[0]	auto[1]	auto[1]	55	1			T20	2		T32	2		T86	1
all_values[7]	auto[1]	auto[0]	auto[1]	150	1			T20	2		T15	3		T65	2
all_values[7]	auto[1]	auto[1]	auto[1]	112	1			T28	1		T31	3		T86	1
all_values[8]	auto[0]	auto[0]	auto[1]	216	1			T15	2		T28	1		T65	2
all_values[8]	auto[0]	auto[1]	auto[1]	168	1			T20	1		T15	1		T28	3
all_values[8]	auto[1]	auto[0]	auto[1]	141	1			T15	3		T28	1		T65	1
all_values[8]	auto[1]	auto[1]	auto[1]	123	1			T20	3		T15	1		T28	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal