Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.59


Total test records in report: 1319
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T1258 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.823483786 Aug 13 05:36:55 PM PDT 24 Aug 13 05:36:56 PM PDT 24 49004883 ps
T1259 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1732575056 Aug 13 05:37:03 PM PDT 24 Aug 13 05:37:04 PM PDT 24 50793107 ps
T1260 /workspace/coverage/cover_reg_top/7.uart_csr_rw.1641615650 Aug 13 05:36:56 PM PDT 24 Aug 13 05:36:57 PM PDT 24 14437872 ps
T1261 /workspace/coverage/cover_reg_top/0.uart_tl_errors.3646633262 Aug 13 05:37:02 PM PDT 24 Aug 13 05:37:04 PM PDT 24 100364329 ps
T1262 /workspace/coverage/cover_reg_top/6.uart_tl_errors.1540450490 Aug 13 05:36:55 PM PDT 24 Aug 13 05:36:57 PM PDT 24 223066534 ps
T1263 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.515282367 Aug 13 05:37:16 PM PDT 24 Aug 13 05:37:17 PM PDT 24 130984071 ps
T1264 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.668324860 Aug 13 05:36:56 PM PDT 24 Aug 13 05:36:57 PM PDT 24 95036209 ps
T1265 /workspace/coverage/cover_reg_top/48.uart_intr_test.533799188 Aug 13 05:37:39 PM PDT 24 Aug 13 05:37:39 PM PDT 24 62558068 ps
T1266 /workspace/coverage/cover_reg_top/11.uart_csr_rw.1917527697 Aug 13 05:37:17 PM PDT 24 Aug 13 05:37:18 PM PDT 24 17332771 ps
T1267 /workspace/coverage/cover_reg_top/42.uart_intr_test.59932645 Aug 13 05:37:27 PM PDT 24 Aug 13 05:37:28 PM PDT 24 12806561 ps
T1268 /workspace/coverage/cover_reg_top/3.uart_intr_test.3931494621 Aug 13 05:36:53 PM PDT 24 Aug 13 05:36:59 PM PDT 24 15595832 ps
T1269 /workspace/coverage/cover_reg_top/12.uart_intr_test.2019404122 Aug 13 05:36:59 PM PDT 24 Aug 13 05:36:59 PM PDT 24 11509592 ps
T1270 /workspace/coverage/cover_reg_top/32.uart_intr_test.1783818321 Aug 13 05:37:21 PM PDT 24 Aug 13 05:37:22 PM PDT 24 14450373 ps
T1271 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2502987553 Aug 13 05:37:05 PM PDT 24 Aug 13 05:37:06 PM PDT 24 50055377 ps
T1272 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1080778724 Aug 13 05:37:26 PM PDT 24 Aug 13 05:37:27 PM PDT 24 32200937 ps
T1273 /workspace/coverage/cover_reg_top/49.uart_intr_test.1412787435 Aug 13 05:37:25 PM PDT 24 Aug 13 05:37:25 PM PDT 24 14428935 ps
T47 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.4117294862 Aug 13 05:36:54 PM PDT 24 Aug 13 05:36:55 PM PDT 24 61802935 ps
T1274 /workspace/coverage/cover_reg_top/5.uart_intr_test.283288172 Aug 13 05:37:02 PM PDT 24 Aug 13 05:37:03 PM PDT 24 14457385 ps
T1275 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.73295973 Aug 13 05:37:21 PM PDT 24 Aug 13 05:37:22 PM PDT 24 27180952 ps
T48 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.4007809601 Aug 13 05:37:04 PM PDT 24 Aug 13 05:37:05 PM PDT 24 32461297 ps
T1276 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.934598872 Aug 13 05:37:29 PM PDT 24 Aug 13 05:37:31 PM PDT 24 86453538 ps
T1277 /workspace/coverage/cover_reg_top/43.uart_intr_test.2475195290 Aug 13 05:37:32 PM PDT 24 Aug 13 05:37:33 PM PDT 24 183028497 ps
T1278 /workspace/coverage/cover_reg_top/14.uart_intr_test.4139570100 Aug 13 05:37:08 PM PDT 24 Aug 13 05:37:09 PM PDT 24 29029672 ps
T1279 /workspace/coverage/cover_reg_top/7.uart_tl_errors.2207913086 Aug 13 05:37:07 PM PDT 24 Aug 13 05:37:09 PM PDT 24 82613263 ps
T1280 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3160104786 Aug 13 05:37:20 PM PDT 24 Aug 13 05:37:21 PM PDT 24 30782554 ps
T1281 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.505937986 Aug 13 05:36:56 PM PDT 24 Aug 13 05:36:56 PM PDT 24 14953652 ps
T1282 /workspace/coverage/cover_reg_top/8.uart_intr_test.1966460505 Aug 13 05:37:02 PM PDT 24 Aug 13 05:37:03 PM PDT 24 32186016 ps
T1283 /workspace/coverage/cover_reg_top/4.uart_tl_errors.1559685269 Aug 13 05:36:58 PM PDT 24 Aug 13 05:37:00 PM PDT 24 259306141 ps
T1284 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1333289355 Aug 13 05:36:56 PM PDT 24 Aug 13 05:36:57 PM PDT 24 30803305 ps
T1285 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.908394762 Aug 13 05:37:08 PM PDT 24 Aug 13 05:37:08 PM PDT 24 68975587 ps
T1286 /workspace/coverage/cover_reg_top/45.uart_intr_test.371174205 Aug 13 05:37:28 PM PDT 24 Aug 13 05:37:29 PM PDT 24 43201718 ps
T1287 /workspace/coverage/cover_reg_top/24.uart_intr_test.4154793251 Aug 13 05:37:17 PM PDT 24 Aug 13 05:37:18 PM PDT 24 40857589 ps
T1288 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3288029819 Aug 13 05:37:10 PM PDT 24 Aug 13 05:37:11 PM PDT 24 23740052 ps
T1289 /workspace/coverage/cover_reg_top/44.uart_intr_test.3054482884 Aug 13 05:37:11 PM PDT 24 Aug 13 05:37:12 PM PDT 24 32756548 ps
T49 /workspace/coverage/cover_reg_top/17.uart_csr_rw.1419833383 Aug 13 05:37:12 PM PDT 24 Aug 13 05:37:18 PM PDT 24 26788557 ps
T1290 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3431068565 Aug 13 05:37:05 PM PDT 24 Aug 13 05:37:06 PM PDT 24 22507542 ps
T1291 /workspace/coverage/cover_reg_top/22.uart_intr_test.169222944 Aug 13 05:37:26 PM PDT 24 Aug 13 05:37:27 PM PDT 24 243839454 ps
T1292 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2961902680 Aug 13 05:37:11 PM PDT 24 Aug 13 05:37:12 PM PDT 24 85527769 ps
T50 /workspace/coverage/cover_reg_top/15.uart_csr_rw.2454484000 Aug 13 05:37:16 PM PDT 24 Aug 13 05:37:17 PM PDT 24 17426686 ps
T1293 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1996798311 Aug 13 05:37:11 PM PDT 24 Aug 13 05:37:12 PM PDT 24 225741243 ps
T1294 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.366303516 Aug 13 05:36:51 PM PDT 24 Aug 13 05:36:52 PM PDT 24 210687789 ps
T1295 /workspace/coverage/cover_reg_top/13.uart_csr_rw.2461256363 Aug 13 05:37:17 PM PDT 24 Aug 13 05:37:17 PM PDT 24 51558354 ps
T51 /workspace/coverage/cover_reg_top/3.uart_csr_rw.748528694 Aug 13 05:36:48 PM PDT 24 Aug 13 05:36:48 PM PDT 24 41900246 ps
T1296 /workspace/coverage/cover_reg_top/3.uart_tl_errors.2265483698 Aug 13 05:36:49 PM PDT 24 Aug 13 05:36:51 PM PDT 24 77165158 ps
T1297 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3083482650 Aug 13 05:37:07 PM PDT 24 Aug 13 05:37:08 PM PDT 24 15963869 ps
T1298 /workspace/coverage/cover_reg_top/1.uart_intr_test.2132217730 Aug 13 05:36:47 PM PDT 24 Aug 13 05:36:48 PM PDT 24 226184274 ps
T1299 /workspace/coverage/cover_reg_top/46.uart_intr_test.891441556 Aug 13 05:37:37 PM PDT 24 Aug 13 05:37:38 PM PDT 24 21734501 ps
T1300 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3661077522 Aug 13 05:36:54 PM PDT 24 Aug 13 05:36:57 PM PDT 24 60581821 ps
T1301 /workspace/coverage/cover_reg_top/37.uart_intr_test.97689337 Aug 13 05:37:35 PM PDT 24 Aug 13 05:37:35 PM PDT 24 23931543 ps
T1302 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.163763005 Aug 13 05:37:06 PM PDT 24 Aug 13 05:37:07 PM PDT 24 36431747 ps
T1303 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.258243715 Aug 13 05:37:09 PM PDT 24 Aug 13 05:37:10 PM PDT 24 38302304 ps
T1304 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1450610698 Aug 13 05:36:55 PM PDT 24 Aug 13 05:36:55 PM PDT 24 27203583 ps
T1305 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.514468783 Aug 13 05:36:42 PM PDT 24 Aug 13 05:36:43 PM PDT 24 84186458 ps
T1306 /workspace/coverage/cover_reg_top/2.uart_tl_errors.4054909234 Aug 13 05:36:55 PM PDT 24 Aug 13 05:36:57 PM PDT 24 398738441 ps
T1307 /workspace/coverage/cover_reg_top/1.uart_tl_errors.4081899787 Aug 13 05:36:51 PM PDT 24 Aug 13 05:36:53 PM PDT 24 1108368504 ps
T1308 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2478687995 Aug 13 05:36:47 PM PDT 24 Aug 13 05:36:48 PM PDT 24 26511062 ps
T52 /workspace/coverage/cover_reg_top/2.uart_csr_rw.1631465939 Aug 13 05:37:00 PM PDT 24 Aug 13 05:37:01 PM PDT 24 17787589 ps
T1309 /workspace/coverage/cover_reg_top/15.uart_tl_errors.2210270430 Aug 13 05:36:59 PM PDT 24 Aug 13 05:37:00 PM PDT 24 22651330 ps
T1310 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1994018029 Aug 13 05:37:03 PM PDT 24 Aug 13 05:37:04 PM PDT 24 290769274 ps
T1311 /workspace/coverage/cover_reg_top/21.uart_intr_test.1618305789 Aug 13 05:37:21 PM PDT 24 Aug 13 05:37:22 PM PDT 24 13765647 ps
T1312 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2064695441 Aug 13 05:37:28 PM PDT 24 Aug 13 05:37:29 PM PDT 24 26342827 ps
T1313 /workspace/coverage/cover_reg_top/13.uart_intr_test.1456724587 Aug 13 05:37:30 PM PDT 24 Aug 13 05:37:31 PM PDT 24 22495317 ps
T1314 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2659925875 Aug 13 05:36:53 PM PDT 24 Aug 13 05:36:54 PM PDT 24 21385761 ps
T1315 /workspace/coverage/cover_reg_top/16.uart_intr_test.4143529849 Aug 13 05:37:07 PM PDT 24 Aug 13 05:37:08 PM PDT 24 35982658 ps
T55 /workspace/coverage/cover_reg_top/16.uart_csr_rw.1728720321 Aug 13 05:37:06 PM PDT 24 Aug 13 05:37:07 PM PDT 24 48871968 ps
T1316 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4104537617 Aug 13 05:37:07 PM PDT 24 Aug 13 05:37:08 PM PDT 24 114311413 ps
T1317 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.900188985 Aug 13 05:37:08 PM PDT 24 Aug 13 05:37:09 PM PDT 24 24845977 ps
T1318 /workspace/coverage/cover_reg_top/19.uart_csr_rw.4122268447 Aug 13 05:37:11 PM PDT 24 Aug 13 05:37:12 PM PDT 24 93209644 ps
T1319 /workspace/coverage/cover_reg_top/34.uart_intr_test.4058303773 Aug 13 05:37:09 PM PDT 24 Aug 13 05:37:10 PM PDT 24 32141973 ps

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.455462446
Short name T9
Test name
Test status
Simulation time 10621664250 ps
CPU time 66.66 seconds
Started Aug 13 05:16:21 PM PDT 24
Finished Aug 13 05:17:27 PM PDT 24
Peak memory 209984 kb
Host smart-9fea3a41-8436-4936-8705-180ff969c032
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455462446 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.455462446
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_stress_all.2954994919
Short name T4
Test name
Test status
Simulation time 154838184965 ps
CPU time 545.38 seconds
Started Aug 13 05:15:32 PM PDT 24
Finished Aug 13 05:24:37 PM PDT 24
Peak memory 200980 kb
Host smart-212aeae8-3301-47fc-a521-49fe9c7bc793
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954994919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2954994919
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all.3207203141
Short name T105
Test name
Test status
Simulation time 116376416469 ps
CPU time 424.61 seconds
Started Aug 13 05:15:12 PM PDT 24
Finished Aug 13 05:22:17 PM PDT 24
Peak memory 200880 kb
Host smart-f1c43082-f781-409c-9356-315b3d8786a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207203141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3207203141
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_intr.718054611
Short name T12
Test name
Test status
Simulation time 47715982359 ps
CPU time 38.25 seconds
Started Aug 13 05:13:47 PM PDT 24
Finished Aug 13 05:14:25 PM PDT 24
Peak memory 200576 kb
Host smart-dc7944ea-695d-431b-aa2b-1e19a320abfc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718054611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.718054611
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/30.uart_stress_all.3714577317
Short name T93
Test name
Test status
Simulation time 221908958531 ps
CPU time 188.23 seconds
Started Aug 13 05:15:05 PM PDT 24
Finished Aug 13 05:18:13 PM PDT 24
Peak memory 200884 kb
Host smart-6defaece-3760-4ff8-9e21-7c3196382974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714577317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3714577317
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all.1682883119
Short name T253
Test name
Test status
Simulation time 258586495169 ps
CPU time 143.09 seconds
Started Aug 13 05:14:08 PM PDT 24
Finished Aug 13 05:16:31 PM PDT 24
Peak memory 209320 kb
Host smart-60788994-34b5-479d-88d2-9958bfd011a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682883119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1682883119
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all.2966405573
Short name T127
Test name
Test status
Simulation time 319900676959 ps
CPU time 630.98 seconds
Started Aug 13 05:14:13 PM PDT 24
Finished Aug 13 05:24:44 PM PDT 24
Peak memory 200888 kb
Host smart-91befd61-47c3-45a3-b1ef-5670176f4599
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966405573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2966405573
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.2925549311
Short name T15
Test name
Test status
Simulation time 18772444099 ps
CPU time 92.4 seconds
Started Aug 13 05:16:30 PM PDT 24
Finished Aug 13 05:18:02 PM PDT 24
Peak memory 216748 kb
Host smart-ebd2b957-7c93-42d1-9b78-5e775ae0e55f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925549311 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.2925549311
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_stress_all.4107168117
Short name T155
Test name
Test status
Simulation time 551692247291 ps
CPU time 342.3 seconds
Started Aug 13 05:16:24 PM PDT 24
Finished Aug 13 05:22:06 PM PDT 24
Peak memory 200924 kb
Host smart-7e97b945-5949-4c3d-861b-8e2375a775e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107168117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.4107168117
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all.242510836
Short name T144
Test name
Test status
Simulation time 211151505839 ps
CPU time 79.33 seconds
Started Aug 13 05:14:20 PM PDT 24
Finished Aug 13 05:15:40 PM PDT 24
Peak memory 200884 kb
Host smart-550ddbcb-06f7-4c8e-a9ec-2c601b09b043
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242510836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.242510836
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1198729359
Short name T13
Test name
Test status
Simulation time 167451638245 ps
CPU time 645.64 seconds
Started Aug 13 05:13:50 PM PDT 24
Finished Aug 13 05:24:36 PM PDT 24
Peak memory 200852 kb
Host smart-6025836e-2528-4177-a1b4-27ceec4dfc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198729359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1198729359
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.207566985
Short name T113
Test name
Test status
Simulation time 102596749333 ps
CPU time 134.87 seconds
Started Aug 13 05:16:20 PM PDT 24
Finished Aug 13 05:18:35 PM PDT 24
Peak memory 200868 kb
Host smart-1944f513-34dd-4022-a5a9-03eb76a61cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207566985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.207566985
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.329110312
Short name T69
Test name
Test status
Simulation time 261931007 ps
CPU time 1.29 seconds
Started Aug 13 05:36:59 PM PDT 24
Finished Aug 13 05:37:00 PM PDT 24
Peak memory 199320 kb
Host smart-d98dc211-d91d-4537-aa59-bd82f08a06c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329110312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.329110312
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/13.uart_alert_test.3580513501
Short name T23
Test name
Test status
Simulation time 29772828 ps
CPU time 0.54 seconds
Started Aug 13 05:14:19 PM PDT 24
Finished Aug 13 05:14:19 PM PDT 24
Peak memory 196176 kb
Host smart-950ab0ff-8c81-4cee-bd42-6df09b8a8b9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580513501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.3580513501
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.4249198192
Short name T45
Test name
Test status
Simulation time 205244534 ps
CPU time 0.8 seconds
Started Aug 13 05:37:01 PM PDT 24
Finished Aug 13 05:37:02 PM PDT 24
Peak memory 196320 kb
Host smart-034c3eab-e666-4751-a0a4-10aec86c21b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249198192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.4249198192
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/default/25.uart_stress_all.1437739174
Short name T254
Test name
Test status
Simulation time 150478963114 ps
CPU time 440.05 seconds
Started Aug 13 05:14:53 PM PDT 24
Finished Aug 13 05:22:13 PM PDT 24
Peak memory 200816 kb
Host smart-27ca0681-a3da-4704-8b55-b4ea6d0081e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437739174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1437739174
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1347784238
Short name T112
Test name
Test status
Simulation time 168699791396 ps
CPU time 222.76 seconds
Started Aug 13 05:17:09 PM PDT 24
Finished Aug 13 05:20:52 PM PDT 24
Peak memory 200844 kb
Host smart-5092f94b-8d96-49a4-8174-07d932226885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347784238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1347784238
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3529468903
Short name T268
Test name
Test status
Simulation time 596475514708 ps
CPU time 53.82 seconds
Started Aug 13 05:14:01 PM PDT 24
Finished Aug 13 05:14:55 PM PDT 24
Peak memory 200772 kb
Host smart-ac13466c-4861-4628-8fce-bcafda2db2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529468903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3529468903
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.617941260
Short name T267
Test name
Test status
Simulation time 83665532903 ps
CPU time 317.3 seconds
Started Aug 13 05:16:10 PM PDT 24
Finished Aug 13 05:21:27 PM PDT 24
Peak memory 200888 kb
Host smart-9731f06f-1f2c-4372-83bd-aacd80cfde74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=617941260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.617941260
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_fifo_full.3674654801
Short name T133
Test name
Test status
Simulation time 158550325325 ps
CPU time 405.35 seconds
Started Aug 13 05:14:01 PM PDT 24
Finished Aug 13 05:20:46 PM PDT 24
Peak memory 200920 kb
Host smart-1ef2a710-2377-43d2-a7c0-5b011774500b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674654801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3674654801
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.3680514168
Short name T87
Test name
Test status
Simulation time 11606549366 ps
CPU time 71.24 seconds
Started Aug 13 05:14:37 PM PDT 24
Finished Aug 13 05:15:48 PM PDT 24
Peak memory 216776 kb
Host smart-e567d843-e19a-4af8-9f1a-b8d05660397f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680514168 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.3680514168
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all.2833634598
Short name T107
Test name
Test status
Simulation time 251345053006 ps
CPU time 87.26 seconds
Started Aug 13 05:13:54 PM PDT 24
Finished Aug 13 05:15:21 PM PDT 24
Peak memory 209256 kb
Host smart-4e339216-2e74-4f79-afe5-4d6df54bdffc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833634598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2833634598
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1796667456
Short name T24
Test name
Test status
Simulation time 58800055 ps
CPU time 0.92 seconds
Started Aug 13 05:13:38 PM PDT 24
Finished Aug 13 05:13:39 PM PDT 24
Peak memory 218884 kb
Host smart-c75a4125-40fe-4b3f-9718-8ea096196c14
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796667456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1796667456
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.65979920
Short name T168
Test name
Test status
Simulation time 174458386588 ps
CPU time 39.7 seconds
Started Aug 13 05:16:55 PM PDT 24
Finished Aug 13 05:17:35 PM PDT 24
Peak memory 200940 kb
Host smart-6abecdd1-03b3-453e-83e8-7e5e09cddc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65979920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.65979920
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_stress_all.1031448643
Short name T337
Test name
Test status
Simulation time 285196658740 ps
CPU time 874.07 seconds
Started Aug 13 05:14:10 PM PDT 24
Finished Aug 13 05:28:44 PM PDT 24
Peak memory 200940 kb
Host smart-c4013ee5-d79a-4283-8a4f-ffd6c2f10e65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031448643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1031448643
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.133606178
Short name T259
Test name
Test status
Simulation time 154377377425 ps
CPU time 190.33 seconds
Started Aug 13 05:13:57 PM PDT 24
Finished Aug 13 05:17:08 PM PDT 24
Peak memory 200816 kb
Host smart-58dcd8eb-3309-4f1d-a6dc-96c05fc0918a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133606178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.133606178
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3254401182
Short name T145
Test name
Test status
Simulation time 133120974668 ps
CPU time 22.77 seconds
Started Aug 13 05:16:55 PM PDT 24
Finished Aug 13 05:17:18 PM PDT 24
Peak memory 200928 kb
Host smart-b887ce77-4e0f-4669-9e1d-4bcbfc3be4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254401182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3254401182
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1407264839
Short name T137
Test name
Test status
Simulation time 118914114487 ps
CPU time 42.08 seconds
Started Aug 13 05:13:55 PM PDT 24
Finished Aug 13 05:14:37 PM PDT 24
Peak memory 200896 kb
Host smart-1ea9d47d-8b3b-4ed1-857a-b65469e7b342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407264839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1407264839
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.3885127037
Short name T128
Test name
Test status
Simulation time 96698553271 ps
CPU time 35.52 seconds
Started Aug 13 05:15:04 PM PDT 24
Finished Aug 13 05:15:40 PM PDT 24
Peak memory 200940 kb
Host smart-bbd06ed1-f662-4164-aaa7-520658199efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885127037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3885127037
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3974954788
Short name T118
Test name
Test status
Simulation time 120835221727 ps
CPU time 187.09 seconds
Started Aug 13 05:16:11 PM PDT 24
Finished Aug 13 05:19:18 PM PDT 24
Peak memory 199292 kb
Host smart-507e4591-2db4-4a29-a4f6-37995ae7484a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974954788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3974954788
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.479833053
Short name T316
Test name
Test status
Simulation time 275204046814 ps
CPU time 191.76 seconds
Started Aug 13 05:17:01 PM PDT 24
Finished Aug 13 05:20:13 PM PDT 24
Peak memory 200948 kb
Host smart-2e7836c2-3b6d-46b2-a607-9a6795909d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479833053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.479833053
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3692676971
Short name T62
Test name
Test status
Simulation time 39725169 ps
CPU time 0.59 seconds
Started Aug 13 05:37:07 PM PDT 24
Finished Aug 13 05:37:08 PM PDT 24
Peak memory 195424 kb
Host smart-40b91c37-ead6-4cc3-87d8-dc5b49bd2d49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692676971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3692676971
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3262862329
Short name T123
Test name
Test status
Simulation time 33219124127 ps
CPU time 24.94 seconds
Started Aug 13 05:16:43 PM PDT 24
Finished Aug 13 05:17:08 PM PDT 24
Peak memory 200876 kb
Host smart-a1761b33-2d9d-4bbe-b00d-c3eb3af61863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262862329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3262862329
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3105838849
Short name T6
Test name
Test status
Simulation time 32982557649 ps
CPU time 30.9 seconds
Started Aug 13 05:13:46 PM PDT 24
Finished Aug 13 05:14:17 PM PDT 24
Peak memory 200940 kb
Host smart-bc16a62c-3478-4458-9abc-5e54ae92828f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105838849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3105838849
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3064546575
Short name T413
Test name
Test status
Simulation time 118826053103 ps
CPU time 273.74 seconds
Started Aug 13 05:14:08 PM PDT 24
Finished Aug 13 05:18:42 PM PDT 24
Peak memory 200824 kb
Host smart-68bce4cf-3fad-40b0-a8b6-f50f935f462a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064546575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3064546575
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3706424745
Short name T28
Test name
Test status
Simulation time 18569849470 ps
CPU time 78.25 seconds
Started Aug 13 05:16:28 PM PDT 24
Finished Aug 13 05:17:47 PM PDT 24
Peak memory 211284 kb
Host smart-c1067002-255a-4124-8734-0292df134bca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706424745 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3706424745
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.4161216690
Short name T360
Test name
Test status
Simulation time 82632369326 ps
CPU time 34.72 seconds
Started Aug 13 05:16:31 PM PDT 24
Finished Aug 13 05:17:06 PM PDT 24
Peak memory 200880 kb
Host smart-6cbb1c03-b9ea-4628-b0b8-8104502bce4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161216690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.4161216690
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_tx_rx.411800084
Short name T111
Test name
Test status
Simulation time 318021308386 ps
CPU time 34.12 seconds
Started Aug 13 05:14:12 PM PDT 24
Finished Aug 13 05:14:46 PM PDT 24
Peak memory 200860 kb
Host smart-617d647a-abcc-451e-b630-8cebc67c9361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411800084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.411800084
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3092711771
Short name T97
Test name
Test status
Simulation time 90660348337 ps
CPU time 35.98 seconds
Started Aug 13 05:16:02 PM PDT 24
Finished Aug 13 05:16:38 PM PDT 24
Peak memory 200912 kb
Host smart-1d520521-9492-420e-9d83-5dd6c37252df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092711771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3092711771
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2405931169
Short name T167
Test name
Test status
Simulation time 122735047366 ps
CPU time 84.55 seconds
Started Aug 13 05:16:45 PM PDT 24
Finished Aug 13 05:18:09 PM PDT 24
Peak memory 200956 kb
Host smart-e956a70c-0ebd-4f3a-b5d6-db22d62c0093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405931169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2405931169
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3463737804
Short name T72
Test name
Test status
Simulation time 135794624 ps
CPU time 1.33 seconds
Started Aug 13 05:36:51 PM PDT 24
Finished Aug 13 05:36:52 PM PDT 24
Peak memory 199504 kb
Host smart-5dd0796e-1f53-4182-af6e-295c56b65edd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463737804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3463737804
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3480613218
Short name T109
Test name
Test status
Simulation time 30197672656 ps
CPU time 50.18 seconds
Started Aug 13 05:14:37 PM PDT 24
Finished Aug 13 05:15:27 PM PDT 24
Peak memory 200848 kb
Host smart-b4192edf-b3f4-4e9f-8164-e0e3930623da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480613218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3480613218
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_stress_all.4291559413
Short name T246
Test name
Test status
Simulation time 268333959356 ps
CPU time 151.2 seconds
Started Aug 13 05:15:38 PM PDT 24
Finished Aug 13 05:18:10 PM PDT 24
Peak memory 217368 kb
Host smart-2cdf030c-ea22-49b2-8acc-f0ab149265a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291559413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.4291559413
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1005223223
Short name T177
Test name
Test status
Simulation time 85583255025 ps
CPU time 37.7 seconds
Started Aug 13 05:16:13 PM PDT 24
Finished Aug 13 05:16:50 PM PDT 24
Peak memory 200868 kb
Host smart-5375a5fd-07f3-4c15-aec6-cb14f5505962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005223223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1005223223
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.3604280914
Short name T34
Test name
Test status
Simulation time 136738676318 ps
CPU time 82.12 seconds
Started Aug 13 05:16:20 PM PDT 24
Finished Aug 13 05:17:43 PM PDT 24
Peak memory 200788 kb
Host smart-bd18b6a8-ed8f-457d-8e82-d8fd4bcc607b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604280914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3604280914
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2786907686
Short name T162
Test name
Test status
Simulation time 88490191999 ps
CPU time 41.46 seconds
Started Aug 13 05:17:04 PM PDT 24
Finished Aug 13 05:17:46 PM PDT 24
Peak memory 200920 kb
Host smart-c3afcbb3-6df1-46dc-8317-baa89300a6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786907686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2786907686
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1009013443
Short name T353
Test name
Test status
Simulation time 68767670270 ps
CPU time 48.36 seconds
Started Aug 13 05:17:06 PM PDT 24
Finished Aug 13 05:17:54 PM PDT 24
Peak memory 200944 kb
Host smart-d6cee9c3-18fe-4320-9e30-d91294df406c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009013443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1009013443
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.1578144747
Short name T115
Test name
Test status
Simulation time 14959412992 ps
CPU time 24.71 seconds
Started Aug 13 05:16:26 PM PDT 24
Finished Aug 13 05:16:50 PM PDT 24
Peak memory 200936 kb
Host smart-ac82bee6-5efd-49e6-a478-b00a71497821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578144747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1578144747
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.2841628891
Short name T173
Test name
Test status
Simulation time 12749692014 ps
CPU time 21.95 seconds
Started Aug 13 05:17:22 PM PDT 24
Finished Aug 13 05:17:44 PM PDT 24
Peak memory 200932 kb
Host smart-bdcea59f-f531-43ce-ac4c-d9dffc028b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841628891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2841628891
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.3238482580
Short name T925
Test name
Test status
Simulation time 106535721151 ps
CPU time 218.35 seconds
Started Aug 13 05:15:20 PM PDT 24
Finished Aug 13 05:18:59 PM PDT 24
Peak memory 200928 kb
Host smart-7964cb04-9b45-4229-bad9-a3093f01aac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238482580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.3238482580
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3525507302
Short name T33
Test name
Test status
Simulation time 35966048280 ps
CPU time 76.49 seconds
Started Aug 13 05:13:42 PM PDT 24
Finished Aug 13 05:14:59 PM PDT 24
Peak memory 200932 kb
Host smart-5c58c1b8-4cb4-42dc-a9f2-749630cf1b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525507302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3525507302
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.29585821
Short name T941
Test name
Test status
Simulation time 79922157607 ps
CPU time 110.36 seconds
Started Aug 13 05:16:56 PM PDT 24
Finished Aug 13 05:18:46 PM PDT 24
Peak memory 200884 kb
Host smart-fa243d7b-11f3-4f2f-8640-e7a27ae6c565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29585821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.29585821
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.4009407088
Short name T465
Test name
Test status
Simulation time 207518552856 ps
CPU time 515.95 seconds
Started Aug 13 05:17:05 PM PDT 24
Finished Aug 13 05:25:42 PM PDT 24
Peak memory 200876 kb
Host smart-5d291f9f-0b0a-4d3a-b320-fed58808567a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009407088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.4009407088
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.396400832
Short name T101
Test name
Test status
Simulation time 120781213050 ps
CPU time 54.22 seconds
Started Aug 13 05:17:16 PM PDT 24
Finished Aug 13 05:18:10 PM PDT 24
Peak memory 200920 kb
Host smart-d0375eb0-41ba-4dd1-87fb-0b636c3ce39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396400832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.396400832
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all.622762521
Short name T363
Test name
Test status
Simulation time 645111347458 ps
CPU time 304.95 seconds
Started Aug 13 05:13:40 PM PDT 24
Finished Aug 13 05:18:45 PM PDT 24
Peak memory 209452 kb
Host smart-b2eb5e37-8b65-401b-9030-da0f09b9d5b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622762521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.622762521
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.785047434
Short name T209
Test name
Test status
Simulation time 67641826136 ps
CPU time 45 seconds
Started Aug 13 05:16:47 PM PDT 24
Finished Aug 13 05:17:32 PM PDT 24
Peak memory 200876 kb
Host smart-fdf253ca-e384-4e42-bcd4-f1a3abb80e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785047434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.785047434
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3272566131
Short name T211
Test name
Test status
Simulation time 77084804532 ps
CPU time 121.6 seconds
Started Aug 13 05:16:43 PM PDT 24
Finished Aug 13 05:18:45 PM PDT 24
Peak memory 200820 kb
Host smart-b091efc8-35dc-41e2-8baf-b7f312cd0b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272566131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3272566131
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.1854118334
Short name T232
Test name
Test status
Simulation time 25804332366 ps
CPU time 17.84 seconds
Started Aug 13 05:16:48 PM PDT 24
Finished Aug 13 05:17:06 PM PDT 24
Peak memory 200924 kb
Host smart-2bfca490-ca80-4eeb-8c6f-3cf161b6ded4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854118334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1854118334
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_noise_filter.734527170
Short name T301
Test name
Test status
Simulation time 156104864154 ps
CPU time 67.58 seconds
Started Aug 13 05:14:33 PM PDT 24
Finished Aug 13 05:15:41 PM PDT 24
Peak memory 201064 kb
Host smart-05f3bcbd-c493-49d8-8597-35bcecf13be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734527170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.734527170
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2471914943
Short name T228
Test name
Test status
Simulation time 24333033530 ps
CPU time 34.23 seconds
Started Aug 13 05:17:04 PM PDT 24
Finished Aug 13 05:17:38 PM PDT 24
Peak memory 200856 kb
Host smart-8ab25114-02dd-4845-b6fe-49fdcc762567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471914943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2471914943
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.633136559
Short name T205
Test name
Test status
Simulation time 14654757094 ps
CPU time 33.88 seconds
Started Aug 13 05:17:06 PM PDT 24
Finished Aug 13 05:17:40 PM PDT 24
Peak memory 200880 kb
Host smart-a1568832-b1b1-439a-8615-c854f104ce21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633136559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.633136559
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2110276884
Short name T234
Test name
Test status
Simulation time 26998550323 ps
CPU time 61.42 seconds
Started Aug 13 05:14:39 PM PDT 24
Finished Aug 13 05:15:40 PM PDT 24
Peak memory 200876 kb
Host smart-90c4943f-a593-4651-b0dc-10311fcf3fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110276884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2110276884
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3552366147
Short name T206
Test name
Test status
Simulation time 71408339863 ps
CPU time 132.01 seconds
Started Aug 13 05:17:10 PM PDT 24
Finished Aug 13 05:19:22 PM PDT 24
Peak memory 200920 kb
Host smart-c5b02c8c-acf6-4438-b85e-f9eede96abc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552366147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3552366147
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.4288302326
Short name T220
Test name
Test status
Simulation time 41744244457 ps
CPU time 23.47 seconds
Started Aug 13 05:17:14 PM PDT 24
Finished Aug 13 05:17:37 PM PDT 24
Peak memory 200912 kb
Host smart-aad4983a-dac9-40b6-9474-7a3717dff662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288302326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.4288302326
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.2892528296
Short name T142
Test name
Test status
Simulation time 122596953234 ps
CPU time 179.64 seconds
Started Aug 13 05:17:17 PM PDT 24
Finished Aug 13 05:20:17 PM PDT 24
Peak memory 200848 kb
Host smart-270bd121-9592-43dd-9011-c1bbb3a55898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892528296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2892528296
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.2076612261
Short name T27
Test name
Test status
Simulation time 62467515750 ps
CPU time 51.67 seconds
Started Aug 13 05:15:39 PM PDT 24
Finished Aug 13 05:16:31 PM PDT 24
Peak memory 217580 kb
Host smart-f6999363-a3fa-4ac6-9bfc-d04694044c2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076612261 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.2076612261
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_intr.867989743
Short name T799
Test name
Test status
Simulation time 154208606600 ps
CPU time 127.02 seconds
Started Aug 13 05:13:47 PM PDT 24
Finished Aug 13 05:15:54 PM PDT 24
Peak memory 199632 kb
Host smart-d706a1c7-f234-462d-968e-230098da50e4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867989743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.867989743
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.3079307530
Short name T121
Test name
Test status
Simulation time 104730917596 ps
CPU time 171.6 seconds
Started Aug 13 05:13:53 PM PDT 24
Finished Aug 13 05:16:45 PM PDT 24
Peak memory 200748 kb
Host smart-034e8e14-8c00-4199-94ce-a8b7f6ae859d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079307530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.3079307530
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1698427323
Short name T358
Test name
Test status
Simulation time 20379378458 ps
CPU time 35.56 seconds
Started Aug 13 05:16:43 PM PDT 24
Finished Aug 13 05:17:18 PM PDT 24
Peak memory 200848 kb
Host smart-7e0c0742-e85b-4015-8fb6-52a0ebdb320c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698427323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1698427323
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3630773922
Short name T42
Test name
Test status
Simulation time 143076954286 ps
CPU time 94.88 seconds
Started Aug 13 05:14:10 PM PDT 24
Finished Aug 13 05:15:45 PM PDT 24
Peak memory 200948 kb
Host smart-50d98776-f4eb-4df2-b807-c4597c34478f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630773922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3630773922
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2561016279
Short name T242
Test name
Test status
Simulation time 192741064821 ps
CPU time 179.77 seconds
Started Aug 13 05:16:42 PM PDT 24
Finished Aug 13 05:19:42 PM PDT 24
Peak memory 200828 kb
Host smart-497c55f8-c0e3-405f-8b48-6e17a9555acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561016279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2561016279
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.307321205
Short name T240
Test name
Test status
Simulation time 17868836275 ps
CPU time 32.29 seconds
Started Aug 13 05:16:43 PM PDT 24
Finished Aug 13 05:17:16 PM PDT 24
Peak memory 200828 kb
Host smart-2ffb357d-41d2-44b7-bf0b-ef2c2a8fa742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307321205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.307321205
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.2885357870
Short name T879
Test name
Test status
Simulation time 63649568519 ps
CPU time 101.01 seconds
Started Aug 13 05:14:08 PM PDT 24
Finished Aug 13 05:15:49 PM PDT 24
Peak memory 200860 kb
Host smart-f8487d53-1aee-40dc-a081-9cd28eed9325
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885357870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2885357870
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2099829800
Short name T219
Test name
Test status
Simulation time 23892032052 ps
CPU time 36.97 seconds
Started Aug 13 05:16:51 PM PDT 24
Finished Aug 13 05:17:28 PM PDT 24
Peak memory 200916 kb
Host smart-a26b44e8-3e88-42b3-b79d-1950dbe27e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099829800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2099829800
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2472740721
Short name T216
Test name
Test status
Simulation time 19105367689 ps
CPU time 16.25 seconds
Started Aug 13 05:16:46 PM PDT 24
Finished Aug 13 05:17:03 PM PDT 24
Peak memory 200712 kb
Host smart-f725742f-2e46-41bf-8602-e877a3f1e7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472740721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2472740721
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1588936529
Short name T229
Test name
Test status
Simulation time 157368288167 ps
CPU time 30.09 seconds
Started Aug 13 05:16:54 PM PDT 24
Finished Aug 13 05:17:24 PM PDT 24
Peak memory 200916 kb
Host smart-8a016a0e-93d0-4e7a-b691-4fd3c4f0eadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588936529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1588936529
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.1288391015
Short name T140
Test name
Test status
Simulation time 34595851061 ps
CPU time 17.96 seconds
Started Aug 13 05:17:07 PM PDT 24
Finished Aug 13 05:17:25 PM PDT 24
Peak memory 200864 kb
Host smart-ccb2345d-8e6d-4293-a9a3-19f8b4470e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288391015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1288391015
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.164112027
Short name T171
Test name
Test status
Simulation time 61452561721 ps
CPU time 26.5 seconds
Started Aug 13 05:17:05 PM PDT 24
Finished Aug 13 05:17:32 PM PDT 24
Peak memory 200872 kb
Host smart-c38887fc-d92d-40d6-8a5f-ae690dfff176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164112027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.164112027
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.996261853
Short name T119
Test name
Test status
Simulation time 61922900484 ps
CPU time 10.17 seconds
Started Aug 13 05:17:05 PM PDT 24
Finished Aug 13 05:17:16 PM PDT 24
Peak memory 200424 kb
Host smart-962213d4-2855-4d3d-8a32-b57657c5dc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996261853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.996261853
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2284265805
Short name T230
Test name
Test status
Simulation time 152513408716 ps
CPU time 19.33 seconds
Started Aug 13 05:17:09 PM PDT 24
Finished Aug 13 05:17:28 PM PDT 24
Peak memory 200832 kb
Host smart-b27c7a1f-de0b-4d68-8966-454615d0bb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284265805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2284265805
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.1921488923
Short name T225
Test name
Test status
Simulation time 25118458775 ps
CPU time 39.79 seconds
Started Aug 13 05:17:14 PM PDT 24
Finished Aug 13 05:17:53 PM PDT 24
Peak memory 200604 kb
Host smart-51a04c8b-929c-47a2-9930-575522b1b22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921488923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1921488923
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2515647598
Short name T243
Test name
Test status
Simulation time 10173989015 ps
CPU time 6.5 seconds
Started Aug 13 05:16:22 PM PDT 24
Finished Aug 13 05:16:29 PM PDT 24
Peak memory 200892 kb
Host smart-132677a9-67b2-4525-8774-c37323f326dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515647598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2515647598
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.458738881
Short name T241
Test name
Test status
Simulation time 92312291446 ps
CPU time 151.79 seconds
Started Aug 13 05:16:29 PM PDT 24
Finished Aug 13 05:19:01 PM PDT 24
Peak memory 200868 kb
Host smart-a7a2d9aa-6794-41ea-99ac-1da9dd59ce16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458738881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.458738881
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3021535620
Short name T231
Test name
Test status
Simulation time 39206552670 ps
CPU time 10.19 seconds
Started Aug 13 05:16:42 PM PDT 24
Finished Aug 13 05:16:52 PM PDT 24
Peak memory 200884 kb
Host smart-c578853a-d553-4618-b592-829d71f3a8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021535620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3021535620
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2948572828
Short name T120
Test name
Test status
Simulation time 74152944065 ps
CPU time 32.15 seconds
Started Aug 13 05:16:40 PM PDT 24
Finished Aug 13 05:17:13 PM PDT 24
Peak memory 200780 kb
Host smart-cd74ffc2-b0f7-4716-af41-f7cd6db36039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948572828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2948572828
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3661077522
Short name T1300
Test name
Test status
Simulation time 60581821 ps
CPU time 2.23 seconds
Started Aug 13 05:36:54 PM PDT 24
Finished Aug 13 05:36:57 PM PDT 24
Peak memory 197920 kb
Host smart-ca32a2df-2b78-47d1-b734-621a2b8a6075
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661077522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3661077522
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2659925875
Short name T1314
Test name
Test status
Simulation time 21385761 ps
CPU time 0.65 seconds
Started Aug 13 05:36:53 PM PDT 24
Finished Aug 13 05:36:54 PM PDT 24
Peak memory 195516 kb
Host smart-6975724d-0725-418a-8039-50094a7cc5c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659925875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2659925875
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2623481897
Short name T1233
Test name
Test status
Simulation time 25984912 ps
CPU time 0.67 seconds
Started Aug 13 05:36:48 PM PDT 24
Finished Aug 13 05:36:54 PM PDT 24
Peak memory 197828 kb
Host smart-bfd685fd-e45a-4ed4-8247-e7e22104738c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623481897 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2623481897
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1977755542
Short name T1253
Test name
Test status
Simulation time 17895578 ps
CPU time 0.58 seconds
Started Aug 13 05:36:51 PM PDT 24
Finished Aug 13 05:36:52 PM PDT 24
Peak memory 194564 kb
Host smart-6874d599-f135-43f2-b644-cf727ea18d67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977755542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1977755542
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.514468783
Short name T1305
Test name
Test status
Simulation time 84186458 ps
CPU time 0.63 seconds
Started Aug 13 05:36:42 PM PDT 24
Finished Aug 13 05:36:43 PM PDT 24
Peak memory 195716 kb
Host smart-5b032a7a-e213-4a69-aeac-764f1b2fed48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514468783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_
outstanding.514468783
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3646633262
Short name T1261
Test name
Test status
Simulation time 100364329 ps
CPU time 1.53 seconds
Started Aug 13 05:37:02 PM PDT 24
Finished Aug 13 05:37:04 PM PDT 24
Peak memory 200200 kb
Host smart-cfdfc8a0-a11b-4aa6-99f7-00f5dad65b68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646633262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3646633262
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.4007809601
Short name T48
Test name
Test status
Simulation time 32461297 ps
CPU time 0.79 seconds
Started Aug 13 05:37:04 PM PDT 24
Finished Aug 13 05:37:05 PM PDT 24
Peak memory 196376 kb
Host smart-252e672e-7dc4-4ab1-bb42-6a5e0d1891cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007809601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.4007809601
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3002377920
Short name T54
Test name
Test status
Simulation time 58813780 ps
CPU time 2.25 seconds
Started Aug 13 05:37:07 PM PDT 24
Finished Aug 13 05:37:10 PM PDT 24
Peak memory 198024 kb
Host smart-a9d9072e-0e5d-4527-bb9b-fc6f6383a309
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002377920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3002377920
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2828760567
Short name T1257
Test name
Test status
Simulation time 17468133 ps
CPU time 0.58 seconds
Started Aug 13 05:36:54 PM PDT 24
Finished Aug 13 05:36:55 PM PDT 24
Peak memory 195424 kb
Host smart-7e8f192a-998f-4b11-aa67-49ee919c9680
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828760567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2828760567
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.329430828
Short name T1197
Test name
Test status
Simulation time 46439025 ps
CPU time 0.82 seconds
Started Aug 13 05:37:04 PM PDT 24
Finished Aug 13 05:37:05 PM PDT 24
Peak memory 198936 kb
Host smart-0377d126-1523-4a1a-94a9-a032a837b852
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329430828 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.329430828
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3637594073
Short name T44
Test name
Test status
Simulation time 59008797 ps
CPU time 0.62 seconds
Started Aug 13 05:37:10 PM PDT 24
Finished Aug 13 05:37:11 PM PDT 24
Peak memory 195804 kb
Host smart-05d06dde-a0d2-47d9-9692-4cf6893845d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637594073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3637594073
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2132217730
Short name T1298
Test name
Test status
Simulation time 226184274 ps
CPU time 0.58 seconds
Started Aug 13 05:36:47 PM PDT 24
Finished Aug 13 05:36:48 PM PDT 24
Peak memory 194568 kb
Host smart-cba0bcb3-b33a-44e2-ab9a-26ef6a4e2144
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132217730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2132217730
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3527258245
Short name T1215
Test name
Test status
Simulation time 117877596 ps
CPU time 0.71 seconds
Started Aug 13 05:36:46 PM PDT 24
Finished Aug 13 05:36:47 PM PDT 24
Peak memory 197064 kb
Host smart-dfbca355-00c3-43d1-8149-8fc85cde6878
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527258245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3527258245
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.4081899787
Short name T1307
Test name
Test status
Simulation time 1108368504 ps
CPU time 1.96 seconds
Started Aug 13 05:36:51 PM PDT 24
Finished Aug 13 05:36:53 PM PDT 24
Peak memory 200168 kb
Host smart-57150d76-9bf1-4a59-8a25-3f6a4aed4578
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081899787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.4081899787
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2369942073
Short name T74
Test name
Test status
Simulation time 70070402 ps
CPU time 1.22 seconds
Started Aug 13 05:36:58 PM PDT 24
Finished Aug 13 05:36:59 PM PDT 24
Peak memory 199588 kb
Host smart-1232836d-53fb-461b-852a-8c09f3e903af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369942073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2369942073
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.900188985
Short name T1317
Test name
Test status
Simulation time 24845977 ps
CPU time 0.76 seconds
Started Aug 13 05:37:08 PM PDT 24
Finished Aug 13 05:37:09 PM PDT 24
Peak memory 198848 kb
Host smart-dc330218-e0c3-44fb-8b0f-b17c2f6f5474
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900188985 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.900188985
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.25403353
Short name T1206
Test name
Test status
Simulation time 15779599 ps
CPU time 0.57 seconds
Started Aug 13 05:37:26 PM PDT 24
Finished Aug 13 05:37:27 PM PDT 24
Peak memory 195380 kb
Host smart-a7478d09-511a-4f7e-87ee-f3978c531005
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25403353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.25403353
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.836639300
Short name T1191
Test name
Test status
Simulation time 13160425 ps
CPU time 0.56 seconds
Started Aug 13 05:37:11 PM PDT 24
Finished Aug 13 05:37:12 PM PDT 24
Peak memory 194572 kb
Host smart-c9d636c2-9095-416d-a8bb-24bd01d7d8b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836639300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.836639300
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2019285330
Short name T1217
Test name
Test status
Simulation time 17787792 ps
CPU time 0.73 seconds
Started Aug 13 05:37:12 PM PDT 24
Finished Aug 13 05:37:12 PM PDT 24
Peak memory 197236 kb
Host smart-bc3ccaeb-9271-4383-9870-a3e13a0dfef9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019285330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2019285330
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3469754548
Short name T1254
Test name
Test status
Simulation time 44009592 ps
CPU time 2.12 seconds
Started Aug 13 05:37:14 PM PDT 24
Finished Aug 13 05:37:16 PM PDT 24
Peak memory 200160 kb
Host smart-0f338265-d2b5-4d60-bfe0-d41027a43372
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469754548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3469754548
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2502987553
Short name T1271
Test name
Test status
Simulation time 50055377 ps
CPU time 0.97 seconds
Started Aug 13 05:37:05 PM PDT 24
Finished Aug 13 05:37:06 PM PDT 24
Peak memory 199176 kb
Host smart-f8f09a9e-6bb8-4812-8099-b144dd4a7534
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502987553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2502987553
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3288029819
Short name T1288
Test name
Test status
Simulation time 23740052 ps
CPU time 0.76 seconds
Started Aug 13 05:37:10 PM PDT 24
Finished Aug 13 05:37:11 PM PDT 24
Peak memory 198784 kb
Host smart-1b56f60a-d76e-4de4-b34b-c5c6f1e3fe7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288029819 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3288029819
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.1917527697
Short name T1266
Test name
Test status
Simulation time 17332771 ps
CPU time 0.6 seconds
Started Aug 13 05:37:17 PM PDT 24
Finished Aug 13 05:37:18 PM PDT 24
Peak memory 195744 kb
Host smart-d2f07df1-5921-4222-8ab1-ac53c9591960
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917527697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1917527697
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.3409174661
Short name T1227
Test name
Test status
Simulation time 19251608 ps
CPU time 0.55 seconds
Started Aug 13 05:37:06 PM PDT 24
Finished Aug 13 05:37:06 PM PDT 24
Peak memory 194588 kb
Host smart-8b42a99c-0f11-4451-8543-d1809e965b5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409174661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3409174661
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.163763005
Short name T1302
Test name
Test status
Simulation time 36431747 ps
CPU time 0.71 seconds
Started Aug 13 05:37:06 PM PDT 24
Finished Aug 13 05:37:07 PM PDT 24
Peak memory 194668 kb
Host smart-985d3402-8a08-4bb9-8a37-42b7a6ef4f5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163763005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr
_outstanding.163763005
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1568940254
Short name T1211
Test name
Test status
Simulation time 202465358 ps
CPU time 1.36 seconds
Started Aug 13 05:37:08 PM PDT 24
Finished Aug 13 05:37:10 PM PDT 24
Peak memory 200224 kb
Host smart-361421cb-fcbb-4594-9926-49af749403c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568940254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1568940254
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1996798311
Short name T1293
Test name
Test status
Simulation time 225741243 ps
CPU time 1.21 seconds
Started Aug 13 05:37:11 PM PDT 24
Finished Aug 13 05:37:12 PM PDT 24
Peak memory 199476 kb
Host smart-a0dd3794-65e5-4719-8803-4f06ae2ef5e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996798311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1996798311
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3431068565
Short name T1290
Test name
Test status
Simulation time 22507542 ps
CPU time 0.64 seconds
Started Aug 13 05:37:05 PM PDT 24
Finished Aug 13 05:37:06 PM PDT 24
Peak memory 197508 kb
Host smart-7e1c6581-ff15-4c2f-b667-b826e073a740
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431068565 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3431068565
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.1843232088
Short name T59
Test name
Test status
Simulation time 31933842 ps
CPU time 0.59 seconds
Started Aug 13 05:37:03 PM PDT 24
Finished Aug 13 05:37:04 PM PDT 24
Peak memory 195520 kb
Host smart-6b3ab4d5-9d20-4633-86bc-346da09ae76d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843232088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1843232088
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2019404122
Short name T1269
Test name
Test status
Simulation time 11509592 ps
CPU time 0.56 seconds
Started Aug 13 05:36:59 PM PDT 24
Finished Aug 13 05:36:59 PM PDT 24
Peak memory 194580 kb
Host smart-24b2d94e-046e-41e2-bb90-2c8718ec9129
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019404122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2019404122
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3083482650
Short name T1297
Test name
Test status
Simulation time 15963869 ps
CPU time 0.68 seconds
Started Aug 13 05:37:07 PM PDT 24
Finished Aug 13 05:37:08 PM PDT 24
Peak memory 195744 kb
Host smart-e84683cc-6c4b-4b12-a0ee-c12e6dfa84fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083482650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3083482650
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.871624509
Short name T1250
Test name
Test status
Simulation time 254795621 ps
CPU time 1.44 seconds
Started Aug 13 05:37:07 PM PDT 24
Finished Aug 13 05:37:08 PM PDT 24
Peak memory 200248 kb
Host smart-99112bf6-8c24-4765-88dd-fecda649434a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871624509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.871624509
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1131044718
Short name T68
Test name
Test status
Simulation time 434619931 ps
CPU time 0.94 seconds
Started Aug 13 05:37:03 PM PDT 24
Finished Aug 13 05:37:04 PM PDT 24
Peak memory 199240 kb
Host smart-ce4617cd-bae5-4001-88d3-90deb2dec888
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131044718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1131044718
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2064695441
Short name T1312
Test name
Test status
Simulation time 26342827 ps
CPU time 1.14 seconds
Started Aug 13 05:37:28 PM PDT 24
Finished Aug 13 05:37:29 PM PDT 24
Peak memory 200220 kb
Host smart-1a3ebfe9-f291-4c8c-a20d-09a59feeac84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064695441 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2064695441
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.2461256363
Short name T1295
Test name
Test status
Simulation time 51558354 ps
CPU time 0.62 seconds
Started Aug 13 05:37:17 PM PDT 24
Finished Aug 13 05:37:17 PM PDT 24
Peak memory 195536 kb
Host smart-1806e05c-a073-4375-817d-238117c671bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461256363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2461256363
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1456724587
Short name T1313
Test name
Test status
Simulation time 22495317 ps
CPU time 0.57 seconds
Started Aug 13 05:37:30 PM PDT 24
Finished Aug 13 05:37:31 PM PDT 24
Peak memory 194420 kb
Host smart-8839fbe8-5a59-44de-9c2a-304f34916bdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456724587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1456724587
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1555298134
Short name T1225
Test name
Test status
Simulation time 28627059 ps
CPU time 0.67 seconds
Started Aug 13 05:37:07 PM PDT 24
Finished Aug 13 05:37:08 PM PDT 24
Peak memory 195900 kb
Host smart-18cb3aaf-94e8-4ae6-b296-7e38fa800321
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555298134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1555298134
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.548754387
Short name T1213
Test name
Test status
Simulation time 273739508 ps
CPU time 1.35 seconds
Started Aug 13 05:37:03 PM PDT 24
Finished Aug 13 05:37:05 PM PDT 24
Peak memory 200212 kb
Host smart-8043eeb3-0d27-483a-9ee8-12da523b3fe2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548754387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.548754387
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3883005510
Short name T70
Test name
Test status
Simulation time 363318752 ps
CPU time 1.29 seconds
Started Aug 13 05:37:05 PM PDT 24
Finished Aug 13 05:37:06 PM PDT 24
Peak memory 199404 kb
Host smart-0ee9be72-9f9b-46db-a2a4-68c6e59e36d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883005510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3883005510
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.4267392866
Short name T1214
Test name
Test status
Simulation time 20753200 ps
CPU time 0.7 seconds
Started Aug 13 05:37:05 PM PDT 24
Finished Aug 13 05:37:06 PM PDT 24
Peak memory 197604 kb
Host smart-c9d2a440-5bf7-4ca9-9e02-e73c863f2671
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267392866 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.4267392866
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1195943412
Short name T60
Test name
Test status
Simulation time 52635685 ps
CPU time 0.62 seconds
Started Aug 13 05:37:09 PM PDT 24
Finished Aug 13 05:37:10 PM PDT 24
Peak memory 195532 kb
Host smart-071aefe3-21b8-49dd-b8ba-a32a3eb025e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195943412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1195943412
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.4139570100
Short name T1278
Test name
Test status
Simulation time 29029672 ps
CPU time 0.58 seconds
Started Aug 13 05:37:08 PM PDT 24
Finished Aug 13 05:37:09 PM PDT 24
Peak memory 194548 kb
Host smart-a283789b-4e5b-4307-b51a-5ef76531a730
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139570100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.4139570100
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.908394762
Short name T1285
Test name
Test status
Simulation time 68975587 ps
CPU time 0.68 seconds
Started Aug 13 05:37:08 PM PDT 24
Finished Aug 13 05:37:08 PM PDT 24
Peak memory 195656 kb
Host smart-14a90f89-4c0f-4766-a01d-e6d80325c3c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908394762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr
_outstanding.908394762
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.3165307552
Short name T1198
Test name
Test status
Simulation time 82494888 ps
CPU time 1.94 seconds
Started Aug 13 05:37:26 PM PDT 24
Finished Aug 13 05:37:33 PM PDT 24
Peak memory 200256 kb
Host smart-b334fd64-ec2b-4e20-b49e-8a14a7978699
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165307552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3165307552
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2685943858
Short name T71
Test name
Test status
Simulation time 157441218 ps
CPU time 1.31 seconds
Started Aug 13 05:37:05 PM PDT 24
Finished Aug 13 05:37:07 PM PDT 24
Peak memory 199656 kb
Host smart-5a43cc59-19ff-4b62-bf9b-c39491055f6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685943858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2685943858
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4104537617
Short name T1316
Test name
Test status
Simulation time 114311413 ps
CPU time 0.85 seconds
Started Aug 13 05:37:07 PM PDT 24
Finished Aug 13 05:37:08 PM PDT 24
Peak memory 199984 kb
Host smart-a49a66f6-7c7f-47f7-89e3-6a73c5ea515b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104537617 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.4104537617
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.2454484000
Short name T50
Test name
Test status
Simulation time 17426686 ps
CPU time 0.62 seconds
Started Aug 13 05:37:16 PM PDT 24
Finished Aug 13 05:37:17 PM PDT 24
Peak memory 195616 kb
Host smart-14906954-e694-4bb6-8470-f5d2db1a93df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454484000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2454484000
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3715768797
Short name T1216
Test name
Test status
Simulation time 29576989 ps
CPU time 0.54 seconds
Started Aug 13 05:37:33 PM PDT 24
Finished Aug 13 05:37:34 PM PDT 24
Peak memory 194568 kb
Host smart-266e21ce-678a-475d-a67d-d1b6bd03c1ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715768797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3715768797
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.515282367
Short name T1263
Test name
Test status
Simulation time 130984071 ps
CPU time 0.79 seconds
Started Aug 13 05:37:16 PM PDT 24
Finished Aug 13 05:37:17 PM PDT 24
Peak memory 197732 kb
Host smart-7a03a573-08aa-4ed8-83e9-53591926dfec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515282367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr
_outstanding.515282367
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2210270430
Short name T1309
Test name
Test status
Simulation time 22651330 ps
CPU time 0.93 seconds
Started Aug 13 05:36:59 PM PDT 24
Finished Aug 13 05:37:00 PM PDT 24
Peak memory 200004 kb
Host smart-41a964a5-99cd-4b09-b93d-537f56367e19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210270430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2210270430
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1994018029
Short name T1310
Test name
Test status
Simulation time 290769274 ps
CPU time 1.23 seconds
Started Aug 13 05:37:03 PM PDT 24
Finished Aug 13 05:37:04 PM PDT 24
Peak memory 199592 kb
Host smart-bfac6f58-ecd2-4c5a-a5a7-7569ee1d5db5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994018029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1994018029
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.934598872
Short name T1276
Test name
Test status
Simulation time 86453538 ps
CPU time 1.09 seconds
Started Aug 13 05:37:29 PM PDT 24
Finished Aug 13 05:37:31 PM PDT 24
Peak memory 200056 kb
Host smart-05b3189c-7654-494d-8bb9-33c1fd131b51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934598872 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.934598872
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1728720321
Short name T55
Test name
Test status
Simulation time 48871968 ps
CPU time 0.61 seconds
Started Aug 13 05:37:06 PM PDT 24
Finished Aug 13 05:37:07 PM PDT 24
Peak memory 195424 kb
Host smart-941a1cee-3436-43b9-a8f9-47497ae2c8d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728720321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1728720321
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.4143529849
Short name T1315
Test name
Test status
Simulation time 35982658 ps
CPU time 0.59 seconds
Started Aug 13 05:37:07 PM PDT 24
Finished Aug 13 05:37:08 PM PDT 24
Peak memory 194580 kb
Host smart-8cea013b-3f3f-438f-a157-d8e36d62d249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143529849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.4143529849
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.258243715
Short name T1303
Test name
Test status
Simulation time 38302304 ps
CPU time 0.67 seconds
Started Aug 13 05:37:09 PM PDT 24
Finished Aug 13 05:37:10 PM PDT 24
Peak memory 194940 kb
Host smart-027dd60d-ce66-493a-8240-7626140a479c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258243715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.258243715
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3085622424
Short name T1194
Test name
Test status
Simulation time 70615681 ps
CPU time 1.46 seconds
Started Aug 13 05:37:06 PM PDT 24
Finished Aug 13 05:37:08 PM PDT 24
Peak memory 200224 kb
Host smart-7091f449-5cff-4456-be9d-1fd16629e104
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085622424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3085622424
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3286511846
Short name T1238
Test name
Test status
Simulation time 144365187 ps
CPU time 0.93 seconds
Started Aug 13 05:37:26 PM PDT 24
Finished Aug 13 05:37:27 PM PDT 24
Peak memory 199096 kb
Host smart-c53eb661-4172-4839-b97b-092f8a603e7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286511846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3286511846
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1795067841
Short name T1186
Test name
Test status
Simulation time 21830071 ps
CPU time 0.76 seconds
Started Aug 13 05:36:58 PM PDT 24
Finished Aug 13 05:37:03 PM PDT 24
Peak memory 199144 kb
Host smart-49c92e13-7251-4727-b073-3ef45e48a173
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795067841 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1795067841
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.1419833383
Short name T49
Test name
Test status
Simulation time 26788557 ps
CPU time 0.6 seconds
Started Aug 13 05:37:12 PM PDT 24
Finished Aug 13 05:37:18 PM PDT 24
Peak memory 195624 kb
Host smart-b68983c1-f56f-4e22-acec-42d57e8443c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419833383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1419833383
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3706525020
Short name T1200
Test name
Test status
Simulation time 38448947 ps
CPU time 0.59 seconds
Started Aug 13 05:37:07 PM PDT 24
Finished Aug 13 05:37:08 PM PDT 24
Peak memory 194568 kb
Host smart-817f243f-839f-4ae4-8a66-20d0a735b79e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706525020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3706525020
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1732575056
Short name T1259
Test name
Test status
Simulation time 50793107 ps
CPU time 0.73 seconds
Started Aug 13 05:37:03 PM PDT 24
Finished Aug 13 05:37:04 PM PDT 24
Peak memory 196616 kb
Host smart-3bccc0e8-d5ee-4a66-bff4-5a1bcf067c16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732575056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.1732575056
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.505323998
Short name T1207
Test name
Test status
Simulation time 19419093 ps
CPU time 0.91 seconds
Started Aug 13 05:37:22 PM PDT 24
Finished Aug 13 05:37:23 PM PDT 24
Peak memory 199900 kb
Host smart-1f593b7a-41d3-4358-8810-6ab80f6beffc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505323998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.505323998
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3164673116
Short name T1232
Test name
Test status
Simulation time 74947350 ps
CPU time 1.24 seconds
Started Aug 13 05:37:15 PM PDT 24
Finished Aug 13 05:37:16 PM PDT 24
Peak memory 199352 kb
Host smart-d6ff30ca-e4fe-4a42-b3a0-d221b7995856
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164673116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3164673116
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3146833149
Short name T1230
Test name
Test status
Simulation time 53488542 ps
CPU time 0.71 seconds
Started Aug 13 05:37:15 PM PDT 24
Finished Aug 13 05:37:16 PM PDT 24
Peak memory 197696 kb
Host smart-61fd53f4-6ccb-45fc-98d3-f8f05cc46f62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146833149 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3146833149
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3003213364
Short name T64
Test name
Test status
Simulation time 17413927 ps
CPU time 0.63 seconds
Started Aug 13 05:37:23 PM PDT 24
Finished Aug 13 05:37:24 PM PDT 24
Peak memory 195600 kb
Host smart-0424a679-17c7-4ced-8991-25c806bfcc43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003213364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3003213364
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.2760464180
Short name T1224
Test name
Test status
Simulation time 21863129 ps
CPU time 0.58 seconds
Started Aug 13 05:37:23 PM PDT 24
Finished Aug 13 05:37:24 PM PDT 24
Peak memory 194528 kb
Host smart-51127f7b-418b-4161-bf4c-fbe0807eaa67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760464180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2760464180
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3654743640
Short name T58
Test name
Test status
Simulation time 26070816 ps
CPU time 0.8 seconds
Started Aug 13 05:37:21 PM PDT 24
Finished Aug 13 05:37:21 PM PDT 24
Peak memory 197248 kb
Host smart-6b160774-b27b-43f1-a5fe-3326cc32b8a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654743640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3654743640
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.437310203
Short name T1209
Test name
Test status
Simulation time 86379663 ps
CPU time 2.4 seconds
Started Aug 13 05:37:05 PM PDT 24
Finished Aug 13 05:37:08 PM PDT 24
Peak memory 200252 kb
Host smart-f193f8d5-f0f2-495d-ba01-99729b822380
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437310203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.437310203
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3803846874
Short name T67
Test name
Test status
Simulation time 55682596 ps
CPU time 0.95 seconds
Started Aug 13 05:37:13 PM PDT 24
Finished Aug 13 05:37:14 PM PDT 24
Peak memory 199016 kb
Host smart-7aef0af5-13ec-495d-9bfe-3a9a5a773408
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803846874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3803846874
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.434323966
Short name T1222
Test name
Test status
Simulation time 53018494 ps
CPU time 0.79 seconds
Started Aug 13 05:37:20 PM PDT 24
Finished Aug 13 05:37:21 PM PDT 24
Peak memory 199784 kb
Host smart-757b5949-d74f-4691-9f65-8b5d7560e5a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434323966 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.434323966
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.4122268447
Short name T1318
Test name
Test status
Simulation time 93209644 ps
CPU time 0.63 seconds
Started Aug 13 05:37:11 PM PDT 24
Finished Aug 13 05:37:12 PM PDT 24
Peak memory 195648 kb
Host smart-f741c66f-185e-42f6-8bdf-6cda90f33e22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122268447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.4122268447
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.351492045
Short name T1196
Test name
Test status
Simulation time 59465683 ps
CPU time 0.56 seconds
Started Aug 13 05:37:18 PM PDT 24
Finished Aug 13 05:37:19 PM PDT 24
Peak memory 194540 kb
Host smart-cdac2498-63e8-457f-8622-bd43ad2eeaeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351492045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.351492045
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3160104786
Short name T1280
Test name
Test status
Simulation time 30782554 ps
CPU time 0.62 seconds
Started Aug 13 05:37:20 PM PDT 24
Finished Aug 13 05:37:21 PM PDT 24
Peak memory 195848 kb
Host smart-21f62405-f025-4fde-9229-726d87b160a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160104786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.3160104786
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2502573715
Short name T1255
Test name
Test status
Simulation time 110873280 ps
CPU time 2.3 seconds
Started Aug 13 05:37:16 PM PDT 24
Finished Aug 13 05:37:18 PM PDT 24
Peak memory 200120 kb
Host smart-56b13d69-f1ac-453c-b3f5-070bc7a03b21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502573715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2502573715
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2961902680
Short name T1292
Test name
Test status
Simulation time 85527769 ps
CPU time 0.95 seconds
Started Aug 13 05:37:11 PM PDT 24
Finished Aug 13 05:37:12 PM PDT 24
Peak memory 198816 kb
Host smart-b29c4bfc-026d-4152-a9ea-dcdb4176a9ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961902680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2961902680
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.274846634
Short name T1220
Test name
Test status
Simulation time 63491783 ps
CPU time 0.66 seconds
Started Aug 13 05:36:47 PM PDT 24
Finished Aug 13 05:36:48 PM PDT 24
Peak memory 194972 kb
Host smart-8cf8249d-af29-4d55-8046-4c46e8d72e59
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274846634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.274846634
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1331412762
Short name T1226
Test name
Test status
Simulation time 509041317 ps
CPU time 1.52 seconds
Started Aug 13 05:37:03 PM PDT 24
Finished Aug 13 05:37:05 PM PDT 24
Peak memory 198180 kb
Host smart-3ed8c054-b38a-48bd-9406-3ced2f46672b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331412762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1331412762
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.4117294862
Short name T47
Test name
Test status
Simulation time 61802935 ps
CPU time 0.58 seconds
Started Aug 13 05:36:54 PM PDT 24
Finished Aug 13 05:36:55 PM PDT 24
Peak memory 195420 kb
Host smart-ddecb186-1c3e-4100-a6a4-33e5c8665e35
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117294862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.4117294862
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1289933196
Short name T1244
Test name
Test status
Simulation time 39881492 ps
CPU time 0.8 seconds
Started Aug 13 05:36:47 PM PDT 24
Finished Aug 13 05:36:48 PM PDT 24
Peak memory 199940 kb
Host smart-fe5b9f6c-5637-4a2e-81a7-28c0b053e09c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289933196 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1289933196
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1631465939
Short name T52
Test name
Test status
Simulation time 17787589 ps
CPU time 0.63 seconds
Started Aug 13 05:37:00 PM PDT 24
Finished Aug 13 05:37:01 PM PDT 24
Peak memory 195776 kb
Host smart-b8d1afe5-817a-4bfa-a62d-ada7e0a4914b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631465939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1631465939
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.776933946
Short name T1221
Test name
Test status
Simulation time 13900762 ps
CPU time 0.55 seconds
Started Aug 13 05:37:01 PM PDT 24
Finished Aug 13 05:37:02 PM PDT 24
Peak memory 194496 kb
Host smart-742a33db-c602-42fb-98ad-7cec797b5dd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776933946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.776933946
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1080778724
Short name T1272
Test name
Test status
Simulation time 32200937 ps
CPU time 0.7 seconds
Started Aug 13 05:37:26 PM PDT 24
Finished Aug 13 05:37:27 PM PDT 24
Peak memory 197056 kb
Host smart-649c4c38-5037-45dd-82a5-0d85ff0fd3e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080778724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.1080778724
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.4054909234
Short name T1306
Test name
Test status
Simulation time 398738441 ps
CPU time 2.14 seconds
Started Aug 13 05:36:55 PM PDT 24
Finished Aug 13 05:36:57 PM PDT 24
Peak memory 200244 kb
Host smart-324ed501-e23a-4028-bcca-73ecb4cee0be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054909234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.4054909234
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.444050178
Short name T1236
Test name
Test status
Simulation time 123947476 ps
CPU time 0.97 seconds
Started Aug 13 05:36:53 PM PDT 24
Finished Aug 13 05:36:55 PM PDT 24
Peak memory 199180 kb
Host smart-991563b1-d04b-44c3-b154-5b678b1d6a66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444050178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.444050178
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3766477813
Short name T1248
Test name
Test status
Simulation time 28932311 ps
CPU time 0.56 seconds
Started Aug 13 05:37:08 PM PDT 24
Finished Aug 13 05:37:09 PM PDT 24
Peak memory 194536 kb
Host smart-6423e835-3da4-48f5-bfd5-a98b5c5f1d4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766477813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3766477813
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1618305789
Short name T1311
Test name
Test status
Simulation time 13765647 ps
CPU time 0.57 seconds
Started Aug 13 05:37:21 PM PDT 24
Finished Aug 13 05:37:22 PM PDT 24
Peak memory 194576 kb
Host smart-67162387-b3cc-4a44-bac1-a03d466ece26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618305789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1618305789
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.169222944
Short name T1291
Test name
Test status
Simulation time 243839454 ps
CPU time 0.63 seconds
Started Aug 13 05:37:26 PM PDT 24
Finished Aug 13 05:37:27 PM PDT 24
Peak memory 194528 kb
Host smart-ce6df215-be2c-4fab-9f18-09ab89af5588
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169222944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.169222944
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.696779198
Short name T1188
Test name
Test status
Simulation time 14872462 ps
CPU time 0.55 seconds
Started Aug 13 05:37:17 PM PDT 24
Finished Aug 13 05:37:18 PM PDT 24
Peak memory 194572 kb
Host smart-2a667a8d-04a0-4e35-a0a0-f6898bbb5447
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696779198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.696779198
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.4154793251
Short name T1287
Test name
Test status
Simulation time 40857589 ps
CPU time 0.6 seconds
Started Aug 13 05:37:17 PM PDT 24
Finished Aug 13 05:37:18 PM PDT 24
Peak memory 194504 kb
Host smart-2a50f8d1-d703-4d4b-ad92-6d10fba5ca15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154793251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.4154793251
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3384891118
Short name T1204
Test name
Test status
Simulation time 45477879 ps
CPU time 0.57 seconds
Started Aug 13 05:37:40 PM PDT 24
Finished Aug 13 05:37:41 PM PDT 24
Peak memory 194552 kb
Host smart-ee33bc1a-4c35-46ec-8803-efe82d23f419
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384891118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3384891118
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.3122786841
Short name T1247
Test name
Test status
Simulation time 64895095 ps
CPU time 0.57 seconds
Started Aug 13 05:37:16 PM PDT 24
Finished Aug 13 05:37:16 PM PDT 24
Peak memory 194544 kb
Host smart-7be94162-91be-4aec-9923-03e3b7a21f9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122786841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3122786841
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.2648342562
Short name T1245
Test name
Test status
Simulation time 11489733 ps
CPU time 0.56 seconds
Started Aug 13 05:37:21 PM PDT 24
Finished Aug 13 05:37:22 PM PDT 24
Peak memory 194568 kb
Host smart-60da534e-926d-4167-a036-7a4b240389c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648342562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2648342562
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.84181621
Short name T1190
Test name
Test status
Simulation time 13095935 ps
CPU time 0.57 seconds
Started Aug 13 05:37:16 PM PDT 24
Finished Aug 13 05:37:17 PM PDT 24
Peak memory 194584 kb
Host smart-9db13313-907c-4c9d-91f8-e37f33fd2f7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84181621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.84181621
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2067413513
Short name T1218
Test name
Test status
Simulation time 25891139 ps
CPU time 0.61 seconds
Started Aug 13 05:37:21 PM PDT 24
Finished Aug 13 05:37:21 PM PDT 24
Peak memory 194552 kb
Host smart-2aa1e279-eac7-4d04-bae6-ab1a2a9da9c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067413513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2067413513
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1450610698
Short name T1304
Test name
Test status
Simulation time 27203583 ps
CPU time 0.67 seconds
Started Aug 13 05:36:55 PM PDT 24
Finished Aug 13 05:36:55 PM PDT 24
Peak memory 195032 kb
Host smart-75ff2913-3da7-4dc9-bab8-1ab7a43e34a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450610698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1450610698
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.668324860
Short name T1264
Test name
Test status
Simulation time 95036209 ps
CPU time 1.57 seconds
Started Aug 13 05:36:56 PM PDT 24
Finished Aug 13 05:36:57 PM PDT 24
Peak memory 198084 kb
Host smart-24f0ac3b-1397-4ee4-ac1b-91010a265b74
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668324860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.668324860
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.823483786
Short name T1258
Test name
Test status
Simulation time 49004883 ps
CPU time 0.58 seconds
Started Aug 13 05:36:55 PM PDT 24
Finished Aug 13 05:36:56 PM PDT 24
Peak memory 195444 kb
Host smart-dd999722-5c9e-4eb8-860b-2ceb263305e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823483786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.823483786
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1620177420
Short name T1210
Test name
Test status
Simulation time 25577523 ps
CPU time 1.21 seconds
Started Aug 13 05:36:55 PM PDT 24
Finished Aug 13 05:36:56 PM PDT 24
Peak memory 200176 kb
Host smart-93b27ef9-3ec9-407c-9d1b-e1e175a1bfd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620177420 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1620177420
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.748528694
Short name T51
Test name
Test status
Simulation time 41900246 ps
CPU time 0.55 seconds
Started Aug 13 05:36:48 PM PDT 24
Finished Aug 13 05:36:48 PM PDT 24
Peak memory 195532 kb
Host smart-031f5357-90a7-4fb5-8113-404527dbc1b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748528694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.748528694
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3931494621
Short name T1268
Test name
Test status
Simulation time 15595832 ps
CPU time 0.59 seconds
Started Aug 13 05:36:53 PM PDT 24
Finished Aug 13 05:36:59 PM PDT 24
Peak memory 194584 kb
Host smart-e149ad4a-58aa-4f73-8aad-ba285878c583
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931494621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3931494621
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1333289355
Short name T1284
Test name
Test status
Simulation time 30803305 ps
CPU time 0.77 seconds
Started Aug 13 05:36:56 PM PDT 24
Finished Aug 13 05:36:57 PM PDT 24
Peak memory 197308 kb
Host smart-690426fe-4739-4634-9b36-fa5b799c0166
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333289355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1333289355
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2265483698
Short name T1296
Test name
Test status
Simulation time 77165158 ps
CPU time 1.97 seconds
Started Aug 13 05:36:49 PM PDT 24
Finished Aug 13 05:36:51 PM PDT 24
Peak memory 200208 kb
Host smart-1331410f-74b0-4597-b64c-05ce8ab58c87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265483698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2265483698
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1579256819
Short name T1249
Test name
Test status
Simulation time 178359492 ps
CPU time 0.94 seconds
Started Aug 13 05:37:28 PM PDT 24
Finished Aug 13 05:37:29 PM PDT 24
Peak memory 198904 kb
Host smart-f42b6cbf-0d9a-45d0-b33b-a8eda2e8363b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579256819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1579256819
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.4260958519
Short name T1195
Test name
Test status
Simulation time 14101085 ps
CPU time 0.56 seconds
Started Aug 13 05:37:46 PM PDT 24
Finished Aug 13 05:37:47 PM PDT 24
Peak memory 194560 kb
Host smart-baba1723-9c8d-4ce0-935e-8820100815ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260958519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.4260958519
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.339427159
Short name T1212
Test name
Test status
Simulation time 54013638 ps
CPU time 0.57 seconds
Started Aug 13 05:37:05 PM PDT 24
Finished Aug 13 05:37:06 PM PDT 24
Peak memory 194448 kb
Host smart-4b969f77-b541-4a30-8976-9e40008e2b8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339427159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.339427159
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1783818321
Short name T1270
Test name
Test status
Simulation time 14450373 ps
CPU time 0.59 seconds
Started Aug 13 05:37:21 PM PDT 24
Finished Aug 13 05:37:22 PM PDT 24
Peak memory 194496 kb
Host smart-248f1e9f-545a-4d20-bdde-f9593549f159
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783818321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1783818321
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.2600948525
Short name T1201
Test name
Test status
Simulation time 39118749 ps
CPU time 0.62 seconds
Started Aug 13 05:37:22 PM PDT 24
Finished Aug 13 05:37:23 PM PDT 24
Peak memory 194556 kb
Host smart-64f04072-6320-4800-8c6d-236f3e864b6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600948525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2600948525
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.4058303773
Short name T1319
Test name
Test status
Simulation time 32141973 ps
CPU time 0.59 seconds
Started Aug 13 05:37:09 PM PDT 24
Finished Aug 13 05:37:10 PM PDT 24
Peak memory 194536 kb
Host smart-d8b4df5e-75df-4057-b5ea-a3d301ae15b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058303773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.4058303773
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.2468006220
Short name T1229
Test name
Test status
Simulation time 13946806 ps
CPU time 0.62 seconds
Started Aug 13 05:37:14 PM PDT 24
Finished Aug 13 05:37:15 PM PDT 24
Peak memory 194596 kb
Host smart-c102b775-7e5f-4092-8ede-6b02cbd626e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468006220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2468006220
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2888916332
Short name T1219
Test name
Test status
Simulation time 34210619 ps
CPU time 0.62 seconds
Started Aug 13 05:37:21 PM PDT 24
Finished Aug 13 05:37:22 PM PDT 24
Peak memory 194536 kb
Host smart-5c95c184-38d3-4075-866a-44383244890e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888916332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2888916332
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.97689337
Short name T1301
Test name
Test status
Simulation time 23931543 ps
CPU time 0.59 seconds
Started Aug 13 05:37:35 PM PDT 24
Finished Aug 13 05:37:35 PM PDT 24
Peak memory 194580 kb
Host smart-d64434d2-23c1-4b73-ab36-9189b1b1fc2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97689337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.97689337
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1043717795
Short name T1241
Test name
Test status
Simulation time 47517130 ps
CPU time 0.6 seconds
Started Aug 13 05:37:09 PM PDT 24
Finished Aug 13 05:37:10 PM PDT 24
Peak memory 194520 kb
Host smart-44e9b035-5d15-4fcf-9168-8bdeee677a1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043717795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1043717795
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1764757452
Short name T1242
Test name
Test status
Simulation time 30265037 ps
CPU time 0.56 seconds
Started Aug 13 05:37:11 PM PDT 24
Finished Aug 13 05:37:12 PM PDT 24
Peak memory 194496 kb
Host smart-fe73549e-6a7a-4768-a661-1ac63355bb9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764757452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1764757452
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3521239708
Short name T46
Test name
Test status
Simulation time 47967122 ps
CPU time 0.74 seconds
Started Aug 13 05:37:13 PM PDT 24
Finished Aug 13 05:37:14 PM PDT 24
Peak memory 196940 kb
Host smart-2159e83e-afb9-4937-9899-a48697602b39
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521239708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3521239708
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1630857943
Short name T1240
Test name
Test status
Simulation time 36715106 ps
CPU time 1.39 seconds
Started Aug 13 05:36:52 PM PDT 24
Finished Aug 13 05:36:54 PM PDT 24
Peak memory 198020 kb
Host smart-3121a9ce-6863-4a16-b41b-476c0869b6b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630857943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1630857943
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2026658286
Short name T1235
Test name
Test status
Simulation time 50434930 ps
CPU time 0.57 seconds
Started Aug 13 05:37:06 PM PDT 24
Finished Aug 13 05:37:07 PM PDT 24
Peak memory 195480 kb
Host smart-4d5c1e48-e9b5-4791-98d6-78c047db2716
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026658286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2026658286
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.81348309
Short name T1203
Test name
Test status
Simulation time 59202108 ps
CPU time 1.1 seconds
Started Aug 13 05:36:59 PM PDT 24
Finished Aug 13 05:37:00 PM PDT 24
Peak memory 200196 kb
Host smart-666ddf55-dfe5-4262-b9f4-f1bdbdfee922
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81348309 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.81348309
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2214531641
Short name T63
Test name
Test status
Simulation time 44396804 ps
CPU time 0.62 seconds
Started Aug 13 05:37:47 PM PDT 24
Finished Aug 13 05:37:48 PM PDT 24
Peak memory 195580 kb
Host smart-137777c0-cbc4-4b40-bb2f-d0250be9cdef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214531641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2214531641
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.4221651441
Short name T1193
Test name
Test status
Simulation time 41876788 ps
CPU time 0.57 seconds
Started Aug 13 05:36:59 PM PDT 24
Finished Aug 13 05:36:59 PM PDT 24
Peak memory 194468 kb
Host smart-0385936a-7114-4e5c-a5f2-be402ff6e84d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221651441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.4221651441
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3811207237
Short name T61
Test name
Test status
Simulation time 35189662 ps
CPU time 0.75 seconds
Started Aug 13 05:36:48 PM PDT 24
Finished Aug 13 05:36:49 PM PDT 24
Peak memory 197148 kb
Host smart-3ac78743-3319-4f62-a46b-475e52c077f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811207237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.3811207237
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1559685269
Short name T1283
Test name
Test status
Simulation time 259306141 ps
CPU time 1.6 seconds
Started Aug 13 05:36:58 PM PDT 24
Finished Aug 13 05:37:00 PM PDT 24
Peak memory 200144 kb
Host smart-fef0bc2e-1e55-4ee3-a5c6-bb8081a81973
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559685269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1559685269
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.366303516
Short name T1294
Test name
Test status
Simulation time 210687789 ps
CPU time 0.92 seconds
Started Aug 13 05:36:51 PM PDT 24
Finished Aug 13 05:36:52 PM PDT 24
Peak memory 199036 kb
Host smart-fe9aed3f-88b5-4531-987e-7db35a43fbe2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366303516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.366303516
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2149316567
Short name T1189
Test name
Test status
Simulation time 16746270 ps
CPU time 0.56 seconds
Started Aug 13 05:37:22 PM PDT 24
Finished Aug 13 05:37:23 PM PDT 24
Peak memory 194568 kb
Host smart-8bb8940f-ae45-42cd-9e1f-e7c8446cdddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149316567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2149316567
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3677565019
Short name T1208
Test name
Test status
Simulation time 23640524 ps
CPU time 0.55 seconds
Started Aug 13 05:37:12 PM PDT 24
Finished Aug 13 05:37:13 PM PDT 24
Peak memory 194556 kb
Host smart-58a2b8d7-2dfd-4ffd-9fcd-134a6b5f4064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677565019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3677565019
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.59932645
Short name T1267
Test name
Test status
Simulation time 12806561 ps
CPU time 0.58 seconds
Started Aug 13 05:37:27 PM PDT 24
Finished Aug 13 05:37:28 PM PDT 24
Peak memory 194420 kb
Host smart-5743fb8f-fc7d-4544-a5e6-17ba3395d38d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59932645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.59932645
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2475195290
Short name T1277
Test name
Test status
Simulation time 183028497 ps
CPU time 0.56 seconds
Started Aug 13 05:37:32 PM PDT 24
Finished Aug 13 05:37:33 PM PDT 24
Peak memory 194416 kb
Host smart-2185b955-d5ff-4cbd-8f41-cf6d991e010c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475195290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2475195290
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3054482884
Short name T1289
Test name
Test status
Simulation time 32756548 ps
CPU time 0.56 seconds
Started Aug 13 05:37:11 PM PDT 24
Finished Aug 13 05:37:12 PM PDT 24
Peak memory 194568 kb
Host smart-f3a7ca2d-b855-4164-b0af-6247d0724c41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054482884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3054482884
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.371174205
Short name T1286
Test name
Test status
Simulation time 43201718 ps
CPU time 0.59 seconds
Started Aug 13 05:37:28 PM PDT 24
Finished Aug 13 05:37:29 PM PDT 24
Peak memory 194564 kb
Host smart-fc4d5444-8c65-4969-86b1-85d86f2811af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371174205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.371174205
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.891441556
Short name T1299
Test name
Test status
Simulation time 21734501 ps
CPU time 0.57 seconds
Started Aug 13 05:37:37 PM PDT 24
Finished Aug 13 05:37:38 PM PDT 24
Peak memory 194576 kb
Host smart-49d18ee0-59aa-44c4-9fa0-a248cb40b035
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891441556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.891441556
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.1987652810
Short name T1251
Test name
Test status
Simulation time 15305449 ps
CPU time 0.56 seconds
Started Aug 13 05:37:35 PM PDT 24
Finished Aug 13 05:37:36 PM PDT 24
Peak memory 194516 kb
Host smart-7fddd564-165d-46d1-8b6a-dd8957f89b2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987652810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1987652810
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.533799188
Short name T1265
Test name
Test status
Simulation time 62558068 ps
CPU time 0.58 seconds
Started Aug 13 05:37:39 PM PDT 24
Finished Aug 13 05:37:39 PM PDT 24
Peak memory 194548 kb
Host smart-dd97f080-bb39-4aa0-af8a-79735ede4a2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533799188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.533799188
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.1412787435
Short name T1273
Test name
Test status
Simulation time 14428935 ps
CPU time 0.57 seconds
Started Aug 13 05:37:25 PM PDT 24
Finished Aug 13 05:37:25 PM PDT 24
Peak memory 194540 kb
Host smart-a63775b5-28ca-4549-9a76-5703d1226e40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412787435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1412787435
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3765202593
Short name T1239
Test name
Test status
Simulation time 80575663 ps
CPU time 0.72 seconds
Started Aug 13 05:36:48 PM PDT 24
Finished Aug 13 05:36:49 PM PDT 24
Peak memory 198448 kb
Host smart-0a2a2433-2c0e-4a00-851e-f1ca1d353565
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765202593 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3765202593
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3948017670
Short name T56
Test name
Test status
Simulation time 10876379 ps
CPU time 0.54 seconds
Started Aug 13 05:36:46 PM PDT 24
Finished Aug 13 05:36:46 PM PDT 24
Peak memory 195508 kb
Host smart-61f5a585-56a6-4b6c-b26a-25a62dc8117c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948017670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3948017670
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.283288172
Short name T1274
Test name
Test status
Simulation time 14457385 ps
CPU time 0.57 seconds
Started Aug 13 05:37:02 PM PDT 24
Finished Aug 13 05:37:03 PM PDT 24
Peak memory 194544 kb
Host smart-f0c52d91-c8fe-432e-8af6-b1cd3c32b5db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283288172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.283288172
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2478687995
Short name T1308
Test name
Test status
Simulation time 26511062 ps
CPU time 0.74 seconds
Started Aug 13 05:36:47 PM PDT 24
Finished Aug 13 05:36:48 PM PDT 24
Peak memory 197352 kb
Host smart-37a375c0-8458-491f-a652-5bf6076c5d86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478687995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2478687995
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.767444435
Short name T1237
Test name
Test status
Simulation time 138740730 ps
CPU time 2.77 seconds
Started Aug 13 05:36:59 PM PDT 24
Finished Aug 13 05:37:02 PM PDT 24
Peak memory 200224 kb
Host smart-8868609b-eb68-4abb-8eee-eec872499510
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767444435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.767444435
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3305679664
Short name T1256
Test name
Test status
Simulation time 281141209 ps
CPU time 0.96 seconds
Started Aug 13 05:37:16 PM PDT 24
Finished Aug 13 05:37:17 PM PDT 24
Peak memory 199200 kb
Host smart-7879c10c-79f2-418a-8bf8-4370adbb8224
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305679664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3305679664
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.4216385851
Short name T1192
Test name
Test status
Simulation time 71667060 ps
CPU time 0.89 seconds
Started Aug 13 05:36:54 PM PDT 24
Finished Aug 13 05:36:55 PM PDT 24
Peak memory 199936 kb
Host smart-90e234ed-9796-421b-a931-99474c2ea05a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216385851 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.4216385851
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3577076311
Short name T1252
Test name
Test status
Simulation time 20747616 ps
CPU time 0.57 seconds
Started Aug 13 05:37:02 PM PDT 24
Finished Aug 13 05:37:03 PM PDT 24
Peak memory 195496 kb
Host smart-1a12503f-9805-44ba-8e51-4f402178c162
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577076311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3577076311
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1459624007
Short name T1202
Test name
Test status
Simulation time 12257203 ps
CPU time 0.57 seconds
Started Aug 13 05:36:52 PM PDT 24
Finished Aug 13 05:36:53 PM PDT 24
Peak memory 194576 kb
Host smart-25fcaead-c37e-4fa4-aa2e-f9dea3aa05dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459624007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1459624007
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1543515735
Short name T1228
Test name
Test status
Simulation time 26518173 ps
CPU time 0.72 seconds
Started Aug 13 05:36:49 PM PDT 24
Finished Aug 13 05:36:50 PM PDT 24
Peak memory 197192 kb
Host smart-ef7c4cdb-dc3e-4b46-b0ae-a2baaf23448b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543515735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1543515735
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1540450490
Short name T1262
Test name
Test status
Simulation time 223066534 ps
CPU time 1.75 seconds
Started Aug 13 05:36:55 PM PDT 24
Finished Aug 13 05:36:57 PM PDT 24
Peak memory 200196 kb
Host smart-47137fcb-a21d-4c10-8124-e373c3e541b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540450490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1540450490
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.224062400
Short name T73
Test name
Test status
Simulation time 54769284 ps
CPU time 0.97 seconds
Started Aug 13 05:37:01 PM PDT 24
Finished Aug 13 05:37:02 PM PDT 24
Peak memory 199392 kb
Host smart-92d05fee-8fec-43a1-81d7-272ae784c094
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224062400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.224062400
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3395757285
Short name T1205
Test name
Test status
Simulation time 102159287 ps
CPU time 0.88 seconds
Started Aug 13 05:37:00 PM PDT 24
Finished Aug 13 05:37:01 PM PDT 24
Peak memory 199884 kb
Host smart-d8e33b2b-326f-43af-9775-737e923ce201
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395757285 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.3395757285
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1641615650
Short name T1260
Test name
Test status
Simulation time 14437872 ps
CPU time 0.63 seconds
Started Aug 13 05:36:56 PM PDT 24
Finished Aug 13 05:36:57 PM PDT 24
Peak memory 195456 kb
Host smart-362104c3-4bb8-40ed-aee9-eb657b95fad2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641615650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1641615650
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2859039889
Short name T1223
Test name
Test status
Simulation time 16758420 ps
CPU time 0.56 seconds
Started Aug 13 05:37:05 PM PDT 24
Finished Aug 13 05:37:05 PM PDT 24
Peak memory 194496 kb
Host smart-225ae31f-9e08-4dae-9c77-1133afd1d7ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859039889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2859039889
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.73295973
Short name T1275
Test name
Test status
Simulation time 27180952 ps
CPU time 0.73 seconds
Started Aug 13 05:37:21 PM PDT 24
Finished Aug 13 05:37:22 PM PDT 24
Peak memory 197100 kb
Host smart-46f70f5e-8469-4e18-95b7-2431b2befa57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73295973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_o
utstanding.73295973
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2207913086
Short name T1279
Test name
Test status
Simulation time 82613263 ps
CPU time 0.97 seconds
Started Aug 13 05:37:07 PM PDT 24
Finished Aug 13 05:37:09 PM PDT 24
Peak memory 199960 kb
Host smart-cbdc1c05-9da2-493e-8c77-93de2dd36279
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207913086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2207913086
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1608309204
Short name T1243
Test name
Test status
Simulation time 179183785 ps
CPU time 1 seconds
Started Aug 13 05:37:13 PM PDT 24
Finished Aug 13 05:37:14 PM PDT 24
Peak memory 199232 kb
Host smart-e715c945-93ac-420c-ab67-e82b2b8d07b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608309204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1608309204
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.868028602
Short name T1199
Test name
Test status
Simulation time 19374154 ps
CPU time 0.69 seconds
Started Aug 13 05:37:00 PM PDT 24
Finished Aug 13 05:37:01 PM PDT 24
Peak memory 198140 kb
Host smart-12f11e21-1d0b-4dab-9ce1-26f60ae72925
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868028602 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.868028602
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3559810391
Short name T43
Test name
Test status
Simulation time 21328582 ps
CPU time 0.57 seconds
Started Aug 13 05:37:07 PM PDT 24
Finished Aug 13 05:37:08 PM PDT 24
Peak memory 195484 kb
Host smart-0353a11a-ff83-4516-9780-5c20fbb30030
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559810391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3559810391
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.1966460505
Short name T1282
Test name
Test status
Simulation time 32186016 ps
CPU time 0.55 seconds
Started Aug 13 05:37:02 PM PDT 24
Finished Aug 13 05:37:03 PM PDT 24
Peak memory 194568 kb
Host smart-0bfe0097-7656-4bf1-9385-d258685c756b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966460505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1966460505
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.505937986
Short name T1281
Test name
Test status
Simulation time 14953652 ps
CPU time 0.62 seconds
Started Aug 13 05:36:56 PM PDT 24
Finished Aug 13 05:36:56 PM PDT 24
Peak memory 195728 kb
Host smart-bb6644a5-bc97-4b6e-a184-f813df885211
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505937986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_
outstanding.505937986
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.191304728
Short name T1246
Test name
Test status
Simulation time 144552943 ps
CPU time 2.15 seconds
Started Aug 13 05:36:52 PM PDT 24
Finished Aug 13 05:36:54 PM PDT 24
Peak memory 200248 kb
Host smart-84f30dc9-10c1-46ae-be3b-8dcfa3b4394c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191304728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.191304728
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1072371207
Short name T66
Test name
Test status
Simulation time 51052019 ps
CPU time 0.97 seconds
Started Aug 13 05:37:06 PM PDT 24
Finished Aug 13 05:37:07 PM PDT 24
Peak memory 199176 kb
Host smart-7a2cc569-871b-4008-a7a5-4c3b31535343
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072371207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1072371207
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1531676794
Short name T1187
Test name
Test status
Simulation time 26033245 ps
CPU time 0.72 seconds
Started Aug 13 05:37:08 PM PDT 24
Finished Aug 13 05:37:09 PM PDT 24
Peak memory 199132 kb
Host smart-7f147fc4-fb2e-4637-b007-553dada139f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531676794 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1531676794
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2000151826
Short name T53
Test name
Test status
Simulation time 90764821 ps
CPU time 0.61 seconds
Started Aug 13 05:37:16 PM PDT 24
Finished Aug 13 05:37:17 PM PDT 24
Peak memory 195528 kb
Host smart-14efada3-dd17-40e7-8789-7db42c457f2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000151826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2000151826
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1965020062
Short name T1234
Test name
Test status
Simulation time 15165576 ps
CPU time 0.56 seconds
Started Aug 13 05:37:08 PM PDT 24
Finished Aug 13 05:37:09 PM PDT 24
Peak memory 194536 kb
Host smart-63532c56-c206-4833-99db-d8e598b94d6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965020062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1965020062
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2667407590
Short name T57
Test name
Test status
Simulation time 18519956 ps
CPU time 0.76 seconds
Started Aug 13 05:37:00 PM PDT 24
Finished Aug 13 05:37:01 PM PDT 24
Peak memory 197320 kb
Host smart-c8e55ea5-7437-4498-a45d-94dc78e7002d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667407590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2667407590
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.954913725
Short name T1231
Test name
Test status
Simulation time 26592444 ps
CPU time 1.29 seconds
Started Aug 13 05:37:05 PM PDT 24
Finished Aug 13 05:37:06 PM PDT 24
Peak memory 200212 kb
Host smart-830eda9c-81e1-4b6b-bd33-fac1e6e7f402
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954913725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.954913725
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/default/0.uart_alert_test.3877389909
Short name T377
Test name
Test status
Simulation time 35199628 ps
CPU time 0.54 seconds
Started Aug 13 05:13:47 PM PDT 24
Finished Aug 13 05:13:48 PM PDT 24
Peak memory 195132 kb
Host smart-f3850597-9169-452e-9d4b-ba9893873e9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877389909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.3877389909
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3477143658
Short name T1156
Test name
Test status
Simulation time 168516334656 ps
CPU time 253.32 seconds
Started Aug 13 05:13:37 PM PDT 24
Finished Aug 13 05:17:50 PM PDT 24
Peak memory 200856 kb
Host smart-25602fdb-7bf6-453c-be24-1d2621a66248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477143658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3477143658
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1163720707
Short name T849
Test name
Test status
Simulation time 25066462645 ps
CPU time 27.81 seconds
Started Aug 13 05:13:33 PM PDT 24
Finished Aug 13 05:14:01 PM PDT 24
Peak memory 200756 kb
Host smart-4a698208-b766-4892-83c9-8d1e3ff7995c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163720707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1163720707
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.4273503568
Short name T1068
Test name
Test status
Simulation time 18997558383 ps
CPU time 28.99 seconds
Started Aug 13 05:13:41 PM PDT 24
Finished Aug 13 05:14:10 PM PDT 24
Peak memory 200880 kb
Host smart-e2e810e9-2070-440a-bfab-80473f183225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273503568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.4273503568
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.2980765400
Short name T578
Test name
Test status
Simulation time 36860729936 ps
CPU time 30.85 seconds
Started Aug 13 05:13:50 PM PDT 24
Finished Aug 13 05:14:21 PM PDT 24
Peak memory 199936 kb
Host smart-207e6735-902c-4f07-bad0-37e3ea10fece
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980765400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2980765400
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2464894098
Short name T987
Test name
Test status
Simulation time 154800790208 ps
CPU time 480.27 seconds
Started Aug 13 05:13:42 PM PDT 24
Finished Aug 13 05:21:43 PM PDT 24
Peak memory 200784 kb
Host smart-2c16fe08-a231-435a-b1f5-73c3a6ce5f07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2464894098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2464894098
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2937638942
Short name T1052
Test name
Test status
Simulation time 3942694688 ps
CPU time 3.64 seconds
Started Aug 13 05:13:47 PM PDT 24
Finished Aug 13 05:13:50 PM PDT 24
Peak memory 199252 kb
Host smart-d1aa792b-eac4-4e1c-a71a-6a0373fc3368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937638942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2937638942
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.783435822
Short name T1102
Test name
Test status
Simulation time 106597407501 ps
CPU time 90.96 seconds
Started Aug 13 05:13:39 PM PDT 24
Finished Aug 13 05:15:11 PM PDT 24
Peak memory 209252 kb
Host smart-29b63aab-3166-44da-b2c6-a5bcfb0bd28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783435822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.783435822
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.2861036619
Short name T589
Test name
Test status
Simulation time 4713300866 ps
CPU time 95.52 seconds
Started Aug 13 05:13:39 PM PDT 24
Finished Aug 13 05:15:14 PM PDT 24
Peak memory 200768 kb
Host smart-5fa889fc-fc8c-47bf-b8fc-4a6f941889e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2861036619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2861036619
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.333412134
Short name T937
Test name
Test status
Simulation time 1380022426 ps
CPU time 3.17 seconds
Started Aug 13 05:13:43 PM PDT 24
Finished Aug 13 05:13:46 PM PDT 24
Peak memory 197668 kb
Host smart-2436e2ed-8f61-428d-989b-e6218d1734ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=333412134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.333412134
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.1769333956
Short name T461
Test name
Test status
Simulation time 73397480291 ps
CPU time 40.41 seconds
Started Aug 13 05:13:41 PM PDT 24
Finished Aug 13 05:14:22 PM PDT 24
Peak memory 200956 kb
Host smart-deb56a30-dec7-4a7c-bb17-2d4d5a2cd8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769333956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.1769333956
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.2154353048
Short name T338
Test name
Test status
Simulation time 54055985972 ps
CPU time 6.04 seconds
Started Aug 13 05:13:45 PM PDT 24
Finished Aug 13 05:13:51 PM PDT 24
Peak memory 195392 kb
Host smart-de08a749-896f-4597-b734-6dbbfad01352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154353048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2154353048
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.1421373303
Short name T1077
Test name
Test status
Simulation time 658919591 ps
CPU time 1.89 seconds
Started Aug 13 05:13:33 PM PDT 24
Finished Aug 13 05:13:35 PM PDT 24
Peak memory 200592 kb
Host smart-e9607a54-4641-41e4-a5b5-2eaa6792c42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421373303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1421373303
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.985765417
Short name T523
Test name
Test status
Simulation time 161310452586 ps
CPU time 98.97 seconds
Started Aug 13 05:13:51 PM PDT 24
Finished Aug 13 05:15:30 PM PDT 24
Peak memory 200804 kb
Host smart-0744bf7d-5da8-49b6-8c80-363dd715c3ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985765417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.985765417
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.1697097139
Short name T436
Test name
Test status
Simulation time 1055246014 ps
CPU time 44.29 seconds
Started Aug 13 05:13:41 PM PDT 24
Finished Aug 13 05:14:25 PM PDT 24
Peak memory 209116 kb
Host smart-556314d1-30c2-40d5-8fd3-7ccf48210a37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697097139 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.1697097139
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.566350813
Short name T1116
Test name
Test status
Simulation time 6932384459 ps
CPU time 22.92 seconds
Started Aug 13 05:13:39 PM PDT 24
Finished Aug 13 05:14:02 PM PDT 24
Peak memory 200164 kb
Host smart-fcd31c03-d3f5-44d3-a5ed-b54109971fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566350813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.566350813
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.952029333
Short name T284
Test name
Test status
Simulation time 49011204144 ps
CPU time 16.96 seconds
Started Aug 13 05:13:33 PM PDT 24
Finished Aug 13 05:13:50 PM PDT 24
Peak memory 200812 kb
Host smart-c454cfef-c12f-42fa-9f77-716e32927e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952029333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.952029333
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.1024867491
Short name T795
Test name
Test status
Simulation time 25256208 ps
CPU time 0.57 seconds
Started Aug 13 05:13:47 PM PDT 24
Finished Aug 13 05:13:48 PM PDT 24
Peak memory 196156 kb
Host smart-644ce5b7-e150-4cb2-89d0-925b6a78d50f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024867491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1024867491
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.335003629
Short name T160
Test name
Test status
Simulation time 123559974879 ps
CPU time 96.91 seconds
Started Aug 13 05:13:43 PM PDT 24
Finished Aug 13 05:15:20 PM PDT 24
Peak memory 200768 kb
Host smart-fcb5dd87-9ac1-4f0c-971e-88367be4e016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335003629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.335003629
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.3376781631
Short name T135
Test name
Test status
Simulation time 166628332642 ps
CPU time 17.15 seconds
Started Aug 13 05:13:40 PM PDT 24
Finished Aug 13 05:13:57 PM PDT 24
Peak memory 200884 kb
Host smart-94828339-06c5-4822-a1fb-acfd95a528f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376781631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3376781631
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.560147463
Short name T378
Test name
Test status
Simulation time 3794938912 ps
CPU time 6.18 seconds
Started Aug 13 05:13:40 PM PDT 24
Finished Aug 13 05:13:46 PM PDT 24
Peak memory 197516 kb
Host smart-b940ffcd-7ca8-42ad-b89b-c62e68d55ee3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560147463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.560147463
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2647728618
Short name T2
Test name
Test status
Simulation time 311284786665 ps
CPU time 340.02 seconds
Started Aug 13 05:13:39 PM PDT 24
Finished Aug 13 05:19:19 PM PDT 24
Peak memory 200928 kb
Host smart-b05245e6-3f02-4616-bda7-ced3ece32fd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2647728618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2647728618
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.2407659386
Short name T710
Test name
Test status
Simulation time 1691822978 ps
CPU time 3.52 seconds
Started Aug 13 05:13:39 PM PDT 24
Finished Aug 13 05:13:43 PM PDT 24
Peak memory 198164 kb
Host smart-62c9e361-a849-42f2-a5f4-af0b57932474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407659386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2407659386
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.3059353971
Short name T582
Test name
Test status
Simulation time 3587964912 ps
CPU time 6.71 seconds
Started Aug 13 05:13:51 PM PDT 24
Finished Aug 13 05:13:58 PM PDT 24
Peak memory 196024 kb
Host smart-f16f941c-4cca-4b5a-be7d-175bad1ff688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059353971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3059353971
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.1349456341
Short name T791
Test name
Test status
Simulation time 15394751302 ps
CPU time 792.68 seconds
Started Aug 13 05:13:51 PM PDT 24
Finished Aug 13 05:27:04 PM PDT 24
Peak memory 200832 kb
Host smart-074a14db-01a5-4c2b-9e80-20daf80ac82d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1349456341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1349456341
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.143756694
Short name T374
Test name
Test status
Simulation time 6650887864 ps
CPU time 65.41 seconds
Started Aug 13 05:13:42 PM PDT 24
Finished Aug 13 05:14:47 PM PDT 24
Peak memory 199948 kb
Host smart-d09171d1-7e9d-405f-af7a-07c679abe247
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=143756694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.143756694
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.438966860
Short name T679
Test name
Test status
Simulation time 87465665293 ps
CPU time 30.32 seconds
Started Aug 13 05:13:42 PM PDT 24
Finished Aug 13 05:14:12 PM PDT 24
Peak memory 200932 kb
Host smart-9a22d9a2-175c-4554-8bcf-2ec81136fea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438966860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.438966860
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.1865960650
Short name T504
Test name
Test status
Simulation time 36730845075 ps
CPU time 9.42 seconds
Started Aug 13 05:13:48 PM PDT 24
Finished Aug 13 05:13:58 PM PDT 24
Peak memory 196840 kb
Host smart-4e487060-34bd-41ae-ae01-6c699a9ee898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865960650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1865960650
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.753133924
Short name T76
Test name
Test status
Simulation time 62131413 ps
CPU time 0.86 seconds
Started Aug 13 05:13:41 PM PDT 24
Finished Aug 13 05:13:42 PM PDT 24
Peak memory 218880 kb
Host smart-7c56b382-c18d-4321-97bb-4a2840533c9a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753133924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.753133924
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.2129019993
Short name T1030
Test name
Test status
Simulation time 488519443 ps
CPU time 1.64 seconds
Started Aug 13 05:13:39 PM PDT 24
Finished Aug 13 05:13:41 PM PDT 24
Peak memory 199300 kb
Host smart-2871147b-360e-4d79-a4cb-c77a09122d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129019993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2129019993
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2306273317
Short name T926
Test name
Test status
Simulation time 4358845027 ps
CPU time 26.35 seconds
Started Aug 13 05:13:40 PM PDT 24
Finished Aug 13 05:14:06 PM PDT 24
Peak memory 209380 kb
Host smart-e8fde824-a076-4978-b569-c80ff86957ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306273317 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2306273317
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.601568016
Short name T967
Test name
Test status
Simulation time 838893372 ps
CPU time 2.8 seconds
Started Aug 13 05:13:48 PM PDT 24
Finished Aug 13 05:13:51 PM PDT 24
Peak memory 199880 kb
Host smart-0f7df458-ed68-4db4-b393-788d18729607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601568016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.601568016
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1965760342
Short name T263
Test name
Test status
Simulation time 57631129870 ps
CPU time 67.64 seconds
Started Aug 13 05:13:39 PM PDT 24
Finished Aug 13 05:14:46 PM PDT 24
Peak memory 200900 kb
Host smart-87261934-bada-4df1-86d9-a5b49436ac5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965760342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1965760342
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.3818428265
Short name T584
Test name
Test status
Simulation time 12854628 ps
CPU time 0.56 seconds
Started Aug 13 05:13:57 PM PDT 24
Finished Aug 13 05:13:58 PM PDT 24
Peak memory 195152 kb
Host smart-fa24c072-2fa0-4dcf-84e6-8185e1358532
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818428265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3818428265
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.347895376
Short name T971
Test name
Test status
Simulation time 37811471296 ps
CPU time 47.97 seconds
Started Aug 13 05:13:59 PM PDT 24
Finished Aug 13 05:14:47 PM PDT 24
Peak memory 200760 kb
Host smart-70dcf6ae-f9c9-4c8b-8e67-2b30a5236184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347895376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.347895376
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.809162465
Short name T226
Test name
Test status
Simulation time 72608227980 ps
CPU time 23.56 seconds
Started Aug 13 05:13:53 PM PDT 24
Finished Aug 13 05:14:17 PM PDT 24
Peak memory 201072 kb
Host smart-6bf4274d-9aa1-42e3-878c-ffa251b3c0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809162465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.809162465
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.1134413606
Short name T402
Test name
Test status
Simulation time 53469803264 ps
CPU time 88.62 seconds
Started Aug 13 05:14:15 PM PDT 24
Finished Aug 13 05:15:44 PM PDT 24
Peak memory 200940 kb
Host smart-159bae5a-f1aa-4820-93d5-694430f2ccfd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134413606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1134413606
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.838703372
Short name T979
Test name
Test status
Simulation time 125183003228 ps
CPU time 333.88 seconds
Started Aug 13 05:13:52 PM PDT 24
Finished Aug 13 05:19:26 PM PDT 24
Peak memory 200900 kb
Host smart-d63bfe7d-7287-471e-b63e-72c578e66b05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=838703372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.838703372
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3416149357
Short name T1065
Test name
Test status
Simulation time 9551541525 ps
CPU time 3.14 seconds
Started Aug 13 05:13:53 PM PDT 24
Finished Aug 13 05:13:56 PM PDT 24
Peak memory 200588 kb
Host smart-0120437b-05aa-4401-89b8-d85bb5546a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416149357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3416149357
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.2906329361
Short name T703
Test name
Test status
Simulation time 29647902438 ps
CPU time 54.31 seconds
Started Aug 13 05:14:00 PM PDT 24
Finished Aug 13 05:14:55 PM PDT 24
Peak memory 200268 kb
Host smart-15a62fce-0495-4e46-91b1-8e5feb4e3cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906329361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2906329361
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.373174644
Short name T964
Test name
Test status
Simulation time 11764708773 ps
CPU time 566.84 seconds
Started Aug 13 05:13:53 PM PDT 24
Finished Aug 13 05:23:20 PM PDT 24
Peak memory 200904 kb
Host smart-2e841a98-6c3a-4c8a-b1c2-87bdb35133cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=373174644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.373174644
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2136914870
Short name T375
Test name
Test status
Simulation time 5947603313 ps
CPU time 11.56 seconds
Started Aug 13 05:13:53 PM PDT 24
Finished Aug 13 05:14:05 PM PDT 24
Peak memory 198872 kb
Host smart-a2d0854d-593f-4870-9110-f4b9ff6c0163
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2136914870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2136914870
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.49596136
Short name T163
Test name
Test status
Simulation time 98233966347 ps
CPU time 41.76 seconds
Started Aug 13 05:14:12 PM PDT 24
Finished Aug 13 05:14:54 PM PDT 24
Peak memory 200928 kb
Host smart-d180052e-f4ad-48f4-9ccb-6d0dc442de79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49596136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.49596136
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2977145481
Short name T871
Test name
Test status
Simulation time 36922493628 ps
CPU time 7.16 seconds
Started Aug 13 05:13:52 PM PDT 24
Finished Aug 13 05:14:00 PM PDT 24
Peak memory 196880 kb
Host smart-10b97ee5-184d-4885-a6f4-af7a3e98e6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977145481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2977145481
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3681670101
Short name T453
Test name
Test status
Simulation time 572738724 ps
CPU time 1.32 seconds
Started Aug 13 05:13:53 PM PDT 24
Finished Aug 13 05:13:55 PM PDT 24
Peak memory 199480 kb
Host smart-0c2730d3-c381-485c-933e-ac076b3c973e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681670101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3681670101
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.3363652988
Short name T646
Test name
Test status
Simulation time 3268710700 ps
CPU time 24.27 seconds
Started Aug 13 05:14:00 PM PDT 24
Finished Aug 13 05:14:25 PM PDT 24
Peak memory 217368 kb
Host smart-3b8eb876-f5cf-45bd-9c07-bb14c0de127e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363652988 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.3363652988
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3943282306
Short name T905
Test name
Test status
Simulation time 637204749 ps
CPU time 2.5 seconds
Started Aug 13 05:14:00 PM PDT 24
Finished Aug 13 05:14:03 PM PDT 24
Peak memory 199620 kb
Host smart-f5389958-d436-4c53-aff6-365ea5e6986c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943282306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3943282306
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.959088779
Short name T1010
Test name
Test status
Simulation time 8726793907 ps
CPU time 13.97 seconds
Started Aug 13 05:13:56 PM PDT 24
Finished Aug 13 05:14:10 PM PDT 24
Peak memory 200780 kb
Host smart-289eb5a1-0717-47ed-813f-a12eff0f56ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959088779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.959088779
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3639080567
Short name T255
Test name
Test status
Simulation time 110024905892 ps
CPU time 75.01 seconds
Started Aug 13 05:16:40 PM PDT 24
Finished Aug 13 05:17:55 PM PDT 24
Peak memory 200832 kb
Host smart-6be93c94-7e6c-4564-9e4e-a2e1c25154f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639080567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3639080567
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.1210750809
Short name T452
Test name
Test status
Simulation time 141440900870 ps
CPU time 58.18 seconds
Started Aug 13 05:16:40 PM PDT 24
Finished Aug 13 05:17:38 PM PDT 24
Peak memory 200852 kb
Host smart-80bba99d-3c69-40f7-b6bb-cb367758f32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210750809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1210750809
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2721990530
Short name T257
Test name
Test status
Simulation time 182351314407 ps
CPU time 55.65 seconds
Started Aug 13 05:16:41 PM PDT 24
Finished Aug 13 05:17:37 PM PDT 24
Peak memory 200836 kb
Host smart-458066bd-a4ee-4346-904f-15e98e938ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721990530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2721990530
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.3969618769
Short name T125
Test name
Test status
Simulation time 26309095148 ps
CPU time 50.65 seconds
Started Aug 13 05:16:43 PM PDT 24
Finished Aug 13 05:17:34 PM PDT 24
Peak memory 200864 kb
Host smart-ddda80c4-7143-4515-a974-f95562b7a9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969618769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3969618769
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.682321538
Short name T706
Test name
Test status
Simulation time 72610769337 ps
CPU time 33.21 seconds
Started Aug 13 05:16:41 PM PDT 24
Finished Aug 13 05:17:15 PM PDT 24
Peak memory 200872 kb
Host smart-ad5649d8-2c05-4dd6-ae8f-e2c10a791127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682321538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.682321538
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.2139414009
Short name T572
Test name
Test status
Simulation time 48321816899 ps
CPU time 36.5 seconds
Started Aug 13 05:16:41 PM PDT 24
Finished Aug 13 05:17:18 PM PDT 24
Peak memory 200868 kb
Host smart-2ae803b7-8cef-46ca-a63b-e8569d1d653e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139414009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.2139414009
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.4160064399
Short name T250
Test name
Test status
Simulation time 259718154639 ps
CPU time 71.41 seconds
Started Aug 13 05:16:40 PM PDT 24
Finished Aug 13 05:17:51 PM PDT 24
Peak memory 200940 kb
Host smart-43b6d7ad-3f99-4188-b9d9-a7885c148996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160064399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.4160064399
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1303526477
Short name T1170
Test name
Test status
Simulation time 151621252433 ps
CPU time 67.02 seconds
Started Aug 13 05:16:40 PM PDT 24
Finished Aug 13 05:17:47 PM PDT 24
Peak memory 200848 kb
Host smart-e96b36ff-6a57-4abf-a2c4-cc7ab8b1a7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303526477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1303526477
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.353809702
Short name T693
Test name
Test status
Simulation time 62785895809 ps
CPU time 37.06 seconds
Started Aug 13 05:16:42 PM PDT 24
Finished Aug 13 05:17:20 PM PDT 24
Peak memory 200788 kb
Host smart-e78b3165-5f8a-4a24-8a9c-3e896134d605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353809702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.353809702
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2029316315
Short name T1112
Test name
Test status
Simulation time 14032638 ps
CPU time 0.58 seconds
Started Aug 13 05:14:09 PM PDT 24
Finished Aug 13 05:14:10 PM PDT 24
Peak memory 195688 kb
Host smart-c98186c4-2c98-4a20-a4ed-4689a561c5a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029316315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2029316315
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.4157664787
Short name T1177
Test name
Test status
Simulation time 28825523186 ps
CPU time 22.28 seconds
Started Aug 13 05:14:05 PM PDT 24
Finished Aug 13 05:14:27 PM PDT 24
Peak memory 200784 kb
Host smart-9e9424a2-372c-4d4e-a271-73c0ad3b6655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157664787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.4157664787
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1366175292
Short name T1185
Test name
Test status
Simulation time 24061488669 ps
CPU time 23.62 seconds
Started Aug 13 05:14:05 PM PDT 24
Finished Aug 13 05:14:29 PM PDT 24
Peak memory 200888 kb
Host smart-8b9acafa-6aaa-4a0e-8ed4-0727d477f534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366175292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1366175292
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.2110966656
Short name T1095
Test name
Test status
Simulation time 36401630136 ps
CPU time 53.46 seconds
Started Aug 13 05:14:02 PM PDT 24
Finished Aug 13 05:14:56 PM PDT 24
Peak memory 200820 kb
Host smart-ea70ca26-1a74-44bd-b97f-508d26aaae03
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110966656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2110966656
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3498260323
Short name T276
Test name
Test status
Simulation time 85656317152 ps
CPU time 78.35 seconds
Started Aug 13 05:14:06 PM PDT 24
Finished Aug 13 05:15:24 PM PDT 24
Peak memory 200872 kb
Host smart-6011f3e2-3ae1-404a-9ec3-6154c436955b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3498260323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3498260323
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.3328794072
Short name T547
Test name
Test status
Simulation time 9405572177 ps
CPU time 15.06 seconds
Started Aug 13 05:13:57 PM PDT 24
Finished Aug 13 05:14:13 PM PDT 24
Peak memory 200888 kb
Host smart-6c09df48-3edb-4627-ba56-c6dbe021b03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328794072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.3328794072
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1053317434
Short name T252
Test name
Test status
Simulation time 101091098854 ps
CPU time 41.58 seconds
Started Aug 13 05:14:00 PM PDT 24
Finished Aug 13 05:14:42 PM PDT 24
Peak memory 199832 kb
Host smart-0b1616ae-3d49-4807-888a-a7d7caf089c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053317434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1053317434
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.2045781422
Short name T875
Test name
Test status
Simulation time 24339178075 ps
CPU time 1486.26 seconds
Started Aug 13 05:14:02 PM PDT 24
Finished Aug 13 05:38:48 PM PDT 24
Peak memory 200840 kb
Host smart-435bea43-ae78-457d-a4d5-c930df0e0070
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2045781422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2045781422
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.360199641
Short name T722
Test name
Test status
Simulation time 6116320068 ps
CPU time 25.38 seconds
Started Aug 13 05:14:01 PM PDT 24
Finished Aug 13 05:14:26 PM PDT 24
Peak memory 200004 kb
Host smart-5a57f44e-1c67-4046-a61a-bdc8d50a40e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=360199641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.360199641
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2986090790
Short name T1158
Test name
Test status
Simulation time 4448646423 ps
CPU time 2.59 seconds
Started Aug 13 05:14:09 PM PDT 24
Finished Aug 13 05:14:12 PM PDT 24
Peak memory 197300 kb
Host smart-517eba9a-018a-4716-a6a8-6635714286ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986090790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2986090790
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2805881212
Short name T558
Test name
Test status
Simulation time 539170271 ps
CPU time 1.31 seconds
Started Aug 13 05:14:00 PM PDT 24
Finished Aug 13 05:14:02 PM PDT 24
Peak memory 200780 kb
Host smart-50a87911-419c-4ca1-9238-067a46c07f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805881212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2805881212
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.3714157361
Short name T789
Test name
Test status
Simulation time 75769913733 ps
CPU time 66.57 seconds
Started Aug 13 05:14:01 PM PDT 24
Finished Aug 13 05:15:08 PM PDT 24
Peak memory 200864 kb
Host smart-ea3da957-58df-4243-953d-ee45adce53fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714157361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3714157361
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.1109732529
Short name T752
Test name
Test status
Simulation time 9885138171 ps
CPU time 24.43 seconds
Started Aug 13 05:14:09 PM PDT 24
Finished Aug 13 05:14:34 PM PDT 24
Peak memory 209212 kb
Host smart-3a9d9780-e993-4d75-909c-f994572ffd46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109732529 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1109732529
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2347677075
Short name T554
Test name
Test status
Simulation time 654891907 ps
CPU time 1.97 seconds
Started Aug 13 05:14:01 PM PDT 24
Finished Aug 13 05:14:03 PM PDT 24
Peak memory 199592 kb
Host smart-697bf0f5-8fe1-4ee5-9699-3b79e78de5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347677075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2347677075
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.85037952
Short name T995
Test name
Test status
Simulation time 24349765621 ps
CPU time 20.77 seconds
Started Aug 13 05:14:00 PM PDT 24
Finished Aug 13 05:14:21 PM PDT 24
Peak memory 200832 kb
Host smart-bf1e0998-2ee0-449f-8189-165efb3ad5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85037952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.85037952
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1104807204
Short name T1121
Test name
Test status
Simulation time 92643803307 ps
CPU time 116.6 seconds
Started Aug 13 05:16:39 PM PDT 24
Finished Aug 13 05:18:36 PM PDT 24
Peak memory 200804 kb
Host smart-699473bf-1643-43f9-afac-93fbe2208a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104807204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1104807204
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.776381610
Short name T1064
Test name
Test status
Simulation time 24586221555 ps
CPU time 10.76 seconds
Started Aug 13 05:16:42 PM PDT 24
Finished Aug 13 05:16:53 PM PDT 24
Peak memory 200944 kb
Host smart-8396e7f0-d2cf-4b4f-b0eb-883a95536d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776381610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.776381610
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3878442845
Short name T1085
Test name
Test status
Simulation time 102997638073 ps
CPU time 76.01 seconds
Started Aug 13 05:16:43 PM PDT 24
Finished Aug 13 05:17:59 PM PDT 24
Peak memory 200828 kb
Host smart-0efce426-81b4-413f-8014-f524583b373f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878442845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3878442845
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1471268477
Short name T424
Test name
Test status
Simulation time 37707550509 ps
CPU time 30.18 seconds
Started Aug 13 05:16:43 PM PDT 24
Finished Aug 13 05:17:14 PM PDT 24
Peak memory 200924 kb
Host smart-2a8cb235-7750-4141-904e-b3090d4c97ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471268477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1471268477
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.319977172
Short name T1117
Test name
Test status
Simulation time 99208478694 ps
CPU time 68.77 seconds
Started Aug 13 05:16:46 PM PDT 24
Finished Aug 13 05:17:55 PM PDT 24
Peak memory 200900 kb
Host smart-b814dd93-b47c-4b63-bdd2-83a5bc9b173e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319977172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.319977172
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.1122531736
Short name T681
Test name
Test status
Simulation time 13477814220 ps
CPU time 54.44 seconds
Started Aug 13 05:16:43 PM PDT 24
Finished Aug 13 05:17:37 PM PDT 24
Peak memory 200876 kb
Host smart-65aa41d6-4f1d-4b45-b7a6-9b08bdf3908b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122531736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1122531736
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.1274369181
Short name T657
Test name
Test status
Simulation time 103270821428 ps
CPU time 41.93 seconds
Started Aug 13 05:16:46 PM PDT 24
Finished Aug 13 05:17:28 PM PDT 24
Peak memory 200808 kb
Host smart-62f4dd1d-3d60-4d88-a520-73c2911be795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274369181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1274369181
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1225125355
Short name T143
Test name
Test status
Simulation time 29815709031 ps
CPU time 30.57 seconds
Started Aug 13 05:16:42 PM PDT 24
Finished Aug 13 05:17:12 PM PDT 24
Peak memory 200828 kb
Host smart-8cc2f001-8c4d-469e-93ce-f98626863d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225125355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1225125355
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3381005188
Short name T508
Test name
Test status
Simulation time 12229580 ps
CPU time 0.58 seconds
Started Aug 13 05:14:03 PM PDT 24
Finished Aug 13 05:14:03 PM PDT 24
Peak memory 196520 kb
Host smart-6de95d88-2821-4bac-977d-a42fd313fcc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381005188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3381005188
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2814744603
Short name T1047
Test name
Test status
Simulation time 27836049886 ps
CPU time 40.81 seconds
Started Aug 13 05:14:01 PM PDT 24
Finished Aug 13 05:14:42 PM PDT 24
Peak memory 200780 kb
Host smart-2f413400-bf5f-41c9-a120-97bf40264833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814744603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2814744603
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2950078298
Short name T515
Test name
Test status
Simulation time 103756924104 ps
CPU time 81.87 seconds
Started Aug 13 05:14:00 PM PDT 24
Finished Aug 13 05:15:23 PM PDT 24
Peak memory 200924 kb
Host smart-36539bfd-1556-48d1-9a94-8976a1149862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950078298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2950078298
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.18154714
Short name T980
Test name
Test status
Simulation time 200076003098 ps
CPU time 148.82 seconds
Started Aug 13 05:14:05 PM PDT 24
Finished Aug 13 05:16:34 PM PDT 24
Peak memory 200820 kb
Host smart-27e66f9d-6a62-4992-8db3-b6b852a258c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18154714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.18154714
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1586467890
Short name T604
Test name
Test status
Simulation time 47932046648 ps
CPU time 299.75 seconds
Started Aug 13 05:14:00 PM PDT 24
Finished Aug 13 05:19:00 PM PDT 24
Peak memory 200876 kb
Host smart-45bbe82b-fe73-4bcb-b2e8-b2973ae727ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1586467890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1586467890
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.2642947725
Short name T555
Test name
Test status
Simulation time 4107330171 ps
CPU time 7.81 seconds
Started Aug 13 05:14:04 PM PDT 24
Finished Aug 13 05:14:12 PM PDT 24
Peak memory 198784 kb
Host smart-cf1389ee-ceb9-4cc2-b215-9b07eafd84ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642947725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2642947725
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.1806285353
Short name T834
Test name
Test status
Simulation time 79398389738 ps
CPU time 39.55 seconds
Started Aug 13 05:14:09 PM PDT 24
Finished Aug 13 05:14:49 PM PDT 24
Peak memory 209148 kb
Host smart-7e2c1489-5e5a-485c-b57c-a37b63c7cd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806285353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1806285353
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.119727652
Short name T1153
Test name
Test status
Simulation time 10964423207 ps
CPU time 281.96 seconds
Started Aug 13 05:14:05 PM PDT 24
Finished Aug 13 05:18:47 PM PDT 24
Peak memory 200940 kb
Host smart-795cfb06-9e23-4711-8d80-640a4bbe8de3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=119727652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.119727652
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.4055007271
Short name T78
Test name
Test status
Simulation time 3268792318 ps
CPU time 5.71 seconds
Started Aug 13 05:14:02 PM PDT 24
Finished Aug 13 05:14:08 PM PDT 24
Peak memory 199868 kb
Host smart-817b7a39-6ca0-45b4-ad7e-8932f0a95e0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4055007271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.4055007271
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.866279067
Short name T334
Test name
Test status
Simulation time 12473994112 ps
CPU time 20 seconds
Started Aug 13 05:14:17 PM PDT 24
Finished Aug 13 05:14:38 PM PDT 24
Peak memory 200900 kb
Host smart-acd0cf3a-802a-4e63-b31d-c20d015dea69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866279067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.866279067
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.2516425055
Short name T765
Test name
Test status
Simulation time 40899998737 ps
CPU time 60.55 seconds
Started Aug 13 05:14:10 PM PDT 24
Finished Aug 13 05:15:11 PM PDT 24
Peak memory 196796 kb
Host smart-37c6f818-3b1d-4c6c-b644-21e09704938e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516425055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2516425055
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2457426581
Short name T410
Test name
Test status
Simulation time 273071686 ps
CPU time 1.3 seconds
Started Aug 13 05:14:03 PM PDT 24
Finished Aug 13 05:14:04 PM PDT 24
Peak memory 199876 kb
Host smart-090b803d-def8-41d4-9c2f-d564143fa107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457426581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2457426581
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.3166618730
Short name T916
Test name
Test status
Simulation time 422724418563 ps
CPU time 342.77 seconds
Started Aug 13 05:13:59 PM PDT 24
Finished Aug 13 05:19:42 PM PDT 24
Peak memory 200776 kb
Host smart-c64e7840-0ab7-4c3d-9f43-598d757b2553
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166618730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3166618730
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1206518803
Short name T790
Test name
Test status
Simulation time 11307136764 ps
CPU time 33.24 seconds
Started Aug 13 05:14:08 PM PDT 24
Finished Aug 13 05:14:42 PM PDT 24
Peak memory 216864 kb
Host smart-d182172e-8eb8-4716-8268-04e7c4debf29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206518803 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1206518803
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.660164695
Short name T398
Test name
Test status
Simulation time 1883027665 ps
CPU time 2.41 seconds
Started Aug 13 05:14:06 PM PDT 24
Finished Aug 13 05:14:09 PM PDT 24
Peak memory 200032 kb
Host smart-0b8abf56-00a3-496a-a309-30650e9d150d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660164695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.660164695
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.3721511522
Short name T903
Test name
Test status
Simulation time 8049331980 ps
CPU time 10.69 seconds
Started Aug 13 05:14:01 PM PDT 24
Finished Aug 13 05:14:12 PM PDT 24
Peak memory 198816 kb
Host smart-abadc8f3-f097-41c8-bed0-8456a7ef537e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721511522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3721511522
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1606448820
Short name T170
Test name
Test status
Simulation time 9970140951 ps
CPU time 16.52 seconds
Started Aug 13 05:16:43 PM PDT 24
Finished Aug 13 05:16:59 PM PDT 24
Peak memory 200776 kb
Host smart-4c4d2160-2b16-49b7-ac4d-35c3a6808e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606448820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1606448820
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.762801350
Short name T676
Test name
Test status
Simulation time 75726998831 ps
CPU time 36.17 seconds
Started Aug 13 05:16:41 PM PDT 24
Finished Aug 13 05:17:17 PM PDT 24
Peak memory 200768 kb
Host smart-5940255e-6fc5-47a0-ad84-3800640c2254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762801350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.762801350
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2096296676
Short name T233
Test name
Test status
Simulation time 224068432691 ps
CPU time 190.59 seconds
Started Aug 13 05:16:43 PM PDT 24
Finished Aug 13 05:19:54 PM PDT 24
Peak memory 200768 kb
Host smart-ee685176-78cb-461c-b2cc-011ca0d8eb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096296676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2096296676
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.621646692
Short name T197
Test name
Test status
Simulation time 130663327141 ps
CPU time 219.46 seconds
Started Aug 13 05:16:45 PM PDT 24
Finished Aug 13 05:20:25 PM PDT 24
Peak memory 200884 kb
Host smart-a8fb0d41-62ef-4fcf-93b5-4d41d6c8114b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621646692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.621646692
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2634490265
Short name T798
Test name
Test status
Simulation time 100009829659 ps
CPU time 74.55 seconds
Started Aug 13 05:16:45 PM PDT 24
Finished Aug 13 05:17:59 PM PDT 24
Peak memory 200816 kb
Host smart-5b28afa0-0b39-4aae-9044-2df7c8f36862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634490265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2634490265
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.683911649
Short name T221
Test name
Test status
Simulation time 38361403572 ps
CPU time 17.3 seconds
Started Aug 13 05:16:41 PM PDT 24
Finished Aug 13 05:16:58 PM PDT 24
Peak memory 200932 kb
Host smart-515446a8-490e-417a-9b86-dad8603baf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683911649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.683911649
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.367665044
Short name T552
Test name
Test status
Simulation time 39744654435 ps
CPU time 22.41 seconds
Started Aug 13 05:16:42 PM PDT 24
Finished Aug 13 05:17:05 PM PDT 24
Peak memory 200936 kb
Host smart-16167cf9-8df3-48e2-ac3c-0a0fd4bbfd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367665044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.367665044
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2903764520
Short name T98
Test name
Test status
Simulation time 93701517764 ps
CPU time 138.89 seconds
Started Aug 13 05:16:42 PM PDT 24
Finished Aug 13 05:19:02 PM PDT 24
Peak memory 200868 kb
Host smart-eeb64ad3-a167-4a10-9b61-0b288153da98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903764520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2903764520
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.256569263
Short name T183
Test name
Test status
Simulation time 98068853031 ps
CPU time 148.87 seconds
Started Aug 13 05:16:45 PM PDT 24
Finished Aug 13 05:19:14 PM PDT 24
Peak memory 200712 kb
Host smart-23268830-2b3f-4ab7-8523-851f6a005443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256569263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.256569263
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.1232425326
Short name T868
Test name
Test status
Simulation time 19545791994 ps
CPU time 31.75 seconds
Started Aug 13 05:14:01 PM PDT 24
Finished Aug 13 05:14:33 PM PDT 24
Peak memory 200864 kb
Host smart-c1b9bafa-7f10-4cfc-9d20-9a4e10fc39ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232425326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1232425326
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.3376362855
Short name T238
Test name
Test status
Simulation time 27493752329 ps
CPU time 10.51 seconds
Started Aug 13 05:14:02 PM PDT 24
Finished Aug 13 05:14:13 PM PDT 24
Peak memory 200940 kb
Host smart-35ec280d-db0d-4f9c-929c-97c95487f9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376362855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3376362855
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.3452731087
Short name T356
Test name
Test status
Simulation time 44881948802 ps
CPU time 38.91 seconds
Started Aug 13 05:14:02 PM PDT 24
Finished Aug 13 05:14:41 PM PDT 24
Peak memory 200048 kb
Host smart-6cbb4a51-915e-4868-b104-24cb7a3808f9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452731087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3452731087
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.596855721
Short name T1005
Test name
Test status
Simulation time 68243105136 ps
CPU time 576.69 seconds
Started Aug 13 05:14:11 PM PDT 24
Finished Aug 13 05:23:48 PM PDT 24
Peak memory 200776 kb
Host smart-55649d20-cbeb-4505-8d0a-8f56f71432b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=596855721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.596855721
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.2598546546
Short name T739
Test name
Test status
Simulation time 5139480482 ps
CPU time 6.07 seconds
Started Aug 13 05:14:04 PM PDT 24
Finished Aug 13 05:14:11 PM PDT 24
Peak memory 200304 kb
Host smart-5c0f06fa-f903-4d95-aea0-4d17367ddc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598546546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.2598546546
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.2603017809
Short name T277
Test name
Test status
Simulation time 39555606527 ps
CPU time 68.08 seconds
Started Aug 13 05:14:03 PM PDT 24
Finished Aug 13 05:15:12 PM PDT 24
Peak memory 201064 kb
Host smart-3e004886-f2ce-481b-ae44-a1ed0e000a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603017809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2603017809
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.1574353044
Short name T542
Test name
Test status
Simulation time 14989571417 ps
CPU time 847.88 seconds
Started Aug 13 05:14:11 PM PDT 24
Finished Aug 13 05:28:19 PM PDT 24
Peak memory 200840 kb
Host smart-e3fcab76-6cde-44fd-970a-381480fdb3bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1574353044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1574353044
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.3060568387
Short name T533
Test name
Test status
Simulation time 2548132541 ps
CPU time 7.44 seconds
Started Aug 13 05:13:59 PM PDT 24
Finished Aug 13 05:14:07 PM PDT 24
Peak memory 199972 kb
Host smart-d1e6c062-cccc-4f21-9938-880453054e72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3060568387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3060568387
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.488062361
Short name T538
Test name
Test status
Simulation time 31321524654 ps
CPU time 26.12 seconds
Started Aug 13 05:14:02 PM PDT 24
Finished Aug 13 05:14:28 PM PDT 24
Peak memory 200920 kb
Host smart-58941a2e-69bb-444f-8bf5-4554e18fb32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488062361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.488062361
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.1438462396
Short name T395
Test name
Test status
Simulation time 5212044511 ps
CPU time 1.88 seconds
Started Aug 13 05:14:00 PM PDT 24
Finished Aug 13 05:14:03 PM PDT 24
Peak memory 197020 kb
Host smart-49b2c65b-a401-4b01-94a4-9be586f4a12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438462396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1438462396
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.464738561
Short name T742
Test name
Test status
Simulation time 6257449666 ps
CPU time 20.34 seconds
Started Aug 13 05:14:01 PM PDT 24
Finished Aug 13 05:14:22 PM PDT 24
Peak memory 200808 kb
Host smart-ed91537e-2791-4fb1-8dbc-b948605d5d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464738561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.464738561
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.4285131435
Short name T772
Test name
Test status
Simulation time 265558571277 ps
CPU time 164.32 seconds
Started Aug 13 05:14:23 PM PDT 24
Finished Aug 13 05:17:08 PM PDT 24
Peak memory 200952 kb
Host smart-9e97967b-469e-49ad-84cc-42169779c3ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285131435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.4285131435
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.799990249
Short name T634
Test name
Test status
Simulation time 3799700733 ps
CPU time 31.4 seconds
Started Aug 13 05:14:03 PM PDT 24
Finished Aug 13 05:14:34 PM PDT 24
Peak memory 217588 kb
Host smart-33320ac0-441b-440f-b67a-7e1d6f478ffa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799990249 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.799990249
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.2658374201
Short name T755
Test name
Test status
Simulation time 760688738 ps
CPU time 3.59 seconds
Started Aug 13 05:14:09 PM PDT 24
Finished Aug 13 05:14:13 PM PDT 24
Peak memory 199832 kb
Host smart-9e982745-7db0-4772-8bfa-2db9a5489e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658374201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2658374201
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.4153964740
Short name T966
Test name
Test status
Simulation time 47806070376 ps
CPU time 35.09 seconds
Started Aug 13 05:14:06 PM PDT 24
Finished Aug 13 05:14:41 PM PDT 24
Peak memory 199728 kb
Host smart-78c31ffd-eb22-4b8e-be81-c9186e39b6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153964740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.4153964740
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2920537410
Short name T597
Test name
Test status
Simulation time 130384848376 ps
CPU time 104.34 seconds
Started Aug 13 05:16:44 PM PDT 24
Finished Aug 13 05:18:28 PM PDT 24
Peak memory 200892 kb
Host smart-4b65d590-408f-4142-a8f6-3f763ab2b642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920537410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2920537410
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.3845770856
Short name T1
Test name
Test status
Simulation time 41111981059 ps
CPU time 17.76 seconds
Started Aug 13 05:16:45 PM PDT 24
Finished Aug 13 05:17:03 PM PDT 24
Peak memory 200728 kb
Host smart-0f56fc15-b9bc-412d-af1c-96ad62b64557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845770856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3845770856
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.488083173
Short name T165
Test name
Test status
Simulation time 120380927784 ps
CPU time 272.09 seconds
Started Aug 13 05:16:43 PM PDT 24
Finished Aug 13 05:21:15 PM PDT 24
Peak memory 200832 kb
Host smart-00695b2b-7354-4642-8ca9-5cab54500ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488083173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.488083173
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.301076638
Short name T537
Test name
Test status
Simulation time 110216810010 ps
CPU time 52.3 seconds
Started Aug 13 05:16:44 PM PDT 24
Finished Aug 13 05:17:36 PM PDT 24
Peak memory 200936 kb
Host smart-2a077e0c-7e58-438a-9a64-e3c62a44c03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301076638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.301076638
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.2954296290
Short name T212
Test name
Test status
Simulation time 255209656408 ps
CPU time 164.34 seconds
Started Aug 13 05:16:43 PM PDT 24
Finished Aug 13 05:19:27 PM PDT 24
Peak memory 200932 kb
Host smart-e1f8fb32-c414-4678-b076-e2dc3693c1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954296290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2954296290
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.3375198624
Short name T759
Test name
Test status
Simulation time 21037696144 ps
CPU time 35.32 seconds
Started Aug 13 05:16:50 PM PDT 24
Finished Aug 13 05:17:26 PM PDT 24
Peak memory 200800 kb
Host smart-4a070258-0dd4-4db8-b115-baa841cbeb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375198624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3375198624
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.967836018
Short name T642
Test name
Test status
Simulation time 189432785107 ps
CPU time 23.39 seconds
Started Aug 13 05:16:47 PM PDT 24
Finished Aug 13 05:17:11 PM PDT 24
Peak memory 200816 kb
Host smart-0bb1f2d0-95cd-445a-8f11-4201fe42cfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967836018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.967836018
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.3840942831
Short name T10
Test name
Test status
Simulation time 41948724230 ps
CPU time 64.73 seconds
Started Aug 13 05:16:47 PM PDT 24
Finished Aug 13 05:17:52 PM PDT 24
Peak memory 200928 kb
Host smart-e05991bf-75c5-4770-ad58-07f13b5d942b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840942831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3840942831
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.1172012255
Short name T1119
Test name
Test status
Simulation time 35799789 ps
CPU time 0.57 seconds
Started Aug 13 05:14:09 PM PDT 24
Finished Aug 13 05:14:09 PM PDT 24
Peak memory 196188 kb
Host smart-f8e6efd7-c659-4be2-9a85-d7668d1b3970
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172012255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1172012255
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.1300989659
Short name T85
Test name
Test status
Simulation time 78956145993 ps
CPU time 11.89 seconds
Started Aug 13 05:14:12 PM PDT 24
Finished Aug 13 05:14:24 PM PDT 24
Peak memory 200828 kb
Host smart-3d076cc5-6ef5-44f9-9278-1a4760e58f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300989659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1300989659
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.882359596
Short name T431
Test name
Test status
Simulation time 14984378621 ps
CPU time 12.81 seconds
Started Aug 13 05:14:17 PM PDT 24
Finished Aug 13 05:14:30 PM PDT 24
Peak memory 200936 kb
Host smart-85a8fdb1-5ecf-499f-a30d-26023e234e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882359596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.882359596
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.3014287194
Short name T1059
Test name
Test status
Simulation time 192179317375 ps
CPU time 101.58 seconds
Started Aug 13 05:14:20 PM PDT 24
Finished Aug 13 05:16:01 PM PDT 24
Peak memory 200852 kb
Host smart-e48601a2-cb6b-4bed-b701-04f409b066ff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014287194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3014287194
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1054351718
Short name T673
Test name
Test status
Simulation time 42485957017 ps
CPU time 97.19 seconds
Started Aug 13 05:14:15 PM PDT 24
Finished Aug 13 05:15:52 PM PDT 24
Peak memory 200936 kb
Host smart-f533afd5-bed8-4b28-b172-faa7d367cd5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1054351718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1054351718
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.768617123
Short name T1150
Test name
Test status
Simulation time 1670808501 ps
CPU time 1.67 seconds
Started Aug 13 05:14:12 PM PDT 24
Finished Aug 13 05:14:13 PM PDT 24
Peak memory 199456 kb
Host smart-ff20cd2f-a7d7-4af6-a23c-a2aafda9327d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768617123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.768617123
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.4290654909
Short name T808
Test name
Test status
Simulation time 129760652069 ps
CPU time 131.88 seconds
Started Aug 13 05:14:14 PM PDT 24
Finished Aug 13 05:16:26 PM PDT 24
Peak memory 200352 kb
Host smart-83d463ef-7c6c-42e4-81ca-309857d7116c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290654909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.4290654909
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.3613776472
Short name T1100
Test name
Test status
Simulation time 18950101413 ps
CPU time 657 seconds
Started Aug 13 05:14:08 PM PDT 24
Finished Aug 13 05:25:05 PM PDT 24
Peak memory 200916 kb
Host smart-4405f7fb-cd21-42ff-bd34-a65e34b361be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3613776472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3613776472
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2037705313
Short name T601
Test name
Test status
Simulation time 3274307532 ps
CPU time 2.01 seconds
Started Aug 13 05:14:10 PM PDT 24
Finished Aug 13 05:14:12 PM PDT 24
Peak memory 199008 kb
Host smart-fa7a9b96-9c32-4e0a-a6a0-37d91eb7150d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2037705313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2037705313
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.726667328
Short name T1167
Test name
Test status
Simulation time 24866455690 ps
CPU time 33.08 seconds
Started Aug 13 05:14:11 PM PDT 24
Finished Aug 13 05:14:44 PM PDT 24
Peak memory 200880 kb
Host smart-f57092ac-2cd5-475c-8082-745c5001b250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726667328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.726667328
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.330804744
Short name T279
Test name
Test status
Simulation time 4950213303 ps
CPU time 8.43 seconds
Started Aug 13 05:14:12 PM PDT 24
Finished Aug 13 05:14:21 PM PDT 24
Peak memory 197032 kb
Host smart-ae777229-688c-4ab3-846e-4d827cb8ad0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330804744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.330804744
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.4098583202
Short name T909
Test name
Test status
Simulation time 680374156 ps
CPU time 1.61 seconds
Started Aug 13 05:14:09 PM PDT 24
Finished Aug 13 05:14:11 PM PDT 24
Peak memory 199644 kb
Host smart-cbdf9e0c-d01a-4440-b294-502be7ada80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098583202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.4098583202
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1706497174
Short name T831
Test name
Test status
Simulation time 2195208655 ps
CPU time 18.24 seconds
Started Aug 13 05:14:27 PM PDT 24
Finished Aug 13 05:14:45 PM PDT 24
Peak memory 200932 kb
Host smart-058ecf6b-0f66-426c-ac08-fd5e807b5fa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706497174 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1706497174
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.3825798244
Short name T495
Test name
Test status
Simulation time 867295846 ps
CPU time 4.63 seconds
Started Aug 13 05:14:14 PM PDT 24
Finished Aug 13 05:14:19 PM PDT 24
Peak memory 200356 kb
Host smart-4d51fd54-bff6-4b14-bc3f-36b4e95026c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825798244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3825798244
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.2369333550
Short name T629
Test name
Test status
Simulation time 117594134932 ps
CPU time 201.53 seconds
Started Aug 13 05:16:47 PM PDT 24
Finished Aug 13 05:20:09 PM PDT 24
Peak memory 200936 kb
Host smart-f1a3c82f-5a90-40d1-8bb2-ff639457e003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369333550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2369333550
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1041065958
Short name T493
Test name
Test status
Simulation time 12693858179 ps
CPU time 20.91 seconds
Started Aug 13 05:16:49 PM PDT 24
Finished Aug 13 05:17:10 PM PDT 24
Peak memory 200812 kb
Host smart-8e909ce4-9126-4cde-8db6-3f355ba85d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041065958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1041065958
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1805191326
Short name T757
Test name
Test status
Simulation time 34303591457 ps
CPU time 14.04 seconds
Started Aug 13 05:16:52 PM PDT 24
Finished Aug 13 05:17:06 PM PDT 24
Peak memory 200928 kb
Host smart-f8d8a9c8-5bde-44f5-ac8f-6b11f574351c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805191326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1805191326
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.1731904990
Short name T247
Test name
Test status
Simulation time 477935732676 ps
CPU time 66.65 seconds
Started Aug 13 05:16:52 PM PDT 24
Finished Aug 13 05:17:59 PM PDT 24
Peak memory 200948 kb
Host smart-3424b2b0-bc15-46dd-9ae5-d11c750a9a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731904990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.1731904990
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3877310834
Short name T439
Test name
Test status
Simulation time 15948278401 ps
CPU time 23.56 seconds
Started Aug 13 05:16:44 PM PDT 24
Finished Aug 13 05:17:08 PM PDT 24
Peak memory 200876 kb
Host smart-5dfcbc80-b75e-4e14-bbb0-5fec05690123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877310834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3877310834
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2012069374
Short name T1002
Test name
Test status
Simulation time 115467157164 ps
CPU time 248.13 seconds
Started Aug 13 05:16:51 PM PDT 24
Finished Aug 13 05:20:59 PM PDT 24
Peak memory 200900 kb
Host smart-dd7ac4df-58c0-4d85-981c-995ef574c704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012069374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2012069374
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1549514314
Short name T186
Test name
Test status
Simulation time 42015661360 ps
CPU time 86.24 seconds
Started Aug 13 05:16:48 PM PDT 24
Finished Aug 13 05:18:14 PM PDT 24
Peak memory 200940 kb
Host smart-0cb934ff-2f7d-46b1-aaac-193b6d74e8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549514314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1549514314
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.2174715401
Short name T954
Test name
Test status
Simulation time 21258687545 ps
CPU time 20.91 seconds
Started Aug 13 05:16:51 PM PDT 24
Finished Aug 13 05:17:12 PM PDT 24
Peak memory 200892 kb
Host smart-e345de2f-a880-4b1d-b292-9fdbae19e989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174715401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2174715401
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.873916882
Short name T222
Test name
Test status
Simulation time 28286060564 ps
CPU time 22.39 seconds
Started Aug 13 05:16:50 PM PDT 24
Finished Aug 13 05:17:13 PM PDT 24
Peak memory 200876 kb
Host smart-a3b94b5d-c5f9-49c3-baaa-28be45738510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873916882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.873916882
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.1896632114
Short name T858
Test name
Test status
Simulation time 116482391295 ps
CPU time 43.16 seconds
Started Aug 13 05:16:45 PM PDT 24
Finished Aug 13 05:17:29 PM PDT 24
Peak memory 200924 kb
Host smart-6668dc35-1d12-4958-aeea-081e12b49210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896632114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1896632114
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.2022951659
Short name T376
Test name
Test status
Simulation time 12025353 ps
CPU time 0.58 seconds
Started Aug 13 05:14:11 PM PDT 24
Finished Aug 13 05:14:12 PM PDT 24
Peak memory 196428 kb
Host smart-4e13b431-a824-4d13-8cfc-f198f2662eee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022951659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2022951659
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2623603701
Short name T154
Test name
Test status
Simulation time 169364167690 ps
CPU time 29.44 seconds
Started Aug 13 05:14:11 PM PDT 24
Finished Aug 13 05:14:40 PM PDT 24
Peak memory 200928 kb
Host smart-592db530-6a3c-4073-a64a-f7f11faa905d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623603701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2623603701
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3994679494
Short name T1179
Test name
Test status
Simulation time 30222982275 ps
CPU time 13.3 seconds
Started Aug 13 05:14:07 PM PDT 24
Finished Aug 13 05:14:20 PM PDT 24
Peak memory 200644 kb
Host smart-b6dcfa6d-7811-4573-9216-370b97074f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994679494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3994679494
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.3717454816
Short name T548
Test name
Test status
Simulation time 18542663060 ps
CPU time 27.15 seconds
Started Aug 13 05:14:11 PM PDT 24
Finished Aug 13 05:14:38 PM PDT 24
Peak memory 200440 kb
Host smart-f7d74009-ea12-434d-84e5-a3a79ab16570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717454816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.3717454816
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.918083522
Short name T355
Test name
Test status
Simulation time 194817363796 ps
CPU time 203.37 seconds
Started Aug 13 05:14:12 PM PDT 24
Finished Aug 13 05:17:36 PM PDT 24
Peak memory 198628 kb
Host smart-774a58db-5918-4d20-8517-f361e5043df1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918083522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.918083522
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1690458263
Short name T927
Test name
Test status
Simulation time 185260311173 ps
CPU time 731.14 seconds
Started Aug 13 05:14:14 PM PDT 24
Finished Aug 13 05:26:25 PM PDT 24
Peak memory 200936 kb
Host smart-af002969-540c-4015-a5c0-941f762c851b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1690458263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1690458263
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.4066546309
Short name T761
Test name
Test status
Simulation time 5251367017 ps
CPU time 9.85 seconds
Started Aug 13 05:14:10 PM PDT 24
Finished Aug 13 05:14:20 PM PDT 24
Peak memory 199588 kb
Host smart-5663a5f6-cb9b-4692-a4c0-2188bf9ca2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066546309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.4066546309
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.203582412
Short name T986
Test name
Test status
Simulation time 176186044037 ps
CPU time 69.79 seconds
Started Aug 13 05:14:20 PM PDT 24
Finished Aug 13 05:15:30 PM PDT 24
Peak memory 209248 kb
Host smart-69e7d5d9-0572-4b79-a1f2-dfb6c2f930f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203582412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.203582412
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1848551568
Short name T339
Test name
Test status
Simulation time 7872174485 ps
CPU time 72.01 seconds
Started Aug 13 05:14:15 PM PDT 24
Finished Aug 13 05:15:27 PM PDT 24
Peak memory 200844 kb
Host smart-88c730b5-02f7-41ce-8af6-05500b8100d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1848551568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1848551568
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.1159733937
Short name T661
Test name
Test status
Simulation time 3259640066 ps
CPU time 6.8 seconds
Started Aug 13 05:14:18 PM PDT 24
Finished Aug 13 05:14:24 PM PDT 24
Peak memory 200016 kb
Host smart-87858a36-d398-4469-85cc-a9bc008158f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1159733937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1159733937
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.3944968049
Short name T157
Test name
Test status
Simulation time 27399238912 ps
CPU time 49.13 seconds
Started Aug 13 05:14:14 PM PDT 24
Finished Aug 13 05:15:03 PM PDT 24
Peak memory 200884 kb
Host smart-b414f59b-f098-429d-a281-da810c3e8365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944968049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3944968049
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.4083849854
Short name T947
Test name
Test status
Simulation time 2346205750 ps
CPU time 0.83 seconds
Started Aug 13 05:14:14 PM PDT 24
Finished Aug 13 05:14:15 PM PDT 24
Peak memory 196452 kb
Host smart-38813104-55bd-4d0c-a27a-8aba4a6d170c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083849854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.4083849854
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1998863309
Short name T1157
Test name
Test status
Simulation time 295901148 ps
CPU time 1.27 seconds
Started Aug 13 05:14:25 PM PDT 24
Finished Aug 13 05:14:27 PM PDT 24
Peak memory 199056 kb
Host smart-3772fdc0-7f26-4aa1-9a59-30c638807715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998863309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1998863309
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.1507448883
Short name T586
Test name
Test status
Simulation time 4086330080 ps
CPU time 84.73 seconds
Started Aug 13 05:14:09 PM PDT 24
Finished Aug 13 05:15:34 PM PDT 24
Peak memory 201200 kb
Host smart-609358ec-0f80-4b59-be5e-e79e5282139c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507448883 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.1507448883
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2560602604
Short name T328
Test name
Test status
Simulation time 1621557461 ps
CPU time 1.6 seconds
Started Aug 13 05:14:21 PM PDT 24
Finished Aug 13 05:14:23 PM PDT 24
Peak memory 199740 kb
Host smart-b9f5dc69-adba-4b75-802f-bb68e147e34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560602604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2560602604
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.102674176
Short name T827
Test name
Test status
Simulation time 78034735123 ps
CPU time 174.29 seconds
Started Aug 13 05:14:09 PM PDT 24
Finished Aug 13 05:17:04 PM PDT 24
Peak memory 200840 kb
Host smart-14974a2e-945e-4c61-a911-4eeb1f1f3ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102674176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.102674176
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.1158151550
Short name T236
Test name
Test status
Simulation time 183567705017 ps
CPU time 48.1 seconds
Started Aug 13 05:16:48 PM PDT 24
Finished Aug 13 05:17:36 PM PDT 24
Peak memory 200800 kb
Host smart-95387c54-47af-4118-998f-24a53c95d317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158151550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1158151550
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3741543608
Short name T141
Test name
Test status
Simulation time 19913419286 ps
CPU time 29.34 seconds
Started Aug 13 05:16:47 PM PDT 24
Finished Aug 13 05:17:17 PM PDT 24
Peak memory 200872 kb
Host smart-a673b3c0-e17e-4073-b8c4-4eafb371242a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741543608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3741543608
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.916101201
Short name T939
Test name
Test status
Simulation time 168106787644 ps
CPU time 302.79 seconds
Started Aug 13 05:16:48 PM PDT 24
Finished Aug 13 05:21:51 PM PDT 24
Peak memory 200936 kb
Host smart-5b27520e-7f83-47a4-a37e-ca8b9abe4028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916101201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.916101201
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2547513306
Short name T641
Test name
Test status
Simulation time 34141769078 ps
CPU time 36.1 seconds
Started Aug 13 05:16:47 PM PDT 24
Finished Aug 13 05:17:23 PM PDT 24
Peak memory 200936 kb
Host smart-b455c22f-bbd6-40ea-a7d5-7d7516e1987d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547513306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2547513306
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.2346687573
Short name T195
Test name
Test status
Simulation time 11116711292 ps
CPU time 10.87 seconds
Started Aug 13 05:16:46 PM PDT 24
Finished Aug 13 05:16:57 PM PDT 24
Peak memory 200808 kb
Host smart-c2ab76c0-5ec2-4f32-8246-2f16e72b60da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346687573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2346687573
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1182318371
Short name T1168
Test name
Test status
Simulation time 36966362783 ps
CPU time 55.69 seconds
Started Aug 13 05:16:52 PM PDT 24
Finished Aug 13 05:17:48 PM PDT 24
Peak memory 200888 kb
Host smart-c9f27089-45ed-4d9f-8518-87815a334629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182318371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1182318371
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2507737117
Short name T872
Test name
Test status
Simulation time 182582431274 ps
CPU time 23.55 seconds
Started Aug 13 05:16:47 PM PDT 24
Finished Aug 13 05:17:11 PM PDT 24
Peak memory 200820 kb
Host smart-e23cbfe9-683f-4dca-8050-f99c612ea1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507737117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2507737117
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.380488260
Short name T164
Test name
Test status
Simulation time 51484700100 ps
CPU time 17.92 seconds
Started Aug 13 05:16:52 PM PDT 24
Finished Aug 13 05:17:10 PM PDT 24
Peak memory 200888 kb
Host smart-28da5d6a-36f5-4129-b846-606a5a563eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380488260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.380488260
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.308104429
Short name T727
Test name
Test status
Simulation time 16027738 ps
CPU time 0.53 seconds
Started Aug 13 05:14:26 PM PDT 24
Finished Aug 13 05:14:27 PM PDT 24
Peak memory 195188 kb
Host smart-2c5ee9d6-fcb7-4715-ab88-03e91e3116fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308104429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.308104429
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.7599288
Short name T500
Test name
Test status
Simulation time 44521988434 ps
CPU time 76.09 seconds
Started Aug 13 05:14:14 PM PDT 24
Finished Aug 13 05:15:30 PM PDT 24
Peak memory 200940 kb
Host smart-953ada87-db7b-4e49-9f03-42558fcd7df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7599288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.7599288
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2349107407
Short name T845
Test name
Test status
Simulation time 12155323816 ps
CPU time 20.4 seconds
Started Aug 13 05:14:18 PM PDT 24
Finished Aug 13 05:14:39 PM PDT 24
Peak memory 200880 kb
Host smart-dc7d79fa-542a-478d-8ed6-0b60f2b039f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349107407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2349107407
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.689591895
Short name T207
Test name
Test status
Simulation time 218839068421 ps
CPU time 186.55 seconds
Started Aug 13 05:14:17 PM PDT 24
Finished Aug 13 05:17:24 PM PDT 24
Peak memory 200780 kb
Host smart-700ef445-8fa5-4245-9219-5da8b03ab44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689591895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.689591895
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1135225409
Short name T958
Test name
Test status
Simulation time 25824979441 ps
CPU time 10.99 seconds
Started Aug 13 05:14:21 PM PDT 24
Finished Aug 13 05:14:32 PM PDT 24
Peak memory 200216 kb
Host smart-238060c2-3d0e-4992-b6c8-4b52ce70f6cf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135225409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1135225409
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.705955961
Short name T864
Test name
Test status
Simulation time 71979643573 ps
CPU time 122.51 seconds
Started Aug 13 05:14:14 PM PDT 24
Finished Aug 13 05:16:16 PM PDT 24
Peak memory 200916 kb
Host smart-e87fbf06-20b5-4cd9-9477-c5eec5f9aada
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=705955961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.705955961
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1908570566
Short name T380
Test name
Test status
Simulation time 2015452641 ps
CPU time 3.97 seconds
Started Aug 13 05:14:16 PM PDT 24
Finished Aug 13 05:14:20 PM PDT 24
Peak memory 199040 kb
Host smart-9d72aec2-9d4c-412e-9b39-4914948eb958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908570566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1908570566
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.1932604283
Short name T1073
Test name
Test status
Simulation time 34807061991 ps
CPU time 58.23 seconds
Started Aug 13 05:14:14 PM PDT 24
Finished Aug 13 05:15:13 PM PDT 24
Peak memory 201148 kb
Host smart-366e70a1-057a-4b4b-8a9c-9267c3c4b952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932604283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1932604283
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.1484036303
Short name T764
Test name
Test status
Simulation time 14638185946 ps
CPU time 199.52 seconds
Started Aug 13 05:14:20 PM PDT 24
Finished Aug 13 05:17:39 PM PDT 24
Peak memory 200876 kb
Host smart-bb5a9ca8-ee95-4e51-8a54-ffbc17a5a201
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1484036303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1484036303
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.561161450
Short name T396
Test name
Test status
Simulation time 1914811871 ps
CPU time 4.07 seconds
Started Aug 13 05:14:14 PM PDT 24
Finished Aug 13 05:14:18 PM PDT 24
Peak memory 199948 kb
Host smart-79ba96cd-a1cc-4370-9c26-619a0550907e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=561161450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.561161450
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.3871067660
Short name T948
Test name
Test status
Simulation time 34954615074 ps
CPU time 49.77 seconds
Started Aug 13 05:14:15 PM PDT 24
Finished Aug 13 05:15:05 PM PDT 24
Peak memory 200876 kb
Host smart-e7aae319-fa63-4795-866c-8085b31ddd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871067660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3871067660
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.232219929
Short name T874
Test name
Test status
Simulation time 3882803990 ps
CPU time 1.85 seconds
Started Aug 13 05:14:14 PM PDT 24
Finished Aug 13 05:14:16 PM PDT 24
Peak memory 196952 kb
Host smart-fc76996d-8496-40f6-bcee-540602d7062c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232219929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.232219929
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.3336513092
Short name T839
Test name
Test status
Simulation time 294090552 ps
CPU time 1.64 seconds
Started Aug 13 05:14:08 PM PDT 24
Finished Aug 13 05:14:10 PM PDT 24
Peak memory 199364 kb
Host smart-a63c7bc1-7909-4fe1-bf40-a09f6f550526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336513092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.3336513092
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.68354665
Short name T513
Test name
Test status
Simulation time 58023563684 ps
CPU time 49.15 seconds
Started Aug 13 05:14:23 PM PDT 24
Finished Aug 13 05:15:13 PM PDT 24
Peak memory 200948 kb
Host smart-ab07f2db-11f6-4d2c-a446-58eaff7a0e3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68354665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.68354665
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.56474340
Short name T732
Test name
Test status
Simulation time 3384181679 ps
CPU time 23.25 seconds
Started Aug 13 05:14:14 PM PDT 24
Finished Aug 13 05:14:38 PM PDT 24
Peak memory 201232 kb
Host smart-234f72ab-1081-462b-b641-122104730c89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56474340 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.56474340
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.805610698
Short name T336
Test name
Test status
Simulation time 1079653480 ps
CPU time 3.02 seconds
Started Aug 13 05:14:23 PM PDT 24
Finished Aug 13 05:14:26 PM PDT 24
Peak memory 199808 kb
Host smart-64a8d6b6-fd1b-483e-88f3-866afa221bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805610698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.805610698
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2667662318
Short name T343
Test name
Test status
Simulation time 115872291739 ps
CPU time 21.86 seconds
Started Aug 13 05:14:22 PM PDT 24
Finished Aug 13 05:14:44 PM PDT 24
Peak memory 200868 kb
Host smart-c0630f5a-1c78-47ad-9b5a-5e0c48fc98f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667662318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2667662318
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1164833445
Short name T619
Test name
Test status
Simulation time 62280703727 ps
CPU time 19.19 seconds
Started Aug 13 05:16:48 PM PDT 24
Finished Aug 13 05:17:08 PM PDT 24
Peak memory 200856 kb
Host smart-9ff98656-76d7-4566-92e0-e0650aad0f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164833445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1164833445
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.566995876
Short name T152
Test name
Test status
Simulation time 260038693353 ps
CPU time 390.45 seconds
Started Aug 13 05:16:52 PM PDT 24
Finished Aug 13 05:23:22 PM PDT 24
Peak memory 200912 kb
Host smart-c083688a-c723-40ec-a7fb-7cba6deaeeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566995876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.566995876
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.423577486
Short name T260
Test name
Test status
Simulation time 52070172352 ps
CPU time 117.44 seconds
Started Aug 13 05:16:47 PM PDT 24
Finished Aug 13 05:18:45 PM PDT 24
Peak memory 200740 kb
Host smart-8c04593a-3748-448c-9bdd-921df0c20c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423577486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.423577486
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.952541147
Short name T969
Test name
Test status
Simulation time 61596606485 ps
CPU time 22.1 seconds
Started Aug 13 05:16:53 PM PDT 24
Finished Aug 13 05:17:16 PM PDT 24
Peak memory 200796 kb
Host smart-458089d1-0db4-494e-93b6-daa7d3881139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952541147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.952541147
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2851887251
Short name T94
Test name
Test status
Simulation time 221296263144 ps
CPU time 176.94 seconds
Started Aug 13 05:16:53 PM PDT 24
Finished Aug 13 05:19:50 PM PDT 24
Peak memory 200728 kb
Host smart-c8f60773-66c1-434f-9504-34a2055e2d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851887251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2851887251
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.292282272
Short name T885
Test name
Test status
Simulation time 82189997938 ps
CPU time 30.81 seconds
Started Aug 13 05:16:55 PM PDT 24
Finished Aug 13 05:17:26 PM PDT 24
Peak memory 200832 kb
Host smart-dd27fea2-1964-4a09-b120-b33620f2b333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292282272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.292282272
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.580745203
Short name T878
Test name
Test status
Simulation time 50074501957 ps
CPU time 18.34 seconds
Started Aug 13 05:16:56 PM PDT 24
Finished Aug 13 05:17:15 PM PDT 24
Peak memory 200932 kb
Host smart-b02afd2f-6a0d-44c3-8208-a3b2aaa7eff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580745203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.580745203
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.3239682818
Short name T192
Test name
Test status
Simulation time 119624174132 ps
CPU time 139.58 seconds
Started Aug 13 05:16:54 PM PDT 24
Finished Aug 13 05:19:14 PM PDT 24
Peak memory 200880 kb
Host smart-b3d808e6-9ec6-4de6-b854-d088fcd9c0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239682818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.3239682818
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.2086405783
Short name T22
Test name
Test status
Simulation time 45100925 ps
CPU time 0.57 seconds
Started Aug 13 05:14:18 PM PDT 24
Finished Aug 13 05:14:19 PM PDT 24
Peak memory 196140 kb
Host smart-c00a3bb5-0aba-4d72-b09a-076ccda3604c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086405783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2086405783
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.824918931
Short name T1015
Test name
Test status
Simulation time 32252105691 ps
CPU time 48.38 seconds
Started Aug 13 05:14:16 PM PDT 24
Finished Aug 13 05:15:04 PM PDT 24
Peak memory 199288 kb
Host smart-ac02f198-7c10-4f85-808a-15dcd478a883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824918931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.824918931
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.2193641743
Short name T929
Test name
Test status
Simulation time 69508188905 ps
CPU time 12.44 seconds
Started Aug 13 05:14:15 PM PDT 24
Finished Aug 13 05:14:28 PM PDT 24
Peak memory 200928 kb
Host smart-6fae850e-b4ed-4675-8818-c55586b29c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193641743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2193641743
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.496464484
Short name T662
Test name
Test status
Simulation time 26099139565 ps
CPU time 13.17 seconds
Started Aug 13 05:14:21 PM PDT 24
Finished Aug 13 05:14:34 PM PDT 24
Peak memory 199008 kb
Host smart-e839e849-6365-4aeb-9269-984426028f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496464484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.496464484
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.2309802635
Short name T320
Test name
Test status
Simulation time 58750794429 ps
CPU time 98.23 seconds
Started Aug 13 05:14:16 PM PDT 24
Finished Aug 13 05:15:54 PM PDT 24
Peak memory 200924 kb
Host smart-e7d536e0-6442-43ac-8e5a-2ed22e392b48
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309802635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2309802635
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2900655119
Short name T528
Test name
Test status
Simulation time 62530661003 ps
CPU time 240.34 seconds
Started Aug 13 05:14:17 PM PDT 24
Finished Aug 13 05:18:18 PM PDT 24
Peak memory 200832 kb
Host smart-65dc8788-ce8a-4d24-9d43-a540ec479747
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2900655119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2900655119
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.54342943
Short name T575
Test name
Test status
Simulation time 9665120629 ps
CPU time 18.24 seconds
Started Aug 13 05:14:15 PM PDT 24
Finished Aug 13 05:14:34 PM PDT 24
Peak memory 199904 kb
Host smart-06e5d476-75f8-4bf5-a560-b344bcc4f1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54342943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.54342943
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.50874422
Short name T427
Test name
Test status
Simulation time 74584744310 ps
CPU time 25.71 seconds
Started Aug 13 05:14:24 PM PDT 24
Finished Aug 13 05:14:50 PM PDT 24
Peak memory 195752 kb
Host smart-b03455b7-aa65-468e-9dc0-89d5deddfb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50874422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.50874422
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.4106550798
Short name T779
Test name
Test status
Simulation time 21137396012 ps
CPU time 283.04 seconds
Started Aug 13 05:14:17 PM PDT 24
Finished Aug 13 05:19:00 PM PDT 24
Peak memory 200916 kb
Host smart-5540533b-c17b-4f5a-bcbf-f729be8e1824
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4106550798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.4106550798
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2004234830
Short name T1092
Test name
Test status
Simulation time 4679848247 ps
CPU time 6.18 seconds
Started Aug 13 05:14:17 PM PDT 24
Finished Aug 13 05:14:23 PM PDT 24
Peak memory 199632 kb
Host smart-2b7b31ed-7b3f-42ff-ad32-c0595797a730
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2004234830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2004234830
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3988826489
Short name T865
Test name
Test status
Simulation time 318429050919 ps
CPU time 315.98 seconds
Started Aug 13 05:14:17 PM PDT 24
Finished Aug 13 05:19:33 PM PDT 24
Peak memory 200928 kb
Host smart-90c866d0-8ee5-49ab-84d9-b70c4a6f259b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988826489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3988826489
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3513202852
Short name T888
Test name
Test status
Simulation time 24488313583 ps
CPU time 41.92 seconds
Started Aug 13 05:14:16 PM PDT 24
Finished Aug 13 05:14:58 PM PDT 24
Peak memory 197216 kb
Host smart-a042a0ce-f64b-4276-a578-09c92f9388ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513202852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3513202852
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1906800834
Short name T623
Test name
Test status
Simulation time 681791721 ps
CPU time 1.91 seconds
Started Aug 13 05:14:21 PM PDT 24
Finished Aug 13 05:14:23 PM PDT 24
Peak memory 199288 kb
Host smart-9747c8cb-8bcb-445d-8013-ab78deed6ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906800834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1906800834
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.3742536649
Short name T801
Test name
Test status
Simulation time 32810908790 ps
CPU time 46.6 seconds
Started Aug 13 05:14:19 PM PDT 24
Finished Aug 13 05:15:05 PM PDT 24
Peak memory 200948 kb
Host smart-e8a74e1f-b01d-48af-b930-42648bb7ba97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742536649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3742536649
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2593225121
Short name T440
Test name
Test status
Simulation time 3619302329 ps
CPU time 30.62 seconds
Started Aug 13 05:14:21 PM PDT 24
Finished Aug 13 05:14:52 PM PDT 24
Peak memory 217260 kb
Host smart-ae7f55b8-0970-47ff-acea-9877275c28f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593225121 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2593225121
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.833318206
Short name T897
Test name
Test status
Simulation time 7090899879 ps
CPU time 42.15 seconds
Started Aug 13 05:14:22 PM PDT 24
Finished Aug 13 05:15:04 PM PDT 24
Peak memory 200884 kb
Host smart-23d7410d-f8ef-4b17-83a8-ef18e2c020bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833318206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.833318206
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.4281342292
Short name T714
Test name
Test status
Simulation time 175418459612 ps
CPU time 13.91 seconds
Started Aug 13 05:14:25 PM PDT 24
Finished Aug 13 05:14:39 PM PDT 24
Peak memory 200868 kb
Host smart-b452e355-9619-4e82-80f6-a42a41928fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281342292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.4281342292
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.1683048530
Short name T503
Test name
Test status
Simulation time 95380534737 ps
CPU time 263.18 seconds
Started Aug 13 05:16:56 PM PDT 24
Finished Aug 13 05:21:19 PM PDT 24
Peak memory 200916 kb
Host smart-857112fa-f74d-4ae5-a2c7-9b5973ac9ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683048530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.1683048530
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2281395372
Short name T202
Test name
Test status
Simulation time 76871325398 ps
CPU time 34.21 seconds
Started Aug 13 05:16:54 PM PDT 24
Finished Aug 13 05:17:28 PM PDT 24
Peak memory 200908 kb
Host smart-63111a6e-a136-4933-b18f-7ef14d9749fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281395372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2281395372
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.951307754
Short name T748
Test name
Test status
Simulation time 162910614952 ps
CPU time 32.12 seconds
Started Aug 13 05:16:56 PM PDT 24
Finished Aug 13 05:17:28 PM PDT 24
Peak memory 200868 kb
Host smart-593fc3f6-c989-4bdf-bf34-27086b4b9dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951307754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.951307754
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.2606964857
Short name T977
Test name
Test status
Simulation time 27722625587 ps
CPU time 30.75 seconds
Started Aug 13 05:16:53 PM PDT 24
Finished Aug 13 05:17:24 PM PDT 24
Peak memory 200844 kb
Host smart-3ba9d7b5-d941-47b9-90bb-8e4202be134e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606964857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2606964857
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.2619220335
Short name T204
Test name
Test status
Simulation time 116338870173 ps
CPU time 120.66 seconds
Started Aug 13 05:16:57 PM PDT 24
Finished Aug 13 05:18:58 PM PDT 24
Peak memory 200184 kb
Host smart-65b3aade-209a-41cc-a244-1a15c20fb5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619220335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.2619220335
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.54479642
Short name T308
Test name
Test status
Simulation time 62397761980 ps
CPU time 20.13 seconds
Started Aug 13 05:16:57 PM PDT 24
Finished Aug 13 05:17:17 PM PDT 24
Peak memory 200096 kb
Host smart-3e3e0e0c-d92d-43aa-9e73-77f4fa4a4d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54479642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.54479642
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.2284341761
Short name T124
Test name
Test status
Simulation time 36595509814 ps
CPU time 32.4 seconds
Started Aug 13 05:16:53 PM PDT 24
Finished Aug 13 05:17:26 PM PDT 24
Peak memory 200852 kb
Host smart-d601f85e-b848-448e-8f7e-e41f84b722cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284341761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2284341761
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1595767292
Short name T549
Test name
Test status
Simulation time 13438617 ps
CPU time 0.55 seconds
Started Aug 13 05:14:22 PM PDT 24
Finished Aug 13 05:14:23 PM PDT 24
Peak memory 196240 kb
Host smart-f6330e28-4f6d-41a1-8953-ffb066dcf975
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595767292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1595767292
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.2272925208
Short name T907
Test name
Test status
Simulation time 78910471816 ps
CPU time 32.55 seconds
Started Aug 13 05:14:16 PM PDT 24
Finished Aug 13 05:14:49 PM PDT 24
Peak memory 200940 kb
Host smart-ef87f65b-4856-4712-9559-540ea4c66a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272925208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2272925208
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2341941561
Short name T169
Test name
Test status
Simulation time 74109421488 ps
CPU time 26.63 seconds
Started Aug 13 05:14:14 PM PDT 24
Finished Aug 13 05:14:41 PM PDT 24
Peak memory 200856 kb
Host smart-46b0d1a5-b069-446f-a8d0-3c83b0316598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341941561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2341941561
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2545517048
Short name T1055
Test name
Test status
Simulation time 12594435703 ps
CPU time 26.58 seconds
Started Aug 13 05:14:14 PM PDT 24
Finished Aug 13 05:14:41 PM PDT 24
Peak memory 200856 kb
Host smart-eff92102-346f-46ad-926c-7c6a73c2ddca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545517048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2545517048
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.3561222612
Short name T844
Test name
Test status
Simulation time 6658092682 ps
CPU time 3.92 seconds
Started Aug 13 05:14:14 PM PDT 24
Finished Aug 13 05:14:18 PM PDT 24
Peak memory 200016 kb
Host smart-38806750-2984-4ad9-b19d-89d33e8a6b17
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561222612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3561222612
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.452425815
Short name T709
Test name
Test status
Simulation time 91016406760 ps
CPU time 348.01 seconds
Started Aug 13 05:14:27 PM PDT 24
Finished Aug 13 05:20:15 PM PDT 24
Peak memory 200852 kb
Host smart-f3928bc3-7a33-4c7f-9745-f530fc42bf57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=452425815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.452425815
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.3154615483
Short name T840
Test name
Test status
Simulation time 8336145542 ps
CPU time 37.66 seconds
Started Aug 13 05:14:26 PM PDT 24
Finished Aug 13 05:15:04 PM PDT 24
Peak memory 200656 kb
Host smart-d5754b4c-0bbb-49e0-a56e-4fe613d162a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154615483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.3154615483
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.686365648
Short name T444
Test name
Test status
Simulation time 34427510177 ps
CPU time 15.29 seconds
Started Aug 13 05:14:16 PM PDT 24
Finished Aug 13 05:14:31 PM PDT 24
Peak memory 195824 kb
Host smart-0fc864ce-31d7-4706-ba55-124668aeb609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686365648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.686365648
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.1649001891
Short name T340
Test name
Test status
Simulation time 8381388252 ps
CPU time 110.75 seconds
Started Aug 13 05:14:21 PM PDT 24
Finished Aug 13 05:16:12 PM PDT 24
Peak memory 200876 kb
Host smart-80c477bb-d873-4be8-a218-b9a476623173
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1649001891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1649001891
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.3546581085
Short name T544
Test name
Test status
Simulation time 5263256833 ps
CPU time 49.59 seconds
Started Aug 13 05:14:24 PM PDT 24
Finished Aug 13 05:15:14 PM PDT 24
Peak memory 199088 kb
Host smart-fe87b1a2-dc69-449c-a870-5c0aa20f3a03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3546581085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3546581085
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1204566550
Short name T999
Test name
Test status
Simulation time 51662205692 ps
CPU time 72.41 seconds
Started Aug 13 05:14:22 PM PDT 24
Finished Aug 13 05:15:34 PM PDT 24
Peak memory 200924 kb
Host smart-4532bfd8-a769-47ce-b3d5-be961db002d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204566550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1204566550
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.3486164918
Short name T455
Test name
Test status
Simulation time 41420640362 ps
CPU time 16.79 seconds
Started Aug 13 05:14:23 PM PDT 24
Finished Aug 13 05:14:40 PM PDT 24
Peak memory 197700 kb
Host smart-1aacf87a-03cd-4121-ae53-5c20d86f31c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486164918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3486164918
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.4260717397
Short name T476
Test name
Test status
Simulation time 720546530 ps
CPU time 2.35 seconds
Started Aug 13 05:14:17 PM PDT 24
Finished Aug 13 05:14:19 PM PDT 24
Peak memory 199552 kb
Host smart-eb3c3890-3914-48a2-8f71-f37fa767da06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260717397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.4260717397
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.686812046
Short name T1149
Test name
Test status
Simulation time 3519744660 ps
CPU time 9.35 seconds
Started Aug 13 05:14:27 PM PDT 24
Finished Aug 13 05:14:37 PM PDT 24
Peak memory 209400 kb
Host smart-4cde8125-ec9f-4382-ac4f-2371541bf7b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686812046 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.686812046
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.857033311
Short name T743
Test name
Test status
Simulation time 7309294183 ps
CPU time 15.23 seconds
Started Aug 13 05:14:21 PM PDT 24
Finished Aug 13 05:14:36 PM PDT 24
Peak memory 200388 kb
Host smart-fe99ebf8-9c18-49ee-9529-cac3e7d6e01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857033311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.857033311
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.1361488585
Short name T291
Test name
Test status
Simulation time 24001744610 ps
CPU time 49.43 seconds
Started Aug 13 05:14:15 PM PDT 24
Finished Aug 13 05:15:05 PM PDT 24
Peak memory 200840 kb
Host smart-8ed41561-be6a-43c1-be6b-4274e8802bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361488585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1361488585
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.1093532948
Short name T210
Test name
Test status
Simulation time 85371760741 ps
CPU time 76.07 seconds
Started Aug 13 05:16:55 PM PDT 24
Finished Aug 13 05:18:11 PM PDT 24
Peak memory 200920 kb
Host smart-4ccf3d17-39fb-425a-9f63-41522e4d16d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093532948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1093532948
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.42451008
Short name T1040
Test name
Test status
Simulation time 32808667262 ps
CPU time 57.06 seconds
Started Aug 13 05:16:53 PM PDT 24
Finished Aug 13 05:17:50 PM PDT 24
Peak memory 200916 kb
Host smart-05cbc9ca-8c42-4898-9d8f-6d78ffd71b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42451008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.42451008
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.2787562582
Short name T1001
Test name
Test status
Simulation time 140461481100 ps
CPU time 109.4 seconds
Started Aug 13 05:16:55 PM PDT 24
Finished Aug 13 05:18:44 PM PDT 24
Peak memory 200784 kb
Host smart-c26dfe96-ba93-40fa-8d09-e7e216ae9655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787562582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.2787562582
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1818068158
Short name T184
Test name
Test status
Simulation time 64038646081 ps
CPU time 101.92 seconds
Started Aug 13 05:16:55 PM PDT 24
Finished Aug 13 05:18:37 PM PDT 24
Peak memory 200928 kb
Host smart-9f7d3641-3b0b-4871-885a-8613110dd8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818068158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1818068158
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.1281676467
Short name T738
Test name
Test status
Simulation time 30301408464 ps
CPU time 22.92 seconds
Started Aug 13 05:16:53 PM PDT 24
Finished Aug 13 05:17:16 PM PDT 24
Peak memory 200912 kb
Host smart-a79bb573-b517-46d4-ae67-8999ae72f452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281676467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1281676467
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1838960844
Short name T194
Test name
Test status
Simulation time 27451111663 ps
CPU time 44.1 seconds
Started Aug 13 05:16:55 PM PDT 24
Finished Aug 13 05:17:39 PM PDT 24
Peak memory 200880 kb
Host smart-b0748dc5-9f83-4b29-8250-388c95992792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838960844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1838960844
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3986365233
Short name T637
Test name
Test status
Simulation time 67071008644 ps
CPU time 20.79 seconds
Started Aug 13 05:16:54 PM PDT 24
Finished Aug 13 05:17:15 PM PDT 24
Peak memory 200708 kb
Host smart-020f267e-16f1-470d-85a8-b4bc67cc6ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986365233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3986365233
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1360958933
Short name T188
Test name
Test status
Simulation time 23927386322 ps
CPU time 48.16 seconds
Started Aug 13 05:16:53 PM PDT 24
Finished Aug 13 05:17:41 PM PDT 24
Peak memory 200856 kb
Host smart-4e8584fd-0f6a-40c0-8f4a-e95956f74f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360958933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1360958933
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3104696611
Short name T286
Test name
Test status
Simulation time 13288318972 ps
CPU time 19.57 seconds
Started Aug 13 05:16:53 PM PDT 24
Finished Aug 13 05:17:13 PM PDT 24
Peak memory 200880 kb
Host smart-bffc3fbf-d3b2-48cc-9378-a0525ce87350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104696611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3104696611
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3834162976
Short name T527
Test name
Test status
Simulation time 77781445842 ps
CPU time 92.5 seconds
Started Aug 13 05:16:54 PM PDT 24
Finished Aug 13 05:18:27 PM PDT 24
Peak memory 200936 kb
Host smart-150cc207-396a-46c6-9eaf-2d1452749dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834162976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3834162976
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2655950899
Short name T1066
Test name
Test status
Simulation time 10382352 ps
CPU time 0.54 seconds
Started Aug 13 05:14:33 PM PDT 24
Finished Aug 13 05:14:33 PM PDT 24
Peak memory 195452 kb
Host smart-84aa578f-e969-47cc-96ca-15c009e0cbda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655950899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2655950899
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.3116097021
Short name T470
Test name
Test status
Simulation time 37250620611 ps
CPU time 16.33 seconds
Started Aug 13 05:14:26 PM PDT 24
Finished Aug 13 05:14:43 PM PDT 24
Peak memory 200884 kb
Host smart-899fb128-0751-438c-b0f5-06e699f2cb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116097021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3116097021
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.2000959819
Short name T1146
Test name
Test status
Simulation time 20377587251 ps
CPU time 36.15 seconds
Started Aug 13 05:14:33 PM PDT 24
Finished Aug 13 05:15:09 PM PDT 24
Peak memory 200876 kb
Host smart-f08a8298-0fe1-4922-a7e0-30c9b51746b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000959819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2000959819
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.1372563216
Short name T129
Test name
Test status
Simulation time 32627848232 ps
CPU time 5.31 seconds
Started Aug 13 05:14:28 PM PDT 24
Finished Aug 13 05:14:33 PM PDT 24
Peak memory 200692 kb
Host smart-d4cdc0ee-e990-4411-bc69-389ee581690e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372563216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.1372563216
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.703945783
Short name T1129
Test name
Test status
Simulation time 5754061989 ps
CPU time 2.52 seconds
Started Aug 13 05:14:37 PM PDT 24
Finished Aug 13 05:14:40 PM PDT 24
Peak memory 197080 kb
Host smart-f02db083-e112-4005-a6e7-c26db30d0c61
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703945783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.703945783
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.1874575924
Short name T643
Test name
Test status
Simulation time 85436542544 ps
CPU time 416.93 seconds
Started Aug 13 05:14:37 PM PDT 24
Finished Aug 13 05:21:35 PM PDT 24
Peak memory 200832 kb
Host smart-4651af56-3bf5-406a-8668-321c82521720
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1874575924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1874575924
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2544702789
Short name T718
Test name
Test status
Simulation time 148423525 ps
CPU time 1.01 seconds
Started Aug 13 05:14:32 PM PDT 24
Finished Aug 13 05:14:33 PM PDT 24
Peak memory 198944 kb
Host smart-6849a50e-1b7a-4e9f-a52a-f4318a9b1e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544702789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2544702789
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.1873055360
Short name T696
Test name
Test status
Simulation time 168491741033 ps
CPU time 64.15 seconds
Started Aug 13 05:14:32 PM PDT 24
Finished Aug 13 05:15:36 PM PDT 24
Peak memory 201044 kb
Host smart-3cbe69aa-98bf-432d-8fe4-2696e719cb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873055360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1873055360
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.2327585371
Short name T934
Test name
Test status
Simulation time 9214013309 ps
CPU time 557.15 seconds
Started Aug 13 05:14:37 PM PDT 24
Finished Aug 13 05:23:54 PM PDT 24
Peak memory 200880 kb
Host smart-42c0ade6-71bf-4bec-9883-d3d105c125d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2327585371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.2327585371
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.2752716760
Short name T489
Test name
Test status
Simulation time 5936555951 ps
CPU time 40.29 seconds
Started Aug 13 05:14:28 PM PDT 24
Finished Aug 13 05:15:08 PM PDT 24
Peak memory 200384 kb
Host smart-25884fb2-1f37-4683-9fc5-cd35e4f44098
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2752716760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2752716760
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2534067712
Short name T1070
Test name
Test status
Simulation time 23574506208 ps
CPU time 34.22 seconds
Started Aug 13 05:14:29 PM PDT 24
Finished Aug 13 05:15:03 PM PDT 24
Peak memory 200796 kb
Host smart-c59cb846-3c2e-42ce-8861-588d2d3eac33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534067712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2534067712
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.983932152
Short name T1161
Test name
Test status
Simulation time 6328161387 ps
CPU time 2.93 seconds
Started Aug 13 05:14:27 PM PDT 24
Finished Aug 13 05:14:30 PM PDT 24
Peak memory 197036 kb
Host smart-ef8204f3-a0fc-44e1-9464-dc746deba605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983932152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.983932152
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1796615243
Short name T796
Test name
Test status
Simulation time 675203485 ps
CPU time 2.33 seconds
Started Aug 13 05:14:27 PM PDT 24
Finished Aug 13 05:14:29 PM PDT 24
Peak memory 199884 kb
Host smart-72a7119e-bf4e-414b-94f8-906367cb5c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796615243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1796615243
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2502273198
Short name T208
Test name
Test status
Simulation time 328349963653 ps
CPU time 1311.63 seconds
Started Aug 13 05:14:38 PM PDT 24
Finished Aug 13 05:36:30 PM PDT 24
Peak memory 200888 kb
Host smart-138c3f6d-0de5-440c-9cb3-4b07f8abc234
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502273198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2502273198
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1767894181
Short name T17
Test name
Test status
Simulation time 3789564358 ps
CPU time 22.11 seconds
Started Aug 13 05:14:30 PM PDT 24
Finished Aug 13 05:14:52 PM PDT 24
Peak memory 216576 kb
Host smart-a232a408-1244-4710-9c32-5dbdd4f3d3cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767894181 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1767894181
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1102393560
Short name T293
Test name
Test status
Simulation time 839084684 ps
CPU time 3.5 seconds
Started Aug 13 05:14:30 PM PDT 24
Finished Aug 13 05:14:33 PM PDT 24
Peak memory 200772 kb
Host smart-7395e4f6-9228-43dd-a0b6-8cf97a4724e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102393560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1102393560
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.34986672
Short name T1063
Test name
Test status
Simulation time 54280916727 ps
CPU time 119.34 seconds
Started Aug 13 05:14:24 PM PDT 24
Finished Aug 13 05:16:24 PM PDT 24
Peak memory 200920 kb
Host smart-7d5df192-36a1-41a1-8040-097bb547803f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34986672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.34986672
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.4286132185
Short name T237
Test name
Test status
Simulation time 179560491812 ps
CPU time 162.25 seconds
Started Aug 13 05:16:54 PM PDT 24
Finished Aug 13 05:19:36 PM PDT 24
Peak memory 200912 kb
Host smart-f86346f6-e248-40e2-949c-4977ff490a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286132185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.4286132185
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.4283207117
Short name T965
Test name
Test status
Simulation time 9302111857 ps
CPU time 5.39 seconds
Started Aug 13 05:16:53 PM PDT 24
Finished Aug 13 05:16:58 PM PDT 24
Peak memory 199724 kb
Host smart-fd31a162-cc2a-4896-ad8e-eaeab85dd796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283207117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.4283207117
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.3833944510
Short name T191
Test name
Test status
Simulation time 106125486837 ps
CPU time 70.36 seconds
Started Aug 13 05:17:05 PM PDT 24
Finished Aug 13 05:18:16 PM PDT 24
Peak memory 200852 kb
Host smart-6f4b82d4-8d84-4ff9-a749-417f92305420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833944510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3833944510
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.164656417
Short name T178
Test name
Test status
Simulation time 70141963179 ps
CPU time 22.18 seconds
Started Aug 13 05:17:03 PM PDT 24
Finished Aug 13 05:17:25 PM PDT 24
Peak memory 200876 kb
Host smart-39c2696f-2392-47f1-8af6-04ed2b72866e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164656417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.164656417
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1308235423
Short name T943
Test name
Test status
Simulation time 15092581189 ps
CPU time 22.06 seconds
Started Aug 13 05:17:05 PM PDT 24
Finished Aug 13 05:17:28 PM PDT 24
Peak memory 200932 kb
Host smart-5ae85190-61d7-47a7-b42b-fcc56105f34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308235423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1308235423
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.640843348
Short name T804
Test name
Test status
Simulation time 10970363643 ps
CPU time 19.61 seconds
Started Aug 13 05:17:04 PM PDT 24
Finished Aug 13 05:17:24 PM PDT 24
Peak memory 200848 kb
Host smart-8f250167-648b-4a7e-a821-ec17d146b634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640843348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.640843348
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.3052405307
Short name T902
Test name
Test status
Simulation time 85394478439 ps
CPU time 29.52 seconds
Started Aug 13 05:17:05 PM PDT 24
Finished Aug 13 05:17:35 PM PDT 24
Peak memory 200880 kb
Host smart-4458ab8e-97aa-4b43-bc1a-d393eaac1731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052405307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3052405307
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1835421180
Short name T707
Test name
Test status
Simulation time 172836628658 ps
CPU time 267.05 seconds
Started Aug 13 05:17:02 PM PDT 24
Finished Aug 13 05:21:29 PM PDT 24
Peak memory 200888 kb
Host smart-2356ade5-f7df-4ea2-8dd3-96fdc1c341e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835421180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1835421180
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1840211788
Short name T175
Test name
Test status
Simulation time 162497356688 ps
CPU time 74.85 seconds
Started Aug 13 05:17:05 PM PDT 24
Finished Aug 13 05:18:20 PM PDT 24
Peak memory 200932 kb
Host smart-387849eb-de91-466e-82cd-1ab4e64f6bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840211788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1840211788
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.23492172
Short name T609
Test name
Test status
Simulation time 12882058 ps
CPU time 0.61 seconds
Started Aug 13 05:13:39 PM PDT 24
Finished Aug 13 05:13:40 PM PDT 24
Peak memory 195468 kb
Host smart-0dfc60e4-e1f9-4e9a-9df4-1f55b7630405
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23492172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.23492172
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2768386787
Short name T942
Test name
Test status
Simulation time 44751814164 ps
CPU time 85.28 seconds
Started Aug 13 05:13:43 PM PDT 24
Finished Aug 13 05:15:08 PM PDT 24
Peak memory 200840 kb
Host smart-8abd0b8e-8c5a-4a09-a56d-ccd8ce3b3107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768386787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2768386787
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1582535719
Short name T944
Test name
Test status
Simulation time 67781108872 ps
CPU time 14.95 seconds
Started Aug 13 05:13:51 PM PDT 24
Finished Aug 13 05:14:06 PM PDT 24
Peak memory 200744 kb
Host smart-a1fe676f-5dbe-49ed-8638-215ee609f920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582535719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1582535719
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.815394764
Short name T595
Test name
Test status
Simulation time 147691930038 ps
CPU time 27.63 seconds
Started Aug 13 05:13:42 PM PDT 24
Finished Aug 13 05:14:10 PM PDT 24
Peak memory 200648 kb
Host smart-5ffba61b-0f78-41e2-a16e-c9c536dc68f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815394764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.815394764
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2571534601
Short name T686
Test name
Test status
Simulation time 31186846500 ps
CPU time 15.79 seconds
Started Aug 13 05:13:41 PM PDT 24
Finished Aug 13 05:13:57 PM PDT 24
Peak memory 200944 kb
Host smart-2f9639ea-9f08-45f6-b05f-e3abac6a7130
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571534601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2571534601
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.4216328415
Short name T502
Test name
Test status
Simulation time 116283079799 ps
CPU time 364.22 seconds
Started Aug 13 05:13:40 PM PDT 24
Finished Aug 13 05:19:44 PM PDT 24
Peak memory 200848 kb
Host smart-0dc593bd-f80f-41ce-97c3-4562a131c57f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4216328415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.4216328415
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.65102373
Short name T675
Test name
Test status
Simulation time 5253991566 ps
CPU time 8.38 seconds
Started Aug 13 05:13:38 PM PDT 24
Finished Aug 13 05:13:46 PM PDT 24
Peak memory 200528 kb
Host smart-604a30c6-16b5-458b-a2a8-605cd115e61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65102373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.65102373
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.1867175623
Short name T697
Test name
Test status
Simulation time 277255338808 ps
CPU time 39.82 seconds
Started Aug 13 05:13:42 PM PDT 24
Finished Aug 13 05:14:22 PM PDT 24
Peak memory 209300 kb
Host smart-8fb29176-2caa-4dc7-8d20-a69f4f231ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867175623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1867175623
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.700703286
Short name T668
Test name
Test status
Simulation time 15973005668 ps
CPU time 917.63 seconds
Started Aug 13 05:13:41 PM PDT 24
Finished Aug 13 05:28:59 PM PDT 24
Peak memory 200928 kb
Host smart-a217d5a8-a58a-4d8e-81ed-9d5daba7672b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=700703286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.700703286
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.276196443
Short name T1107
Test name
Test status
Simulation time 4104196570 ps
CPU time 28.24 seconds
Started Aug 13 05:13:39 PM PDT 24
Finished Aug 13 05:14:07 PM PDT 24
Peak memory 199240 kb
Host smart-868af4fc-b31c-456e-b7a5-df90a3ea46cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=276196443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.276196443
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.591325762
Short name T423
Test name
Test status
Simulation time 23485545377 ps
CPU time 35.71 seconds
Started Aug 13 05:13:40 PM PDT 24
Finished Aug 13 05:14:16 PM PDT 24
Peak memory 201088 kb
Host smart-8086fec7-7812-4d34-8e92-27cd3b578550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591325762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.591325762
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2224888563
Short name T80
Test name
Test status
Simulation time 43562076843 ps
CPU time 17.11 seconds
Started Aug 13 05:13:39 PM PDT 24
Finished Aug 13 05:13:56 PM PDT 24
Peak memory 196660 kb
Host smart-b20883b1-d421-48b9-97ad-0afd0739b572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224888563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2224888563
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.4105844145
Short name T25
Test name
Test status
Simulation time 114914131 ps
CPU time 0.88 seconds
Started Aug 13 05:13:40 PM PDT 24
Finished Aug 13 05:13:41 PM PDT 24
Peak memory 218920 kb
Host smart-16be709e-2e85-498b-a9f9-b88a1cd3ffc1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105844145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.4105844145
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.3055095600
Short name T1076
Test name
Test status
Simulation time 502089442 ps
CPU time 2.11 seconds
Started Aug 13 05:13:44 PM PDT 24
Finished Aug 13 05:13:47 PM PDT 24
Peak memory 200308 kb
Host smart-7156d3fc-43c3-4b66-89cc-e6ee16faced6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055095600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.3055095600
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.3570822084
Short name T1046
Test name
Test status
Simulation time 287253912318 ps
CPU time 202.07 seconds
Started Aug 13 05:13:42 PM PDT 24
Finished Aug 13 05:17:05 PM PDT 24
Peak memory 200860 kb
Host smart-a50231af-c1fe-452e-aafa-d39dd4982689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570822084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3570822084
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.660827529
Short name T1152
Test name
Test status
Simulation time 3492412995 ps
CPU time 47.29 seconds
Started Aug 13 05:13:40 PM PDT 24
Finished Aug 13 05:14:28 PM PDT 24
Peak memory 210424 kb
Host smart-c176ffd4-09da-4dc1-9734-68a7ee71c3f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660827529 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.660827529
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3894215698
Short name T1013
Test name
Test status
Simulation time 595057933 ps
CPU time 1.31 seconds
Started Aug 13 05:13:47 PM PDT 24
Finished Aug 13 05:13:48 PM PDT 24
Peak memory 199096 kb
Host smart-43487d8c-a910-4e0f-9378-03886ec0631b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894215698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3894215698
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.558562940
Short name T475
Test name
Test status
Simulation time 44326075543 ps
CPU time 64.95 seconds
Started Aug 13 05:13:41 PM PDT 24
Finished Aug 13 05:14:46 PM PDT 24
Peak memory 200860 kb
Host smart-7ceb7de2-a4a3-45a4-b182-b5f3cd565888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558562940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.558562940
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.3347470451
Short name T384
Test name
Test status
Simulation time 59098443 ps
CPU time 0.56 seconds
Started Aug 13 05:14:30 PM PDT 24
Finished Aug 13 05:14:31 PM PDT 24
Peak memory 196232 kb
Host smart-be309146-3e70-4500-8a4c-1e7ca9373a7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347470451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3347470451
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1244398871
Short name T420
Test name
Test status
Simulation time 33906500420 ps
CPU time 55.5 seconds
Started Aug 13 05:14:29 PM PDT 24
Finished Aug 13 05:15:25 PM PDT 24
Peak memory 200852 kb
Host smart-fccc375e-82cc-4b02-bc21-dea62c67657e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244398871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1244398871
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3856704420
Short name T161
Test name
Test status
Simulation time 19769600027 ps
CPU time 18.18 seconds
Started Aug 13 05:14:33 PM PDT 24
Finished Aug 13 05:14:51 PM PDT 24
Peak memory 200920 kb
Host smart-5b27e021-cc78-4839-b9c7-759362e0b410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856704420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3856704420
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1123075299
Short name T1155
Test name
Test status
Simulation time 67144130920 ps
CPU time 38.08 seconds
Started Aug 13 05:14:30 PM PDT 24
Finished Aug 13 05:15:08 PM PDT 24
Peak memory 200840 kb
Host smart-5ac62d22-78fc-4d70-9a29-d9f2117d7f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123075299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1123075299
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.2495019878
Short name T950
Test name
Test status
Simulation time 15852765329 ps
CPU time 4.19 seconds
Started Aug 13 05:14:30 PM PDT 24
Finished Aug 13 05:14:34 PM PDT 24
Peak memory 200524 kb
Host smart-a8b9d28c-ccb1-43ae-bd30-bae5df93388e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495019878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2495019878
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1674858356
Short name T311
Test name
Test status
Simulation time 46903941890 ps
CPU time 198.65 seconds
Started Aug 13 05:14:30 PM PDT 24
Finished Aug 13 05:17:49 PM PDT 24
Peak memory 200924 kb
Host smart-0fcff6e6-34ea-4ce5-83ea-57a47322bd6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1674858356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1674858356
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.597249800
Short name T1094
Test name
Test status
Simulation time 12749656781 ps
CPU time 2.86 seconds
Started Aug 13 05:14:37 PM PDT 24
Finished Aug 13 05:14:40 PM PDT 24
Peak memory 200732 kb
Host smart-87013404-ef7f-4f82-9484-45e37b346984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597249800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.597249800
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_perf.474165568
Short name T747
Test name
Test status
Simulation time 6594659588 ps
CPU time 336.12 seconds
Started Aug 13 05:14:30 PM PDT 24
Finished Aug 13 05:20:07 PM PDT 24
Peak memory 200864 kb
Host smart-204fc422-18ee-4385-85fe-7244dc8d60e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=474165568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.474165568
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2928982983
Short name T781
Test name
Test status
Simulation time 2116935028 ps
CPU time 14.88 seconds
Started Aug 13 05:14:38 PM PDT 24
Finished Aug 13 05:14:53 PM PDT 24
Peak memory 200008 kb
Host smart-9d00b97f-2ad1-4c96-8976-ed9a8fd457ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2928982983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2928982983
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.660920910
Short name T41
Test name
Test status
Simulation time 148441845919 ps
CPU time 29.54 seconds
Started Aug 13 05:14:33 PM PDT 24
Finished Aug 13 05:15:03 PM PDT 24
Peak memory 200720 kb
Host smart-876aba0e-c2c2-404f-83da-82afcb50027c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660920910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.660920910
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.2826116969
Short name T1004
Test name
Test status
Simulation time 3001909235 ps
CPU time 5.46 seconds
Started Aug 13 05:14:37 PM PDT 24
Finished Aug 13 05:14:43 PM PDT 24
Peak memory 196852 kb
Host smart-6ed3129f-ba9b-405a-94a7-34a30272152a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826116969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2826116969
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.63819517
Short name T501
Test name
Test status
Simulation time 480613903 ps
CPU time 1.99 seconds
Started Aug 13 05:14:32 PM PDT 24
Finished Aug 13 05:14:34 PM PDT 24
Peak memory 200840 kb
Host smart-74bd1434-dfcc-4a14-b696-0cc3bc7be72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63819517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.63819517
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.767940986
Short name T873
Test name
Test status
Simulation time 151403548660 ps
CPU time 399.16 seconds
Started Aug 13 05:14:37 PM PDT 24
Finished Aug 13 05:21:17 PM PDT 24
Peak memory 200940 kb
Host smart-355dfcbe-ecf7-4be7-943f-9fd5d5414025
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767940986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.767940986
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.3772607277
Short name T771
Test name
Test status
Simulation time 3717621465 ps
CPU time 49.42 seconds
Started Aug 13 05:14:38 PM PDT 24
Finished Aug 13 05:15:27 PM PDT 24
Peak memory 216440 kb
Host smart-1c3f1f51-976c-4481-b012-7978499c05fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772607277 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.3772607277
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2674592577
Short name T425
Test name
Test status
Simulation time 160764547 ps
CPU time 0.92 seconds
Started Aug 13 05:14:29 PM PDT 24
Finished Aug 13 05:14:30 PM PDT 24
Peak memory 198032 kb
Host smart-5b15c916-8e0b-440f-a103-baec23f2282b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674592577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2674592577
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3692089491
Short name T843
Test name
Test status
Simulation time 14629700188 ps
CPU time 25.33 seconds
Started Aug 13 05:14:33 PM PDT 24
Finished Aug 13 05:14:58 PM PDT 24
Peak memory 200944 kb
Host smart-8434916d-613a-461d-85d9-4c74ba870387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692089491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3692089491
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1662336587
Short name T1056
Test name
Test status
Simulation time 31114073254 ps
CPU time 47.08 seconds
Started Aug 13 05:17:06 PM PDT 24
Finished Aug 13 05:17:53 PM PDT 24
Peak memory 200940 kb
Host smart-e515c17c-9cf2-47b8-9ef4-84a5cdd5c04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662336587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1662336587
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1626256066
Short name T1089
Test name
Test status
Simulation time 17305987867 ps
CPU time 33.35 seconds
Started Aug 13 05:17:03 PM PDT 24
Finished Aug 13 05:17:37 PM PDT 24
Peak memory 200848 kb
Host smart-19f25899-b227-4a0d-8daa-69bc37a0ffdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626256066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1626256066
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3191291604
Short name T585
Test name
Test status
Simulation time 52988524834 ps
CPU time 75.11 seconds
Started Aug 13 05:17:03 PM PDT 24
Finished Aug 13 05:18:18 PM PDT 24
Peak memory 200684 kb
Host smart-f037bdc3-566e-410d-adfd-55258e93fc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191291604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3191291604
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.393674347
Short name T362
Test name
Test status
Simulation time 39666702166 ps
CPU time 23.54 seconds
Started Aug 13 05:17:03 PM PDT 24
Finished Aug 13 05:17:26 PM PDT 24
Peak memory 200804 kb
Host smart-64ff13d3-4931-40e3-a45b-70b5a4716948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393674347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.393674347
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1547437173
Short name T199
Test name
Test status
Simulation time 82833364506 ps
CPU time 36.69 seconds
Started Aug 13 05:17:04 PM PDT 24
Finished Aug 13 05:17:41 PM PDT 24
Peak memory 200940 kb
Host smart-0044aa7d-1402-47b5-948a-2e7732f28123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547437173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1547437173
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.4080132068
Short name T780
Test name
Test status
Simulation time 6425693312 ps
CPU time 5.85 seconds
Started Aug 13 05:17:07 PM PDT 24
Finished Aug 13 05:17:13 PM PDT 24
Peak memory 200920 kb
Host smart-f5bcfb68-96a0-4559-8a8e-9f03da3180d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080132068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.4080132068
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.4042795861
Short name T608
Test name
Test status
Simulation time 16271057 ps
CPU time 0.55 seconds
Started Aug 13 05:14:40 PM PDT 24
Finished Aug 13 05:14:40 PM PDT 24
Peak memory 196524 kb
Host smart-f9d7f283-87cc-437f-8ca6-4049e7a05b8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042795861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.4042795861
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.1968596382
Short name T471
Test name
Test status
Simulation time 275994662935 ps
CPU time 443.93 seconds
Started Aug 13 05:14:29 PM PDT 24
Finished Aug 13 05:21:53 PM PDT 24
Peak memory 200836 kb
Host smart-76945067-5a9b-4f45-95a8-b42cf614332d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968596382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.1968596382
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2414598
Short name T136
Test name
Test status
Simulation time 125227322732 ps
CPU time 26.12 seconds
Started Aug 13 05:14:28 PM PDT 24
Finished Aug 13 05:14:54 PM PDT 24
Peak memory 200744 kb
Host smart-b8d17e22-d5a3-4e6a-9195-e8d165be5c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2414598
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.574725956
Short name T820
Test name
Test status
Simulation time 57793193219 ps
CPU time 21.48 seconds
Started Aug 13 05:14:34 PM PDT 24
Finished Aug 13 05:14:55 PM PDT 24
Peak memory 200792 kb
Host smart-7092dff7-d3aa-43cb-9205-266c98e9a6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574725956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.574725956
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.615212869
Short name T499
Test name
Test status
Simulation time 43634104183 ps
CPU time 83.36 seconds
Started Aug 13 05:14:36 PM PDT 24
Finished Aug 13 05:16:00 PM PDT 24
Peak memory 200944 kb
Host smart-e39f0eee-02c5-4117-bff2-7f0cdb887cac
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615212869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.615212869
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.553425040
Short name T553
Test name
Test status
Simulation time 83977345389 ps
CPU time 62.02 seconds
Started Aug 13 05:14:36 PM PDT 24
Finished Aug 13 05:15:38 PM PDT 24
Peak memory 200916 kb
Host smart-7ec29496-f8c8-4f90-bff4-04800b390732
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=553425040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.553425040
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.3214631901
Short name T1111
Test name
Test status
Simulation time 3300726209 ps
CPU time 7.77 seconds
Started Aug 13 05:14:37 PM PDT 24
Finished Aug 13 05:14:44 PM PDT 24
Peak memory 200436 kb
Host smart-eeffb5ef-4d24-4583-bce6-1e8fb681793d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214631901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3214631901
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.2655006956
Short name T419
Test name
Test status
Simulation time 39302515368 ps
CPU time 34.72 seconds
Started Aug 13 05:14:29 PM PDT 24
Finished Aug 13 05:15:04 PM PDT 24
Peak memory 201128 kb
Host smart-d8779cd6-e4ed-4f33-af57-c0fd85bf50fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655006956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.2655006956
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.1992222450
Short name T536
Test name
Test status
Simulation time 20089126279 ps
CPU time 107.72 seconds
Started Aug 13 05:14:37 PM PDT 24
Finished Aug 13 05:16:24 PM PDT 24
Peak memory 200832 kb
Host smart-5f3cfcf1-64ce-43c6-a09d-b9ad5de59569
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1992222450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1992222450
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.1911828371
Short name T411
Test name
Test status
Simulation time 3907370132 ps
CPU time 14.53 seconds
Started Aug 13 05:14:30 PM PDT 24
Finished Aug 13 05:14:45 PM PDT 24
Peak memory 199728 kb
Host smart-c3ad985f-f7b4-4afe-8604-91139cc04657
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1911828371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1911828371
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.4228686506
Short name T1016
Test name
Test status
Simulation time 71358304730 ps
CPU time 10.39 seconds
Started Aug 13 05:14:30 PM PDT 24
Finished Aug 13 05:14:40 PM PDT 24
Peak memory 200952 kb
Host smart-dc1ddd00-efb0-46d7-956b-3bce3ee4ede0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228686506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.4228686506
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.107131977
Short name T957
Test name
Test status
Simulation time 25158872188 ps
CPU time 6.05 seconds
Started Aug 13 05:14:37 PM PDT 24
Finished Aug 13 05:14:43 PM PDT 24
Peak memory 197028 kb
Host smart-c8db7647-21b1-441c-967b-8527f93db994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107131977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.107131977
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1816695753
Short name T1023
Test name
Test status
Simulation time 5557466153 ps
CPU time 17.51 seconds
Started Aug 13 05:14:37 PM PDT 24
Finished Aug 13 05:14:54 PM PDT 24
Peak memory 200752 kb
Host smart-b464e35a-f1b2-4247-841f-abeca02f25c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816695753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1816695753
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.370751637
Short name T640
Test name
Test status
Simulation time 33746192190 ps
CPU time 46.46 seconds
Started Aug 13 05:14:37 PM PDT 24
Finished Aug 13 05:15:24 PM PDT 24
Peak memory 200860 kb
Host smart-c14b61f0-e7b7-470a-b219-20291be23eb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370751637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.370751637
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.3093514117
Short name T1067
Test name
Test status
Simulation time 3804988430 ps
CPU time 1.34 seconds
Started Aug 13 05:14:38 PM PDT 24
Finished Aug 13 05:14:40 PM PDT 24
Peak memory 199840 kb
Host smart-586eb03a-fc44-40dd-8b51-444afcd147b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093514117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3093514117
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2621767496
Short name T917
Test name
Test status
Simulation time 28115753549 ps
CPU time 9.31 seconds
Started Aug 13 05:14:31 PM PDT 24
Finished Aug 13 05:14:40 PM PDT 24
Peak memory 200928 kb
Host smart-86d71ae4-4a4a-4940-878f-f97ad0ada754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621767496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2621767496
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2315398566
Short name T278
Test name
Test status
Simulation time 118277143996 ps
CPU time 173.45 seconds
Started Aug 13 05:17:01 PM PDT 24
Finished Aug 13 05:19:55 PM PDT 24
Peak memory 200840 kb
Host smart-8aaef86d-5ec7-4168-9a37-cb6b3afc3dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315398566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2315398566
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3308901132
Short name T814
Test name
Test status
Simulation time 87894012900 ps
CPU time 64.94 seconds
Started Aug 13 05:17:02 PM PDT 24
Finished Aug 13 05:18:07 PM PDT 24
Peak memory 200768 kb
Host smart-624cde9e-26d6-44fa-843d-04bde0ee2f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308901132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3308901132
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2572190472
Short name T1036
Test name
Test status
Simulation time 78851241840 ps
CPU time 490.16 seconds
Started Aug 13 05:17:05 PM PDT 24
Finished Aug 13 05:25:16 PM PDT 24
Peak memory 200880 kb
Host smart-c289458f-74ea-4b68-afe9-c47f7b2f31f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572190472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2572190472
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.3073119412
Short name T1072
Test name
Test status
Simulation time 7559336188 ps
CPU time 12.92 seconds
Started Aug 13 05:17:04 PM PDT 24
Finished Aug 13 05:17:17 PM PDT 24
Peak memory 200920 kb
Host smart-d4f9cc30-4a97-4aba-8039-4031645f27e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073119412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3073119412
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.263933983
Short name T235
Test name
Test status
Simulation time 219205344276 ps
CPU time 39.27 seconds
Started Aug 13 05:17:05 PM PDT 24
Finished Aug 13 05:17:45 PM PDT 24
Peak memory 200864 kb
Host smart-73b0263c-19f2-4e17-9e56-ff377e9f311c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263933983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.263933983
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3686218896
Short name T189
Test name
Test status
Simulation time 119053148310 ps
CPU time 98.86 seconds
Started Aug 13 05:17:03 PM PDT 24
Finished Aug 13 05:18:42 PM PDT 24
Peak memory 200876 kb
Host smart-e671557b-8338-422e-9fde-e742029d30ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686218896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3686218896
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.1837960742
Short name T282
Test name
Test status
Simulation time 107925607018 ps
CPU time 77.03 seconds
Started Aug 13 05:17:05 PM PDT 24
Finished Aug 13 05:18:22 PM PDT 24
Peak memory 200936 kb
Host smart-9759aa1f-9224-4668-a062-fd99ddc22b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837960742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1837960742
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1957636391
Short name T767
Test name
Test status
Simulation time 4919859840 ps
CPU time 8.89 seconds
Started Aug 13 05:17:04 PM PDT 24
Finished Aug 13 05:17:13 PM PDT 24
Peak memory 200664 kb
Host smart-e3272e6e-8325-43f8-b6d2-6aa6a16e9297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957636391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1957636391
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3513517418
Short name T1075
Test name
Test status
Simulation time 13624026 ps
CPU time 0.57 seconds
Started Aug 13 05:14:38 PM PDT 24
Finished Aug 13 05:14:39 PM PDT 24
Peak memory 196476 kb
Host smart-9e915076-6d19-4a25-ac90-acf067c9b498
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513517418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3513517418
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3005496602
Short name T149
Test name
Test status
Simulation time 206087349065 ps
CPU time 83.3 seconds
Started Aug 13 05:14:36 PM PDT 24
Finished Aug 13 05:15:59 PM PDT 24
Peak memory 200816 kb
Host smart-d0e13d43-bf30-48c0-9f0b-a553f23c67d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005496602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3005496602
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.899527894
Short name T626
Test name
Test status
Simulation time 115522312147 ps
CPU time 34.34 seconds
Started Aug 13 05:14:38 PM PDT 24
Finished Aug 13 05:15:12 PM PDT 24
Peak memory 200864 kb
Host smart-0d4702b9-dae6-43c3-b4f8-ca944ab399f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899527894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.899527894
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_intr.3356376942
Short name T99
Test name
Test status
Simulation time 35994807943 ps
CPU time 32 seconds
Started Aug 13 05:14:37 PM PDT 24
Finished Aug 13 05:15:09 PM PDT 24
Peak memory 199952 kb
Host smart-0d27b264-2687-4f8e-84c7-f437a65a8d8f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356376942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3356376942
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.4131721276
Short name T1138
Test name
Test status
Simulation time 185597998690 ps
CPU time 320.89 seconds
Started Aug 13 05:14:38 PM PDT 24
Finished Aug 13 05:19:59 PM PDT 24
Peak memory 200872 kb
Host smart-b54e5a5d-0982-4fe5-b824-a65431021d08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4131721276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.4131721276
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.3308358615
Short name T683
Test name
Test status
Simulation time 344108438 ps
CPU time 1.08 seconds
Started Aug 13 05:14:36 PM PDT 24
Finished Aug 13 05:14:37 PM PDT 24
Peak memory 198180 kb
Host smart-61561c96-8741-4b08-b520-0699e1d52eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308358615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3308358615
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.2492100476
Short name T741
Test name
Test status
Simulation time 36737706236 ps
CPU time 63.62 seconds
Started Aug 13 05:14:37 PM PDT 24
Finished Aug 13 05:15:41 PM PDT 24
Peak memory 201108 kb
Host smart-6b789fee-f287-41d1-aa09-0eaf1d88cb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492100476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2492100476
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.3298431636
Short name T272
Test name
Test status
Simulation time 4211606407 ps
CPU time 186.4 seconds
Started Aug 13 05:14:39 PM PDT 24
Finished Aug 13 05:17:45 PM PDT 24
Peak memory 201076 kb
Host smart-3e940f7b-3b4b-4cb0-89e5-f0c2999dfcc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3298431636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3298431636
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.572709494
Short name T369
Test name
Test status
Simulation time 1909240453 ps
CPU time 9.53 seconds
Started Aug 13 05:14:39 PM PDT 24
Finished Aug 13 05:14:49 PM PDT 24
Peak memory 200012 kb
Host smart-90625eff-d7e1-4c15-b06d-f9e39ec7942c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=572709494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.572709494
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.911771209
Short name T716
Test name
Test status
Simulation time 73327766499 ps
CPU time 29.6 seconds
Started Aug 13 05:14:38 PM PDT 24
Finished Aug 13 05:15:07 PM PDT 24
Peak memory 200428 kb
Host smart-28a6ae42-289f-4feb-9969-1ef30aeb9cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911771209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.911771209
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.3812681060
Short name T1109
Test name
Test status
Simulation time 2943346844 ps
CPU time 1.04 seconds
Started Aug 13 05:14:37 PM PDT 24
Finished Aug 13 05:14:39 PM PDT 24
Peak memory 197404 kb
Host smart-0b6c5bbf-9020-42f4-b631-fccbdabced9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812681060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3812681060
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.11949186
Short name T305
Test name
Test status
Simulation time 289886295 ps
CPU time 1.18 seconds
Started Aug 13 05:14:37 PM PDT 24
Finished Aug 13 05:14:39 PM PDT 24
Peak memory 199504 kb
Host smart-86b35543-5918-424c-9bb0-d2a3249e661a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11949186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.11949186
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.4257494360
Short name T851
Test name
Test status
Simulation time 71655953812 ps
CPU time 276.87 seconds
Started Aug 13 05:14:38 PM PDT 24
Finished Aug 13 05:19:15 PM PDT 24
Peak memory 209304 kb
Host smart-5c175bd5-0224-4bf4-a4be-4454505c6a2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257494360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.4257494360
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.1636972670
Short name T89
Test name
Test status
Simulation time 1967524681 ps
CPU time 25.9 seconds
Started Aug 13 05:14:39 PM PDT 24
Finished Aug 13 05:15:05 PM PDT 24
Peak memory 209136 kb
Host smart-6cda9247-90fa-4cbd-a099-cfe75d9d0a50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636972670 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1636972670
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.3091847691
Short name T429
Test name
Test status
Simulation time 1145575007 ps
CPU time 1.82 seconds
Started Aug 13 05:14:35 PM PDT 24
Finished Aug 13 05:14:37 PM PDT 24
Peak memory 199808 kb
Host smart-bd9d6f7d-aebc-4e6d-ae09-12437e7195d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091847691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3091847691
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1888360393
Short name T519
Test name
Test status
Simulation time 54644876101 ps
CPU time 26.13 seconds
Started Aug 13 05:14:35 PM PDT 24
Finished Aug 13 05:15:01 PM PDT 24
Peak memory 200908 kb
Host smart-d9f8e813-277f-4c24-a1e0-65d7430e8fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888360393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1888360393
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.443090634
Short name T409
Test name
Test status
Simulation time 197390669756 ps
CPU time 102.11 seconds
Started Aug 13 05:17:04 PM PDT 24
Finished Aug 13 05:18:46 PM PDT 24
Peak memory 200876 kb
Host smart-00a3790b-1fcc-4bf2-93a0-62092d2b3c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443090634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.443090634
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3482583102
Short name T153
Test name
Test status
Simulation time 139995601384 ps
CPU time 212.43 seconds
Started Aug 13 05:17:05 PM PDT 24
Finished Aug 13 05:20:37 PM PDT 24
Peak memory 200936 kb
Host smart-eb82ea81-900e-4925-9ec2-47605a89f57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482583102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3482583102
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.297669868
Short name T823
Test name
Test status
Simulation time 22852791523 ps
CPU time 44.86 seconds
Started Aug 13 05:17:04 PM PDT 24
Finished Aug 13 05:17:49 PM PDT 24
Peak memory 200924 kb
Host smart-fd95dfb1-72b2-40a4-87f1-0a4d5de02671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297669868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.297669868
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1230603338
Short name T1096
Test name
Test status
Simulation time 41258556494 ps
CPU time 34.71 seconds
Started Aug 13 05:17:02 PM PDT 24
Finished Aug 13 05:17:36 PM PDT 24
Peak memory 200872 kb
Host smart-f32fb05b-21db-4cef-a743-55194ec62ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230603338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1230603338
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3152718093
Short name T680
Test name
Test status
Simulation time 26871678121 ps
CPU time 9.95 seconds
Started Aug 13 05:17:03 PM PDT 24
Finished Aug 13 05:17:13 PM PDT 24
Peak memory 200848 kb
Host smart-9dd56c43-fc16-480f-a0e8-993064494946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152718093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3152718093
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.997520959
Short name T95
Test name
Test status
Simulation time 148057196650 ps
CPU time 66.01 seconds
Started Aug 13 05:17:04 PM PDT 24
Finished Aug 13 05:18:10 PM PDT 24
Peak memory 200792 kb
Host smart-ac9c7b30-78b5-4e99-9392-e7b52d305952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997520959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.997520959
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3729667838
Short name T265
Test name
Test status
Simulation time 13778496429 ps
CPU time 13.54 seconds
Started Aug 13 05:17:09 PM PDT 24
Finished Aug 13 05:17:22 PM PDT 24
Peak memory 200924 kb
Host smart-abd87db6-bf8d-4437-bbb5-8e9abc0c4e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729667838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3729667838
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3255870550
Short name T994
Test name
Test status
Simulation time 131339918671 ps
CPU time 50.56 seconds
Started Aug 13 05:17:10 PM PDT 24
Finished Aug 13 05:18:01 PM PDT 24
Peak memory 200928 kb
Host smart-358c1701-8e24-494a-979b-2f57fe7b814e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255870550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3255870550
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.2367347960
Short name T371
Test name
Test status
Simulation time 14257581 ps
CPU time 0.56 seconds
Started Aug 13 05:14:46 PM PDT 24
Finished Aug 13 05:14:46 PM PDT 24
Peak memory 195792 kb
Host smart-68c6a5d1-4f87-439a-a56e-075123ed1506
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367347960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2367347960
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2741542141
Short name T329
Test name
Test status
Simulation time 171414657130 ps
CPU time 61.59 seconds
Started Aug 13 05:14:35 PM PDT 24
Finished Aug 13 05:15:36 PM PDT 24
Peak memory 200868 kb
Host smart-cb1590cf-e377-40a4-9892-9b9a43b4515c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741542141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2741542141
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.1598093570
Short name T892
Test name
Test status
Simulation time 48092173151 ps
CPU time 80.07 seconds
Started Aug 13 05:14:34 PM PDT 24
Finished Aug 13 05:15:54 PM PDT 24
Peak memory 200860 kb
Host smart-75d0c847-7fa5-4f64-ae2e-befb90039714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598093570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.1598093570
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_intr.3041104651
Short name T877
Test name
Test status
Simulation time 31605625480 ps
CPU time 19.43 seconds
Started Aug 13 05:14:35 PM PDT 24
Finished Aug 13 05:14:55 PM PDT 24
Peak memory 200792 kb
Host smart-3165a6d9-6519-4ee4-b988-9866a1e06ee7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041104651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3041104651
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.2118557753
Short name T262
Test name
Test status
Simulation time 98511994876 ps
CPU time 187.31 seconds
Started Aug 13 05:14:43 PM PDT 24
Finished Aug 13 05:17:51 PM PDT 24
Peak memory 200916 kb
Host smart-66c4139d-cb51-4680-ad4e-4628d3b6ecbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2118557753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2118557753
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.2767324364
Short name T546
Test name
Test status
Simulation time 4274955067 ps
CPU time 9.37 seconds
Started Aug 13 05:14:44 PM PDT 24
Finished Aug 13 05:14:54 PM PDT 24
Peak memory 200336 kb
Host smart-cd74d9ae-fb01-4ce1-92af-52c4d1037573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767324364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2767324364
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.3676183421
Short name T451
Test name
Test status
Simulation time 9125845142 ps
CPU time 8.43 seconds
Started Aug 13 05:14:37 PM PDT 24
Finished Aug 13 05:14:46 PM PDT 24
Peak memory 196884 kb
Host smart-eee63c17-2ecc-4064-b14a-a9abb2625951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676183421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.3676183421
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.1775434887
Short name T35
Test name
Test status
Simulation time 19036523799 ps
CPU time 73.76 seconds
Started Aug 13 05:14:43 PM PDT 24
Finished Aug 13 05:15:57 PM PDT 24
Peak memory 200796 kb
Host smart-dacd8700-f0c3-450b-935c-0533eb217e00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1775434887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1775434887
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.2588138982
Short name T1022
Test name
Test status
Simulation time 1287206911 ps
CPU time 1.07 seconds
Started Aug 13 05:14:39 PM PDT 24
Finished Aug 13 05:14:40 PM PDT 24
Peak memory 196512 kb
Host smart-ea305de8-d2e6-47d7-a824-2015f02dcd19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2588138982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2588138982
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.438266121
Short name T1053
Test name
Test status
Simulation time 94947846318 ps
CPU time 43.06 seconds
Started Aug 13 05:14:44 PM PDT 24
Finished Aug 13 05:15:27 PM PDT 24
Peak memory 200912 kb
Host smart-e36c616d-8d0e-4d1c-9473-05e4a0217d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438266121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.438266121
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.1784537305
Short name T593
Test name
Test status
Simulation time 1821397783 ps
CPU time 3.47 seconds
Started Aug 13 05:14:44 PM PDT 24
Finished Aug 13 05:14:47 PM PDT 24
Peak memory 196432 kb
Host smart-51cea383-4daa-4930-84d7-c542c6981e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784537305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1784537305
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.2590188695
Short name T1012
Test name
Test status
Simulation time 5543156887 ps
CPU time 19.23 seconds
Started Aug 13 05:14:38 PM PDT 24
Finished Aug 13 05:14:58 PM PDT 24
Peak memory 200696 kb
Host smart-531fa3cb-e085-444f-8cfc-0b47b4ec52b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590188695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2590188695
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.1956288952
Short name T1062
Test name
Test status
Simulation time 309047381692 ps
CPU time 122.11 seconds
Started Aug 13 05:14:44 PM PDT 24
Finished Aug 13 05:16:46 PM PDT 24
Peak memory 200908 kb
Host smart-1cbd458e-a596-4de8-9598-39629c697987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956288952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1956288952
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3354329443
Short name T705
Test name
Test status
Simulation time 1707598034 ps
CPU time 20.98 seconds
Started Aug 13 05:14:42 PM PDT 24
Finished Aug 13 05:15:03 PM PDT 24
Peak memory 217220 kb
Host smart-7697f1a8-b850-4c57-a288-1a1389efb16f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354329443 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3354329443
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.3332894872
Short name T481
Test name
Test status
Simulation time 1041676940 ps
CPU time 2.9 seconds
Started Aug 13 05:14:44 PM PDT 24
Finished Aug 13 05:14:47 PM PDT 24
Peak memory 200492 kb
Host smart-4202c589-cd23-43ca-9e5d-75968306ee1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332894872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3332894872
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.665539468
Short name T754
Test name
Test status
Simulation time 57389314217 ps
CPU time 22.7 seconds
Started Aug 13 05:14:38 PM PDT 24
Finished Aug 13 05:15:01 PM PDT 24
Peak memory 200900 kb
Host smart-bbe5be69-f933-4308-928f-788446c46a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665539468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.665539468
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1987828405
Short name T8
Test name
Test status
Simulation time 18325712990 ps
CPU time 25.63 seconds
Started Aug 13 05:17:13 PM PDT 24
Finished Aug 13 05:17:39 PM PDT 24
Peak memory 200916 kb
Host smart-ea7044b2-808f-498d-a123-0e04f34c75e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987828405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1987828405
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.821429436
Short name T1045
Test name
Test status
Simulation time 66403703988 ps
CPU time 24.09 seconds
Started Aug 13 05:17:09 PM PDT 24
Finished Aug 13 05:17:34 PM PDT 24
Peak memory 200924 kb
Host smart-5980c4cf-066a-4de4-97cc-3d4c8ad54f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821429436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.821429436
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3972880782
Short name T82
Test name
Test status
Simulation time 38148636375 ps
CPU time 14.59 seconds
Started Aug 13 05:17:10 PM PDT 24
Finished Aug 13 05:17:24 PM PDT 24
Peak memory 200828 kb
Host smart-98dadc74-203a-492e-b87a-4b2d8582edba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972880782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3972880782
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.445702108
Short name T359
Test name
Test status
Simulation time 22264632388 ps
CPU time 15.45 seconds
Started Aug 13 05:17:10 PM PDT 24
Finished Aug 13 05:17:26 PM PDT 24
Peak memory 200892 kb
Host smart-dc3d4163-1463-497d-af66-ad41b4410e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445702108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.445702108
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3574136973
Short name T911
Test name
Test status
Simulation time 45797159089 ps
CPU time 25.02 seconds
Started Aug 13 05:17:15 PM PDT 24
Finished Aug 13 05:17:40 PM PDT 24
Peak memory 200852 kb
Host smart-19a2846f-8b80-468d-b640-eddc1ec1adec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574136973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3574136973
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.3515070739
Short name T327
Test name
Test status
Simulation time 243174837556 ps
CPU time 408.39 seconds
Started Aug 13 05:17:13 PM PDT 24
Finished Aug 13 05:24:02 PM PDT 24
Peak memory 200932 kb
Host smart-a99f2a68-c8cf-4f54-93ac-a2d8fbf0fa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515070739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3515070739
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.2841248130
Short name T373
Test name
Test status
Simulation time 42663445 ps
CPU time 0.55 seconds
Started Aug 13 05:14:43 PM PDT 24
Finished Aug 13 05:14:44 PM PDT 24
Peak memory 195896 kb
Host smart-43791c17-1db7-496c-a840-f99317892d69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841248130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2841248130
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3814148953
Short name T1137
Test name
Test status
Simulation time 103652399860 ps
CPU time 40.68 seconds
Started Aug 13 05:14:45 PM PDT 24
Finished Aug 13 05:15:26 PM PDT 24
Peak memory 200668 kb
Host smart-bab1b803-1415-4e6a-8fb2-ff7f7286c48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814148953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3814148953
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.1862771908
Short name T134
Test name
Test status
Simulation time 36188611584 ps
CPU time 54.98 seconds
Started Aug 13 05:14:43 PM PDT 24
Finished Aug 13 05:15:39 PM PDT 24
Peak memory 200840 kb
Host smart-0932d6ca-2925-4227-b699-eb34e59852f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862771908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1862771908
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.471734557
Short name T587
Test name
Test status
Simulation time 89515313620 ps
CPU time 118.19 seconds
Started Aug 13 05:14:45 PM PDT 24
Finished Aug 13 05:16:43 PM PDT 24
Peak memory 200816 kb
Host smart-312ce3a0-6671-40e8-ba6e-a5b6486629fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471734557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.471734557
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.1157776439
Short name T534
Test name
Test status
Simulation time 194830948504 ps
CPU time 64.1 seconds
Started Aug 13 05:14:44 PM PDT 24
Finished Aug 13 05:15:48 PM PDT 24
Peak memory 197908 kb
Host smart-faf36d97-abab-4553-a61b-c8818b7ba3d1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157776439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1157776439
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1548738038
Short name T621
Test name
Test status
Simulation time 137286728567 ps
CPU time 1279.11 seconds
Started Aug 13 05:14:48 PM PDT 24
Finished Aug 13 05:36:07 PM PDT 24
Peak memory 200820 kb
Host smart-3e3abbef-b850-4254-9af1-67baf5eec35e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1548738038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1548738038
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.1715227678
Short name T559
Test name
Test status
Simulation time 1185208548 ps
CPU time 3.23 seconds
Started Aug 13 05:14:47 PM PDT 24
Finished Aug 13 05:14:50 PM PDT 24
Peak memory 199696 kb
Host smart-6c354c06-53c3-493a-bde8-8bfc239985f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715227678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1715227678
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.4109248491
Short name T596
Test name
Test status
Simulation time 29631143930 ps
CPU time 55.94 seconds
Started Aug 13 05:14:45 PM PDT 24
Finished Aug 13 05:15:41 PM PDT 24
Peak memory 201144 kb
Host smart-3382c1c4-d690-496b-914e-fea4bca2f5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109248491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.4109248491
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2704541674
Short name T335
Test name
Test status
Simulation time 16373003719 ps
CPU time 208.42 seconds
Started Aug 13 05:14:44 PM PDT 24
Finished Aug 13 05:18:12 PM PDT 24
Peak memory 200840 kb
Host smart-cfadd3f0-9018-4422-91ca-c8d422bc55d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2704541674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2704541674
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3698891791
Short name T40
Test name
Test status
Simulation time 2031584544 ps
CPU time 2.83 seconds
Started Aug 13 05:14:44 PM PDT 24
Finished Aug 13 05:14:47 PM PDT 24
Peak memory 198900 kb
Host smart-242e1ab5-a1c1-455d-9793-416b65d755ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3698891791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3698891791
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.4165253577
Short name T803
Test name
Test status
Simulation time 31059395430 ps
CPU time 30.98 seconds
Started Aug 13 05:14:46 PM PDT 24
Finished Aug 13 05:15:17 PM PDT 24
Peak memory 200724 kb
Host smart-7f1e83de-63a7-48df-a48a-0b9b92fbc4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165253577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.4165253577
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.377712244
Short name T769
Test name
Test status
Simulation time 3537080467 ps
CPU time 5.9 seconds
Started Aug 13 05:14:44 PM PDT 24
Finished Aug 13 05:14:50 PM PDT 24
Peak memory 197364 kb
Host smart-07609f87-a286-4053-a92f-d68e89d2fff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377712244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.377712244
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1325583984
Short name T974
Test name
Test status
Simulation time 849921947 ps
CPU time 3.46 seconds
Started Aug 13 05:14:44 PM PDT 24
Finished Aug 13 05:14:47 PM PDT 24
Peak memory 199800 kb
Host smart-f05bb76f-06dd-4172-96ad-7c2c5b4cc013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325583984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1325583984
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.871541733
Short name T695
Test name
Test status
Simulation time 53729867175 ps
CPU time 32.71 seconds
Started Aug 13 05:14:43 PM PDT 24
Finished Aug 13 05:15:16 PM PDT 24
Peak memory 200940 kb
Host smart-a6904f8f-6f89-47e6-bd6c-37ef75fef2dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871541733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.871541733
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2463902350
Short name T1099
Test name
Test status
Simulation time 13808064682 ps
CPU time 44.72 seconds
Started Aug 13 05:14:43 PM PDT 24
Finished Aug 13 05:15:28 PM PDT 24
Peak memory 217428 kb
Host smart-cc898bde-2b61-43f6-b65b-7b3972be2b44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463902350 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2463902350
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1685620647
Short name T740
Test name
Test status
Simulation time 7837563749 ps
CPU time 8.35 seconds
Started Aug 13 05:14:44 PM PDT 24
Finished Aug 13 05:14:52 PM PDT 24
Peak memory 200668 kb
Host smart-522382d6-27bb-4537-bfc4-f47d57821139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685620647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1685620647
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.1113106776
Short name T919
Test name
Test status
Simulation time 74935389907 ps
CPU time 115.4 seconds
Started Aug 13 05:14:45 PM PDT 24
Finished Aug 13 05:16:40 PM PDT 24
Peak memory 200844 kb
Host smart-ed70c927-5295-4f8c-83d6-2f86f5126694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113106776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1113106776
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.909532189
Short name T541
Test name
Test status
Simulation time 70568596794 ps
CPU time 29.6 seconds
Started Aug 13 05:17:11 PM PDT 24
Finished Aug 13 05:17:40 PM PDT 24
Peak memory 200896 kb
Host smart-32a29307-a003-4f5a-aa0a-bc4613348379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909532189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.909532189
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.431145762
Short name T174
Test name
Test status
Simulation time 134425093057 ps
CPU time 227.26 seconds
Started Aug 13 05:17:14 PM PDT 24
Finished Aug 13 05:21:01 PM PDT 24
Peak memory 200796 kb
Host smart-da46ab2d-998c-4b02-9bed-3da0e23a3a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431145762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.431145762
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2921701435
Short name T728
Test name
Test status
Simulation time 51992913744 ps
CPU time 27.95 seconds
Started Aug 13 05:17:08 PM PDT 24
Finished Aug 13 05:17:36 PM PDT 24
Peak memory 200952 kb
Host smart-c1087716-c8f7-41d5-be7e-8f13714c5097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921701435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2921701435
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.165325983
Short name T1103
Test name
Test status
Simulation time 79609134116 ps
CPU time 24.05 seconds
Started Aug 13 05:17:08 PM PDT 24
Finished Aug 13 05:17:32 PM PDT 24
Peak memory 200644 kb
Host smart-72ddb110-b25d-4a1d-a505-9a409700b51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165325983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.165325983
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2983066332
Short name T285
Test name
Test status
Simulation time 56797995783 ps
CPU time 29.41 seconds
Started Aug 13 05:17:10 PM PDT 24
Finished Aug 13 05:17:40 PM PDT 24
Peak memory 200716 kb
Host smart-5d5f59c0-5ee7-4d44-8992-0bc6824d2c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983066332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2983066332
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.1840430752
Short name T138
Test name
Test status
Simulation time 73039728625 ps
CPU time 35.27 seconds
Started Aug 13 05:17:09 PM PDT 24
Finished Aug 13 05:17:44 PM PDT 24
Peak memory 200844 kb
Host smart-a834565c-6db1-43d1-92b3-3a5303f31b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840430752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.1840430752
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1243962848
Short name T176
Test name
Test status
Simulation time 67136284425 ps
CPU time 59.67 seconds
Started Aug 13 05:17:12 PM PDT 24
Finished Aug 13 05:18:11 PM PDT 24
Peak memory 200932 kb
Host smart-88c05c20-3d35-40ee-be5b-c839e2ba6290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243962848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1243962848
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.432419797
Short name T895
Test name
Test status
Simulation time 118321332383 ps
CPU time 51.58 seconds
Started Aug 13 05:17:12 PM PDT 24
Finished Aug 13 05:18:04 PM PDT 24
Peak memory 200876 kb
Host smart-a7dcf779-05f6-45fb-949b-2d466e6605d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432419797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.432419797
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.948545036
Short name T990
Test name
Test status
Simulation time 371590448196 ps
CPU time 34.2 seconds
Started Aug 13 05:17:13 PM PDT 24
Finished Aug 13 05:17:47 PM PDT 24
Peak memory 200912 kb
Host smart-13464883-cd0e-4d80-a632-d7ccb269e970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948545036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.948545036
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.55080901
Short name T524
Test name
Test status
Simulation time 22157290 ps
CPU time 0.53 seconds
Started Aug 13 05:14:50 PM PDT 24
Finished Aug 13 05:14:50 PM PDT 24
Peak memory 196432 kb
Host smart-9bdca0cf-935a-47bd-9876-697fe794d9cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55080901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.55080901
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.369921562
Short name T660
Test name
Test status
Simulation time 115473430276 ps
CPU time 54.79 seconds
Started Aug 13 05:14:54 PM PDT 24
Finished Aug 13 05:15:49 PM PDT 24
Peak memory 200880 kb
Host smart-b782d84e-4578-4ccf-b045-91c11f70c0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369921562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.369921562
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2652537192
Short name T946
Test name
Test status
Simulation time 189741367928 ps
CPU time 192.35 seconds
Started Aug 13 05:14:52 PM PDT 24
Finished Aug 13 05:18:04 PM PDT 24
Peak memory 200992 kb
Host smart-75912e3f-0628-408b-ab31-961d65aad01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652537192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2652537192
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2743318656
Short name T810
Test name
Test status
Simulation time 6890613010 ps
CPU time 12.98 seconds
Started Aug 13 05:14:54 PM PDT 24
Finished Aug 13 05:15:07 PM PDT 24
Peak memory 200912 kb
Host smart-61f12c80-89cd-4c0e-98cc-abf2607710fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743318656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2743318656
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.3443423181
Short name T104
Test name
Test status
Simulation time 100860476957 ps
CPU time 79.19 seconds
Started Aug 13 05:14:52 PM PDT 24
Finished Aug 13 05:16:12 PM PDT 24
Peak memory 197108 kb
Host smart-cd842baf-e3d2-4d02-846d-a36235497edb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443423181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3443423181
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.3077205502
Short name T1011
Test name
Test status
Simulation time 220722417591 ps
CPU time 925.61 seconds
Started Aug 13 05:14:52 PM PDT 24
Finished Aug 13 05:30:18 PM PDT 24
Peak memory 200840 kb
Host smart-42112bc6-f5a8-4dc4-9bd1-4a11259c6ad2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3077205502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3077205502
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.1626731455
Short name T520
Test name
Test status
Simulation time 7198827056 ps
CPU time 4.62 seconds
Started Aug 13 05:14:51 PM PDT 24
Finished Aug 13 05:14:56 PM PDT 24
Peak memory 199448 kb
Host smart-1c750946-3863-4fe9-a238-b49a75e4178a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626731455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1626731455
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3029162061
Short name T924
Test name
Test status
Simulation time 53329994397 ps
CPU time 21.15 seconds
Started Aug 13 05:14:52 PM PDT 24
Finished Aug 13 05:15:13 PM PDT 24
Peak memory 201060 kb
Host smart-7c6c07ec-513d-458d-b49e-1f626a9b00d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029162061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3029162061
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3147971401
Short name T11
Test name
Test status
Simulation time 13498568747 ps
CPU time 61.05 seconds
Started Aug 13 05:14:53 PM PDT 24
Finished Aug 13 05:15:54 PM PDT 24
Peak memory 200776 kb
Host smart-eedd5953-93d3-40a1-a8de-ade77be60d83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3147971401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3147971401
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.4049356726
Short name T391
Test name
Test status
Simulation time 5138856678 ps
CPU time 11.4 seconds
Started Aug 13 05:14:54 PM PDT 24
Finished Aug 13 05:15:06 PM PDT 24
Peak memory 198912 kb
Host smart-f76ce985-a763-4cc3-aa5a-8167faac8571
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4049356726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.4049356726
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1029212426
Short name T1083
Test name
Test status
Simulation time 63063919592 ps
CPU time 82.91 seconds
Started Aug 13 05:14:54 PM PDT 24
Finished Aug 13 05:16:17 PM PDT 24
Peak memory 200900 kb
Host smart-448dd272-b8e4-4c3f-a936-538a98117ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029212426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1029212426
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.1567567838
Short name T959
Test name
Test status
Simulation time 5476609331 ps
CPU time 8.64 seconds
Started Aug 13 05:14:55 PM PDT 24
Finished Aug 13 05:15:03 PM PDT 24
Peak memory 197188 kb
Host smart-47df72d0-e2e5-4efb-a6a0-bec9ceb626f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567567838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1567567838
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.2899513301
Short name T1041
Test name
Test status
Simulation time 106680645 ps
CPU time 0.91 seconds
Started Aug 13 05:14:51 PM PDT 24
Finished Aug 13 05:14:52 PM PDT 24
Peak memory 197984 kb
Host smart-64037057-7b92-4e5d-ad8c-d317a3d361d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899513301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2899513301
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.1605899896
Short name T887
Test name
Test status
Simulation time 5169822443 ps
CPU time 34.77 seconds
Started Aug 13 05:14:54 PM PDT 24
Finished Aug 13 05:15:29 PM PDT 24
Peak memory 217316 kb
Host smart-a2e2b8a4-0763-450f-b03e-2b6b5b654973
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605899896 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1605899896
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.3987736381
Short name T832
Test name
Test status
Simulation time 933388382 ps
CPU time 5.33 seconds
Started Aug 13 05:14:52 PM PDT 24
Finished Aug 13 05:14:57 PM PDT 24
Peak memory 200608 kb
Host smart-18f45cea-d857-438e-94d3-b3a567f52444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987736381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3987736381
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.1236570458
Short name T654
Test name
Test status
Simulation time 43373484952 ps
CPU time 94.88 seconds
Started Aug 13 05:14:53 PM PDT 24
Finished Aug 13 05:16:28 PM PDT 24
Peak memory 200828 kb
Host smart-0109e78d-3a5d-4b8d-b767-035d87c9ae18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236570458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.1236570458
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2234616954
Short name T862
Test name
Test status
Simulation time 10572375223 ps
CPU time 20.81 seconds
Started Aug 13 05:17:08 PM PDT 24
Finished Aug 13 05:17:28 PM PDT 24
Peak memory 201024 kb
Host smart-548cbc82-374e-49dd-9bdc-45a79d05fe4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234616954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2234616954
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.667524159
Short name T841
Test name
Test status
Simulation time 95490144000 ps
CPU time 192.83 seconds
Started Aug 13 05:17:09 PM PDT 24
Finished Aug 13 05:20:22 PM PDT 24
Peak memory 200856 kb
Host smart-4cf14b54-0a95-40bf-8092-03c992c35c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667524159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.667524159
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.3722475055
Short name T850
Test name
Test status
Simulation time 107730447439 ps
CPU time 374.35 seconds
Started Aug 13 05:17:12 PM PDT 24
Finished Aug 13 05:23:27 PM PDT 24
Peak memory 200864 kb
Host smart-07e2f1e5-2029-4940-b8f9-b1e433964458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722475055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3722475055
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.3951346098
Short name T187
Test name
Test status
Simulation time 52701592076 ps
CPU time 90.09 seconds
Started Aug 13 05:17:09 PM PDT 24
Finished Aug 13 05:18:39 PM PDT 24
Peak memory 200924 kb
Host smart-42b3a257-b0e0-4e63-b277-8f9542e09080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951346098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3951346098
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.2861740121
Short name T36
Test name
Test status
Simulation time 9274128535 ps
CPU time 12.6 seconds
Started Aug 13 05:17:12 PM PDT 24
Finished Aug 13 05:17:25 PM PDT 24
Peak memory 200936 kb
Host smart-5899afdc-5066-427d-91c6-20233f47a87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861740121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2861740121
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.1640236627
Short name T1132
Test name
Test status
Simulation time 87764916040 ps
CPU time 37.66 seconds
Started Aug 13 05:17:13 PM PDT 24
Finished Aug 13 05:17:51 PM PDT 24
Peak memory 200912 kb
Host smart-8cd70ea1-be2c-414f-ae53-9b092301a714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640236627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1640236627
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.533978820
Short name T200
Test name
Test status
Simulation time 23258455204 ps
CPU time 20.46 seconds
Started Aug 13 05:17:10 PM PDT 24
Finished Aug 13 05:17:31 PM PDT 24
Peak memory 200796 kb
Host smart-d7b43079-561f-4996-9166-bad58832aacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533978820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.533978820
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.622207154
Short name T976
Test name
Test status
Simulation time 111301145105 ps
CPU time 83.92 seconds
Started Aug 13 05:17:08 PM PDT 24
Finished Aug 13 05:18:32 PM PDT 24
Peak memory 200860 kb
Host smart-9bee51df-a36c-4b01-b0c6-c13abaa898ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622207154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.622207154
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3361670284
Short name T699
Test name
Test status
Simulation time 13310169164 ps
CPU time 28.76 seconds
Started Aug 13 05:17:12 PM PDT 24
Finished Aug 13 05:17:40 PM PDT 24
Peak memory 200876 kb
Host smart-41a40432-a90b-4085-acee-d7db7197a4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361670284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3361670284
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.3771433573
Short name T1131
Test name
Test status
Simulation time 11855468040 ps
CPU time 9.64 seconds
Started Aug 13 05:17:16 PM PDT 24
Finished Aug 13 05:17:26 PM PDT 24
Peak memory 200848 kb
Host smart-9e3ee354-e249-4dd9-918b-b44f06fe54e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771433573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3771433573
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.3594098096
Short name T869
Test name
Test status
Simulation time 42678274 ps
CPU time 0.58 seconds
Started Aug 13 05:14:53 PM PDT 24
Finished Aug 13 05:14:53 PM PDT 24
Peak memory 196452 kb
Host smart-d133abde-345b-4430-81ca-40c01af9dce0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594098096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3594098096
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1079520691
Short name T713
Test name
Test status
Simulation time 219542302660 ps
CPU time 26.66 seconds
Started Aug 13 05:14:51 PM PDT 24
Finished Aug 13 05:15:18 PM PDT 24
Peak memory 200796 kb
Host smart-dcd530c7-a20b-4b53-ab39-1e744c8d0806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079520691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1079520691
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.2332861918
Short name T564
Test name
Test status
Simulation time 97323028344 ps
CPU time 43.53 seconds
Started Aug 13 05:14:54 PM PDT 24
Finished Aug 13 05:15:37 PM PDT 24
Peak memory 200932 kb
Host smart-e923b14c-4f6d-49e1-ba79-86705a357930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332861918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2332861918
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3901549942
Short name T37
Test name
Test status
Simulation time 193650099770 ps
CPU time 326.44 seconds
Started Aug 13 05:14:54 PM PDT 24
Finished Aug 13 05:20:20 PM PDT 24
Peak memory 200908 kb
Host smart-d1cbffe4-6163-43c1-85f4-3e9e3764163b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901549942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3901549942
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.441093276
Short name T825
Test name
Test status
Simulation time 18301939460 ps
CPU time 7.43 seconds
Started Aug 13 05:14:51 PM PDT 24
Finished Aug 13 05:14:59 PM PDT 24
Peak memory 200464 kb
Host smart-924afa1b-cfce-4cf7-b281-1302c3de7727
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441093276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.441093276
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.3259758659
Short name T583
Test name
Test status
Simulation time 112004482539 ps
CPU time 1154.58 seconds
Started Aug 13 05:14:53 PM PDT 24
Finished Aug 13 05:34:08 PM PDT 24
Peak memory 200884 kb
Host smart-5b643963-a117-4b4c-a41d-a503c1a8de90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3259758659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3259758659
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.1633257146
Short name T473
Test name
Test status
Simulation time 7571972554 ps
CPU time 4.66 seconds
Started Aug 13 05:14:54 PM PDT 24
Finished Aug 13 05:14:59 PM PDT 24
Peak memory 198580 kb
Host smart-dbaeaf7a-eade-4c98-832d-2be89defeba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633257146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1633257146
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1314830220
Short name T688
Test name
Test status
Simulation time 99235802255 ps
CPU time 51.51 seconds
Started Aug 13 05:14:54 PM PDT 24
Finished Aug 13 05:15:46 PM PDT 24
Peak memory 201096 kb
Host smart-43081a0a-cba6-42c0-8092-413589de1ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314830220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1314830220
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.3585307939
Short name T532
Test name
Test status
Simulation time 19589579493 ps
CPU time 959.33 seconds
Started Aug 13 05:14:56 PM PDT 24
Finished Aug 13 05:30:56 PM PDT 24
Peak memory 200936 kb
Host smart-08f96cbc-0524-4891-a429-d3d10ab587b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3585307939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3585307939
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.410118526
Short name T379
Test name
Test status
Simulation time 6011293184 ps
CPU time 28.51 seconds
Started Aug 13 05:14:52 PM PDT 24
Finished Aug 13 05:15:21 PM PDT 24
Peak memory 200036 kb
Host smart-34ce0eba-6f0f-491e-9357-885c48bdc508
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=410118526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.410118526
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.1658428146
Short name T270
Test name
Test status
Simulation time 77435973142 ps
CPU time 20.1 seconds
Started Aug 13 05:14:53 PM PDT 24
Finished Aug 13 05:15:13 PM PDT 24
Peak memory 200780 kb
Host smart-3f9bafb3-b8e0-4f60-a55b-e896f9f2ed34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658428146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1658428146
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.2219279125
Short name T403
Test name
Test status
Simulation time 41502766977 ps
CPU time 15.23 seconds
Started Aug 13 05:14:56 PM PDT 24
Finished Aug 13 05:15:12 PM PDT 24
Peak memory 196956 kb
Host smart-f2134f4a-f635-4037-be6f-c0ecdb0dc6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219279125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2219279125
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.4188362693
Short name T289
Test name
Test status
Simulation time 849549887 ps
CPU time 2.07 seconds
Started Aug 13 05:14:53 PM PDT 24
Finished Aug 13 05:14:55 PM PDT 24
Peak memory 200556 kb
Host smart-870c1d80-e638-4a32-9995-32906674f838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188362693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.4188362693
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.2859004046
Short name T306
Test name
Test status
Simulation time 73474697769 ps
CPU time 184.55 seconds
Started Aug 13 05:14:54 PM PDT 24
Finished Aug 13 05:17:59 PM PDT 24
Peak memory 200900 kb
Host smart-ea302830-c141-4f37-b45a-ec962e9af264
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859004046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2859004046
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3688600237
Short name T656
Test name
Test status
Simulation time 11604172905 ps
CPU time 24.39 seconds
Started Aug 13 05:14:51 PM PDT 24
Finished Aug 13 05:15:16 PM PDT 24
Peak memory 209372 kb
Host smart-1690263f-6d78-4dc4-bda0-10ca3492cee9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688600237 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3688600237
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3899204061
Short name T1171
Test name
Test status
Simulation time 1194486031 ps
CPU time 5.04 seconds
Started Aug 13 05:14:55 PM PDT 24
Finished Aug 13 05:15:00 PM PDT 24
Peak memory 200548 kb
Host smart-20e3194e-804e-44bf-a641-432fbbe07ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899204061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3899204061
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1854782968
Short name T866
Test name
Test status
Simulation time 82473263853 ps
CPU time 36.6 seconds
Started Aug 13 05:14:49 PM PDT 24
Finished Aug 13 05:15:26 PM PDT 24
Peak memory 200936 kb
Host smart-3838f1b9-eadc-41a3-b1f0-58e01182481d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854782968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1854782968
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1628543276
Short name T244
Test name
Test status
Simulation time 55503476903 ps
CPU time 17.99 seconds
Started Aug 13 05:17:16 PM PDT 24
Finished Aug 13 05:17:34 PM PDT 24
Peak memory 200908 kb
Host smart-14958391-eb01-479d-85cc-b7f4bc90d7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628543276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1628543276
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3603259335
Short name T110
Test name
Test status
Simulation time 32972525033 ps
CPU time 39.17 seconds
Started Aug 13 05:17:20 PM PDT 24
Finished Aug 13 05:18:00 PM PDT 24
Peak memory 200880 kb
Host smart-6780e82a-b5af-47e9-a6a0-25391b288334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603259335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3603259335
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1064643252
Short name T645
Test name
Test status
Simulation time 46921378333 ps
CPU time 15.76 seconds
Started Aug 13 05:17:16 PM PDT 24
Finished Aug 13 05:17:32 PM PDT 24
Peak memory 200884 kb
Host smart-4b8dbd70-8729-416a-90a5-9594e8e6cf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064643252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1064643252
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.424877587
Short name T83
Test name
Test status
Simulation time 33530067239 ps
CPU time 18 seconds
Started Aug 13 05:17:15 PM PDT 24
Finished Aug 13 05:17:33 PM PDT 24
Peak memory 200932 kb
Host smart-110ec928-0322-44e9-b3a5-37146293c636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424877587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.424877587
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.22420585
Short name T1082
Test name
Test status
Simulation time 10917845435 ps
CPU time 18.26 seconds
Started Aug 13 05:17:16 PM PDT 24
Finished Aug 13 05:17:34 PM PDT 24
Peak memory 200704 kb
Host smart-72594c23-4f66-44a9-87b0-66d57a5b82e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22420585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.22420585
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2930422388
Short name T148
Test name
Test status
Simulation time 7788465226 ps
CPU time 15.34 seconds
Started Aug 13 05:17:15 PM PDT 24
Finished Aug 13 05:17:31 PM PDT 24
Peak memory 200776 kb
Host smart-7d0db51f-4612-4f62-8432-b08bbc94ab18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930422388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2930422388
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1365605057
Short name T768
Test name
Test status
Simulation time 97277089948 ps
CPU time 41.88 seconds
Started Aug 13 05:17:16 PM PDT 24
Finished Aug 13 05:17:58 PM PDT 24
Peak memory 200920 kb
Host smart-0a30a915-c285-486d-9cc6-f90ef353ba4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365605057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1365605057
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.3396588956
Short name T1024
Test name
Test status
Simulation time 165545688223 ps
CPU time 137.88 seconds
Started Aug 13 05:17:21 PM PDT 24
Finished Aug 13 05:19:39 PM PDT 24
Peak memory 200932 kb
Host smart-373a919c-5d5b-44ac-b1ba-23a9bbf11fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396588956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.3396588956
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.264628204
Short name T719
Test name
Test status
Simulation time 121565100181 ps
CPU time 182.75 seconds
Started Aug 13 05:17:15 PM PDT 24
Finished Aug 13 05:20:18 PM PDT 24
Peak memory 200880 kb
Host smart-2abc37e6-8a30-40b1-97ae-c7ec888dfb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264628204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.264628204
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3693671320
Short name T880
Test name
Test status
Simulation time 13135057 ps
CPU time 0.56 seconds
Started Aug 13 05:14:58 PM PDT 24
Finished Aug 13 05:14:59 PM PDT 24
Peak memory 196504 kb
Host smart-9e04de8a-c159-4636-b8ae-b4c968ec31f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693671320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3693671320
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.2866046079
Short name T617
Test name
Test status
Simulation time 448596093593 ps
CPU time 191.27 seconds
Started Aug 13 05:14:53 PM PDT 24
Finished Aug 13 05:18:04 PM PDT 24
Peak memory 200856 kb
Host smart-76cc98a1-0a55-432d-835a-96caea9fc3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866046079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2866046079
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.326781857
Short name T826
Test name
Test status
Simulation time 13695144944 ps
CPU time 14.13 seconds
Started Aug 13 05:14:52 PM PDT 24
Finished Aug 13 05:15:07 PM PDT 24
Peak memory 200928 kb
Host smart-75e41539-41bd-499c-a0fd-6757a7266dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326781857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.326781857
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.2261886973
Short name T1021
Test name
Test status
Simulation time 60611253560 ps
CPU time 91.4 seconds
Started Aug 13 05:14:52 PM PDT 24
Finished Aug 13 05:16:23 PM PDT 24
Peak memory 200876 kb
Host smart-d1b2b62f-1126-4565-a5e8-fce43a874edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261886973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2261886973
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.2136105570
Short name T103
Test name
Test status
Simulation time 42590421805 ps
CPU time 25.02 seconds
Started Aug 13 05:14:53 PM PDT 24
Finished Aug 13 05:15:18 PM PDT 24
Peak memory 200892 kb
Host smart-ddc92cd9-5d8c-47c2-98d3-f70c74626233
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136105570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2136105570
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1179803937
Short name T856
Test name
Test status
Simulation time 147757845758 ps
CPU time 290.33 seconds
Started Aug 13 05:14:59 PM PDT 24
Finished Aug 13 05:19:50 PM PDT 24
Peak memory 200876 kb
Host smart-463417c3-0d8b-4e89-9001-203349155e32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1179803937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1179803937
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1360796286
Short name T412
Test name
Test status
Simulation time 1218555404 ps
CPU time 7.56 seconds
Started Aug 13 05:14:55 PM PDT 24
Finished Aug 13 05:15:03 PM PDT 24
Peak memory 200784 kb
Host smart-99360161-be3e-453e-ad5b-da11bf5a4854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360796286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1360796286
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.275785561
Short name T723
Test name
Test status
Simulation time 146717455568 ps
CPU time 63.28 seconds
Started Aug 13 05:14:52 PM PDT 24
Finished Aug 13 05:15:56 PM PDT 24
Peak memory 199956 kb
Host smart-5e25d123-1a6d-4c00-8d59-b8aa0e9e31ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275785561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.275785561
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.1685414166
Short name T664
Test name
Test status
Simulation time 13353754659 ps
CPU time 100.1 seconds
Started Aug 13 05:14:55 PM PDT 24
Finished Aug 13 05:16:35 PM PDT 24
Peak memory 200884 kb
Host smart-45b87eb3-0d00-404b-954e-b903fb7644ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1685414166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1685414166
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.482444303
Short name T860
Test name
Test status
Simulation time 5782492346 ps
CPU time 49.58 seconds
Started Aug 13 05:14:53 PM PDT 24
Finished Aug 13 05:15:43 PM PDT 24
Peak memory 199688 kb
Host smart-44163261-c8b1-4903-a332-ed08431bc8c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=482444303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.482444303
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2770737768
Short name T729
Test name
Test status
Simulation time 16565274258 ps
CPU time 14.46 seconds
Started Aug 13 05:14:53 PM PDT 24
Finished Aug 13 05:15:07 PM PDT 24
Peak memory 200672 kb
Host smart-5969cf0e-6c58-419c-86b8-ca4bce1499ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770737768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2770737768
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.2168627420
Short name T913
Test name
Test status
Simulation time 32660475986 ps
CPU time 49.91 seconds
Started Aug 13 05:14:52 PM PDT 24
Finished Aug 13 05:15:42 PM PDT 24
Peak memory 196760 kb
Host smart-ab4ab842-d6c2-4186-ad69-5981c375c68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168627420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2168627420
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.2513168929
Short name T689
Test name
Test status
Simulation time 930867199 ps
CPU time 2.87 seconds
Started Aug 13 05:14:52 PM PDT 24
Finished Aug 13 05:14:55 PM PDT 24
Peak memory 199196 kb
Host smart-9a82f896-0728-4816-809c-80aa5f02f0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513168929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2513168929
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1953017811
Short name T1020
Test name
Test status
Simulation time 711922457046 ps
CPU time 328.99 seconds
Started Aug 13 05:15:02 PM PDT 24
Finished Aug 13 05:20:31 PM PDT 24
Peak memory 200872 kb
Host smart-2e720cb9-4d33-4e78-b3ff-03715638f8ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953017811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1953017811
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3851754355
Short name T1035
Test name
Test status
Simulation time 3228515970 ps
CPU time 45.77 seconds
Started Aug 13 05:14:59 PM PDT 24
Finished Aug 13 05:15:44 PM PDT 24
Peak memory 216336 kb
Host smart-30a5e5e4-ab4a-4b56-823e-ac1e26c0f928
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851754355 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3851754355
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2204066895
Short name T469
Test name
Test status
Simulation time 7642909900 ps
CPU time 21.67 seconds
Started Aug 13 05:14:53 PM PDT 24
Finished Aug 13 05:15:14 PM PDT 24
Peak memory 200792 kb
Host smart-763ced56-7157-4e06-9439-00246f0e076f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204066895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2204066895
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.1598222656
Short name T525
Test name
Test status
Simulation time 26445027892 ps
CPU time 37.58 seconds
Started Aug 13 05:14:54 PM PDT 24
Finished Aug 13 05:15:32 PM PDT 24
Peak memory 200932 kb
Host smart-4cc7e24c-b4ba-47f0-b490-9367e2c56a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598222656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1598222656
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3058389528
Short name T139
Test name
Test status
Simulation time 29378779400 ps
CPU time 51.89 seconds
Started Aug 13 05:17:15 PM PDT 24
Finished Aug 13 05:18:07 PM PDT 24
Peak memory 200840 kb
Host smart-76b81d84-fdc1-44d8-8e1f-f9b30e204c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058389528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3058389528
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.1159733837
Short name T998
Test name
Test status
Simulation time 111079704947 ps
CPU time 192.96 seconds
Started Aug 13 05:17:16 PM PDT 24
Finished Aug 13 05:20:29 PM PDT 24
Peak memory 200836 kb
Host smart-ebf34ffb-aac3-48c1-9965-4d948094f086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159733837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1159733837
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.450212
Short name T460
Test name
Test status
Simulation time 59421309226 ps
CPU time 41.99 seconds
Started Aug 13 05:17:15 PM PDT 24
Finished Aug 13 05:17:57 PM PDT 24
Peak memory 200876 kb
Host smart-1ae09ebe-9bcd-410e-a71d-7ef3832f0dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.450212
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.512697793
Short name T1080
Test name
Test status
Simulation time 35262679516 ps
CPU time 11.97 seconds
Started Aug 13 05:17:15 PM PDT 24
Finished Aug 13 05:17:27 PM PDT 24
Peak memory 200936 kb
Host smart-15d8eadf-c7a4-4505-851d-6b6481d1c0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512697793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.512697793
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1710632714
Short name T39
Test name
Test status
Simulation time 157537220979 ps
CPU time 55.91 seconds
Started Aug 13 05:17:16 PM PDT 24
Finished Aug 13 05:18:12 PM PDT 24
Peak memory 200844 kb
Host smart-cc0ed1d9-f08e-4388-ad4f-80ab513c06d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710632714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1710632714
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3880086253
Short name T1141
Test name
Test status
Simulation time 57358858493 ps
CPU time 22.87 seconds
Started Aug 13 05:17:17 PM PDT 24
Finished Aug 13 05:17:40 PM PDT 24
Peak memory 200888 kb
Host smart-722bf6e8-1771-4ecc-91d9-e94b7570d799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880086253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3880086253
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.4136873073
Short name T1165
Test name
Test status
Simulation time 83141283655 ps
CPU time 115.69 seconds
Started Aug 13 05:17:22 PM PDT 24
Finished Aug 13 05:19:17 PM PDT 24
Peak memory 200932 kb
Host smart-d53feabb-dd80-4847-b943-cce382058be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136873073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.4136873073
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.3443018758
Short name T201
Test name
Test status
Simulation time 30917095053 ps
CPU time 52.08 seconds
Started Aug 13 05:17:15 PM PDT 24
Finished Aug 13 05:18:07 PM PDT 24
Peak memory 200832 kb
Host smart-3f2100ff-6847-4e1f-85e0-836f728a4e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443018758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3443018758
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3533956845
Short name T1135
Test name
Test status
Simulation time 14388562 ps
CPU time 0.56 seconds
Started Aug 13 05:15:00 PM PDT 24
Finished Aug 13 05:15:00 PM PDT 24
Peak memory 196128 kb
Host smart-a9fec326-cf9f-4ca6-b697-1676f8f18b89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533956845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3533956845
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.2455613399
Short name T540
Test name
Test status
Simulation time 102473117442 ps
CPU time 36.62 seconds
Started Aug 13 05:14:58 PM PDT 24
Finished Aug 13 05:15:35 PM PDT 24
Peak memory 200924 kb
Host smart-a6edd280-9836-42ae-b25f-57f2e25579f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455613399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2455613399
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1302834186
Short name T580
Test name
Test status
Simulation time 67303038681 ps
CPU time 56.91 seconds
Started Aug 13 05:14:58 PM PDT 24
Finished Aug 13 05:15:55 PM PDT 24
Peak memory 200768 kb
Host smart-6c19051b-3590-474e-9568-afd56f6a2641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302834186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1302834186
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2737047382
Short name T224
Test name
Test status
Simulation time 37913741417 ps
CPU time 62.05 seconds
Started Aug 13 05:15:00 PM PDT 24
Finished Aug 13 05:16:03 PM PDT 24
Peak memory 200928 kb
Host smart-47975cd1-24e6-441d-9c46-96e6dba767cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737047382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2737047382
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.2013291754
Short name T859
Test name
Test status
Simulation time 206630527181 ps
CPU time 65.62 seconds
Started Aug 13 05:15:02 PM PDT 24
Finished Aug 13 05:16:08 PM PDT 24
Peak memory 200060 kb
Host smart-5f28016e-2cd7-4d07-ae49-057c054559f6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013291754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2013291754
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.402730744
Short name T510
Test name
Test status
Simulation time 125645953578 ps
CPU time 1188.98 seconds
Started Aug 13 05:15:01 PM PDT 24
Finished Aug 13 05:34:50 PM PDT 24
Peak memory 200868 kb
Host smart-ae399ade-eff1-4169-a418-66f818b95c43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=402730744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.402730744
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2712764070
Short name T1032
Test name
Test status
Simulation time 66184117 ps
CPU time 0.65 seconds
Started Aug 13 05:14:58 PM PDT 24
Finished Aug 13 05:14:59 PM PDT 24
Peak memory 196836 kb
Host smart-c33a0508-0df4-4ebf-87fb-921367117ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712764070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2712764070
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.2270335011
Short name T1033
Test name
Test status
Simulation time 33614127664 ps
CPU time 58.97 seconds
Started Aug 13 05:15:02 PM PDT 24
Finished Aug 13 05:16:01 PM PDT 24
Peak memory 209256 kb
Host smart-cf73f6dc-777f-43a7-adb7-5350a94025da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270335011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2270335011
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.2090322538
Short name T794
Test name
Test status
Simulation time 3853420623 ps
CPU time 113.31 seconds
Started Aug 13 05:14:59 PM PDT 24
Finished Aug 13 05:16:52 PM PDT 24
Peak memory 201076 kb
Host smart-d29d9d10-f14f-46fc-aa16-942249999b93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2090322538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2090322538
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.3575106431
Short name T389
Test name
Test status
Simulation time 5532427531 ps
CPU time 12 seconds
Started Aug 13 05:14:58 PM PDT 24
Finished Aug 13 05:15:10 PM PDT 24
Peak memory 198748 kb
Host smart-536255f8-f5c3-4802-95f0-03d889525849
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3575106431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3575106431
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3384501455
Short name T1026
Test name
Test status
Simulation time 67318112355 ps
CPU time 28.51 seconds
Started Aug 13 05:14:56 PM PDT 24
Finished Aug 13 05:15:25 PM PDT 24
Peak memory 200896 kb
Host smart-0075a743-940d-453c-9aec-d2c34799e792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384501455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3384501455
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2465109720
Short name T983
Test name
Test status
Simulation time 521610609 ps
CPU time 1.01 seconds
Started Aug 13 05:14:57 PM PDT 24
Finished Aug 13 05:14:58 PM PDT 24
Peak memory 196372 kb
Host smart-cc4f7d3a-5232-4a24-825d-673e12d8c292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465109720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2465109720
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.1415657034
Short name T828
Test name
Test status
Simulation time 945501428 ps
CPU time 2.65 seconds
Started Aug 13 05:15:02 PM PDT 24
Finished Aug 13 05:15:05 PM PDT 24
Peak memory 199468 kb
Host smart-3b183609-caa8-4d26-8366-0ec039926666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415657034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1415657034
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.3410386742
Short name T1003
Test name
Test status
Simulation time 456559853950 ps
CPU time 403.27 seconds
Started Aug 13 05:14:58 PM PDT 24
Finished Aug 13 05:21:41 PM PDT 24
Peak memory 209284 kb
Host smart-dae74960-feea-4a80-82a2-0d9b4dfb44eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410386742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3410386742
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.949336348
Short name T910
Test name
Test status
Simulation time 4037960012 ps
CPU time 21.28 seconds
Started Aug 13 05:14:58 PM PDT 24
Finished Aug 13 05:15:19 PM PDT 24
Peak memory 209368 kb
Host smart-c0e53665-6041-4430-9b13-ff681fcd0736
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949336348 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.949336348
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1422116252
Short name T407
Test name
Test status
Simulation time 976854012 ps
CPU time 3.21 seconds
Started Aug 13 05:15:00 PM PDT 24
Finished Aug 13 05:15:03 PM PDT 24
Peak memory 199228 kb
Host smart-b5bf15a9-d283-4be8-af1e-645475ffdc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422116252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1422116252
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.1152226334
Short name T106
Test name
Test status
Simulation time 22087959313 ps
CPU time 31.72 seconds
Started Aug 13 05:14:58 PM PDT 24
Finished Aug 13 05:15:29 PM PDT 24
Peak memory 200880 kb
Host smart-0e1b678c-ba8a-4269-b489-27098ce7bdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152226334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1152226334
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.1105155812
Short name T345
Test name
Test status
Simulation time 16612768067 ps
CPU time 15.77 seconds
Started Aug 13 05:17:16 PM PDT 24
Finished Aug 13 05:17:32 PM PDT 24
Peak memory 200828 kb
Host smart-16a63f0b-549c-40c5-9939-839af09e121e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105155812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1105155812
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3437774020
Short name T218
Test name
Test status
Simulation time 200218825567 ps
CPU time 43.15 seconds
Started Aug 13 05:17:20 PM PDT 24
Finished Aug 13 05:18:04 PM PDT 24
Peak memory 200880 kb
Host smart-b5f9f4da-13e3-4f91-a342-e5067f714f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437774020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3437774020
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2676979154
Short name T690
Test name
Test status
Simulation time 144987289464 ps
CPU time 134.15 seconds
Started Aug 13 05:17:20 PM PDT 24
Finished Aug 13 05:19:34 PM PDT 24
Peak memory 200932 kb
Host smart-76df8cc3-2df3-4a3c-879a-c41f9f5711e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676979154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2676979154
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.3939428632
Short name T651
Test name
Test status
Simulation time 22730785220 ps
CPU time 32.4 seconds
Started Aug 13 05:17:22 PM PDT 24
Finished Aug 13 05:17:55 PM PDT 24
Peak memory 199228 kb
Host smart-8a3b3629-8769-478d-a316-3eddac612257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939428632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3939428632
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.4149766986
Short name T203
Test name
Test status
Simulation time 171621362565 ps
CPU time 319.73 seconds
Started Aug 13 05:17:23 PM PDT 24
Finished Aug 13 05:22:43 PM PDT 24
Peak memory 201064 kb
Host smart-764eb8f3-9cb0-4dfc-8e0d-2b1a3502a1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149766986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.4149766986
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2045228423
Short name T615
Test name
Test status
Simulation time 18057573719 ps
CPU time 41.31 seconds
Started Aug 13 05:17:24 PM PDT 24
Finished Aug 13 05:18:05 PM PDT 24
Peak memory 199288 kb
Host smart-4faae9cc-f8c2-424c-86f0-974ffcb31454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045228423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2045228423
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.2999134676
Short name T731
Test name
Test status
Simulation time 40314794089 ps
CPU time 24.62 seconds
Started Aug 13 05:17:23 PM PDT 24
Finished Aug 13 05:17:47 PM PDT 24
Peak memory 200916 kb
Host smart-ddd8445f-f7e1-463f-91f2-c030c659041a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999134676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2999134676
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.384887724
Short name T490
Test name
Test status
Simulation time 82102891005 ps
CPU time 29.93 seconds
Started Aug 13 05:17:21 PM PDT 24
Finished Aug 13 05:17:51 PM PDT 24
Peak memory 200944 kb
Host smart-dece2891-f4a2-4a05-93be-45b77f15e5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384887724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.384887724
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1870527445
Short name T323
Test name
Test status
Simulation time 113521372508 ps
CPU time 82.05 seconds
Started Aug 13 05:17:23 PM PDT 24
Finished Aug 13 05:18:45 PM PDT 24
Peak memory 200936 kb
Host smart-0a9d13e3-8ee8-40b4-a95b-90944ebe622e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870527445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1870527445
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3662380655
Short name T227
Test name
Test status
Simulation time 24168992523 ps
CPU time 34.65 seconds
Started Aug 13 05:17:22 PM PDT 24
Finished Aug 13 05:17:57 PM PDT 24
Peak memory 200820 kb
Host smart-f9535eaf-c601-4a2c-a70a-b739ac5fffc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662380655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3662380655
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3851247416
Short name T811
Test name
Test status
Simulation time 19645474 ps
CPU time 0.53 seconds
Started Aug 13 05:15:06 PM PDT 24
Finished Aug 13 05:15:06 PM PDT 24
Peak memory 195216 kb
Host smart-fe745f79-f512-4c20-b71b-a9ae0adc58f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851247416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3851247416
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2786927382
Short name T491
Test name
Test status
Simulation time 36663043122 ps
CPU time 15.77 seconds
Started Aug 13 05:14:58 PM PDT 24
Finished Aug 13 05:15:14 PM PDT 24
Peak memory 200920 kb
Host smart-8156e3de-4856-4f5e-ac2c-b62c69cd3183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786927382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2786927382
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3272959077
Short name T1069
Test name
Test status
Simulation time 114368400166 ps
CPU time 52.07 seconds
Started Aug 13 05:14:57 PM PDT 24
Finished Aug 13 05:15:49 PM PDT 24
Peak memory 200880 kb
Host smart-fd83d501-7990-4eb1-909d-d9f44d419c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272959077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3272959077
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3247388479
Short name T181
Test name
Test status
Simulation time 124458753028 ps
CPU time 105.13 seconds
Started Aug 13 05:14:58 PM PDT 24
Finished Aug 13 05:16:43 PM PDT 24
Peak memory 201008 kb
Host smart-4dbfeef6-1ca5-458e-94dc-4c31a97c042c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247388479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3247388479
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2581507775
Short name T529
Test name
Test status
Simulation time 68944520049 ps
CPU time 32.08 seconds
Started Aug 13 05:15:03 PM PDT 24
Finished Aug 13 05:15:35 PM PDT 24
Peak memory 200820 kb
Host smart-a16cf34a-4313-4658-8013-1648c56fa082
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581507775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2581507775
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2457025838
Short name T569
Test name
Test status
Simulation time 259121418502 ps
CPU time 329.15 seconds
Started Aug 13 05:15:06 PM PDT 24
Finished Aug 13 05:20:35 PM PDT 24
Peak memory 200768 kb
Host smart-21fa1145-f4f8-4eb3-bbed-7561d3874789
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2457025838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2457025838
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.2258935619
Short name T889
Test name
Test status
Simulation time 76178149 ps
CPU time 0.61 seconds
Started Aug 13 05:15:04 PM PDT 24
Finished Aug 13 05:15:05 PM PDT 24
Peak memory 196756 kb
Host smart-33c3741a-9beb-40ef-a286-c7fcdafa90d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258935619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2258935619
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.4115250117
Short name T484
Test name
Test status
Simulation time 81153589482 ps
CPU time 140.95 seconds
Started Aug 13 05:15:00 PM PDT 24
Finished Aug 13 05:17:21 PM PDT 24
Peak memory 200956 kb
Host smart-964e062c-78ad-44bb-9317-85a15ada4047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115250117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.4115250117
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.1711518124
Short name T1084
Test name
Test status
Simulation time 7554731352 ps
CPU time 487.19 seconds
Started Aug 13 05:15:07 PM PDT 24
Finished Aug 13 05:23:14 PM PDT 24
Peak memory 200920 kb
Host smart-96ad52bb-63f5-4a95-9ccb-1d07edce895a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1711518124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1711518124
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.3697842774
Short name T756
Test name
Test status
Simulation time 5584812489 ps
CPU time 40.47 seconds
Started Aug 13 05:15:01 PM PDT 24
Finished Aug 13 05:15:41 PM PDT 24
Peak memory 200832 kb
Host smart-09bc03fc-ca48-4c42-a277-66c1514715a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3697842774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3697842774
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2788516707
Short name T297
Test name
Test status
Simulation time 34733667883 ps
CPU time 52.32 seconds
Started Aug 13 05:14:58 PM PDT 24
Finished Aug 13 05:15:50 PM PDT 24
Peak memory 197436 kb
Host smart-66590db9-df71-4edd-9495-574a5952dea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788516707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2788516707
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.84738875
Short name T616
Test name
Test status
Simulation time 10530784699 ps
CPU time 40.04 seconds
Started Aug 13 05:14:57 PM PDT 24
Finished Aug 13 05:15:38 PM PDT 24
Peak memory 200444 kb
Host smart-49996cae-b75e-441c-9099-bd4e7783e34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84738875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.84738875
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.3262401193
Short name T130
Test name
Test status
Simulation time 303365877114 ps
CPU time 129.06 seconds
Started Aug 13 05:15:05 PM PDT 24
Finished Aug 13 05:17:14 PM PDT 24
Peak memory 217316 kb
Host smart-63253720-8950-4ef2-8780-4546727cfc13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262401193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3262401193
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.2795682720
Short name T302
Test name
Test status
Simulation time 3278182335 ps
CPU time 17.79 seconds
Started Aug 13 05:15:06 PM PDT 24
Finished Aug 13 05:15:24 PM PDT 24
Peak memory 217140 kb
Host smart-77ca509b-5fb0-4819-b641-3aa2e577c41b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795682720 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.2795682720
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1708833875
Short name T658
Test name
Test status
Simulation time 759700207 ps
CPU time 1.8 seconds
Started Aug 13 05:15:05 PM PDT 24
Finished Aug 13 05:15:06 PM PDT 24
Peak memory 199672 kb
Host smart-00a14b8e-3f8b-4ff1-a664-fbd7b421eaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708833875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1708833875
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.249801912
Short name T819
Test name
Test status
Simulation time 112880003959 ps
CPU time 59.07 seconds
Started Aug 13 05:15:00 PM PDT 24
Finished Aug 13 05:15:59 PM PDT 24
Peak memory 200848 kb
Host smart-75a283f9-064f-40b0-84d7-eefb260beaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249801912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.249801912
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.2342684037
Short name T158
Test name
Test status
Simulation time 31627426308 ps
CPU time 11.09 seconds
Started Aug 13 05:17:23 PM PDT 24
Finished Aug 13 05:17:35 PM PDT 24
Peak memory 200936 kb
Host smart-dd42f32c-2afc-4a95-821f-c18648f95e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342684037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2342684037
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.2021376114
Short name T77
Test name
Test status
Simulation time 55060561099 ps
CPU time 45.81 seconds
Started Aug 13 05:17:23 PM PDT 24
Finished Aug 13 05:18:09 PM PDT 24
Peak memory 200828 kb
Host smart-edb2c688-fa28-40ba-9de6-e1c95a56e629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021376114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2021376114
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.3796859476
Short name T670
Test name
Test status
Simulation time 83334443936 ps
CPU time 263.7 seconds
Started Aug 13 05:17:23 PM PDT 24
Finished Aug 13 05:21:47 PM PDT 24
Peak memory 200884 kb
Host smart-99bef32d-b140-481d-b83c-a546b4366f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796859476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3796859476
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1550485456
Short name T692
Test name
Test status
Simulation time 42991930940 ps
CPU time 18.64 seconds
Started Aug 13 05:17:21 PM PDT 24
Finished Aug 13 05:17:40 PM PDT 24
Peak memory 200896 kb
Host smart-3f3e5dce-d126-4c26-9b38-cc8a9672d12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550485456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1550485456
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.388287445
Short name T445
Test name
Test status
Simulation time 144514401472 ps
CPU time 52.31 seconds
Started Aug 13 05:17:22 PM PDT 24
Finished Aug 13 05:18:14 PM PDT 24
Peak memory 200792 kb
Host smart-ba61a4b7-bac8-4b61-b6fa-b865805e07c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388287445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.388287445
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1989702538
Short name T956
Test name
Test status
Simulation time 11707646271 ps
CPU time 29.14 seconds
Started Aug 13 05:17:22 PM PDT 24
Finished Aug 13 05:17:52 PM PDT 24
Peak memory 200924 kb
Host smart-e73993a5-db2f-44a1-8d14-8a0e59f339e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989702538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1989702538
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.280281054
Short name T114
Test name
Test status
Simulation time 256567112862 ps
CPU time 53.73 seconds
Started Aug 13 05:17:22 PM PDT 24
Finished Aug 13 05:18:16 PM PDT 24
Peak memory 200816 kb
Host smart-d328cd47-9723-4cda-8cd8-146039189830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280281054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.280281054
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.482075731
Short name T223
Test name
Test status
Simulation time 158424589919 ps
CPU time 182.07 seconds
Started Aug 13 05:17:23 PM PDT 24
Finished Aug 13 05:20:25 PM PDT 24
Peak memory 200908 kb
Host smart-da7b0642-9196-4566-86af-4e7c00db4383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482075731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.482075731
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.2481020314
Short name T156
Test name
Test status
Simulation time 50923302899 ps
CPU time 45.98 seconds
Started Aug 13 05:17:22 PM PDT 24
Finished Aug 13 05:18:08 PM PDT 24
Peak memory 200876 kb
Host smart-d0e36535-ebe8-4ae3-add1-319eb4e81a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481020314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2481020314
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3199434710
Short name T931
Test name
Test status
Simulation time 66924376624 ps
CPU time 204.85 seconds
Started Aug 13 05:17:27 PM PDT 24
Finished Aug 13 05:20:52 PM PDT 24
Peak memory 200936 kb
Host smart-ab026a20-e42e-4861-83fb-b4f5f9403df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199434710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3199434710
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1481773788
Short name T435
Test name
Test status
Simulation time 28124356 ps
CPU time 0.54 seconds
Started Aug 13 05:13:45 PM PDT 24
Finished Aug 13 05:13:45 PM PDT 24
Peak memory 195516 kb
Host smart-f6ebe8e9-4133-403a-b035-188e8eb0f4d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481773788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1481773788
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.988368080
Short name T821
Test name
Test status
Simulation time 39147469014 ps
CPU time 71.13 seconds
Started Aug 13 05:13:44 PM PDT 24
Finished Aug 13 05:14:55 PM PDT 24
Peak memory 200868 kb
Host smart-b0287ef6-4640-40ac-9d97-893841316b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988368080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.988368080
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3702959043
Short name T290
Test name
Test status
Simulation time 66043934537 ps
CPU time 96.63 seconds
Started Aug 13 05:13:52 PM PDT 24
Finished Aug 13 05:15:29 PM PDT 24
Peak memory 200768 kb
Host smart-02d953a0-2582-43dc-aaaf-d9007a81f2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702959043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3702959043
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2390364382
Short name T1091
Test name
Test status
Simulation time 75423005862 ps
CPU time 33.65 seconds
Started Aug 13 05:13:44 PM PDT 24
Finished Aug 13 05:14:18 PM PDT 24
Peak memory 200876 kb
Host smart-040c043b-9ad5-41ba-8403-7feae09f864a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390364382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2390364382
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.73659890
Short name T1060
Test name
Test status
Simulation time 103729810380 ps
CPU time 936.92 seconds
Started Aug 13 05:13:49 PM PDT 24
Finished Aug 13 05:29:26 PM PDT 24
Peak memory 200872 kb
Host smart-bb27bf52-4dae-4c04-8703-9271c1f2ef39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=73659890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.73659890
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2653571042
Short name T383
Test name
Test status
Simulation time 2402677391 ps
CPU time 2.83 seconds
Started Aug 13 05:13:47 PM PDT 24
Finished Aug 13 05:13:50 PM PDT 24
Peak memory 199148 kb
Host smart-3ce77af5-b5fc-4689-a8a8-a5857b0b5a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653571042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2653571042
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.2890967822
Short name T631
Test name
Test status
Simulation time 50341863400 ps
CPU time 22.5 seconds
Started Aug 13 05:13:47 PM PDT 24
Finished Aug 13 05:14:10 PM PDT 24
Peak memory 201020 kb
Host smart-c90f9e01-9741-4f14-900a-7624850dedd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890967822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2890967822
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.2220717222
Short name T443
Test name
Test status
Simulation time 24193163433 ps
CPU time 657.91 seconds
Started Aug 13 05:13:49 PM PDT 24
Finished Aug 13 05:24:47 PM PDT 24
Peak memory 200972 kb
Host smart-8ac8dd42-be68-4868-a852-57c5a10dc3c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2220717222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2220717222
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3360363522
Short name T477
Test name
Test status
Simulation time 6024178801 ps
CPU time 29.78 seconds
Started Aug 13 05:13:52 PM PDT 24
Finished Aug 13 05:14:22 PM PDT 24
Peak memory 199936 kb
Host smart-738a3ef4-5974-47ae-90a1-b714ce021ad4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3360363522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3360363522
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1324156065
Short name T724
Test name
Test status
Simulation time 150106111998 ps
CPU time 247.89 seconds
Started Aug 13 05:13:46 PM PDT 24
Finished Aug 13 05:17:54 PM PDT 24
Peak memory 200868 kb
Host smart-0ca45fa3-f75b-4b4f-90e9-0b857bd29af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324156065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1324156065
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.3099793988
Short name T521
Test name
Test status
Simulation time 607236647 ps
CPU time 1.16 seconds
Started Aug 13 05:13:45 PM PDT 24
Finished Aug 13 05:13:46 PM PDT 24
Peak memory 196384 kb
Host smart-641ba94d-cfef-4df9-9376-87720e29d283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099793988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3099793988
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.778678913
Short name T75
Test name
Test status
Simulation time 39964116 ps
CPU time 0.79 seconds
Started Aug 13 05:13:46 PM PDT 24
Finished Aug 13 05:13:47 PM PDT 24
Peak memory 219072 kb
Host smart-717e922a-5cc8-4774-9784-fc938937ffa7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778678913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.778678913
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.3909947616
Short name T579
Test name
Test status
Simulation time 5645935052 ps
CPU time 19.59 seconds
Started Aug 13 05:13:51 PM PDT 24
Finished Aug 13 05:14:11 PM PDT 24
Peak memory 200220 kb
Host smart-ca60a8c8-eff3-4367-b8c3-f5ba6bef4d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909947616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3909947616
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.275433083
Short name T357
Test name
Test status
Simulation time 182922081477 ps
CPU time 575.57 seconds
Started Aug 13 05:13:45 PM PDT 24
Finished Aug 13 05:23:21 PM PDT 24
Peak memory 209360 kb
Host smart-782df363-d935-440d-a8e4-1ee8d1ba3edb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275433083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.275433083
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.437805899
Short name T350
Test name
Test status
Simulation time 11216577895 ps
CPU time 51.02 seconds
Started Aug 13 05:13:47 PM PDT 24
Finished Aug 13 05:14:38 PM PDT 24
Peak memory 217320 kb
Host smart-afe81d6d-c983-4186-8b7a-db9a246b381d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437805899 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.437805899
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.977228744
Short name T3
Test name
Test status
Simulation time 1039461052 ps
CPU time 1.4 seconds
Started Aug 13 05:13:53 PM PDT 24
Finished Aug 13 05:13:54 PM PDT 24
Peak memory 199288 kb
Host smart-7ca49eba-0f6a-443b-bf20-a729a47ebab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977228744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.977228744
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3631395239
Short name T638
Test name
Test status
Simulation time 47769525710 ps
CPU time 18.38 seconds
Started Aug 13 05:13:44 PM PDT 24
Finished Aug 13 05:14:03 PM PDT 24
Peak memory 200880 kb
Host smart-b55d454b-64dc-4c8a-900d-e97474fd2466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631395239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3631395239
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1773255232
Short name T441
Test name
Test status
Simulation time 20427868 ps
CPU time 0.55 seconds
Started Aug 13 05:15:07 PM PDT 24
Finished Aug 13 05:15:08 PM PDT 24
Peak memory 196116 kb
Host smart-b54b5324-df30-4d66-96d6-d8012d95ce6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773255232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1773255232
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3327218461
Short name T313
Test name
Test status
Simulation time 48129088027 ps
CPU time 16.74 seconds
Started Aug 13 05:15:06 PM PDT 24
Finished Aug 13 05:15:23 PM PDT 24
Peak memory 200772 kb
Host smart-69de1b23-e0a4-40f9-8b85-7cbdd5dec8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327218461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3327218461
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.636191600
Short name T833
Test name
Test status
Simulation time 124504171957 ps
CPU time 87.02 seconds
Started Aug 13 05:15:06 PM PDT 24
Finished Aug 13 05:16:33 PM PDT 24
Peak memory 200904 kb
Host smart-fdf4d785-141c-4fc8-8240-cf17b60baae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636191600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.636191600
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3807502117
Short name T426
Test name
Test status
Simulation time 57251485132 ps
CPU time 24.73 seconds
Started Aug 13 05:15:06 PM PDT 24
Finished Aug 13 05:15:31 PM PDT 24
Peak memory 200656 kb
Host smart-cd24c99f-1b46-459a-a09b-9de3ec7c5689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807502117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3807502117
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.3935410414
Short name T867
Test name
Test status
Simulation time 53892127087 ps
CPU time 43.77 seconds
Started Aug 13 05:15:08 PM PDT 24
Finished Aug 13 05:15:52 PM PDT 24
Peak memory 200388 kb
Host smart-42ce2df9-10a5-4d53-ae2f-575f4cb3e64e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935410414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3935410414
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.947537878
Short name T1088
Test name
Test status
Simulation time 60549398848 ps
CPU time 460.56 seconds
Started Aug 13 05:15:08 PM PDT 24
Finished Aug 13 05:22:49 PM PDT 24
Peak memory 200940 kb
Host smart-458d32dd-c027-4815-a911-f36587e5b322
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=947537878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.947537878
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1801692661
Short name T721
Test name
Test status
Simulation time 309593860 ps
CPU time 0.69 seconds
Started Aug 13 05:15:05 PM PDT 24
Finished Aug 13 05:15:06 PM PDT 24
Peak memory 196324 kb
Host smart-d12ed7c5-57b1-4d84-9dfd-5dbf10410216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801692661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1801692661
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.3790826039
Short name T735
Test name
Test status
Simulation time 17395014932 ps
CPU time 18.64 seconds
Started Aug 13 05:15:05 PM PDT 24
Finished Aug 13 05:15:24 PM PDT 24
Peak memory 199848 kb
Host smart-06030b28-ba1b-4296-b653-13c35f5eaea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790826039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3790826039
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.973262699
Short name T824
Test name
Test status
Simulation time 15500204154 ps
CPU time 41.13 seconds
Started Aug 13 05:15:08 PM PDT 24
Finished Aug 13 05:15:49 PM PDT 24
Peak memory 200812 kb
Host smart-d52aeab1-64b0-4320-9cd2-df08fbec2e41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=973262699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.973262699
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.1129602149
Short name T492
Test name
Test status
Simulation time 6937349883 ps
CPU time 33.94 seconds
Started Aug 13 05:15:06 PM PDT 24
Finished Aug 13 05:15:40 PM PDT 24
Peak memory 199652 kb
Host smart-5cdc62e2-5b5e-48f3-9c20-b0118e62e480
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1129602149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1129602149
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.2455228068
Short name T599
Test name
Test status
Simulation time 61816166295 ps
CPU time 104.81 seconds
Started Aug 13 05:15:05 PM PDT 24
Finished Aug 13 05:16:50 PM PDT 24
Peak memory 200924 kb
Host smart-feb8b8cb-1819-4b06-aec5-1c851ad818d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455228068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2455228068
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.2112456244
Short name T806
Test name
Test status
Simulation time 4459556066 ps
CPU time 2.54 seconds
Started Aug 13 05:15:09 PM PDT 24
Finished Aug 13 05:15:11 PM PDT 24
Peak memory 196960 kb
Host smart-ab575bb1-2811-406e-b89b-b1dd246d5858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112456244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2112456244
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.217164351
Short name T404
Test name
Test status
Simulation time 672638266 ps
CPU time 1.78 seconds
Started Aug 13 05:15:07 PM PDT 24
Finished Aug 13 05:15:09 PM PDT 24
Peak memory 199540 kb
Host smart-07e73c18-6f9b-4d59-b08f-527ba72fabfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217164351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.217164351
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3497026045
Short name T352
Test name
Test status
Simulation time 30628344239 ps
CPU time 39.31 seconds
Started Aug 13 05:15:06 PM PDT 24
Finished Aug 13 05:15:45 PM PDT 24
Peak memory 217340 kb
Host smart-52c6fe0b-bd28-471b-8d5c-b1e917bdece9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497026045 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3497026045
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3686551314
Short name T468
Test name
Test status
Simulation time 1182207414 ps
CPU time 4.89 seconds
Started Aug 13 05:15:06 PM PDT 24
Finished Aug 13 05:15:11 PM PDT 24
Peak memory 200752 kb
Host smart-9046006f-5299-4728-96b1-9e8c23430d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686551314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3686551314
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.257738513
Short name T896
Test name
Test status
Simulation time 125655472143 ps
CPU time 55.41 seconds
Started Aug 13 05:15:07 PM PDT 24
Finished Aug 13 05:16:02 PM PDT 24
Peak memory 200848 kb
Host smart-cc6bb842-7f49-42ec-b652-38816e0d825f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257738513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.257738513
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1818841739
Short name T809
Test name
Test status
Simulation time 13322824 ps
CPU time 0.55 seconds
Started Aug 13 05:15:15 PM PDT 24
Finished Aug 13 05:15:15 PM PDT 24
Peak memory 194632 kb
Host smart-84eb7393-818e-4972-9090-c8a877740c24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818841739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1818841739
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1967839007
Short name T659
Test name
Test status
Simulation time 30151101177 ps
CPU time 46.05 seconds
Started Aug 13 05:15:07 PM PDT 24
Finished Aug 13 05:15:53 PM PDT 24
Peak memory 200928 kb
Host smart-576fc539-9a0d-4a33-8515-741a1a612447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967839007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1967839007
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1534689499
Short name T434
Test name
Test status
Simulation time 162414647530 ps
CPU time 265.1 seconds
Started Aug 13 05:15:06 PM PDT 24
Finished Aug 13 05:19:31 PM PDT 24
Peak memory 200876 kb
Host smart-92c0f7c3-9b35-4d79-8b3f-d63f51215624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534689499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1534689499
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.190466972
Short name T249
Test name
Test status
Simulation time 173051866982 ps
CPU time 296.39 seconds
Started Aug 13 05:15:10 PM PDT 24
Finished Aug 13 05:20:07 PM PDT 24
Peak memory 200848 kb
Host smart-a49732fa-a5b1-4a55-ae7d-3c2b33eb316e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190466972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.190466972
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2747045290
Short name T1154
Test name
Test status
Simulation time 36351313096 ps
CPU time 80.49 seconds
Started Aug 13 05:15:12 PM PDT 24
Finished Aug 13 05:16:32 PM PDT 24
Peak memory 200888 kb
Host smart-fc8e14d5-136c-4f36-9384-d10a644e6727
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747045290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2747045290
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.2631416772
Short name T702
Test name
Test status
Simulation time 58627719113 ps
CPU time 595.52 seconds
Started Aug 13 05:15:10 PM PDT 24
Finished Aug 13 05:25:06 PM PDT 24
Peak memory 200864 kb
Host smart-28f6d9ea-b8a6-4bfa-9632-abd430566fb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2631416772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2631416772
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.3524916700
Short name T394
Test name
Test status
Simulation time 6307311199 ps
CPU time 3.35 seconds
Started Aug 13 05:15:15 PM PDT 24
Finished Aug 13 05:15:18 PM PDT 24
Peak memory 198860 kb
Host smart-a3865707-293f-4ae7-ad47-ffd221ebe7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524916700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3524916700
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.2480933036
Short name T736
Test name
Test status
Simulation time 89794903402 ps
CPU time 82.17 seconds
Started Aug 13 05:15:11 PM PDT 24
Finished Aug 13 05:16:33 PM PDT 24
Peak memory 200844 kb
Host smart-1131e622-ceb3-4cd2-91ba-f7c8a0b65905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480933036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2480933036
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.3460246237
Short name T1175
Test name
Test status
Simulation time 22795924620 ps
CPU time 70.23 seconds
Started Aug 13 05:15:13 PM PDT 24
Finished Aug 13 05:16:23 PM PDT 24
Peak memory 200928 kb
Host smart-4f809e46-abf2-4a1a-bc37-1f06c8d08aed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3460246237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3460246237
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.968669120
Short name T671
Test name
Test status
Simulation time 4847551862 ps
CPU time 39.28 seconds
Started Aug 13 05:15:13 PM PDT 24
Finished Aug 13 05:15:52 PM PDT 24
Peak memory 200048 kb
Host smart-373603d3-a5ea-4d3d-83da-c5cb127da8ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=968669120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.968669120
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1530278168
Short name T930
Test name
Test status
Simulation time 47626148444 ps
CPU time 73.22 seconds
Started Aug 13 05:15:12 PM PDT 24
Finished Aug 13 05:16:25 PM PDT 24
Peak memory 200920 kb
Host smart-cc6531db-05b4-4c93-b8be-7704c68a14d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530278168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1530278168
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.3616964452
Short name T84
Test name
Test status
Simulation time 3325565007 ps
CPU time 5.14 seconds
Started Aug 13 05:15:12 PM PDT 24
Finished Aug 13 05:15:17 PM PDT 24
Peak memory 196996 kb
Host smart-81c8a35a-3387-4fe0-bc2d-402066f564b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616964452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3616964452
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.149447931
Short name T463
Test name
Test status
Simulation time 5876043520 ps
CPU time 16.44 seconds
Started Aug 13 05:15:06 PM PDT 24
Finished Aug 13 05:15:23 PM PDT 24
Peak memory 200844 kb
Host smart-823d2555-9df0-49cb-aea6-1a8df4fb4028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149447931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.149447931
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.3806181335
Short name T836
Test name
Test status
Simulation time 11034680591 ps
CPU time 50.07 seconds
Started Aug 13 05:15:13 PM PDT 24
Finished Aug 13 05:16:04 PM PDT 24
Peak memory 217516 kb
Host smart-e296aae7-fbf9-46ec-a55f-3e238c48a13c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806181335 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.3806181335
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1048550267
Short name T1148
Test name
Test status
Simulation time 12662232419 ps
CPU time 5.22 seconds
Started Aug 13 05:15:13 PM PDT 24
Finished Aug 13 05:15:18 PM PDT 24
Peak memory 200796 kb
Host smart-24f40071-5e69-431b-9062-476b949c6641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048550267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1048550267
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3600520446
Short name T314
Test name
Test status
Simulation time 23122164703 ps
CPU time 37.91 seconds
Started Aug 13 05:15:09 PM PDT 24
Finished Aug 13 05:15:47 PM PDT 24
Peak memory 200828 kb
Host smart-be7d047c-9446-4607-bf2c-5f8df5de94f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600520446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3600520446
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2659727465
Short name T1043
Test name
Test status
Simulation time 22756946 ps
CPU time 0.55 seconds
Started Aug 13 05:15:15 PM PDT 24
Finished Aug 13 05:15:16 PM PDT 24
Peak memory 195228 kb
Host smart-c9a45290-6ffa-4665-92e3-3f1759ceb7e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659727465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2659727465
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1982085979
Short name T126
Test name
Test status
Simulation time 61176071202 ps
CPU time 23.27 seconds
Started Aug 13 05:15:13 PM PDT 24
Finished Aug 13 05:15:36 PM PDT 24
Peak memory 200816 kb
Host smart-b877f175-51a5-471d-a1de-9f3c0018efd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982085979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1982085979
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2901679173
Short name T146
Test name
Test status
Simulation time 15577663688 ps
CPU time 24.71 seconds
Started Aug 13 05:15:15 PM PDT 24
Finished Aug 13 05:15:40 PM PDT 24
Peak memory 200928 kb
Host smart-7b4cd29d-a700-4c63-a433-77b3d95f3b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901679173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2901679173
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1730221842
Short name T560
Test name
Test status
Simulation time 114871712906 ps
CPU time 182.55 seconds
Started Aug 13 05:15:14 PM PDT 24
Finished Aug 13 05:18:17 PM PDT 24
Peak memory 200744 kb
Host smart-ae4b97c7-9ca3-4f5c-a871-6203f83b5fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730221842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1730221842
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2658051116
Short name T936
Test name
Test status
Simulation time 229430902931 ps
CPU time 94.84 seconds
Started Aug 13 05:15:11 PM PDT 24
Finished Aug 13 05:16:46 PM PDT 24
Peak memory 200792 kb
Host smart-3296eef5-c5c9-4739-ae30-b22215f1c3d9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658051116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2658051116
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.3430720549
Short name T1125
Test name
Test status
Simulation time 134770709008 ps
CPU time 452.97 seconds
Started Aug 13 05:15:16 PM PDT 24
Finished Aug 13 05:22:49 PM PDT 24
Peak memory 200936 kb
Host smart-1effaf51-61dd-4150-8496-c54e990391da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3430720549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3430720549
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.414744863
Short name T945
Test name
Test status
Simulation time 11107509321 ps
CPU time 11.52 seconds
Started Aug 13 05:15:15 PM PDT 24
Finished Aug 13 05:15:26 PM PDT 24
Peak memory 200836 kb
Host smart-f6bd5f80-f22d-4351-acb9-b4df1e3aae7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414744863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.414744863
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.3544603237
Short name T854
Test name
Test status
Simulation time 57137618907 ps
CPU time 46.5 seconds
Started Aug 13 05:15:11 PM PDT 24
Finished Aug 13 05:15:58 PM PDT 24
Peak memory 199800 kb
Host smart-eaff1810-8569-40a2-81c9-cc848380d837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544603237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3544603237
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1848508196
Short name T1081
Test name
Test status
Simulation time 19760268207 ps
CPU time 963.71 seconds
Started Aug 13 05:15:15 PM PDT 24
Finished Aug 13 05:31:19 PM PDT 24
Peak memory 200888 kb
Host smart-bb5de705-4435-4d62-873a-1f7e9efcad86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1848508196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1848508196
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3833931714
Short name T365
Test name
Test status
Simulation time 7766048139 ps
CPU time 6.63 seconds
Started Aug 13 05:15:15 PM PDT 24
Finished Aug 13 05:15:22 PM PDT 24
Peak memory 199996 kb
Host smart-3b795b70-8a99-4768-ab45-062082738497
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3833931714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3833931714
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.644166228
Short name T884
Test name
Test status
Simulation time 50380073018 ps
CPU time 13.53 seconds
Started Aug 13 05:15:13 PM PDT 24
Finished Aug 13 05:15:26 PM PDT 24
Peak memory 200868 kb
Host smart-0adcdb99-47dc-4f80-bba4-26aff07b1291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644166228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.644166228
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.773579465
Short name T333
Test name
Test status
Simulation time 2657156525 ps
CPU time 4.86 seconds
Started Aug 13 05:15:14 PM PDT 24
Finished Aug 13 05:15:19 PM PDT 24
Peak memory 195816 kb
Host smart-aacf91df-e309-4600-8e6a-6b09065eb221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773579465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.773579465
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3806240186
Short name T1114
Test name
Test status
Simulation time 5835633752 ps
CPU time 19.51 seconds
Started Aug 13 05:15:15 PM PDT 24
Finished Aug 13 05:15:35 PM PDT 24
Peak memory 200896 kb
Host smart-5ebad15d-e5d1-49da-bfba-7765493c89e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806240186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3806240186
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.2077590133
Short name T955
Test name
Test status
Simulation time 664250184600 ps
CPU time 127.69 seconds
Started Aug 13 05:15:11 PM PDT 24
Finished Aug 13 05:17:19 PM PDT 24
Peak memory 209440 kb
Host smart-c6311148-1f88-40c9-9ac6-e24935f39139
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077590133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2077590133
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3984201624
Short name T421
Test name
Test status
Simulation time 5498032590 ps
CPU time 27.61 seconds
Started Aug 13 05:15:15 PM PDT 24
Finished Aug 13 05:15:43 PM PDT 24
Peak memory 217276 kb
Host smart-47695261-5060-413a-bf18-4eecc04c338e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984201624 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3984201624
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2976039947
Short name T653
Test name
Test status
Simulation time 6079547168 ps
CPU time 14.11 seconds
Started Aug 13 05:15:13 PM PDT 24
Finished Aug 13 05:15:27 PM PDT 24
Peak memory 200800 kb
Host smart-007fa03a-226e-40dd-b182-eda5bbb71b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976039947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2976039947
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.834564291
Short name T733
Test name
Test status
Simulation time 8409351867 ps
CPU time 11.01 seconds
Started Aug 13 05:15:12 PM PDT 24
Finished Aug 13 05:15:23 PM PDT 24
Peak memory 197304 kb
Host smart-c8f56e15-da4d-429d-b784-d58541824a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834564291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.834564291
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.2689515481
Short name T985
Test name
Test status
Simulation time 24919463 ps
CPU time 0.58 seconds
Started Aug 13 05:15:18 PM PDT 24
Finished Aug 13 05:15:19 PM PDT 24
Peak memory 196220 kb
Host smart-db584aeb-9858-47fb-be29-7c7a8bc1c5f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689515481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2689515481
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1123940722
Short name T307
Test name
Test status
Simulation time 133636771959 ps
CPU time 306.07 seconds
Started Aug 13 05:15:19 PM PDT 24
Finished Aug 13 05:20:25 PM PDT 24
Peak memory 200820 kb
Host smart-d50eb097-6865-4f30-b01e-25262e9a521a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123940722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1123940722
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.171516887
Short name T894
Test name
Test status
Simulation time 225112717569 ps
CPU time 31.24 seconds
Started Aug 13 05:15:20 PM PDT 24
Finished Aug 13 05:15:51 PM PDT 24
Peak memory 200876 kb
Host smart-d053b6f2-138e-49a4-a1a8-b41102df62d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171516887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.171516887
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.4215978451
Short name T193
Test name
Test status
Simulation time 29132701504 ps
CPU time 14.36 seconds
Started Aug 13 05:15:20 PM PDT 24
Finished Aug 13 05:15:35 PM PDT 24
Peak memory 200956 kb
Host smart-5d952261-bd6f-4b53-a0ca-5fa5466f2fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215978451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.4215978451
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.1707753683
Short name T899
Test name
Test status
Simulation time 8523445565 ps
CPU time 12.46 seconds
Started Aug 13 05:15:20 PM PDT 24
Finished Aug 13 05:15:33 PM PDT 24
Peak memory 197808 kb
Host smart-3ee69674-9018-4fa1-ace5-3f6f2cffdc13
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707753683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1707753683
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1290053456
Short name T332
Test name
Test status
Simulation time 61683305373 ps
CPU time 145.13 seconds
Started Aug 13 05:15:21 PM PDT 24
Finished Aug 13 05:17:46 PM PDT 24
Peak memory 200840 kb
Host smart-50b15040-ccc3-4004-aa98-39c8c830fce6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1290053456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1290053456
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.77228078
Short name T857
Test name
Test status
Simulation time 5701643006 ps
CPU time 5.68 seconds
Started Aug 13 05:15:21 PM PDT 24
Finished Aug 13 05:15:27 PM PDT 24
Peak memory 200484 kb
Host smart-47430787-0801-4636-9397-3dcac7a38f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77228078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.77228078
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.3103974246
Short name T348
Test name
Test status
Simulation time 38497121686 ps
CPU time 14.64 seconds
Started Aug 13 05:15:25 PM PDT 24
Finished Aug 13 05:15:40 PM PDT 24
Peak memory 200872 kb
Host smart-ed4b3099-d9c5-4506-8a1c-14f841bd4e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103974246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.3103974246
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.1991805538
Short name T666
Test name
Test status
Simulation time 14796024055 ps
CPU time 156.34 seconds
Started Aug 13 05:15:20 PM PDT 24
Finished Aug 13 05:17:57 PM PDT 24
Peak memory 200808 kb
Host smart-e2d5a38a-4482-4e89-8c15-fbf95cbe99f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1991805538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1991805538
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.1503411422
Short name T792
Test name
Test status
Simulation time 3976760069 ps
CPU time 7.91 seconds
Started Aug 13 05:15:19 PM PDT 24
Finished Aug 13 05:15:27 PM PDT 24
Peak memory 198768 kb
Host smart-3212a77f-f9e4-48fa-aa5c-ac435e88bf80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1503411422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1503411422
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2425235429
Short name T322
Test name
Test status
Simulation time 83284985766 ps
CPU time 115.79 seconds
Started Aug 13 05:15:21 PM PDT 24
Finished Aug 13 05:17:17 PM PDT 24
Peak memory 200616 kb
Host smart-d969d170-3685-4602-b008-1534821901f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425235429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2425235429
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.2829728884
Short name T1037
Test name
Test status
Simulation time 3850641717 ps
CPU time 5.74 seconds
Started Aug 13 05:15:19 PM PDT 24
Finished Aug 13 05:15:25 PM PDT 24
Peak memory 197216 kb
Host smart-c167e690-4d93-4250-8153-e493cf5a1103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829728884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2829728884
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1866916521
Short name T387
Test name
Test status
Simulation time 698223359 ps
CPU time 1.42 seconds
Started Aug 13 05:15:16 PM PDT 24
Finished Aug 13 05:15:18 PM PDT 24
Peak memory 200824 kb
Host smart-7c31f02f-76e4-448c-8596-9dfa87f3479e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866916521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1866916521
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3916993015
Short name T745
Test name
Test status
Simulation time 526476445752 ps
CPU time 383.2 seconds
Started Aug 13 05:15:21 PM PDT 24
Finished Aug 13 05:21:44 PM PDT 24
Peak memory 209332 kb
Host smart-4f346448-dac6-4107-a7ff-7fee7e489bff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916993015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3916993015
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.1027004150
Short name T478
Test name
Test status
Simulation time 2376525254 ps
CPU time 25.87 seconds
Started Aug 13 05:15:21 PM PDT 24
Finished Aug 13 05:15:47 PM PDT 24
Peak memory 209240 kb
Host smart-5f6dd40c-064a-4c2b-ad8d-f65d82f1482f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027004150 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1027004150
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.616236125
Short name T786
Test name
Test status
Simulation time 777243137 ps
CPU time 3.66 seconds
Started Aug 13 05:15:24 PM PDT 24
Finished Aug 13 05:15:28 PM PDT 24
Peak memory 199232 kb
Host smart-21e7061e-e555-4fe2-b1a2-1e004e8558ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616236125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.616236125
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.868258822
Short name T275
Test name
Test status
Simulation time 10395534896 ps
CPU time 4.59 seconds
Started Aug 13 05:15:10 PM PDT 24
Finished Aug 13 05:15:15 PM PDT 24
Peak memory 199572 kb
Host smart-4a25e654-74bd-429e-bc87-84649e014b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868258822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.868258822
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2114158846
Short name T406
Test name
Test status
Simulation time 44367498 ps
CPU time 0.56 seconds
Started Aug 13 05:15:25 PM PDT 24
Finished Aug 13 05:15:26 PM PDT 24
Peak memory 195696 kb
Host smart-1744c63d-e955-4496-83d9-8bc42e0df4fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114158846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2114158846
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3208946504
Short name T655
Test name
Test status
Simulation time 145365148021 ps
CPU time 40.37 seconds
Started Aug 13 05:15:22 PM PDT 24
Finished Aug 13 05:16:03 PM PDT 24
Peak memory 200856 kb
Host smart-d81077e9-ad99-4a1a-bf11-1eb84c70decd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208946504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3208946504
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.32791270
Short name T1113
Test name
Test status
Simulation time 144183998810 ps
CPU time 53.58 seconds
Started Aug 13 05:15:21 PM PDT 24
Finished Aug 13 05:16:14 PM PDT 24
Peak memory 200704 kb
Host smart-dfe2002b-3d42-41ba-8abc-139dc6f0f1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32791270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.32791270
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.1036057057
Short name T785
Test name
Test status
Simulation time 179154781216 ps
CPU time 246.58 seconds
Started Aug 13 05:15:20 PM PDT 24
Finished Aug 13 05:19:27 PM PDT 24
Peak memory 200888 kb
Host smart-201505e2-c420-491e-9b6a-3572f961a9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036057057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1036057057
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3574363067
Short name T717
Test name
Test status
Simulation time 37592255448 ps
CPU time 71.56 seconds
Started Aug 13 05:15:25 PM PDT 24
Finished Aug 13 05:16:36 PM PDT 24
Peak memory 200924 kb
Host smart-ff205da7-7192-4dc7-956c-f8f0c677eadc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574363067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3574363067
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.280120236
Short name T486
Test name
Test status
Simulation time 122008028248 ps
CPU time 773.7 seconds
Started Aug 13 05:15:25 PM PDT 24
Finished Aug 13 05:28:19 PM PDT 24
Peak memory 200924 kb
Host smart-fb84bb6c-610a-4d5a-9ff5-088a5b35a19e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=280120236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.280120236
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3089583868
Short name T1025
Test name
Test status
Simulation time 1230973355 ps
CPU time 2.3 seconds
Started Aug 13 05:15:21 PM PDT 24
Finished Aug 13 05:15:24 PM PDT 24
Peak memory 199212 kb
Host smart-120f2794-9ba2-4339-adf4-e17033e5301a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089583868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3089583868
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.985393451
Short name T437
Test name
Test status
Simulation time 54056963659 ps
CPU time 41.92 seconds
Started Aug 13 05:15:19 PM PDT 24
Finished Aug 13 05:16:01 PM PDT 24
Peak memory 199600 kb
Host smart-8917e63d-29fe-411a-8e7d-340310a9c5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985393451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.985393451
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1472821024
Short name T415
Test name
Test status
Simulation time 20175542858 ps
CPU time 846.38 seconds
Started Aug 13 05:15:24 PM PDT 24
Finished Aug 13 05:29:30 PM PDT 24
Peak memory 200828 kb
Host smart-1a90c8ed-b0e8-4197-b8fc-e80bcd71e9c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1472821024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1472821024
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1650938143
Short name T386
Test name
Test status
Simulation time 7152677427 ps
CPU time 32.23 seconds
Started Aug 13 05:15:20 PM PDT 24
Finished Aug 13 05:15:53 PM PDT 24
Peak memory 198960 kb
Host smart-9c945fd7-a21a-466c-8cd9-fd6e73e1000d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1650938143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1650938143
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.608020148
Short name T273
Test name
Test status
Simulation time 1660148645 ps
CPU time 1.82 seconds
Started Aug 13 05:15:20 PM PDT 24
Finished Aug 13 05:15:22 PM PDT 24
Peak memory 196524 kb
Host smart-64c2a112-d275-45bb-88e7-9f044af8f4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608020148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.608020148
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.2986001121
Short name T346
Test name
Test status
Simulation time 267996361 ps
CPU time 1.6 seconds
Started Aug 13 05:15:19 PM PDT 24
Finished Aug 13 05:15:20 PM PDT 24
Peak memory 200372 kb
Host smart-b91c3653-2a9c-4af4-ab0a-e32a2c1ac7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986001121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2986001121
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.1550383532
Short name T312
Test name
Test status
Simulation time 160682108349 ps
CPU time 263.88 seconds
Started Aug 13 05:15:19 PM PDT 24
Finished Aug 13 05:19:43 PM PDT 24
Peak memory 200948 kb
Host smart-07febf81-0f5d-4611-9746-32ecfc171d12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550383532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1550383532
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1760407319
Short name T960
Test name
Test status
Simulation time 4205946180 ps
CPU time 36.88 seconds
Started Aug 13 05:15:20 PM PDT 24
Finished Aug 13 05:15:57 PM PDT 24
Peak memory 217308 kb
Host smart-c4e6be4c-8264-4998-85be-261639b268c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760407319 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1760407319
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.74207940
Short name T1008
Test name
Test status
Simulation time 2174955798 ps
CPU time 1.69 seconds
Started Aug 13 05:15:20 PM PDT 24
Finished Aug 13 05:15:22 PM PDT 24
Peak memory 199800 kb
Host smart-483d7333-61da-4ded-b93b-cc12ef4cafed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74207940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.74207940
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.4208016945
Short name T430
Test name
Test status
Simulation time 15445386005 ps
CPU time 6.55 seconds
Started Aug 13 05:15:21 PM PDT 24
Finished Aug 13 05:15:28 PM PDT 24
Peak memory 200908 kb
Host smart-3dfc56b2-06f2-415c-a037-39a1d87b1153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208016945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.4208016945
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.4127336104
Short name T457
Test name
Test status
Simulation time 13104638 ps
CPU time 0.58 seconds
Started Aug 13 05:15:31 PM PDT 24
Finished Aug 13 05:15:31 PM PDT 24
Peak memory 196244 kb
Host smart-3e355d7d-7f94-4848-8ca4-adff919bff2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127336104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.4127336104
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2828780163
Short name T1126
Test name
Test status
Simulation time 125992949217 ps
CPU time 223.21 seconds
Started Aug 13 05:15:21 PM PDT 24
Finished Aug 13 05:19:04 PM PDT 24
Peak memory 200728 kb
Host smart-b793d214-ae07-4a6d-973c-0b2f617d0fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828780163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2828780163
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2818105743
Short name T131
Test name
Test status
Simulation time 113412205531 ps
CPU time 52.95 seconds
Started Aug 13 05:15:19 PM PDT 24
Finished Aug 13 05:16:12 PM PDT 24
Peak memory 200824 kb
Host smart-d2ab1a3f-ee1a-4a5f-93f9-ad7cbf3e55e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818105743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2818105743
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2995813924
Short name T287
Test name
Test status
Simulation time 41279545686 ps
CPU time 120.02 seconds
Started Aug 13 05:15:30 PM PDT 24
Finished Aug 13 05:17:30 PM PDT 24
Peak memory 200912 kb
Host smart-ee563559-14d0-4c91-a8f0-f7cf86cfe8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995813924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2995813924
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.2780080266
Short name T1078
Test name
Test status
Simulation time 39447061945 ps
CPU time 71.75 seconds
Started Aug 13 05:15:29 PM PDT 24
Finished Aug 13 05:16:42 PM PDT 24
Peak memory 200896 kb
Host smart-1d30246b-007b-4151-b4f8-910dcf9dfe71
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780080266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2780080266
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3451294813
Short name T38
Test name
Test status
Simulation time 164317803001 ps
CPU time 1383.99 seconds
Started Aug 13 05:15:30 PM PDT 24
Finished Aug 13 05:38:34 PM PDT 24
Peak memory 200896 kb
Host smart-f9d3f8f9-f2c5-4a7d-a4e8-92dc4793d979
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3451294813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3451294813
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.431461493
Short name T685
Test name
Test status
Simulation time 6167174052 ps
CPU time 4.12 seconds
Started Aug 13 05:15:32 PM PDT 24
Finished Aug 13 05:15:37 PM PDT 24
Peak memory 199800 kb
Host smart-e7f887c6-d86b-4496-8c1e-9fcc33e7fbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431461493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.431461493
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.494531942
Short name T309
Test name
Test status
Simulation time 89329171399 ps
CPU time 137.14 seconds
Started Aug 13 05:15:29 PM PDT 24
Finished Aug 13 05:17:47 PM PDT 24
Peak memory 201004 kb
Host smart-12a5b87a-7260-40aa-a55e-298f54f0ca25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494531942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.494531942
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.3580845528
Short name T261
Test name
Test status
Simulation time 15554232847 ps
CPU time 52.76 seconds
Started Aug 13 05:15:28 PM PDT 24
Finished Aug 13 05:16:21 PM PDT 24
Peak memory 200920 kb
Host smart-ad2fbe6d-1f4d-4898-b72a-d57c9d9fb809
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3580845528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3580845528
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.967863975
Short name T1127
Test name
Test status
Simulation time 3456464826 ps
CPU time 30.44 seconds
Started Aug 13 05:15:28 PM PDT 24
Finished Aug 13 05:15:59 PM PDT 24
Peak memory 198960 kb
Host smart-740a8d91-ee12-405c-a773-5ec0e816bd06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=967863975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.967863975
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1389087826
Short name T179
Test name
Test status
Simulation time 63575023345 ps
CPU time 58.03 seconds
Started Aug 13 05:15:30 PM PDT 24
Finished Aug 13 05:16:28 PM PDT 24
Peak memory 200924 kb
Host smart-ea137eb6-2a39-4e2d-a7ca-e36f2338ddf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389087826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1389087826
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.948931243
Short name T571
Test name
Test status
Simulation time 6682066740 ps
CPU time 2.39 seconds
Started Aug 13 05:15:29 PM PDT 24
Finished Aug 13 05:15:32 PM PDT 24
Peak memory 197044 kb
Host smart-ec4836f2-29ee-4834-968e-027eba6996db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948931243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.948931243
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.538516231
Short name T628
Test name
Test status
Simulation time 5536460061 ps
CPU time 13.67 seconds
Started Aug 13 05:15:19 PM PDT 24
Finished Aug 13 05:15:33 PM PDT 24
Peak memory 200908 kb
Host smart-85313640-f20f-4e7d-bb5f-a65b2cf536a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538516231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.538516231
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2528182433
Short name T996
Test name
Test status
Simulation time 5406969951 ps
CPU time 13.3 seconds
Started Aug 13 05:15:28 PM PDT 24
Finished Aug 13 05:15:41 PM PDT 24
Peak memory 216660 kb
Host smart-8d7e784b-7947-442c-8713-44b2206a5bd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528182433 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2528182433
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.1877262003
Short name T1039
Test name
Test status
Simulation time 950974952 ps
CPU time 3.22 seconds
Started Aug 13 05:15:29 PM PDT 24
Finished Aug 13 05:15:33 PM PDT 24
Peak memory 199820 kb
Host smart-40565498-82f7-4105-b9d7-9a46301ef031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877262003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.1877262003
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2915525733
Short name T330
Test name
Test status
Simulation time 43989694486 ps
CPU time 75.07 seconds
Started Aug 13 05:15:22 PM PDT 24
Finished Aug 13 05:16:37 PM PDT 24
Peak memory 200868 kb
Host smart-b3c864f1-a7f1-40f4-83d3-fe4276145bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915525733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2915525733
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.1774176307
Short name T870
Test name
Test status
Simulation time 53474177 ps
CPU time 0.56 seconds
Started Aug 13 05:15:27 PM PDT 24
Finished Aug 13 05:15:27 PM PDT 24
Peak memory 196504 kb
Host smart-a10c1e54-947c-4850-aa6a-85524530408e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774176307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1774176307
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2054535339
Short name T989
Test name
Test status
Simulation time 66883028029 ps
CPU time 27.96 seconds
Started Aug 13 05:15:30 PM PDT 24
Finished Aug 13 05:15:58 PM PDT 24
Peak memory 200868 kb
Host smart-32c73ddb-e9c6-4d8b-950c-9a2e54566b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054535339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2054535339
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.1462691284
Short name T295
Test name
Test status
Simulation time 24186670596 ps
CPU time 18.21 seconds
Started Aug 13 05:15:30 PM PDT 24
Finished Aug 13 05:15:48 PM PDT 24
Peak memory 200888 kb
Host smart-f6ddf05a-ce78-4ec2-ad4c-951d597fb8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462691284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1462691284
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3252997742
Short name T1110
Test name
Test status
Simulation time 129404379503 ps
CPU time 215.6 seconds
Started Aug 13 05:15:29 PM PDT 24
Finished Aug 13 05:19:05 PM PDT 24
Peak memory 200936 kb
Host smart-48fddf7d-43e6-4fd2-8652-2e92bc10d6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252997742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3252997742
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.1030311152
Short name T951
Test name
Test status
Simulation time 12512357381 ps
CPU time 20.96 seconds
Started Aug 13 05:15:32 PM PDT 24
Finished Aug 13 05:15:53 PM PDT 24
Peak memory 197960 kb
Host smart-e7cc3be9-4348-46cf-930a-0e530b7588c3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030311152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1030311152
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.558676268
Short name T283
Test name
Test status
Simulation time 83728666592 ps
CPU time 449.32 seconds
Started Aug 13 05:15:28 PM PDT 24
Finished Aug 13 05:22:57 PM PDT 24
Peak memory 200860 kb
Host smart-aa0c75c3-8b85-4305-8571-4275037d0d1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=558676268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.558676268
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1510092209
Short name T514
Test name
Test status
Simulation time 11607434973 ps
CPU time 13.53 seconds
Started Aug 13 05:15:26 PM PDT 24
Finished Aug 13 05:15:40 PM PDT 24
Peak memory 200828 kb
Host smart-27f26bf2-058a-4f71-a09f-cdbc4505f52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510092209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1510092209
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3512283057
Short name T304
Test name
Test status
Simulation time 48195327296 ps
CPU time 74.73 seconds
Started Aug 13 05:15:28 PM PDT 24
Finished Aug 13 05:16:43 PM PDT 24
Peak memory 201016 kb
Host smart-d9c9a3b4-d48f-4a02-9976-3bad8cfd6a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512283057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3512283057
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.4135516674
Short name T300
Test name
Test status
Simulation time 12094321195 ps
CPU time 685.79 seconds
Started Aug 13 05:15:30 PM PDT 24
Finished Aug 13 05:26:56 PM PDT 24
Peak memory 200792 kb
Host smart-7da3f786-bfdc-4a8c-a4fa-67e3fc4e5360
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4135516674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.4135516674
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.618260039
Short name T7
Test name
Test status
Simulation time 4786767063 ps
CPU time 45.58 seconds
Started Aug 13 05:15:27 PM PDT 24
Finished Aug 13 05:16:13 PM PDT 24
Peak memory 200100 kb
Host smart-71f768fc-eba2-4126-a730-6722b33e4fe0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=618260039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.618260039
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2183867483
Short name T456
Test name
Test status
Simulation time 101600391856 ps
CPU time 82.93 seconds
Started Aug 13 05:15:29 PM PDT 24
Finished Aug 13 05:16:52 PM PDT 24
Peak memory 200880 kb
Host smart-3c9a36e2-c163-43ed-9cf4-44217371e66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183867483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2183867483
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.187180212
Short name T388
Test name
Test status
Simulation time 3910496030 ps
CPU time 2.35 seconds
Started Aug 13 05:15:29 PM PDT 24
Finished Aug 13 05:15:31 PM PDT 24
Peak memory 197788 kb
Host smart-338c0357-e121-4038-9599-77d8045cfd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187180212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.187180212
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1468307838
Short name T393
Test name
Test status
Simulation time 488395834 ps
CPU time 1.16 seconds
Started Aug 13 05:15:27 PM PDT 24
Finished Aug 13 05:15:28 PM PDT 24
Peak memory 199612 kb
Host smart-aedcd8a3-2634-487e-b6d3-7fa1d76b0d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468307838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1468307838
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.1990329968
Short name T1115
Test name
Test status
Simulation time 148333558972 ps
CPU time 61.66 seconds
Started Aug 13 05:15:27 PM PDT 24
Finished Aug 13 05:16:29 PM PDT 24
Peak memory 201144 kb
Host smart-8cbb8789-c694-4314-9856-a288bb776a29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990329968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1990329968
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1631842677
Short name T31
Test name
Test status
Simulation time 4628763020 ps
CPU time 60.9 seconds
Started Aug 13 05:15:28 PM PDT 24
Finished Aug 13 05:16:29 PM PDT 24
Peak memory 209036 kb
Host smart-f3ffc894-8ff2-43cb-a71d-08a7a8feaee1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631842677 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1631842677
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3917031653
Short name T784
Test name
Test status
Simulation time 1966638040 ps
CPU time 2.67 seconds
Started Aug 13 05:15:29 PM PDT 24
Finished Aug 13 05:15:32 PM PDT 24
Peak memory 200512 kb
Host smart-c6430275-d469-4dcd-b9d4-528eddda57db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917031653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3917031653
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.867009023
Short name T349
Test name
Test status
Simulation time 3291566563 ps
CPU time 2.04 seconds
Started Aug 13 05:15:30 PM PDT 24
Finished Aug 13 05:15:32 PM PDT 24
Peak memory 197992 kb
Host smart-ec58b76c-3238-457b-a88f-e74bd01b922b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867009023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.867009023
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.28070036
Short name T367
Test name
Test status
Simulation time 25859868 ps
CPU time 0.56 seconds
Started Aug 13 05:15:40 PM PDT 24
Finished Aug 13 05:15:41 PM PDT 24
Peak memory 196176 kb
Host smart-dc8a2172-8f35-47cd-8bf1-ad9212580164
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28070036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.28070036
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.1987236655
Short name T962
Test name
Test status
Simulation time 108309780907 ps
CPU time 24.02 seconds
Started Aug 13 05:15:29 PM PDT 24
Finished Aug 13 05:15:53 PM PDT 24
Peak memory 200868 kb
Host smart-348c7adf-2ac7-427f-a0ad-d90ae28c53b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987236655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1987236655
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.146312943
Short name T122
Test name
Test status
Simulation time 63104730515 ps
CPU time 99.49 seconds
Started Aug 13 05:15:29 PM PDT 24
Finished Aug 13 05:17:08 PM PDT 24
Peak memory 200940 kb
Host smart-472f545f-87c7-45fb-805b-61fce71f1c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146312943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.146312943
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1672648163
Short name T846
Test name
Test status
Simulation time 29561228765 ps
CPU time 13.29 seconds
Started Aug 13 05:15:30 PM PDT 24
Finished Aug 13 05:15:44 PM PDT 24
Peak memory 200860 kb
Host smart-c7f29a5c-8167-4ff1-9a84-5932d2a3bb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672648163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1672648163
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2938720690
Short name T644
Test name
Test status
Simulation time 15674468707 ps
CPU time 24.72 seconds
Started Aug 13 05:15:38 PM PDT 24
Finished Aug 13 05:16:03 PM PDT 24
Peak memory 197900 kb
Host smart-7a4107b2-e1f3-474a-9a23-ea16b25605f6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938720690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2938720690
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2402100744
Short name T708
Test name
Test status
Simulation time 113543556047 ps
CPU time 202.07 seconds
Started Aug 13 05:15:40 PM PDT 24
Finished Aug 13 05:19:02 PM PDT 24
Peak memory 200948 kb
Host smart-8751d36e-b907-476e-9589-bf9558774930
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2402100744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2402100744
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2043953070
Short name T526
Test name
Test status
Simulation time 199332177 ps
CPU time 1.4 seconds
Started Aug 13 05:15:40 PM PDT 24
Finished Aug 13 05:15:42 PM PDT 24
Peak memory 198780 kb
Host smart-372582e5-b8af-4e6b-9b74-e53cf0f9cfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043953070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2043953070
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.3787771233
Short name T763
Test name
Test status
Simulation time 50593918181 ps
CPU time 33.67 seconds
Started Aug 13 05:15:39 PM PDT 24
Finished Aug 13 05:16:13 PM PDT 24
Peak memory 201124 kb
Host smart-bec2c8bf-1f00-4bcd-ae35-58b2f7507c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787771233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3787771233
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.1136866631
Short name T494
Test name
Test status
Simulation time 6775199705 ps
CPU time 398.03 seconds
Started Aug 13 05:15:39 PM PDT 24
Finished Aug 13 05:22:18 PM PDT 24
Peak memory 200752 kb
Host smart-dfac2766-8b94-4cb1-8a3e-4367918c9a6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1136866631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1136866631
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3485568666
Short name T385
Test name
Test status
Simulation time 1915639082 ps
CPU time 13.24 seconds
Started Aug 13 05:15:30 PM PDT 24
Finished Aug 13 05:15:43 PM PDT 24
Peak memory 198988 kb
Host smart-f10bdf3f-e1b4-4dc7-b61f-9867875ab9e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3485568666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3485568666
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.322127176
Short name T886
Test name
Test status
Simulation time 154730517502 ps
CPU time 118.71 seconds
Started Aug 13 05:15:41 PM PDT 24
Finished Aug 13 05:17:40 PM PDT 24
Peak memory 200848 kb
Host smart-3db6ba26-eb35-4264-95cd-143a49babec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322127176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.322127176
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.2693091294
Short name T793
Test name
Test status
Simulation time 4743762044 ps
CPU time 2.59 seconds
Started Aug 13 05:15:38 PM PDT 24
Finished Aug 13 05:15:41 PM PDT 24
Peak memory 197244 kb
Host smart-978ca708-7873-485b-929d-c7842f07bade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693091294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2693091294
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.2473594430
Short name T891
Test name
Test status
Simulation time 457497147 ps
CPU time 1.18 seconds
Started Aug 13 05:15:27 PM PDT 24
Finished Aug 13 05:15:29 PM PDT 24
Peak memory 199540 kb
Host smart-cfa52223-10da-4422-947b-6d24c64ffd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473594430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2473594430
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.4152817608
Short name T712
Test name
Test status
Simulation time 84947471041 ps
CPU time 164.62 seconds
Started Aug 13 05:15:39 PM PDT 24
Finished Aug 13 05:18:24 PM PDT 24
Peak memory 209160 kb
Host smart-58318cda-9b55-489c-9422-80b311b4fa5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152817608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.4152817608
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1112413785
Short name T88
Test name
Test status
Simulation time 3712693745 ps
CPU time 18.77 seconds
Started Aug 13 05:15:39 PM PDT 24
Finished Aug 13 05:15:58 PM PDT 24
Peak memory 200992 kb
Host smart-57f12849-7f3b-42cc-9dcb-dfc0fa18fc95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112413785 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1112413785
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1740241934
Short name T652
Test name
Test status
Simulation time 3801195707 ps
CPU time 1.94 seconds
Started Aug 13 05:15:38 PM PDT 24
Finished Aug 13 05:15:40 PM PDT 24
Peak memory 200032 kb
Host smart-334b7b01-c0d3-42dd-822c-e85722de5f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740241934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1740241934
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.732741161
Short name T505
Test name
Test status
Simulation time 9289548272 ps
CPU time 14.3 seconds
Started Aug 13 05:15:30 PM PDT 24
Finished Aug 13 05:15:44 PM PDT 24
Peak memory 200880 kb
Host smart-11929072-9452-40a3-acfc-3bcb7cd206b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732741161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.732741161
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.1208970291
Short name T405
Test name
Test status
Simulation time 36250373 ps
CPU time 0.54 seconds
Started Aug 13 05:15:38 PM PDT 24
Finished Aug 13 05:15:39 PM PDT 24
Peak memory 196188 kb
Host smart-67017762-703a-47fa-8992-d54abd81b38d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208970291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1208970291
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3780689043
Short name T266
Test name
Test status
Simulation time 144247021747 ps
CPU time 101.64 seconds
Started Aug 13 05:15:38 PM PDT 24
Finished Aug 13 05:17:20 PM PDT 24
Peak memory 200924 kb
Host smart-da2ba99c-5062-4bac-be59-1d393a1cec13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780689043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3780689043
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.821946633
Short name T574
Test name
Test status
Simulation time 185020261342 ps
CPU time 63.87 seconds
Started Aug 13 05:15:40 PM PDT 24
Finished Aug 13 05:16:45 PM PDT 24
Peak memory 200868 kb
Host smart-d2215184-4c5c-4cd2-a89e-b37581eed911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821946633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.821946633
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.4231936984
Short name T1058
Test name
Test status
Simulation time 18327179679 ps
CPU time 14.99 seconds
Started Aug 13 05:15:37 PM PDT 24
Finished Aug 13 05:15:52 PM PDT 24
Peak memory 200880 kb
Host smart-9f6f8942-a2a1-4cfe-b43b-123157841d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231936984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.4231936984
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3581191761
Short name T296
Test name
Test status
Simulation time 156949651417 ps
CPU time 130.63 seconds
Started Aug 13 05:15:40 PM PDT 24
Finished Aug 13 05:17:51 PM PDT 24
Peak memory 200588 kb
Host smart-23119863-962d-4806-ba8e-b8bb546d57ab
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581191761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3581191761
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1601044893
Short name T952
Test name
Test status
Simulation time 96822834825 ps
CPU time 276.03 seconds
Started Aug 13 05:15:39 PM PDT 24
Finished Aug 13 05:20:16 PM PDT 24
Peak memory 200920 kb
Host smart-2298310c-c802-4082-a376-aa7fcdaf39d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1601044893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1601044893
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.3909646058
Short name T459
Test name
Test status
Simulation time 11665009624 ps
CPU time 20.41 seconds
Started Aug 13 05:15:39 PM PDT 24
Finished Aug 13 05:16:00 PM PDT 24
Peak memory 200904 kb
Host smart-95cc9728-0a14-4147-b848-537667e2e580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909646058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3909646058
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.756704724
Short name T326
Test name
Test status
Simulation time 48252787808 ps
CPU time 42.1 seconds
Started Aug 13 05:15:39 PM PDT 24
Finished Aug 13 05:16:21 PM PDT 24
Peak memory 209184 kb
Host smart-fba93259-977a-43e2-b474-11e3b5eb6304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756704724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.756704724
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.1805623091
Short name T817
Test name
Test status
Simulation time 9018590180 ps
CPU time 81.57 seconds
Started Aug 13 05:15:40 PM PDT 24
Finished Aug 13 05:17:02 PM PDT 24
Peak memory 200932 kb
Host smart-cd30b455-78a8-4295-ad5a-69e8ca501161
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1805623091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1805623091
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.1095347133
Short name T605
Test name
Test status
Simulation time 1929184669 ps
CPU time 2.77 seconds
Started Aug 13 05:15:39 PM PDT 24
Finished Aug 13 05:15:42 PM PDT 24
Peak memory 198304 kb
Host smart-09a1080a-afc0-487f-88f6-eb7725cc367a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1095347133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1095347133
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.634956302
Short name T511
Test name
Test status
Simulation time 78150695438 ps
CPU time 30.1 seconds
Started Aug 13 05:15:38 PM PDT 24
Finished Aug 13 05:16:08 PM PDT 24
Peak memory 200652 kb
Host smart-fb1ac55f-2e7e-4791-8298-8f9aad468e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634956302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.634956302
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2793824225
Short name T963
Test name
Test status
Simulation time 1917032176 ps
CPU time 1.39 seconds
Started Aug 13 05:15:39 PM PDT 24
Finished Aug 13 05:15:40 PM PDT 24
Peak memory 196556 kb
Host smart-2b164ccd-0be8-40ec-93a8-d53604e1c67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793824225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2793824225
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2381855465
Short name T450
Test name
Test status
Simulation time 716455692 ps
CPU time 2.5 seconds
Started Aug 13 05:15:38 PM PDT 24
Finished Aug 13 05:15:41 PM PDT 24
Peak memory 200784 kb
Host smart-e71afcef-0d9f-45b9-ad8a-b2a8352273fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381855465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2381855465
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.181220811
Short name T485
Test name
Test status
Simulation time 3087227635 ps
CPU time 1.1 seconds
Started Aug 13 05:15:40 PM PDT 24
Finished Aug 13 05:15:41 PM PDT 24
Peak memory 199168 kb
Host smart-77167147-5beb-4026-b22f-222ba34ce96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181220811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.181220811
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2772961702
Short name T1184
Test name
Test status
Simulation time 48517341546 ps
CPU time 7.79 seconds
Started Aug 13 05:15:40 PM PDT 24
Finished Aug 13 05:15:48 PM PDT 24
Peak memory 200880 kb
Host smart-3c9508f2-cdcd-4099-bee9-69f35e58b9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772961702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2772961702
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.3478236301
Short name T483
Test name
Test status
Simulation time 35790881 ps
CPU time 0.52 seconds
Started Aug 13 05:15:46 PM PDT 24
Finished Aug 13 05:15:47 PM PDT 24
Peak memory 196400 kb
Host smart-91b93c3e-b8fc-477e-a04d-5dfbcd144d7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478236301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3478236301
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.4123520883
Short name T117
Test name
Test status
Simulation time 98965442716 ps
CPU time 134.36 seconds
Started Aug 13 05:15:38 PM PDT 24
Finished Aug 13 05:17:53 PM PDT 24
Peak memory 200928 kb
Host smart-61886355-4e39-4664-9826-7ca683ac62c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123520883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.4123520883
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.1277523233
Short name T1054
Test name
Test status
Simulation time 153002807422 ps
CPU time 114.68 seconds
Started Aug 13 05:15:39 PM PDT 24
Finished Aug 13 05:17:34 PM PDT 24
Peak memory 200924 kb
Host smart-8c0c0752-82b0-4e35-93fd-d6d3dc89546a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277523233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1277523233
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.3175730624
Short name T815
Test name
Test status
Simulation time 111689286733 ps
CPU time 225.42 seconds
Started Aug 13 05:15:39 PM PDT 24
Finished Aug 13 05:19:25 PM PDT 24
Peak memory 200876 kb
Host smart-d9596f0e-6a72-4950-934e-8150e962514c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175730624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3175730624
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1493974425
Short name T774
Test name
Test status
Simulation time 22596715679 ps
CPU time 9.07 seconds
Started Aug 13 05:15:40 PM PDT 24
Finished Aug 13 05:15:50 PM PDT 24
Peak memory 198620 kb
Host smart-c88e8a12-c6d7-4caa-9174-8224bfb0ab87
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493974425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1493974425
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.3914445362
Short name T496
Test name
Test status
Simulation time 214010102866 ps
CPU time 347.8 seconds
Started Aug 13 05:15:46 PM PDT 24
Finished Aug 13 05:21:34 PM PDT 24
Peak memory 200924 kb
Host smart-2e2a24a9-3029-4e9d-b826-c803f6b79dff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3914445362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3914445362
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.907937478
Short name T498
Test name
Test status
Simulation time 5848487197 ps
CPU time 11.6 seconds
Started Aug 13 05:15:59 PM PDT 24
Finished Aug 13 05:16:11 PM PDT 24
Peak memory 200292 kb
Host smart-3f252cd9-ce08-47e5-a15b-ee5cf954901b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907937478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.907937478
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.818328040
Short name T1136
Test name
Test status
Simulation time 11629522694 ps
CPU time 10.28 seconds
Started Aug 13 05:15:38 PM PDT 24
Finished Aug 13 05:15:49 PM PDT 24
Peak memory 200860 kb
Host smart-d86d93b9-7771-4f24-85a2-7d2b490ba966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818328040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.818328040
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.529809073
Short name T893
Test name
Test status
Simulation time 13174462599 ps
CPU time 183.17 seconds
Started Aug 13 05:15:45 PM PDT 24
Finished Aug 13 05:18:48 PM PDT 24
Peak memory 200924 kb
Host smart-403fbba2-a7e5-44ee-8b9d-091003fc4236
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=529809073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.529809073
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.2249029708
Short name T725
Test name
Test status
Simulation time 4329080559 ps
CPU time 5.6 seconds
Started Aug 13 05:15:38 PM PDT 24
Finished Aug 13 05:15:44 PM PDT 24
Peak memory 200004 kb
Host smart-715e363d-46e4-4176-b58b-f3ca5215384e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2249029708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2249029708
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2451738534
Short name T274
Test name
Test status
Simulation time 122550711101 ps
CPU time 51.54 seconds
Started Aug 13 05:15:40 PM PDT 24
Finished Aug 13 05:16:31 PM PDT 24
Peak memory 200792 kb
Host smart-71e387bf-5fc8-444f-89cf-1944dcc4a76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451738534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2451738534
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.2008739803
Short name T1163
Test name
Test status
Simulation time 2957130384 ps
CPU time 4.93 seconds
Started Aug 13 05:15:41 PM PDT 24
Finished Aug 13 05:15:46 PM PDT 24
Peak memory 197392 kb
Host smart-8c5698e3-6154-4582-8ebe-082978f79273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008739803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2008739803
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.800218283
Short name T940
Test name
Test status
Simulation time 889933247 ps
CPU time 4.51 seconds
Started Aug 13 05:15:39 PM PDT 24
Finished Aug 13 05:15:43 PM PDT 24
Peak memory 199900 kb
Host smart-cc959f41-ff1d-4209-939b-947af9eaa105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800218283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.800218283
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.326457076
Short name T556
Test name
Test status
Simulation time 60870765775 ps
CPU time 90.34 seconds
Started Aug 13 05:16:01 PM PDT 24
Finished Aug 13 05:17:31 PM PDT 24
Peak memory 201060 kb
Host smart-2cb528e5-828f-4f45-beb2-520933a129c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326457076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.326457076
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1231984116
Short name T618
Test name
Test status
Simulation time 20033983259 ps
CPU time 98.2 seconds
Started Aug 13 05:15:48 PM PDT 24
Finished Aug 13 05:17:26 PM PDT 24
Peak memory 217220 kb
Host smart-53958a4b-7600-4d7b-8d03-d35a9a1295fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231984116 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1231984116
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.819803258
Short name T1142
Test name
Test status
Simulation time 1391267973 ps
CPU time 1.94 seconds
Started Aug 13 05:15:46 PM PDT 24
Finished Aug 13 05:15:48 PM PDT 24
Peak memory 199388 kb
Host smart-89dd2427-c9f0-451e-9767-a82d609da311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819803258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.819803258
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1822501975
Short name T632
Test name
Test status
Simulation time 39152750035 ps
CPU time 80.53 seconds
Started Aug 13 05:15:37 PM PDT 24
Finished Aug 13 05:16:58 PM PDT 24
Peak memory 200892 kb
Host smart-a24f3d4b-12b5-42f6-84dd-64ff20dcfa9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822501975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1822501975
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.2478873238
Short name T1105
Test name
Test status
Simulation time 34271580 ps
CPU time 0.53 seconds
Started Aug 13 05:13:47 PM PDT 24
Finished Aug 13 05:13:48 PM PDT 24
Peak memory 196244 kb
Host smart-463f48f8-29f2-418a-befa-034ec683eb6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478873238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2478873238
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2605486031
Short name T292
Test name
Test status
Simulation time 122402860483 ps
CPU time 248.08 seconds
Started Aug 13 05:13:46 PM PDT 24
Finished Aug 13 05:17:55 PM PDT 24
Peak memory 200872 kb
Host smart-ced0e518-6db2-45d8-b916-a0191b050c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605486031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2605486031
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1235364285
Short name T938
Test name
Test status
Simulation time 43908595239 ps
CPU time 63.19 seconds
Started Aug 13 05:13:49 PM PDT 24
Finished Aug 13 05:14:53 PM PDT 24
Peak memory 200928 kb
Host smart-c29bb65f-ec71-4de1-a0fd-36d45df7e2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235364285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1235364285
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.787139960
Short name T684
Test name
Test status
Simulation time 77608567937 ps
CPU time 27.19 seconds
Started Aug 13 05:13:47 PM PDT 24
Finished Aug 13 05:14:14 PM PDT 24
Peak memory 199832 kb
Host smart-3eba04d6-7b4e-4732-b967-a5c7628e5140
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787139960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.787139960
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3156008591
Short name T466
Test name
Test status
Simulation time 76181408789 ps
CPU time 650.93 seconds
Started Aug 13 05:13:51 PM PDT 24
Finished Aug 13 05:24:43 PM PDT 24
Peak memory 200948 kb
Host smart-756c151e-9907-424a-9f1c-ed0056284363
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3156008591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3156008591
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.575945168
Short name T368
Test name
Test status
Simulation time 2917259400 ps
CPU time 4.69 seconds
Started Aug 13 05:13:51 PM PDT 24
Finished Aug 13 05:13:56 PM PDT 24
Peak memory 196760 kb
Host smart-5923dc7d-7e9a-4f1a-976e-37912009dd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575945168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.575945168
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.387380369
Short name T978
Test name
Test status
Simulation time 76083238957 ps
CPU time 64.23 seconds
Started Aug 13 05:13:49 PM PDT 24
Finished Aug 13 05:14:53 PM PDT 24
Peak memory 209280 kb
Host smart-9b31da3b-7af7-4b77-a990-4a6383a39448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387380369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.387380369
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.1262116359
Short name T462
Test name
Test status
Simulation time 4689473068 ps
CPU time 31.34 seconds
Started Aug 13 05:13:50 PM PDT 24
Finished Aug 13 05:14:21 PM PDT 24
Peak memory 200812 kb
Host smart-a65c654e-bd7c-4203-8f29-4b5e1c3dc70f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1262116359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1262116359
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2214239939
Short name T1128
Test name
Test status
Simulation time 5825763994 ps
CPU time 5.27 seconds
Started Aug 13 05:13:45 PM PDT 24
Finished Aug 13 05:13:50 PM PDT 24
Peak memory 199000 kb
Host smart-33d4665e-5721-4784-a82b-00b17d57eb1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2214239939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2214239939
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1010047984
Short name T691
Test name
Test status
Simulation time 4493878809 ps
CPU time 2.64 seconds
Started Aug 13 05:13:48 PM PDT 24
Finished Aug 13 05:13:50 PM PDT 24
Peak memory 199444 kb
Host smart-00a25a9e-4636-4442-a872-aea5ff5192f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010047984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1010047984
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.448327699
Short name T497
Test name
Test status
Simulation time 2033293328 ps
CPU time 4.04 seconds
Started Aug 13 05:13:47 PM PDT 24
Finished Aug 13 05:13:51 PM PDT 24
Peak memory 196308 kb
Host smart-42fbf14a-0a47-4de9-a550-2bb6819bfeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448327699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.448327699
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2713004926
Short name T26
Test name
Test status
Simulation time 644889269 ps
CPU time 0.82 seconds
Started Aug 13 05:13:45 PM PDT 24
Finished Aug 13 05:13:46 PM PDT 24
Peak memory 218844 kb
Host smart-cbc2b45e-c647-44a8-af4c-6d5c3f27cfb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713004926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2713004926
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.2033661723
Short name T882
Test name
Test status
Simulation time 913131802 ps
CPU time 1.64 seconds
Started Aug 13 05:13:48 PM PDT 24
Finished Aug 13 05:13:50 PM PDT 24
Peak memory 199292 kb
Host smart-16b7d772-5489-443b-a7cf-6ab8733b6522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033661723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2033661723
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2283328696
Short name T530
Test name
Test status
Simulation time 300893875505 ps
CPU time 506.88 seconds
Started Aug 13 05:13:45 PM PDT 24
Finished Aug 13 05:22:12 PM PDT 24
Peak memory 200916 kb
Host smart-cea5b84d-f05b-4c89-ac37-c6d6fcfb5bd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283328696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2283328696
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.854543883
Short name T622
Test name
Test status
Simulation time 4534105601 ps
CPU time 64.78 seconds
Started Aug 13 05:13:48 PM PDT 24
Finished Aug 13 05:14:53 PM PDT 24
Peak memory 217548 kb
Host smart-8a6b2343-71f2-41d7-becc-ce0eb1038d09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854543883 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.854543883
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3313374226
Short name T1029
Test name
Test status
Simulation time 387392012 ps
CPU time 1.52 seconds
Started Aug 13 05:13:49 PM PDT 24
Finished Aug 13 05:13:51 PM PDT 24
Peak memory 198860 kb
Host smart-41d62a0b-3854-47d8-9016-7302fc031beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313374226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3313374226
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3547110008
Short name T517
Test name
Test status
Simulation time 6279796171 ps
CPU time 10.87 seconds
Started Aug 13 05:13:47 PM PDT 24
Finished Aug 13 05:13:58 PM PDT 24
Peak memory 199936 kb
Host smart-9cf7245e-5871-4d2d-bf3d-78564cd832ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547110008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3547110008
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.3961941388
Short name T975
Test name
Test status
Simulation time 42153451 ps
CPU time 0.54 seconds
Started Aug 13 05:15:44 PM PDT 24
Finished Aug 13 05:15:45 PM PDT 24
Peak memory 196256 kb
Host smart-bc54f595-3d62-4b9c-bc4d-9564469e9ba9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961941388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3961941388
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.1918937306
Short name T132
Test name
Test status
Simulation time 127126393218 ps
CPU time 35.62 seconds
Started Aug 13 05:15:44 PM PDT 24
Finished Aug 13 05:16:20 PM PDT 24
Peak memory 200788 kb
Host smart-823692ba-13b0-4801-b14f-695d138ab30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918937306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1918937306
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2822905076
Short name T598
Test name
Test status
Simulation time 84208440304 ps
CPU time 140.33 seconds
Started Aug 13 05:15:43 PM PDT 24
Finished Aug 13 05:18:04 PM PDT 24
Peak memory 200876 kb
Host smart-02b6dfa5-47a1-4993-abf8-e3c02d1aea42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822905076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2822905076
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.2943816433
Short name T853
Test name
Test status
Simulation time 16507618094 ps
CPU time 23.7 seconds
Started Aug 13 05:15:48 PM PDT 24
Finished Aug 13 05:16:12 PM PDT 24
Peak memory 200916 kb
Host smart-3b1b8d24-dd21-429d-bb64-e96ef56da582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943816433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2943816433
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3391852964
Short name T449
Test name
Test status
Simulation time 53130255483 ps
CPU time 55.84 seconds
Started Aug 13 05:15:43 PM PDT 24
Finished Aug 13 05:16:39 PM PDT 24
Peak memory 200768 kb
Host smart-09d997a6-0807-4318-b297-3f72e109f1af
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391852964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3391852964
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2075087928
Short name T1049
Test name
Test status
Simulation time 85516843734 ps
CPU time 115.99 seconds
Started Aug 13 05:15:45 PM PDT 24
Finished Aug 13 05:17:42 PM PDT 24
Peak memory 200852 kb
Host smart-9f6c5fd4-729a-4f4f-8a92-dd2ec60b76ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2075087928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2075087928
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3634745594
Short name T603
Test name
Test status
Simulation time 8837789753 ps
CPU time 14.3 seconds
Started Aug 13 05:15:45 PM PDT 24
Finished Aug 13 05:16:00 PM PDT 24
Peak memory 200856 kb
Host smart-4c8b5a54-0185-4100-8524-e1aa36873a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634745594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3634745594
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.2291730538
Short name T288
Test name
Test status
Simulation time 62457177508 ps
CPU time 102.84 seconds
Started Aug 13 05:15:44 PM PDT 24
Finished Aug 13 05:17:27 PM PDT 24
Peak memory 209252 kb
Host smart-20a1c454-c82b-47c8-b98d-2d66feb7ec82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291730538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2291730538
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.2715576574
Short name T981
Test name
Test status
Simulation time 16099937283 ps
CPU time 968.84 seconds
Started Aug 13 05:15:49 PM PDT 24
Finished Aug 13 05:31:58 PM PDT 24
Peak memory 200916 kb
Host smart-c07cccbb-0d70-43bc-a596-dee1f9a61ce0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2715576574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2715576574
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.2728746397
Short name T401
Test name
Test status
Simulation time 4734248896 ps
CPU time 44.49 seconds
Started Aug 13 05:15:46 PM PDT 24
Finished Aug 13 05:16:31 PM PDT 24
Peak memory 198688 kb
Host smart-854824bb-8785-4187-ad5c-7a3452141aa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2728746397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2728746397
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.453269653
Short name T1000
Test name
Test status
Simulation time 11734839012 ps
CPU time 19.84 seconds
Started Aug 13 05:15:46 PM PDT 24
Finished Aug 13 05:16:06 PM PDT 24
Peak memory 200112 kb
Host smart-183f3a6e-b6a1-4606-9811-034266d6fafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453269653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.453269653
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.323681071
Short name T923
Test name
Test status
Simulation time 4781787739 ps
CPU time 8.24 seconds
Started Aug 13 05:15:49 PM PDT 24
Finished Aug 13 05:15:58 PM PDT 24
Peak memory 197396 kb
Host smart-0e920be5-f163-4e4e-b2f3-da527a43c21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323681071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.323681071
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3529494546
Short name T838
Test name
Test status
Simulation time 494420728 ps
CPU time 2.93 seconds
Started Aug 13 05:15:43 PM PDT 24
Finished Aug 13 05:15:46 PM PDT 24
Peak memory 199932 kb
Host smart-954a0733-dd27-4752-bf48-390b41f07a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529494546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3529494546
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.3911617359
Short name T1093
Test name
Test status
Simulation time 241192215722 ps
CPU time 1062.38 seconds
Started Aug 13 05:15:45 PM PDT 24
Finished Aug 13 05:33:27 PM PDT 24
Peak memory 209344 kb
Host smart-650e3308-1a0a-4747-84b8-414ff37233c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911617359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3911617359
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3105644806
Short name T807
Test name
Test status
Simulation time 4889368433 ps
CPU time 15.61 seconds
Started Aug 13 05:15:45 PM PDT 24
Finished Aug 13 05:16:01 PM PDT 24
Peak memory 217068 kb
Host smart-a6d09d12-09af-4008-9fd8-1ba1381fc4da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105644806 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3105644806
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.4141115538
Short name T81
Test name
Test status
Simulation time 2554825192 ps
CPU time 1.59 seconds
Started Aug 13 05:15:44 PM PDT 24
Finished Aug 13 05:15:46 PM PDT 24
Peak memory 198236 kb
Host smart-89229456-b48f-48fb-92b4-89ddb3c6a6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141115538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.4141115538
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1952617683
Short name T766
Test name
Test status
Simulation time 16637280441 ps
CPU time 14.18 seconds
Started Aug 13 05:15:45 PM PDT 24
Finished Aug 13 05:15:59 PM PDT 24
Peak memory 200636 kb
Host smart-23dc0cf1-1e14-49ac-b6a9-68a61b75ab29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952617683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1952617683
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2335072815
Short name T1172
Test name
Test status
Simulation time 34519304 ps
CPU time 0.56 seconds
Started Aug 13 05:15:59 PM PDT 24
Finished Aug 13 05:15:59 PM PDT 24
Peak memory 196240 kb
Host smart-bab9f6ee-2699-43b0-9325-8399b6576c6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335072815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2335072815
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.4093123518
Short name T682
Test name
Test status
Simulation time 36420244991 ps
CPU time 34.3 seconds
Started Aug 13 05:15:45 PM PDT 24
Finished Aug 13 05:16:20 PM PDT 24
Peak memory 200864 kb
Host smart-93d4768b-16f7-43f7-a545-364a160c25ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093123518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.4093123518
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3596732876
Short name T647
Test name
Test status
Simulation time 18664664570 ps
CPU time 31.22 seconds
Started Aug 13 05:15:59 PM PDT 24
Finished Aug 13 05:16:30 PM PDT 24
Peak memory 200920 kb
Host smart-6ebd8325-59ef-4c69-b62c-be8d04356014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596732876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3596732876
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3486387637
Short name T1087
Test name
Test status
Simulation time 138459465652 ps
CPU time 20.63 seconds
Started Aug 13 05:15:59 PM PDT 24
Finished Aug 13 05:16:20 PM PDT 24
Peak memory 200940 kb
Host smart-1e155b67-dac3-4109-9197-0656efb9348e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486387637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3486387637
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2520691896
Short name T777
Test name
Test status
Simulation time 9234059594 ps
CPU time 22.78 seconds
Started Aug 13 05:15:45 PM PDT 24
Finished Aug 13 05:16:08 PM PDT 24
Peak memory 200652 kb
Host smart-2fe77fb5-5d96-42ed-b3db-260dca7a9ac0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520691896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2520691896
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.2399004891
Short name T1176
Test name
Test status
Simulation time 93312785956 ps
CPU time 823.16 seconds
Started Aug 13 05:15:44 PM PDT 24
Finished Aug 13 05:29:27 PM PDT 24
Peak memory 200956 kb
Host smart-e58f6bb0-83cc-4957-bf52-ca77c345fc8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2399004891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2399004891
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.4107249258
Short name T730
Test name
Test status
Simulation time 5501616048 ps
CPU time 2.03 seconds
Started Aug 13 05:15:44 PM PDT 24
Finished Aug 13 05:15:46 PM PDT 24
Peak memory 199688 kb
Host smart-3b350d14-ef89-4b84-bab6-e0855d631b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107249258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.4107249258
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.1415726698
Short name T711
Test name
Test status
Simulation time 52858426553 ps
CPU time 90.51 seconds
Started Aug 13 05:15:48 PM PDT 24
Finished Aug 13 05:17:18 PM PDT 24
Peak memory 200988 kb
Host smart-1e290c1d-2dc8-488f-8f8a-28b5c5fb885a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415726698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1415726698
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3198110732
Short name T557
Test name
Test status
Simulation time 14602256737 ps
CPU time 404.49 seconds
Started Aug 13 05:15:45 PM PDT 24
Finished Aug 13 05:22:30 PM PDT 24
Peak memory 200912 kb
Host smart-de59fa67-c8d2-4d1d-9ff6-f735f8352cea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3198110732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3198110732
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3790964408
Short name T568
Test name
Test status
Simulation time 5340774226 ps
CPU time 10.7 seconds
Started Aug 13 05:15:45 PM PDT 24
Finished Aug 13 05:15:56 PM PDT 24
Peak memory 200412 kb
Host smart-98aa734d-c052-4f32-8d32-8454b819af6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3790964408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3790964408
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.1723157998
Short name T1108
Test name
Test status
Simulation time 26895867400 ps
CPU time 20.67 seconds
Started Aug 13 05:15:44 PM PDT 24
Finished Aug 13 05:16:04 PM PDT 24
Peak memory 200900 kb
Host smart-ce02054a-10c5-43df-ad35-d63ed089a8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723157998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1723157998
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3735894278
Short name T665
Test name
Test status
Simulation time 6696860499 ps
CPU time 10.91 seconds
Started Aug 13 05:15:46 PM PDT 24
Finished Aug 13 05:15:57 PM PDT 24
Peak memory 197224 kb
Host smart-3cb7c1a6-2e09-4108-9eb0-9229a087c521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735894278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3735894278
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2346789661
Short name T932
Test name
Test status
Simulation time 5531955126 ps
CPU time 9.4 seconds
Started Aug 13 05:15:45 PM PDT 24
Finished Aug 13 05:15:55 PM PDT 24
Peak memory 200364 kb
Host smart-c02b720c-9aec-42ea-a89d-c301fea504e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346789661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2346789661
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.3981213115
Short name T914
Test name
Test status
Simulation time 610949659333 ps
CPU time 255.51 seconds
Started Aug 13 05:15:46 PM PDT 24
Finished Aug 13 05:20:02 PM PDT 24
Peak memory 200896 kb
Host smart-a3e91d1f-fcc3-4fcc-ad58-cea7ec919573
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981213115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3981213115
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.1246828561
Short name T908
Test name
Test status
Simulation time 16440372892 ps
CPU time 49.01 seconds
Started Aug 13 05:15:48 PM PDT 24
Finished Aug 13 05:16:37 PM PDT 24
Peak memory 211164 kb
Host smart-e32910ef-605c-43f7-a89f-606e1638f981
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246828561 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.1246828561
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.4177948122
Short name T667
Test name
Test status
Simulation time 6439205626 ps
CPU time 23.95 seconds
Started Aug 13 05:15:44 PM PDT 24
Finished Aug 13 05:16:08 PM PDT 24
Peak memory 200740 kb
Host smart-d6945dc9-d215-4091-978b-715424292bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177948122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.4177948122
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1834602092
Short name T906
Test name
Test status
Simulation time 193585479670 ps
CPU time 35.66 seconds
Started Aug 13 05:15:49 PM PDT 24
Finished Aug 13 05:16:25 PM PDT 24
Peak memory 200908 kb
Host smart-7ec30e1f-7a65-4157-b1ed-e086256ad6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834602092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1834602092
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.4112027365
Short name T762
Test name
Test status
Simulation time 14983401 ps
CPU time 0.56 seconds
Started Aug 13 05:15:49 PM PDT 24
Finished Aug 13 05:15:50 PM PDT 24
Peak memory 196432 kb
Host smart-ee7afe8a-d239-4e9f-b37f-986ce2b23a21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112027365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.4112027365
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2531940598
Short name T1090
Test name
Test status
Simulation time 227861363266 ps
CPU time 95.66 seconds
Started Aug 13 05:15:45 PM PDT 24
Finished Aug 13 05:17:21 PM PDT 24
Peak memory 200928 kb
Host smart-30440a70-4d29-4f44-a789-dcd7446d84d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531940598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2531940598
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3018285138
Short name T988
Test name
Test status
Simulation time 63755171428 ps
CPU time 85.21 seconds
Started Aug 13 05:15:48 PM PDT 24
Finished Aug 13 05:17:13 PM PDT 24
Peak memory 200428 kb
Host smart-8f5068c4-cb37-465b-ae4b-9fc1164a366e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018285138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3018285138
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.609331763
Short name T1162
Test name
Test status
Simulation time 24851628894 ps
CPU time 47.05 seconds
Started Aug 13 05:15:49 PM PDT 24
Finished Aug 13 05:16:36 PM PDT 24
Peak memory 200848 kb
Host smart-5252d515-ab7e-4ec4-b943-2afd16d7ebd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609331763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.609331763
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2445249055
Short name T102
Test name
Test status
Simulation time 32821776236 ps
CPU time 14.73 seconds
Started Aug 13 05:15:51 PM PDT 24
Finished Aug 13 05:16:06 PM PDT 24
Peak memory 200400 kb
Host smart-19ce3755-f858-403d-97f8-eee543205bce
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445249055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2445249055
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.821681545
Short name T715
Test name
Test status
Simulation time 135928216023 ps
CPU time 1103.7 seconds
Started Aug 13 05:15:52 PM PDT 24
Finished Aug 13 05:34:16 PM PDT 24
Peak memory 200920 kb
Host smart-06be4a13-d1b6-494a-b225-fda940a9d031
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=821681545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.821681545
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1072692335
Short name T674
Test name
Test status
Simulation time 753141441 ps
CPU time 0.7 seconds
Started Aug 13 05:15:59 PM PDT 24
Finished Aug 13 05:16:00 PM PDT 24
Peak memory 196920 kb
Host smart-ccd73048-e10d-49a9-8433-27761e785b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072692335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1072692335
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3649978258
Short name T883
Test name
Test status
Simulation time 129406164627 ps
CPU time 87.11 seconds
Started Aug 13 05:15:53 PM PDT 24
Finished Aug 13 05:17:20 PM PDT 24
Peak memory 200744 kb
Host smart-749313a9-4dd8-4038-8b3a-074c335e4dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649978258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3649978258
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.722891284
Short name T1130
Test name
Test status
Simulation time 5696602506 ps
CPU time 157.92 seconds
Started Aug 13 05:15:52 PM PDT 24
Finished Aug 13 05:18:30 PM PDT 24
Peak memory 200868 kb
Host smart-160a1c60-39d4-4e94-95af-3d0462047634
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=722891284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.722891284
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.2584810105
Short name T408
Test name
Test status
Simulation time 2590311675 ps
CPU time 4.48 seconds
Started Aug 13 05:16:01 PM PDT 24
Finished Aug 13 05:16:06 PM PDT 24
Peak memory 199060 kb
Host smart-11325871-34d0-4468-9bc5-19a33a42c836
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2584810105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2584810105
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.2659966605
Short name T829
Test name
Test status
Simulation time 78355551875 ps
CPU time 26.82 seconds
Started Aug 13 05:15:51 PM PDT 24
Finished Aug 13 05:16:18 PM PDT 24
Peak memory 200860 kb
Host smart-e2f7d41b-3d13-4ae5-b3b7-c0559965618c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659966605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2659966605
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1212475636
Short name T1104
Test name
Test status
Simulation time 2732352253 ps
CPU time 1.61 seconds
Started Aug 13 05:15:51 PM PDT 24
Finished Aug 13 05:15:52 PM PDT 24
Peak memory 197364 kb
Host smart-3468b869-5183-4321-b55f-b232a0aecf52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212475636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1212475636
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1573150433
Short name T318
Test name
Test status
Simulation time 447787274 ps
CPU time 1.86 seconds
Started Aug 13 05:15:46 PM PDT 24
Finished Aug 13 05:15:48 PM PDT 24
Peak memory 200520 kb
Host smart-dc5b7d01-07ad-4711-b7fb-67635176bd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573150433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1573150433
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.4120029726
Short name T700
Test name
Test status
Simulation time 199402558912 ps
CPU time 837.75 seconds
Started Aug 13 05:15:53 PM PDT 24
Finished Aug 13 05:29:51 PM PDT 24
Peak memory 200744 kb
Host smart-d76ee2e5-2107-4768-9333-1259a3262343
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120029726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.4120029726
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.959919818
Short name T1034
Test name
Test status
Simulation time 4285363430 ps
CPU time 11.82 seconds
Started Aug 13 05:15:53 PM PDT 24
Finished Aug 13 05:16:05 PM PDT 24
Peak memory 209004 kb
Host smart-2ae42ee3-bae4-4b86-b2ff-d9c6f257cfba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959919818 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.959919818
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.851744189
Short name T876
Test name
Test status
Simulation time 11573751778 ps
CPU time 6.62 seconds
Started Aug 13 05:15:51 PM PDT 24
Finished Aug 13 05:15:58 PM PDT 24
Peak memory 200840 kb
Host smart-2ae6c8ab-6cde-494d-88b9-ca78a3465be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851744189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.851744189
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.416006832
Short name T479
Test name
Test status
Simulation time 66983178934 ps
CPU time 30.44 seconds
Started Aug 13 05:15:47 PM PDT 24
Finished Aug 13 05:16:17 PM PDT 24
Peak memory 200872 kb
Host smart-2198273d-5fab-438a-910c-d196aa4bef8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416006832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.416006832
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.635506876
Short name T581
Test name
Test status
Simulation time 19644460 ps
CPU time 0.55 seconds
Started Aug 13 05:15:52 PM PDT 24
Finished Aug 13 05:15:52 PM PDT 24
Peak memory 195848 kb
Host smart-9a8269de-9b79-4cd4-a07c-eaf41e3269d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635506876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.635506876
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.2302335279
Short name T760
Test name
Test status
Simulation time 4715100528 ps
CPU time 7.69 seconds
Started Aug 13 05:15:50 PM PDT 24
Finished Aug 13 05:15:58 PM PDT 24
Peak memory 199280 kb
Host smart-678b4fc1-29a7-48c0-a0ef-516b15e5b3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302335279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2302335279
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.170542772
Short name T215
Test name
Test status
Simulation time 105021386211 ps
CPU time 40.86 seconds
Started Aug 13 05:15:50 PM PDT 24
Finished Aug 13 05:16:31 PM PDT 24
Peak memory 200904 kb
Host smart-f58ea10b-2248-4cc6-894e-1ece2d06794a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170542772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.170542772
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.4068893654
Short name T416
Test name
Test status
Simulation time 4985832811 ps
CPU time 2.41 seconds
Started Aug 13 05:15:50 PM PDT 24
Finished Aug 13 05:15:53 PM PDT 24
Peak memory 196748 kb
Host smart-a7f930d8-3233-44ec-888d-ad078fffe3f6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068893654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.4068893654
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.446421875
Short name T918
Test name
Test status
Simulation time 117051871597 ps
CPU time 1058.83 seconds
Started Aug 13 05:15:54 PM PDT 24
Finished Aug 13 05:33:33 PM PDT 24
Peak memory 200876 kb
Host smart-5f071294-689e-458a-988f-558460ffd2b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=446421875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.446421875
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.893636351
Short name T566
Test name
Test status
Simulation time 101490235 ps
CPU time 0.89 seconds
Started Aug 13 05:15:52 PM PDT 24
Finished Aug 13 05:15:53 PM PDT 24
Peak memory 197860 kb
Host smart-0b9440df-63f1-4a31-9793-0007f1f635bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893636351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.893636351
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.2704213411
Short name T324
Test name
Test status
Simulation time 102913812849 ps
CPU time 44.53 seconds
Started Aug 13 05:15:52 PM PDT 24
Finished Aug 13 05:16:37 PM PDT 24
Peak memory 201100 kb
Host smart-75d09156-bf5b-4ef7-a4ae-7d03903d065f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704213411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2704213411
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1996095522
Short name T382
Test name
Test status
Simulation time 5221032883 ps
CPU time 79.97 seconds
Started Aug 13 05:15:50 PM PDT 24
Finished Aug 13 05:17:10 PM PDT 24
Peak memory 200840 kb
Host smart-41111241-47fc-4b2a-8bf7-68825da7343b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1996095522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1996095522
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2961088744
Short name T744
Test name
Test status
Simulation time 3709290966 ps
CPU time 13.79 seconds
Started Aug 13 05:15:59 PM PDT 24
Finished Aug 13 05:16:13 PM PDT 24
Peak memory 199960 kb
Host smart-325f5f31-b855-4b8c-bc4e-23a77aae04a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2961088744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2961088744
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1595262367
Short name T428
Test name
Test status
Simulation time 112163362325 ps
CPU time 66.14 seconds
Started Aug 13 05:16:02 PM PDT 24
Finished Aug 13 05:17:08 PM PDT 24
Peak memory 200888 kb
Host smart-80be3e23-4a53-4251-8758-4da438a21a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595262367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1595262367
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.250024493
Short name T390
Test name
Test status
Simulation time 650031384 ps
CPU time 1.47 seconds
Started Aug 13 05:15:51 PM PDT 24
Finished Aug 13 05:15:52 PM PDT 24
Peak memory 196540 kb
Host smart-c7650da4-9490-46c5-9b20-ed7011784d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250024493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.250024493
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1285126264
Short name T915
Test name
Test status
Simulation time 5877594776 ps
CPU time 12.95 seconds
Started Aug 13 05:16:01 PM PDT 24
Finished Aug 13 05:16:14 PM PDT 24
Peak memory 200836 kb
Host smart-fc65d8a5-bd43-4ec8-af96-77331005aef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285126264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1285126264
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.3723589099
Short name T607
Test name
Test status
Simulation time 143293215048 ps
CPU time 601.81 seconds
Started Aug 13 05:15:51 PM PDT 24
Finished Aug 13 05:25:53 PM PDT 24
Peak memory 209156 kb
Host smart-445617eb-0236-48fc-baed-b1f99a78d58b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723589099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3723589099
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.1211452171
Short name T861
Test name
Test status
Simulation time 1571171518 ps
CPU time 15.14 seconds
Started Aug 13 05:15:50 PM PDT 24
Finished Aug 13 05:16:06 PM PDT 24
Peak memory 209328 kb
Host smart-67665984-1019-420d-b1ca-05b21dd06e13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211452171 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.1211452171
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.1383558967
Short name T506
Test name
Test status
Simulation time 9586482219 ps
CPU time 10.35 seconds
Started Aug 13 05:15:53 PM PDT 24
Finished Aug 13 05:16:04 PM PDT 24
Peak memory 200740 kb
Host smart-c576ad1f-5f87-4268-a68f-c0558b574c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383558967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1383558967
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1266862787
Short name T1151
Test name
Test status
Simulation time 151372540328 ps
CPU time 16.55 seconds
Started Aug 13 05:15:53 PM PDT 24
Finished Aug 13 05:16:10 PM PDT 24
Peak memory 200860 kb
Host smart-d64e5c1e-b8c9-4c42-8765-e92dd4c79c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266862787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1266862787
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.444893386
Short name T438
Test name
Test status
Simulation time 56471265 ps
CPU time 0.56 seconds
Started Aug 13 05:15:59 PM PDT 24
Finished Aug 13 05:16:00 PM PDT 24
Peak memory 196512 kb
Host smart-30b3c59c-3d8d-4ec8-afbe-96c8176f86ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444893386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.444893386
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.240585344
Short name T935
Test name
Test status
Simulation time 109393306604 ps
CPU time 158.49 seconds
Started Aug 13 05:15:52 PM PDT 24
Finished Aug 13 05:18:30 PM PDT 24
Peak memory 200928 kb
Host smart-8ebfd28c-64c0-4a18-a725-e1cf7dbd30b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240585344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.240585344
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1328475239
Short name T1124
Test name
Test status
Simulation time 161251397690 ps
CPU time 19.21 seconds
Started Aug 13 05:16:01 PM PDT 24
Finished Aug 13 05:16:20 PM PDT 24
Peak memory 200924 kb
Host smart-e6ea9f7a-742a-4263-a65c-5cead0ab2b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328475239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1328475239
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.295306337
Short name T1101
Test name
Test status
Simulation time 70222091614 ps
CPU time 27.83 seconds
Started Aug 13 05:15:53 PM PDT 24
Finished Aug 13 05:16:21 PM PDT 24
Peak memory 200940 kb
Host smart-f0708e0b-a575-4fc8-b55b-6e61c09006fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295306337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.295306337
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.4203322041
Short name T610
Test name
Test status
Simulation time 9527255309 ps
CPU time 4.07 seconds
Started Aug 13 05:15:58 PM PDT 24
Finished Aug 13 05:16:02 PM PDT 24
Peak memory 197644 kb
Host smart-4dba0e8f-347c-42ef-b31e-4edc4e62cdfc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203322041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.4203322041
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.739927026
Short name T746
Test name
Test status
Simulation time 189063267485 ps
CPU time 144.55 seconds
Started Aug 13 05:16:17 PM PDT 24
Finished Aug 13 05:18:42 PM PDT 24
Peak memory 200840 kb
Host smart-c05f8d06-6b0c-4b43-a1c7-b54885b9c655
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=739927026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.739927026
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1842297731
Short name T848
Test name
Test status
Simulation time 4848746287 ps
CPU time 3.09 seconds
Started Aug 13 05:16:00 PM PDT 24
Finished Aug 13 05:16:03 PM PDT 24
Peak memory 198464 kb
Host smart-fefa1bc0-90b4-4b49-838a-4c99878cb791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842297731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1842297731
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.780343349
Short name T433
Test name
Test status
Simulation time 8316736901 ps
CPU time 13.31 seconds
Started Aug 13 05:15:58 PM PDT 24
Finished Aug 13 05:16:11 PM PDT 24
Peak memory 196084 kb
Host smart-7336d415-fceb-4778-be1e-32de3d0dd7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780343349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.780343349
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.3347258934
Short name T299
Test name
Test status
Simulation time 8048825544 ps
CPU time 101.15 seconds
Started Aug 13 05:15:57 PM PDT 24
Finished Aug 13 05:17:38 PM PDT 24
Peak memory 200920 kb
Host smart-2f4aa71b-618d-49e6-b118-8df77910d3b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3347258934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3347258934
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.1429008988
Short name T5
Test name
Test status
Simulation time 6732060827 ps
CPU time 54.99 seconds
Started Aug 13 05:15:56 PM PDT 24
Finished Aug 13 05:16:51 PM PDT 24
Peak memory 198932 kb
Host smart-0378589b-1ec0-4e13-8ef3-862bbda8abf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1429008988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1429008988
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3191106162
Short name T805
Test name
Test status
Simulation time 104775435904 ps
CPU time 63.36 seconds
Started Aug 13 05:15:58 PM PDT 24
Finished Aug 13 05:17:01 PM PDT 24
Peak memory 200924 kb
Host smart-46d8c838-f0c9-4432-9105-c2623d4b469c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191106162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3191106162
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.4213036644
Short name T813
Test name
Test status
Simulation time 3816233947 ps
CPU time 6.41 seconds
Started Aug 13 05:15:58 PM PDT 24
Finished Aug 13 05:16:05 PM PDT 24
Peak memory 197496 kb
Host smart-bfb00c51-3aaa-469f-8a85-1b656f6434eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213036644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.4213036644
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.289849524
Short name T627
Test name
Test status
Simulation time 6053428175 ps
CPU time 11.88 seconds
Started Aug 13 05:15:59 PM PDT 24
Finished Aug 13 05:16:11 PM PDT 24
Peak memory 200220 kb
Host smart-410ecefc-6d3a-4325-9374-2c2a369b9183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289849524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.289849524
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.3640194613
Short name T847
Test name
Test status
Simulation time 225239789801 ps
CPU time 405.43 seconds
Started Aug 13 05:15:58 PM PDT 24
Finished Aug 13 05:22:44 PM PDT 24
Peak memory 200932 kb
Host smart-361f1dd0-9365-4073-b86e-9308be37ff5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640194613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3640194613
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.4035029737
Short name T351
Test name
Test status
Simulation time 3763976894 ps
CPU time 49.14 seconds
Started Aug 13 05:15:59 PM PDT 24
Finished Aug 13 05:16:48 PM PDT 24
Peak memory 217464 kb
Host smart-b8fa9db2-ffc1-4d76-8bec-70cc0af7bea3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035029737 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.4035029737
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1904110736
Short name T341
Test name
Test status
Simulation time 412499499 ps
CPU time 1.9 seconds
Started Aug 13 05:15:57 PM PDT 24
Finished Aug 13 05:15:59 PM PDT 24
Peak memory 199316 kb
Host smart-339e80c7-ac89-468e-ae09-84843d87aad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904110736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1904110736
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.1945518946
Short name T782
Test name
Test status
Simulation time 65374038075 ps
CPU time 25.81 seconds
Started Aug 13 05:15:49 PM PDT 24
Finished Aug 13 05:16:15 PM PDT 24
Peak memory 200708 kb
Host smart-ac09d278-c2b5-41a7-baaf-a4a5b88c51ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945518946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1945518946
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.577980638
Short name T1123
Test name
Test status
Simulation time 61688173 ps
CPU time 0.58 seconds
Started Aug 13 05:16:14 PM PDT 24
Finished Aug 13 05:16:15 PM PDT 24
Peak memory 196220 kb
Host smart-b74f745c-161f-4680-b647-fe9ab01101e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577980638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.577980638
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.2783105372
Short name T802
Test name
Test status
Simulation time 50262265165 ps
CPU time 30.5 seconds
Started Aug 13 05:15:58 PM PDT 24
Finished Aug 13 05:16:29 PM PDT 24
Peak memory 200920 kb
Host smart-39ab676a-bf0c-45cf-bdc5-e3d401299fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783105372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2783105372
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.2566056984
Short name T325
Test name
Test status
Simulation time 127410391359 ps
CPU time 263.55 seconds
Started Aug 13 05:16:00 PM PDT 24
Finished Aug 13 05:20:24 PM PDT 24
Peak memory 200876 kb
Host smart-6ad5a027-1c7b-43f7-a282-2ef0e8d37159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566056984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2566056984
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.3730629180
Short name T1173
Test name
Test status
Simulation time 56387510550 ps
CPU time 46.47 seconds
Started Aug 13 05:15:59 PM PDT 24
Finished Aug 13 05:16:46 PM PDT 24
Peak memory 200940 kb
Host smart-2810677b-373b-483e-90f8-870c5e5f24ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730629180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3730629180
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.914197256
Short name T100
Test name
Test status
Simulation time 47792412945 ps
CPU time 21.76 seconds
Started Aug 13 05:15:59 PM PDT 24
Finished Aug 13 05:16:21 PM PDT 24
Peak memory 200868 kb
Host smart-11686fbf-83c3-4135-bf95-0950de15e05e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914197256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.914197256
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.845821343
Short name T1019
Test name
Test status
Simulation time 54984363968 ps
CPU time 187.9 seconds
Started Aug 13 05:16:12 PM PDT 24
Finished Aug 13 05:19:20 PM PDT 24
Peak memory 200924 kb
Host smart-c7f7e780-08d9-4d4b-a0b3-75fe8e7f25c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=845821343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.845821343
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1428180919
Short name T1134
Test name
Test status
Simulation time 3115851101 ps
CPU time 4.49 seconds
Started Aug 13 05:15:59 PM PDT 24
Finished Aug 13 05:16:04 PM PDT 24
Peak memory 200828 kb
Host smart-4a182aba-d5aa-4f45-983c-a7575a84a78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428180919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1428180919
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1699871675
Short name T912
Test name
Test status
Simulation time 1904985768 ps
CPU time 1.44 seconds
Started Aug 13 05:16:02 PM PDT 24
Finished Aug 13 05:16:03 PM PDT 24
Peak memory 195460 kb
Host smart-4b4c6e08-ed8b-462f-a29f-3f67394ef5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699871675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1699871675
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.530635952
Short name T361
Test name
Test status
Simulation time 11649766588 ps
CPU time 732.74 seconds
Started Aug 13 05:16:11 PM PDT 24
Finished Aug 13 05:28:24 PM PDT 24
Peak memory 200836 kb
Host smart-90fb8bca-44d9-43cf-9170-6493fa6aaa53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=530635952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.530635952
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.543896919
Short name T750
Test name
Test status
Simulation time 1889213046 ps
CPU time 8.52 seconds
Started Aug 13 05:15:58 PM PDT 24
Finished Aug 13 05:16:06 PM PDT 24
Peak memory 199024 kb
Host smart-ff7eca7b-7bd1-4909-9c84-0e620264e7ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=543896919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.543896919
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3632334905
Short name T749
Test name
Test status
Simulation time 117257581501 ps
CPU time 173.18 seconds
Started Aug 13 05:15:59 PM PDT 24
Finished Aug 13 05:18:52 PM PDT 24
Peak memory 200832 kb
Host smart-d9918824-6cb5-4469-a7b6-d12ff2dcdff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632334905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3632334905
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.1816344027
Short name T370
Test name
Test status
Simulation time 571923080 ps
CPU time 1.08 seconds
Started Aug 13 05:15:58 PM PDT 24
Finished Aug 13 05:15:59 PM PDT 24
Peak memory 196356 kb
Host smart-91b0c070-3359-4f9a-9139-888352e14da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816344027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.1816344027
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.191892909
Short name T726
Test name
Test status
Simulation time 718515890 ps
CPU time 2.6 seconds
Started Aug 13 05:15:58 PM PDT 24
Finished Aug 13 05:16:00 PM PDT 24
Peak memory 200348 kb
Host smart-2d1703e5-6719-48a1-8853-a84826f09d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191892909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.191892909
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2013351577
Short name T614
Test name
Test status
Simulation time 173394307339 ps
CPU time 238.24 seconds
Started Aug 13 05:16:12 PM PDT 24
Finished Aug 13 05:20:11 PM PDT 24
Peak memory 200924 kb
Host smart-7369d449-b065-46c3-91d4-ec9a68d24baa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013351577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2013351577
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3756545976
Short name T1097
Test name
Test status
Simulation time 7724899587 ps
CPU time 13.6 seconds
Started Aug 13 05:16:00 PM PDT 24
Finished Aug 13 05:16:13 PM PDT 24
Peak memory 200856 kb
Host smart-3aa37768-a297-4302-aa3c-b468a2428604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756545976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3756545976
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.278292343
Short name T672
Test name
Test status
Simulation time 9894823519 ps
CPU time 22.19 seconds
Started Aug 13 05:15:59 PM PDT 24
Finished Aug 13 05:16:21 PM PDT 24
Peak memory 200852 kb
Host smart-c8df6107-e64a-4d8c-b6fb-b5d50c234a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278292343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.278292343
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2814942172
Short name T816
Test name
Test status
Simulation time 14350341 ps
CPU time 0.59 seconds
Started Aug 13 05:16:11 PM PDT 24
Finished Aug 13 05:16:12 PM PDT 24
Peak memory 196428 kb
Host smart-9e18dd60-929e-4fb9-b2f4-044c8789dba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814942172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2814942172
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.3635724178
Short name T116
Test name
Test status
Simulation time 132312948589 ps
CPU time 62.59 seconds
Started Aug 13 05:16:13 PM PDT 24
Finished Aug 13 05:17:16 PM PDT 24
Peak memory 200844 kb
Host smart-c705570e-6b38-44e6-8a8e-4c70681de4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635724178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3635724178
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.4256781248
Short name T1048
Test name
Test status
Simulation time 28010437311 ps
CPU time 23.85 seconds
Started Aug 13 05:16:10 PM PDT 24
Finished Aug 13 05:16:34 PM PDT 24
Peak memory 200536 kb
Host smart-8d3a061b-0344-4961-9533-c32bef087f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256781248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.4256781248
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3095720166
Short name T830
Test name
Test status
Simulation time 20886760930 ps
CPU time 18.58 seconds
Started Aug 13 05:16:13 PM PDT 24
Finished Aug 13 05:16:32 PM PDT 24
Peak memory 200620 kb
Host smart-e2244e46-b998-48e1-9a7e-3e04d85fa4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095720166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3095720166
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.1185317321
Short name T14
Test name
Test status
Simulation time 22430311970 ps
CPU time 8.22 seconds
Started Aug 13 05:16:10 PM PDT 24
Finished Aug 13 05:16:18 PM PDT 24
Peak memory 200228 kb
Host smart-83416bae-a4ad-4bc1-99b2-5f4ee31d1edf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185317321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1185317321
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_loopback.3767035826
Short name T1061
Test name
Test status
Simulation time 8479963166 ps
CPU time 16.67 seconds
Started Aug 13 05:16:12 PM PDT 24
Finished Aug 13 05:16:29 PM PDT 24
Peak memory 200576 kb
Host smart-046e1666-edb8-419e-8760-fdf1745bba37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767035826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3767035826
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3190471114
Short name T953
Test name
Test status
Simulation time 102713522390 ps
CPU time 49.3 seconds
Started Aug 13 05:16:10 PM PDT 24
Finished Aug 13 05:17:00 PM PDT 24
Peak memory 200560 kb
Host smart-316c01ee-7c7c-4080-b1a7-c7c308b74699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190471114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3190471114
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.2172378383
Short name T602
Test name
Test status
Simulation time 17468441995 ps
CPU time 937.71 seconds
Started Aug 13 05:16:14 PM PDT 24
Finished Aug 13 05:31:52 PM PDT 24
Peak memory 200860 kb
Host smart-8d2b526a-6484-405d-a56f-ca092ce2616b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2172378383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2172378383
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2560021859
Short name T890
Test name
Test status
Simulation time 3370033668 ps
CPU time 9.94 seconds
Started Aug 13 05:16:10 PM PDT 24
Finished Aug 13 05:16:21 PM PDT 24
Peak memory 199356 kb
Host smart-ee5b82d7-4984-4ee4-938f-04f0b1229919
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2560021859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2560021859
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.874530362
Short name T901
Test name
Test status
Simulation time 72431403001 ps
CPU time 45.14 seconds
Started Aug 13 05:16:12 PM PDT 24
Finished Aug 13 05:16:57 PM PDT 24
Peak memory 200916 kb
Host smart-67210fd4-b508-4a3d-b647-12de7f53dfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874530362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.874530362
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.2081259773
Short name T881
Test name
Test status
Simulation time 3271977959 ps
CPU time 5.28 seconds
Started Aug 13 05:16:14 PM PDT 24
Finished Aug 13 05:16:20 PM PDT 24
Peak memory 197440 kb
Host smart-4f65ed09-9d28-4dc4-a80d-87e56df4dcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081259773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2081259773
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.1207659238
Short name T961
Test name
Test status
Simulation time 974037152 ps
CPU time 3.26 seconds
Started Aug 13 05:16:12 PM PDT 24
Finished Aug 13 05:16:15 PM PDT 24
Peak memory 199828 kb
Host smart-98703fba-8d07-4777-9597-d3ea58701ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207659238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1207659238
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.882168685
Short name T172
Test name
Test status
Simulation time 334402210172 ps
CPU time 135.72 seconds
Started Aug 13 05:16:13 PM PDT 24
Finished Aug 13 05:18:28 PM PDT 24
Peak memory 209340 kb
Host smart-c5a9d60f-8437-43a1-a2ca-5c92a1b243a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882168685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.882168685
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1841243918
Short name T545
Test name
Test status
Simulation time 9937049713 ps
CPU time 12.01 seconds
Started Aug 13 05:16:11 PM PDT 24
Finished Aug 13 05:16:23 PM PDT 24
Peak memory 209400 kb
Host smart-494db4b5-4457-4da7-be5d-13a6c44c30f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841243918 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1841243918
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.335990056
Short name T922
Test name
Test status
Simulation time 889454632 ps
CPU time 2.01 seconds
Started Aug 13 05:16:11 PM PDT 24
Finished Aug 13 05:16:13 PM PDT 24
Peak memory 200088 kb
Host smart-815ed8ed-ca6f-4728-bca6-92049926e7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335990056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.335990056
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.817450396
Short name T734
Test name
Test status
Simulation time 17620175317 ps
CPU time 12.93 seconds
Started Aug 13 05:16:13 PM PDT 24
Finished Aug 13 05:16:26 PM PDT 24
Peak memory 198564 kb
Host smart-91a8d73b-da06-428c-b0c3-e507d31e35c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817450396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.817450396
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.855016655
Short name T694
Test name
Test status
Simulation time 16060764 ps
CPU time 0.55 seconds
Started Aug 13 05:16:08 PM PDT 24
Finished Aug 13 05:16:09 PM PDT 24
Peak memory 196248 kb
Host smart-eb2d70cf-d0b0-4d63-a81d-49277254b5de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855016655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.855016655
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.780090715
Short name T591
Test name
Test status
Simulation time 128040226952 ps
CPU time 181.38 seconds
Started Aug 13 05:16:10 PM PDT 24
Finished Aug 13 05:19:11 PM PDT 24
Peak memory 200848 kb
Host smart-d9059531-cdca-456d-b297-dc92a6c256d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780090715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.780090715
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.4168030333
Short name T198
Test name
Test status
Simulation time 101551928127 ps
CPU time 114.77 seconds
Started Aug 13 05:16:10 PM PDT 24
Finished Aug 13 05:18:05 PM PDT 24
Peak memory 200876 kb
Host smart-9b10e5ec-206b-4772-bba1-ef6f19fb5401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168030333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.4168030333
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2731891960
Short name T280
Test name
Test status
Simulation time 39436872909 ps
CPU time 17.18 seconds
Started Aug 13 05:16:12 PM PDT 24
Finished Aug 13 05:16:29 PM PDT 24
Peak memory 200932 kb
Host smart-25f9e3e5-3337-4019-bd91-06edffe434f9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731891960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2731891960
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.1972274504
Short name T1120
Test name
Test status
Simulation time 112828790041 ps
CPU time 491.65 seconds
Started Aug 13 05:16:10 PM PDT 24
Finished Aug 13 05:24:21 PM PDT 24
Peak memory 200900 kb
Host smart-7bc6994a-dce6-4dc0-aa87-819bab65eee0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1972274504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.1972274504
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3109052649
Short name T633
Test name
Test status
Simulation time 10224651297 ps
CPU time 17.59 seconds
Started Aug 13 05:16:10 PM PDT 24
Finished Aug 13 05:16:28 PM PDT 24
Peak memory 199956 kb
Host smart-e1cb0ae5-b283-4216-87b1-c93a7a743b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109052649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3109052649
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2006784712
Short name T997
Test name
Test status
Simulation time 60626521723 ps
CPU time 24.39 seconds
Started Aug 13 05:16:12 PM PDT 24
Finished Aug 13 05:16:37 PM PDT 24
Peak memory 200852 kb
Host smart-4fcedffb-a818-4b93-8541-68a20d4fe3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006784712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2006784712
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1932605045
Short name T271
Test name
Test status
Simulation time 40795566362 ps
CPU time 391.38 seconds
Started Aug 13 05:16:12 PM PDT 24
Finished Aug 13 05:22:43 PM PDT 24
Peak memory 200920 kb
Host smart-50c2630f-d17e-4d61-8dce-eaf2c3a5fc24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1932605045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1932605045
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.2771708138
Short name T612
Test name
Test status
Simulation time 5823802208 ps
CPU time 17.65 seconds
Started Aug 13 05:16:09 PM PDT 24
Finished Aug 13 05:16:27 PM PDT 24
Peak memory 200872 kb
Host smart-f51823b2-8e84-4bc8-b814-ebd0ec02d425
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2771708138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2771708138
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3482145056
Short name T472
Test name
Test status
Simulation time 57278734781 ps
CPU time 83.56 seconds
Started Aug 13 05:16:12 PM PDT 24
Finished Aug 13 05:17:35 PM PDT 24
Peak memory 200908 kb
Host smart-e73a5a2a-ad76-4388-aeaf-538cd52880c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482145056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3482145056
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3134767376
Short name T904
Test name
Test status
Simulation time 4737082163 ps
CPU time 2.46 seconds
Started Aug 13 05:16:11 PM PDT 24
Finished Aug 13 05:16:14 PM PDT 24
Peak memory 197064 kb
Host smart-d96736b5-b0cc-4bb7-9d24-0fcd799d7086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134767376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3134767376
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3653485209
Short name T1181
Test name
Test status
Simulation time 5381457028 ps
CPU time 9.85 seconds
Started Aug 13 05:16:11 PM PDT 24
Finished Aug 13 05:16:21 PM PDT 24
Peak memory 200644 kb
Host smart-27c36b4c-1dae-4908-bf13-97a860a6edfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653485209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3653485209
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1722640580
Short name T770
Test name
Test status
Simulation time 17838158188 ps
CPU time 83.74 seconds
Started Aug 13 05:16:10 PM PDT 24
Finished Aug 13 05:17:34 PM PDT 24
Peak memory 211008 kb
Host smart-481f79c0-2ddc-450f-97a4-80e427521c05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722640580 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1722640580
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.237722146
Short name T1143
Test name
Test status
Simulation time 1314157016 ps
CPU time 3.66 seconds
Started Aug 13 05:16:13 PM PDT 24
Finished Aug 13 05:16:17 PM PDT 24
Peak memory 199304 kb
Host smart-e30c2227-7c39-4edf-92b5-16db37d381e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237722146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.237722146
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.751244168
Short name T1183
Test name
Test status
Simulation time 16672662813 ps
CPU time 23.67 seconds
Started Aug 13 05:16:11 PM PDT 24
Finished Aug 13 05:16:34 PM PDT 24
Peak memory 199816 kb
Host smart-4983ebcb-b349-4d37-a912-bf54d2cf8243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751244168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.751244168
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3114381482
Short name T852
Test name
Test status
Simulation time 12518323 ps
CPU time 0.53 seconds
Started Aug 13 05:16:12 PM PDT 24
Finished Aug 13 05:16:13 PM PDT 24
Peak memory 195228 kb
Host smart-1386addb-9e20-4689-8c39-34f6ce0b7b22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114381482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3114381482
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.3608103144
Short name T606
Test name
Test status
Simulation time 31826277292 ps
CPU time 16.68 seconds
Started Aug 13 05:16:11 PM PDT 24
Finished Aug 13 05:16:28 PM PDT 24
Peak memory 200868 kb
Host smart-533b0751-4f2a-4e56-ba58-0ca3e82aeefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608103144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3608103144
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2767875103
Short name T487
Test name
Test status
Simulation time 33035855669 ps
CPU time 20.57 seconds
Started Aug 13 05:16:10 PM PDT 24
Finished Aug 13 05:16:31 PM PDT 24
Peak memory 200564 kb
Host smart-b71b6112-efe9-4f12-863f-9169db60ad3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767875103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2767875103
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.2493097378
Short name T214
Test name
Test status
Simulation time 100057554629 ps
CPU time 77.03 seconds
Started Aug 13 05:16:14 PM PDT 24
Finished Aug 13 05:17:31 PM PDT 24
Peak memory 200848 kb
Host smart-d5b29d27-e713-439f-a25e-e853a847bcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493097378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2493097378
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.3896799964
Short name T516
Test name
Test status
Simulation time 37763044379 ps
CPU time 26.31 seconds
Started Aug 13 05:16:15 PM PDT 24
Finished Aug 13 05:16:41 PM PDT 24
Peak memory 200840 kb
Host smart-380e7d9b-2771-4bea-b46e-c3d53ae28120
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896799964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3896799964
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.3908806127
Short name T1133
Test name
Test status
Simulation time 303249185296 ps
CPU time 403.89 seconds
Started Aug 13 05:16:13 PM PDT 24
Finished Aug 13 05:22:57 PM PDT 24
Peak memory 200808 kb
Host smart-e7096057-1665-4c62-b840-e799984f3641
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3908806127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3908806127
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.110454504
Short name T1042
Test name
Test status
Simulation time 4338433309 ps
CPU time 8.5 seconds
Started Aug 13 05:16:14 PM PDT 24
Finished Aug 13 05:16:23 PM PDT 24
Peak memory 199764 kb
Host smart-29bf78d8-11e7-4e28-a181-76224740e24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110454504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.110454504
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.3485566067
Short name T788
Test name
Test status
Simulation time 32942590985 ps
CPU time 63.03 seconds
Started Aug 13 05:16:14 PM PDT 24
Finished Aug 13 05:17:17 PM PDT 24
Peak memory 201016 kb
Host smart-a4ccfad8-5749-4c9b-b218-9e767f066b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485566067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.3485566067
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.2912194287
Short name T639
Test name
Test status
Simulation time 13891593241 ps
CPU time 575.59 seconds
Started Aug 13 05:16:14 PM PDT 24
Finished Aug 13 05:25:49 PM PDT 24
Peak memory 200868 kb
Host smart-494ce521-0e26-4839-8230-6ab7f2ba1a04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2912194287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2912194287
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.3791631384
Short name T454
Test name
Test status
Simulation time 7160127129 ps
CPU time 16.14 seconds
Started Aug 13 05:16:15 PM PDT 24
Finished Aug 13 05:16:31 PM PDT 24
Peak memory 200784 kb
Host smart-6f231945-3b29-4713-92e5-9cd8928ab530
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3791631384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3791631384
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.3916471424
Short name T251
Test name
Test status
Simulation time 100205174616 ps
CPU time 140.92 seconds
Started Aug 13 05:16:21 PM PDT 24
Finished Aug 13 05:18:42 PM PDT 24
Peak memory 200828 kb
Host smart-4261c79d-6418-49ea-a32d-920ba1bbe071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916471424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3916471424
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.236270852
Short name T1139
Test name
Test status
Simulation time 2376632008 ps
CPU time 3.89 seconds
Started Aug 13 05:16:15 PM PDT 24
Finished Aug 13 05:16:19 PM PDT 24
Peak memory 196940 kb
Host smart-0b5049c6-5815-4c89-a17f-6113bbbc93a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236270852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.236270852
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3817202201
Short name T650
Test name
Test status
Simulation time 115173024 ps
CPU time 0.92 seconds
Started Aug 13 05:16:10 PM PDT 24
Finished Aug 13 05:16:11 PM PDT 24
Peak memory 199544 kb
Host smart-8e48b9b1-501a-44cd-ad74-e9c0ce1e0977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817202201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3817202201
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.3087924070
Short name T65
Test name
Test status
Simulation time 127933804531 ps
CPU time 121.65 seconds
Started Aug 13 05:16:22 PM PDT 24
Finished Aug 13 05:18:23 PM PDT 24
Peak memory 200852 kb
Host smart-c24f3996-b9f5-4d20-a6ef-f4653fd8f295
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087924070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3087924070
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.4254972825
Short name T90
Test name
Test status
Simulation time 2014070192 ps
CPU time 23.3 seconds
Started Aug 13 05:16:14 PM PDT 24
Finished Aug 13 05:16:37 PM PDT 24
Peak memory 200856 kb
Host smart-d52682f2-5ca5-460d-8a4f-d9eb0f4742b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254972825 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.4254972825
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.2908136675
Short name T842
Test name
Test status
Simulation time 454569750 ps
CPU time 1.56 seconds
Started Aug 13 05:16:14 PM PDT 24
Finished Aug 13 05:16:16 PM PDT 24
Peak memory 198736 kb
Host smart-3d8dd79f-0d4a-44b0-bc34-ff1b71aaebd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908136675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2908136675
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3390529732
Short name T1180
Test name
Test status
Simulation time 34274553665 ps
CPU time 57.08 seconds
Started Aug 13 05:16:13 PM PDT 24
Finished Aug 13 05:17:10 PM PDT 24
Peak memory 200932 kb
Host smart-8f54b51c-7c0b-4d38-966c-8c9407cb2e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390529732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3390529732
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1077080367
Short name T418
Test name
Test status
Simulation time 15124947 ps
CPU time 0.57 seconds
Started Aug 13 05:16:21 PM PDT 24
Finished Aug 13 05:16:22 PM PDT 24
Peak memory 196248 kb
Host smart-b22705fb-661f-427d-8c54-5fd0af2f4e0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077080367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1077080367
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.85221229
Short name T704
Test name
Test status
Simulation time 191326727440 ps
CPU time 152.87 seconds
Started Aug 13 05:16:21 PM PDT 24
Finished Aug 13 05:18:54 PM PDT 24
Peak memory 200900 kb
Host smart-0d6262be-f0ea-44aa-88c3-db815ac7c116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85221229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.85221229
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.1463563840
Short name T150
Test name
Test status
Simulation time 97669688368 ps
CPU time 216.23 seconds
Started Aug 13 05:16:21 PM PDT 24
Finished Aug 13 05:19:58 PM PDT 24
Peak memory 200912 kb
Host smart-a8b277f1-6656-4d11-ba30-ddce84c2fe61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463563840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1463563840
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_intr.514631091
Short name T16
Test name
Test status
Simulation time 4837133728 ps
CPU time 4.48 seconds
Started Aug 13 05:16:15 PM PDT 24
Finished Aug 13 05:16:20 PM PDT 24
Peak memory 196988 kb
Host smart-8b40d8cd-4766-4474-b652-549f6a6e5a22
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514631091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.514631091
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.2976930399
Short name T562
Test name
Test status
Simulation time 44878348297 ps
CPU time 207.33 seconds
Started Aug 13 05:16:21 PM PDT 24
Finished Aug 13 05:19:49 PM PDT 24
Peak memory 200932 kb
Host smart-904163c8-433a-4226-aa62-01835c53de34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2976930399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2976930399
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.180658765
Short name T366
Test name
Test status
Simulation time 5464097808 ps
CPU time 11.38 seconds
Started Aug 13 05:16:21 PM PDT 24
Finished Aug 13 05:16:32 PM PDT 24
Peak memory 199740 kb
Host smart-93c1862f-e7aa-4389-975a-f72d2d097af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180658765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.180658765
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.671937753
Short name T1118
Test name
Test status
Simulation time 298889729023 ps
CPU time 181.65 seconds
Started Aug 13 05:16:14 PM PDT 24
Finished Aug 13 05:19:16 PM PDT 24
Peak memory 201144 kb
Host smart-6ded48eb-8b49-4942-a106-d85589a0c8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671937753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.671937753
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.1200491446
Short name T933
Test name
Test status
Simulation time 11612357247 ps
CPU time 141.42 seconds
Started Aug 13 05:16:20 PM PDT 24
Finished Aug 13 05:18:42 PM PDT 24
Peak memory 200924 kb
Host smart-a792da24-cdd6-402a-8c9e-06101743e841
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1200491446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1200491446
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.3069548620
Short name T1182
Test name
Test status
Simulation time 3898271572 ps
CPU time 19.53 seconds
Started Aug 13 05:16:15 PM PDT 24
Finished Aug 13 05:16:35 PM PDT 24
Peak memory 198944 kb
Host smart-b12449d0-3874-4d6e-bf81-8aeeee1b72b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3069548620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3069548620
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2251534488
Short name T822
Test name
Test status
Simulation time 21068007884 ps
CPU time 53.3 seconds
Started Aug 13 05:16:22 PM PDT 24
Finished Aug 13 05:17:15 PM PDT 24
Peak memory 200852 kb
Host smart-1019c549-e119-4a8e-887a-9d6a5f65f194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251534488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2251534488
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.2017573079
Short name T855
Test name
Test status
Simulation time 1794108027 ps
CPU time 1.4 seconds
Started Aug 13 05:16:19 PM PDT 24
Finished Aug 13 05:16:21 PM PDT 24
Peak memory 194792 kb
Host smart-2f315673-c31c-417a-8a94-0807412191f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017573079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2017573079
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2688345221
Short name T613
Test name
Test status
Simulation time 686802196 ps
CPU time 2.82 seconds
Started Aug 13 05:16:11 PM PDT 24
Finished Aug 13 05:16:14 PM PDT 24
Peak memory 199224 kb
Host smart-aec1a4fc-3992-49a4-9182-bad1a05cee37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688345221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2688345221
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.1816473658
Short name T837
Test name
Test status
Simulation time 447026167780 ps
CPU time 484.48 seconds
Started Aug 13 05:16:21 PM PDT 24
Finished Aug 13 05:24:26 PM PDT 24
Peak memory 200876 kb
Host smart-35c1b335-3be6-4aea-891e-b7c7e4cf2eb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816473658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1816473658
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.481739222
Short name T467
Test name
Test status
Simulation time 10156699103 ps
CPU time 58.5 seconds
Started Aug 13 05:16:18 PM PDT 24
Finished Aug 13 05:17:17 PM PDT 24
Peak memory 209048 kb
Host smart-ac16960e-1c9c-40b8-9f4c-6edd9e3e05b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481739222 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.481739222
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.283469953
Short name T635
Test name
Test status
Simulation time 2515762506 ps
CPU time 2.01 seconds
Started Aug 13 05:16:15 PM PDT 24
Finished Aug 13 05:16:17 PM PDT 24
Peak memory 200888 kb
Host smart-65725f6c-8362-4190-b40d-4b729d3b19b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283469953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.283469953
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1272652927
Short name T1140
Test name
Test status
Simulation time 100685620379 ps
CPU time 169.83 seconds
Started Aug 13 05:16:15 PM PDT 24
Finished Aug 13 05:19:05 PM PDT 24
Peak memory 200936 kb
Host smart-46a4182d-739c-41ac-a180-7888a09364e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272652927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1272652927
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.218728449
Short name T381
Test name
Test status
Simulation time 14506924 ps
CPU time 0.57 seconds
Started Aug 13 05:13:49 PM PDT 24
Finished Aug 13 05:13:50 PM PDT 24
Peak memory 196496 kb
Host smart-b7797bd2-8bf7-4017-80aa-6076fb194ba3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218728449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.218728449
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.89446221
Short name T720
Test name
Test status
Simulation time 160477968613 ps
CPU time 116.56 seconds
Started Aug 13 05:13:47 PM PDT 24
Finished Aug 13 05:15:44 PM PDT 24
Peak memory 200884 kb
Host smart-62b102ca-c2d8-45fb-84f1-e5043d1e6ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89446221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.89446221
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.3661480323
Short name T447
Test name
Test status
Simulation time 171043349659 ps
CPU time 512.64 seconds
Started Aug 13 05:13:47 PM PDT 24
Finished Aug 13 05:22:20 PM PDT 24
Peak memory 200920 kb
Host smart-24c9bc4e-8a27-460a-b92f-46bc17caef5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661480323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3661480323
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.463187918
Short name T245
Test name
Test status
Simulation time 162557082491 ps
CPU time 237.42 seconds
Started Aug 13 05:13:49 PM PDT 24
Finished Aug 13 05:17:47 PM PDT 24
Peak memory 200932 kb
Host smart-8698c87b-2fa0-452c-8b0f-a1e90df0419e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463187918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.463187918
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.567663092
Short name T835
Test name
Test status
Simulation time 49438325027 ps
CPU time 71.07 seconds
Started Aug 13 05:13:49 PM PDT 24
Finished Aug 13 05:15:00 PM PDT 24
Peak memory 200788 kb
Host smart-14b9b396-40d0-4a79-84f6-2a882cd973d1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567663092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.567663092
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.895805251
Short name T984
Test name
Test status
Simulation time 103241092629 ps
CPU time 215.23 seconds
Started Aug 13 05:13:47 PM PDT 24
Finished Aug 13 05:17:23 PM PDT 24
Peak memory 200900 kb
Host smart-fd78e216-6d20-4585-9720-44e6c4ff7c0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=895805251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.895805251
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.1987769118
Short name T399
Test name
Test status
Simulation time 2219035767 ps
CPU time 2.9 seconds
Started Aug 13 05:13:53 PM PDT 24
Finished Aug 13 05:13:56 PM PDT 24
Peak memory 199180 kb
Host smart-f8593dca-9441-4c34-a45a-2c97b7e004ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987769118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1987769118
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.2589453840
Short name T256
Test name
Test status
Simulation time 25920526929 ps
CPU time 56.38 seconds
Started Aug 13 05:13:46 PM PDT 24
Finished Aug 13 05:14:43 PM PDT 24
Peak memory 199708 kb
Host smart-e1e89fc8-8289-448b-b676-3b73f6f8e1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589453840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2589453840
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.1828282227
Short name T269
Test name
Test status
Simulation time 23971137253 ps
CPU time 1082.21 seconds
Started Aug 13 05:13:48 PM PDT 24
Finished Aug 13 05:31:50 PM PDT 24
Peak memory 200800 kb
Host smart-d6c8de9c-6ece-45aa-a18b-b1792c872702
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1828282227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.1828282227
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1407929333
Short name T863
Test name
Test status
Simulation time 1569868418 ps
CPU time 4.43 seconds
Started Aug 13 05:13:47 PM PDT 24
Finished Aug 13 05:13:52 PM PDT 24
Peak memory 198992 kb
Host smart-83c727ff-9950-4132-a0d2-e70ff6cf9df3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1407929333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1407929333
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3467653719
Short name T315
Test name
Test status
Simulation time 112758761475 ps
CPU time 179.69 seconds
Started Aug 13 05:13:47 PM PDT 24
Finished Aug 13 05:16:47 PM PDT 24
Peak memory 200836 kb
Host smart-14218161-e9df-4680-bc2e-837f1a40f4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467653719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3467653719
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.2139310037
Short name T590
Test name
Test status
Simulation time 32226123825 ps
CPU time 18.12 seconds
Started Aug 13 05:13:48 PM PDT 24
Finished Aug 13 05:14:06 PM PDT 24
Peak memory 196660 kb
Host smart-b51f443c-9094-404e-92dd-c4aaa765c71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139310037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2139310037
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.993820306
Short name T294
Test name
Test status
Simulation time 6249245619 ps
CPU time 12.23 seconds
Started Aug 13 05:13:48 PM PDT 24
Finished Aug 13 05:14:01 PM PDT 24
Peak memory 200604 kb
Host smart-08119c06-aa0b-4466-88ed-918417375676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993820306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.993820306
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.1247445631
Short name T783
Test name
Test status
Simulation time 108122202794 ps
CPU time 195.61 seconds
Started Aug 13 05:13:52 PM PDT 24
Finished Aug 13 05:17:08 PM PDT 24
Peak memory 200848 kb
Host smart-6748c894-0104-4944-b2b3-6ebff45dd3e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247445631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1247445631
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.1750190018
Short name T531
Test name
Test status
Simulation time 18859466462 ps
CPU time 27.9 seconds
Started Aug 13 05:13:49 PM PDT 24
Finished Aug 13 05:14:17 PM PDT 24
Peak memory 210380 kb
Host smart-bef679d4-067e-4564-9d4f-9414607d718b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750190018 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1750190018
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.3668865179
Short name T776
Test name
Test status
Simulation time 472279709 ps
CPU time 1.92 seconds
Started Aug 13 05:13:49 PM PDT 24
Finished Aug 13 05:13:51 PM PDT 24
Peak memory 199680 kb
Host smart-a901c891-42ff-4070-b6bd-419ac44a49a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668865179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3668865179
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2239883325
Short name T509
Test name
Test status
Simulation time 38887074293 ps
CPU time 17.18 seconds
Started Aug 13 05:13:47 PM PDT 24
Finished Aug 13 05:14:04 PM PDT 24
Peak memory 200928 kb
Host smart-25d2cde8-8c8f-4c2f-877e-bda33f83e3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239883325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2239883325
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.4205481536
Short name T592
Test name
Test status
Simulation time 31209538298 ps
CPU time 19.03 seconds
Started Aug 13 05:16:21 PM PDT 24
Finished Aug 13 05:16:40 PM PDT 24
Peak memory 200788 kb
Host smart-d1285525-0337-4fc4-a288-59b3f0b2f8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205481536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.4205481536
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.1973814510
Short name T1178
Test name
Test status
Simulation time 4187667007 ps
CPU time 68.91 seconds
Started Aug 13 05:16:19 PM PDT 24
Finished Aug 13 05:17:28 PM PDT 24
Peak memory 217560 kb
Host smart-39a9be93-57b2-4398-a1a5-ead2ce6b81f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973814510 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.1973814510
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.2663443453
Short name T86
Test name
Test status
Simulation time 5085207674 ps
CPU time 43.97 seconds
Started Aug 13 05:16:26 PM PDT 24
Finished Aug 13 05:17:10 PM PDT 24
Peak memory 201396 kb
Host smart-7d85318c-7e15-4d31-8b0a-86e30d48a24f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663443453 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.2663443453
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2979297462
Short name T992
Test name
Test status
Simulation time 106420595727 ps
CPU time 352.36 seconds
Started Aug 13 05:16:29 PM PDT 24
Finished Aug 13 05:22:22 PM PDT 24
Peak memory 200860 kb
Host smart-33ba6b97-9f8f-4890-b305-d5474d348a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979297462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2979297462
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1663681723
Short name T778
Test name
Test status
Simulation time 10918683541 ps
CPU time 26.39 seconds
Started Aug 13 05:16:21 PM PDT 24
Finished Aug 13 05:16:48 PM PDT 24
Peak memory 209096 kb
Host smart-89f91c35-04b2-4389-8e4a-92b4f1372ee9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663681723 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1663681723
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.2782659614
Short name T258
Test name
Test status
Simulation time 23022720446 ps
CPU time 36.38 seconds
Started Aug 13 05:16:18 PM PDT 24
Finished Aug 13 05:16:54 PM PDT 24
Peak memory 200708 kb
Host smart-715b351c-3779-44e6-aa55-ae6922e50115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782659614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2782659614
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.110282042
Short name T701
Test name
Test status
Simulation time 4958066829 ps
CPU time 43.29 seconds
Started Aug 13 05:16:22 PM PDT 24
Finished Aug 13 05:17:05 PM PDT 24
Peak memory 216536 kb
Host smart-8fe4581e-4515-49ef-91bf-377dcab31011
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110282042 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.110282042
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.657311932
Short name T30
Test name
Test status
Simulation time 7544094436 ps
CPU time 38.25 seconds
Started Aug 13 05:16:21 PM PDT 24
Finished Aug 13 05:17:00 PM PDT 24
Peak memory 217276 kb
Host smart-e37a00d9-fe72-4369-870d-928d2ddd8d1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657311932 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.657311932
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.65787404
Short name T417
Test name
Test status
Simulation time 79459244292 ps
CPU time 28.07 seconds
Started Aug 13 05:16:21 PM PDT 24
Finished Aug 13 05:16:49 PM PDT 24
Peak memory 200872 kb
Host smart-65c6fd21-f70e-45cc-8dc2-f95850480e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65787404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.65787404
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.602899477
Short name T281
Test name
Test status
Simulation time 14596535627 ps
CPU time 80.48 seconds
Started Aug 13 05:16:29 PM PDT 24
Finished Aug 13 05:17:50 PM PDT 24
Peak memory 216604 kb
Host smart-2121df71-24e1-463d-b7e9-85ff893eb581
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602899477 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.602899477
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.2119256958
Short name T1009
Test name
Test status
Simulation time 108915611798 ps
CPU time 42.57 seconds
Started Aug 13 05:16:19 PM PDT 24
Finished Aug 13 05:17:02 PM PDT 24
Peak memory 200912 kb
Host smart-1128a133-349c-44fd-bf0f-4defa779260c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119256958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2119256958
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.1761132052
Short name T1159
Test name
Test status
Simulation time 2773254354 ps
CPU time 17.13 seconds
Started Aug 13 05:16:19 PM PDT 24
Finished Aug 13 05:16:36 PM PDT 24
Peak memory 216880 kb
Host smart-5f695a25-9ded-4b66-a153-4e196452fdf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761132052 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.1761132052
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1182468996
Short name T32
Test name
Test status
Simulation time 9629961954 ps
CPU time 25.94 seconds
Started Aug 13 05:16:22 PM PDT 24
Finished Aug 13 05:16:48 PM PDT 24
Peak memory 217268 kb
Host smart-0caf1dcc-4811-41fe-aace-bcf614b2ff61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182468996 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1182468996
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1657047057
Short name T800
Test name
Test status
Simulation time 23844716506 ps
CPU time 27.42 seconds
Started Aug 13 05:16:21 PM PDT 24
Finished Aug 13 05:16:49 PM PDT 24
Peak memory 200876 kb
Host smart-20b74477-8f1d-42a5-bd3d-17336663879a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657047057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1657047057
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.3779033990
Short name T649
Test name
Test status
Simulation time 15850815957 ps
CPU time 81.85 seconds
Started Aug 13 05:16:21 PM PDT 24
Finished Aug 13 05:17:43 PM PDT 24
Peak memory 216732 kb
Host smart-ffd42e83-3c75-4046-84b7-1712b71fc2f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779033990 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3779033990
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3932833508
Short name T182
Test name
Test status
Simulation time 150521276501 ps
CPU time 195.26 seconds
Started Aug 13 05:16:20 PM PDT 24
Finished Aug 13 05:19:36 PM PDT 24
Peak memory 200724 kb
Host smart-d55f0622-f8c3-4e01-80c2-349021f6b17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932833508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3932833508
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3185987490
Short name T611
Test name
Test status
Simulation time 3182169394 ps
CPU time 37.84 seconds
Started Aug 13 05:16:18 PM PDT 24
Finished Aug 13 05:16:56 PM PDT 24
Peak memory 209168 kb
Host smart-d18ce074-997c-45ad-b548-34cd9cc0db7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185987490 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3185987490
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3598532153
Short name T442
Test name
Test status
Simulation time 48562638 ps
CPU time 0.55 seconds
Started Aug 13 05:13:57 PM PDT 24
Finished Aug 13 05:13:58 PM PDT 24
Peak memory 196164 kb
Host smart-eeded4e6-3a97-44d7-936a-d904eed283ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598532153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3598532153
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.247666327
Short name T1006
Test name
Test status
Simulation time 170725317574 ps
CPU time 76.89 seconds
Started Aug 13 05:13:49 PM PDT 24
Finished Aug 13 05:15:07 PM PDT 24
Peak memory 200808 kb
Host smart-bd4c2f02-02ae-4ae3-adf1-1898df35eda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247666327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.247666327
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.172520773
Short name T190
Test name
Test status
Simulation time 165618006355 ps
CPU time 287.22 seconds
Started Aug 13 05:13:48 PM PDT 24
Finished Aug 13 05:18:35 PM PDT 24
Peak memory 200924 kb
Host smart-ff0ed0c0-1022-4f12-8f02-fdc632fb1273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172520773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.172520773
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1540177682
Short name T1174
Test name
Test status
Simulation time 55401324936 ps
CPU time 74.62 seconds
Started Aug 13 05:13:47 PM PDT 24
Finished Aug 13 05:15:01 PM PDT 24
Peak memory 200920 kb
Host smart-6968b339-eb30-4e64-ba5c-10ba515f8943
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1540177682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1540177682
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.3382844105
Short name T1169
Test name
Test status
Simulation time 9226866644 ps
CPU time 15.47 seconds
Started Aug 13 05:13:49 PM PDT 24
Finished Aug 13 05:14:04 PM PDT 24
Peak memory 200764 kb
Host smart-89609276-4341-4d2e-b8c6-017289e2101c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382844105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3382844105
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.671130393
Short name T1071
Test name
Test status
Simulation time 40298823217 ps
CPU time 26.78 seconds
Started Aug 13 05:13:47 PM PDT 24
Finished Aug 13 05:14:13 PM PDT 24
Peak memory 200428 kb
Host smart-49a34366-2c9f-4b1d-aee2-e244e7a2e8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671130393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.671130393
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.843856975
Short name T1086
Test name
Test status
Simulation time 16012406385 ps
CPU time 225.77 seconds
Started Aug 13 05:13:48 PM PDT 24
Finished Aug 13 05:17:34 PM PDT 24
Peak memory 200764 kb
Host smart-13a2b96f-19f5-4d50-b551-d0de4edd12f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=843856975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.843856975
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.203276060
Short name T920
Test name
Test status
Simulation time 4098101083 ps
CPU time 29.6 seconds
Started Aug 13 05:13:48 PM PDT 24
Finished Aug 13 05:14:17 PM PDT 24
Peak memory 200228 kb
Host smart-2caf3d83-75f6-4c31-b46d-797e3beccc79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=203276060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.203276060
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.34516625
Short name T310
Test name
Test status
Simulation time 127745256591 ps
CPU time 54.87 seconds
Started Aug 13 05:13:46 PM PDT 24
Finished Aug 13 05:14:41 PM PDT 24
Peak memory 200908 kb
Host smart-5802a4df-0d0a-4105-bf8b-0971ff63ad2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34516625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.34516625
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.496478367
Short name T678
Test name
Test status
Simulation time 341390964 ps
CPU time 1.12 seconds
Started Aug 13 05:13:48 PM PDT 24
Finished Aug 13 05:13:50 PM PDT 24
Peak memory 196336 kb
Host smart-c6e8509d-4276-4a56-a927-cf2ea9f06cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496478367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.496478367
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.3177817679
Short name T753
Test name
Test status
Simulation time 800016068 ps
CPU time 4.45 seconds
Started Aug 13 05:13:48 PM PDT 24
Finished Aug 13 05:13:52 PM PDT 24
Peak memory 199824 kb
Host smart-65766614-ae84-49e3-91f6-ba244817a463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177817679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3177817679
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.994766426
Short name T196
Test name
Test status
Simulation time 143157957099 ps
CPU time 342.8 seconds
Started Aug 13 05:13:51 PM PDT 24
Finished Aug 13 05:19:34 PM PDT 24
Peak memory 200932 kb
Host smart-c4f8fac2-83b5-420f-9e59-8af87eece643
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994766426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.994766426
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1223545530
Short name T92
Test name
Test status
Simulation time 9549651854 ps
CPU time 23.62 seconds
Started Aug 13 05:13:51 PM PDT 24
Finished Aug 13 05:14:15 PM PDT 24
Peak memory 217104 kb
Host smart-c14b83d5-2e94-4d6a-96c1-20738be30415
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223545530 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1223545530
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.1605266740
Short name T563
Test name
Test status
Simulation time 667438473 ps
CPU time 2.58 seconds
Started Aug 13 05:13:47 PM PDT 24
Finished Aug 13 05:13:50 PM PDT 24
Peak memory 200504 kb
Host smart-e50b298f-2708-41ce-bda6-88511e81daa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605266740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1605266740
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.959471177
Short name T698
Test name
Test status
Simulation time 39072789571 ps
CPU time 11.59 seconds
Started Aug 13 05:13:48 PM PDT 24
Finished Aug 13 05:14:00 PM PDT 24
Peak memory 200912 kb
Host smart-7666dd9c-1c8c-4551-a057-3fbb8a6928b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959471177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.959471177
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1328174947
Short name T248
Test name
Test status
Simulation time 35225049243 ps
CPU time 18.39 seconds
Started Aug 13 05:16:22 PM PDT 24
Finished Aug 13 05:16:40 PM PDT 24
Peak memory 200940 kb
Host smart-c4b53ff5-6d96-48f1-8111-a02383a5347c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328174947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1328174947
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3037427568
Short name T993
Test name
Test status
Simulation time 40340495264 ps
CPU time 42.56 seconds
Started Aug 13 05:16:29 PM PDT 24
Finished Aug 13 05:17:12 PM PDT 24
Peak memory 200952 kb
Host smart-212cb9bb-ff89-4602-a2ad-b06bd90a8457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037427568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3037427568
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1541432521
Short name T982
Test name
Test status
Simulation time 3273984457 ps
CPU time 35.62 seconds
Started Aug 13 05:16:22 PM PDT 24
Finished Aug 13 05:16:57 PM PDT 24
Peak memory 216796 kb
Host smart-a39b44cf-6f35-4ebd-9719-0340ddd06465
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541432521 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1541432521
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.1075254506
Short name T108
Test name
Test status
Simulation time 109165944194 ps
CPU time 162.12 seconds
Started Aug 13 05:16:29 PM PDT 24
Finished Aug 13 05:19:11 PM PDT 24
Peak memory 200956 kb
Host smart-f5bef00f-944b-4d87-9361-a072d63b5921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075254506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1075254506
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.2604803556
Short name T321
Test name
Test status
Simulation time 18552995665 ps
CPU time 59.36 seconds
Started Aug 13 05:16:22 PM PDT 24
Finished Aug 13 05:17:21 PM PDT 24
Peak memory 217544 kb
Host smart-144c77e2-4292-4c68-a7d8-5be9a1e58e5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604803556 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2604803556
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3185827164
Short name T239
Test name
Test status
Simulation time 254412937351 ps
CPU time 56.76 seconds
Started Aug 13 05:16:22 PM PDT 24
Finished Aug 13 05:17:19 PM PDT 24
Peak memory 200928 kb
Host smart-7601a065-e76a-4df0-8442-3b3da334ea81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185827164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3185827164
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.1740439391
Short name T91
Test name
Test status
Simulation time 1748336329 ps
CPU time 20.01 seconds
Started Aug 13 05:16:30 PM PDT 24
Finished Aug 13 05:16:50 PM PDT 24
Peak memory 217464 kb
Host smart-5e1133e5-c1ef-4352-9743-414dd677beaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740439391 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.1740439391
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.3573249018
Short name T464
Test name
Test status
Simulation time 5254879701 ps
CPU time 54.9 seconds
Started Aug 13 05:16:25 PM PDT 24
Finished Aug 13 05:17:20 PM PDT 24
Peak memory 209288 kb
Host smart-519f46e8-ffb3-4b75-91c4-40053025ce53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573249018 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.3573249018
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2524117070
Short name T970
Test name
Test status
Simulation time 193609414757 ps
CPU time 343.71 seconds
Started Aug 13 05:16:29 PM PDT 24
Finished Aug 13 05:22:13 PM PDT 24
Peak memory 200896 kb
Host smart-14daf840-01a4-43d8-ad5b-75b8fe2d25c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524117070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2524117070
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.2106405497
Short name T298
Test name
Test status
Simulation time 25493323669 ps
CPU time 37.18 seconds
Started Aug 13 05:16:29 PM PDT 24
Finished Aug 13 05:17:06 PM PDT 24
Peak memory 217368 kb
Host smart-0b3061a5-1b55-4aa3-8e1d-fbacfe47e03e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106405497 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2106405497
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3798313317
Short name T991
Test name
Test status
Simulation time 20629948749 ps
CPU time 33.14 seconds
Started Aug 13 05:16:26 PM PDT 24
Finished Aug 13 05:16:59 PM PDT 24
Peak memory 200908 kb
Host smart-1777d818-8674-4360-bb89-4fee9e5b9593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798313317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3798313317
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.140641089
Short name T1166
Test name
Test status
Simulation time 6202394435 ps
CPU time 100.54 seconds
Started Aug 13 05:16:27 PM PDT 24
Finished Aug 13 05:18:08 PM PDT 24
Peak memory 217500 kb
Host smart-b9cf8c30-6333-4c1f-80ec-7537be663bf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140641089 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.140641089
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1516006242
Short name T570
Test name
Test status
Simulation time 101562358305 ps
CPU time 166.84 seconds
Started Aug 13 05:16:26 PM PDT 24
Finished Aug 13 05:19:13 PM PDT 24
Peak memory 200748 kb
Host smart-c019bbb2-d956-4f46-8b5f-4aa49106ace0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516006242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1516006242
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3983648421
Short name T480
Test name
Test status
Simulation time 5102516797 ps
CPU time 18.75 seconds
Started Aug 13 05:16:29 PM PDT 24
Finished Aug 13 05:16:48 PM PDT 24
Peak memory 209208 kb
Host smart-eaea3c43-660f-469f-a03f-33f01f07fe81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983648421 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3983648421
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.361843093
Short name T488
Test name
Test status
Simulation time 53546980902 ps
CPU time 78.9 seconds
Started Aug 13 05:16:28 PM PDT 24
Finished Aug 13 05:17:47 PM PDT 24
Peak memory 200932 kb
Host smart-fe0853a0-3ce1-4074-bc6d-3fdc5cb11884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361843093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.361843093
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.986547250
Short name T414
Test name
Test status
Simulation time 3123465351 ps
CPU time 17.46 seconds
Started Aug 13 05:16:28 PM PDT 24
Finished Aug 13 05:16:46 PM PDT 24
Peak memory 216348 kb
Host smart-ac267c58-f395-4936-b7dd-260bd8ea571d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986547250 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.986547250
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.3021698071
Short name T539
Test name
Test status
Simulation time 12117259 ps
CPU time 0.57 seconds
Started Aug 13 05:13:51 PM PDT 24
Finished Aug 13 05:13:52 PM PDT 24
Peak memory 196244 kb
Host smart-f050ff47-1bd0-4912-bbd1-e504769e531a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021698071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3021698071
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3139139897
Short name T573
Test name
Test status
Simulation time 27246081659 ps
CPU time 43.53 seconds
Started Aug 13 05:13:51 PM PDT 24
Finished Aug 13 05:14:35 PM PDT 24
Peak memory 200808 kb
Host smart-4043235f-c776-496c-91ae-1701f5a4804e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139139897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3139139897
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.1140210459
Short name T669
Test name
Test status
Simulation time 36632332140 ps
CPU time 63.68 seconds
Started Aug 13 05:13:53 PM PDT 24
Finished Aug 13 05:14:57 PM PDT 24
Peak memory 200864 kb
Host smart-54d761d6-d24a-40c9-9495-2d11ad420a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140210459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1140210459
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_intr.133135475
Short name T354
Test name
Test status
Simulation time 37364841754 ps
CPU time 49.22 seconds
Started Aug 13 05:13:47 PM PDT 24
Finished Aug 13 05:14:37 PM PDT 24
Peak memory 199960 kb
Host smart-63a443dd-8600-431d-96c3-61d3026e0ff4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133135475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.133135475
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3380484932
Short name T550
Test name
Test status
Simulation time 60949289859 ps
CPU time 601.79 seconds
Started Aug 13 05:13:53 PM PDT 24
Finished Aug 13 05:23:55 PM PDT 24
Peak memory 200864 kb
Host smart-6e02f3c0-dc6d-4b0c-a969-bdef51c49a10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3380484932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3380484932
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2005693500
Short name T19
Test name
Test status
Simulation time 5199590845 ps
CPU time 2.81 seconds
Started Aug 13 05:13:48 PM PDT 24
Finished Aug 13 05:13:51 PM PDT 24
Peak memory 198168 kb
Host smart-113c2c77-c778-46ff-b804-ca9b49db4797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005693500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2005693500
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.1396131388
Short name T758
Test name
Test status
Simulation time 355467370220 ps
CPU time 60.33 seconds
Started Aug 13 05:13:49 PM PDT 24
Finished Aug 13 05:14:50 PM PDT 24
Peak memory 209304 kb
Host smart-a0ab03fe-c3ea-49b0-b2a3-764e88812bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396131388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1396131388
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.2027909784
Short name T900
Test name
Test status
Simulation time 15175522899 ps
CPU time 847.92 seconds
Started Aug 13 05:13:53 PM PDT 24
Finished Aug 13 05:28:01 PM PDT 24
Peak memory 200780 kb
Host smart-76312579-a208-4282-8e3e-d9c2549fdc90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2027909784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2027909784
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.890411061
Short name T482
Test name
Test status
Simulation time 1298885170 ps
CPU time 1.05 seconds
Started Aug 13 05:13:48 PM PDT 24
Finished Aug 13 05:13:49 PM PDT 24
Peak memory 196392 kb
Host smart-dba19c48-5469-4509-aaa6-aba276f92836
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=890411061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.890411061
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1181721840
Short name T458
Test name
Test status
Simulation time 100593241081 ps
CPU time 33.98 seconds
Started Aug 13 05:13:48 PM PDT 24
Finished Aug 13 05:14:22 PM PDT 24
Peak memory 200944 kb
Host smart-8220b4cd-3497-467f-86d6-46fe872da434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181721840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1181721840
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1256722919
Short name T400
Test name
Test status
Simulation time 2062217730 ps
CPU time 1.64 seconds
Started Aug 13 05:13:48 PM PDT 24
Finished Aug 13 05:13:50 PM PDT 24
Peak memory 196484 kb
Host smart-6031ac93-8792-4cb2-bc7c-bb5be6102601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256722919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1256722919
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1230720057
Short name T630
Test name
Test status
Simulation time 90291212 ps
CPU time 0.97 seconds
Started Aug 13 05:13:53 PM PDT 24
Finished Aug 13 05:13:54 PM PDT 24
Peak memory 199228 kb
Host smart-d001368d-fe2e-466f-976e-2cd9b4e72994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230720057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1230720057
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.850632777
Short name T342
Test name
Test status
Simulation time 277842124292 ps
CPU time 380.39 seconds
Started Aug 13 05:13:54 PM PDT 24
Finished Aug 13 05:20:14 PM PDT 24
Peak memory 200916 kb
Host smart-b08eecab-3e6a-48c6-abf3-b4106b64386f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850632777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.850632777
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.831891012
Short name T29
Test name
Test status
Simulation time 1561722070 ps
CPU time 21.17 seconds
Started Aug 13 05:14:05 PM PDT 24
Finished Aug 13 05:14:27 PM PDT 24
Peak memory 209324 kb
Host smart-05b11c4e-89d1-4ce0-9600-84b514d043dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831891012 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.831891012
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.2163237128
Short name T317
Test name
Test status
Simulation time 7009539792 ps
CPU time 23.23 seconds
Started Aug 13 05:13:49 PM PDT 24
Finished Aug 13 05:14:12 PM PDT 24
Peak memory 200576 kb
Host smart-05138831-fb55-4b6e-8ee1-3a3b65843373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163237128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2163237128
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.601289398
Short name T1014
Test name
Test status
Simulation time 60514371324 ps
CPU time 100.83 seconds
Started Aug 13 05:13:48 PM PDT 24
Finished Aug 13 05:15:29 PM PDT 24
Peak memory 200840 kb
Host smart-f8d10561-0f46-4fa3-8941-cd90f02b64c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601289398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.601289398
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2685456900
Short name T1145
Test name
Test status
Simulation time 185463719282 ps
CPU time 304.82 seconds
Started Aug 13 05:16:26 PM PDT 24
Finished Aug 13 05:21:31 PM PDT 24
Peak memory 200532 kb
Host smart-b755e22d-a324-4d91-a4a4-55d25d51ff3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685456900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2685456900
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.4253802681
Short name T319
Test name
Test status
Simulation time 1389527223 ps
CPU time 15.26 seconds
Started Aug 13 05:16:25 PM PDT 24
Finished Aug 13 05:16:41 PM PDT 24
Peak memory 217308 kb
Host smart-54f019bf-ccdf-4684-8419-69b551aa82c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253802681 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.4253802681
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.2156481819
Short name T928
Test name
Test status
Simulation time 69934753477 ps
CPU time 47.19 seconds
Started Aug 13 05:16:26 PM PDT 24
Finished Aug 13 05:17:13 PM PDT 24
Peak memory 200940 kb
Host smart-849ce36d-67e1-495f-bdcb-a694cf04ceca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156481819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2156481819
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3718814951
Short name T567
Test name
Test status
Simulation time 2594923360 ps
CPU time 44.01 seconds
Started Aug 13 05:16:26 PM PDT 24
Finished Aug 13 05:17:10 PM PDT 24
Peak memory 209356 kb
Host smart-816b2df4-34ce-4d63-a2ed-25ac85ced199
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718814951 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3718814951
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.1808384731
Short name T397
Test name
Test status
Simulation time 14530005063 ps
CPU time 12.21 seconds
Started Aug 13 05:16:28 PM PDT 24
Finished Aug 13 05:16:40 PM PDT 24
Peak memory 200440 kb
Host smart-4a907228-ee6b-4830-b1eb-e4edef1b5a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808384731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1808384731
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.1486040400
Short name T264
Test name
Test status
Simulation time 13630610715 ps
CPU time 53.36 seconds
Started Aug 13 05:16:28 PM PDT 24
Finished Aug 13 05:17:22 PM PDT 24
Peak memory 217576 kb
Host smart-89ee5fed-54af-4aea-8056-a6cb62f7263f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486040400 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1486040400
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.30242341
Short name T949
Test name
Test status
Simulation time 100671613443 ps
CPU time 158.33 seconds
Started Aug 13 05:16:25 PM PDT 24
Finished Aug 13 05:19:04 PM PDT 24
Peak memory 200844 kb
Host smart-4a9ce6f1-0f70-40b4-93fb-3ebf5b0ba4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30242341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.30242341
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3217318826
Short name T422
Test name
Test status
Simulation time 4162460667 ps
CPU time 34.04 seconds
Started Aug 13 05:16:27 PM PDT 24
Finished Aug 13 05:17:01 PM PDT 24
Peak memory 217540 kb
Host smart-76c41f7d-4287-41b7-be92-2b36ce510e98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217318826 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3217318826
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2478570923
Short name T522
Test name
Test status
Simulation time 238756349302 ps
CPU time 54.43 seconds
Started Aug 13 05:16:28 PM PDT 24
Finished Aug 13 05:17:22 PM PDT 24
Peak memory 200924 kb
Host smart-52e88449-92ec-4733-8004-6eafef84ab76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478570923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2478570923
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3869038126
Short name T1160
Test name
Test status
Simulation time 11794762837 ps
CPU time 37.12 seconds
Started Aug 13 05:16:27 PM PDT 24
Finished Aug 13 05:17:04 PM PDT 24
Peak memory 209396 kb
Host smart-8dc90a43-56f8-411a-9e7f-2c080bdc0244
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869038126 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3869038126
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.753920357
Short name T185
Test name
Test status
Simulation time 24733865456 ps
CPU time 35.02 seconds
Started Aug 13 05:16:28 PM PDT 24
Finished Aug 13 05:17:03 PM PDT 24
Peak memory 200720 kb
Host smart-c48c4ad0-dc9d-40d4-a781-48efc26af97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753920357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.753920357
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1443530080
Short name T1050
Test name
Test status
Simulation time 1738688321 ps
CPU time 14.42 seconds
Started Aug 13 05:16:27 PM PDT 24
Finished Aug 13 05:16:41 PM PDT 24
Peak memory 200816 kb
Host smart-df834497-3704-47cb-88c2-c00a231797a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443530080 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1443530080
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.506342421
Short name T331
Test name
Test status
Simulation time 42272201892 ps
CPU time 68.83 seconds
Started Aug 13 05:16:27 PM PDT 24
Finished Aug 13 05:17:36 PM PDT 24
Peak memory 200924 kb
Host smart-ecaed7eb-4b7c-4104-b090-3dbcbcd10ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506342421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.506342421
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1994728313
Short name T159
Test name
Test status
Simulation time 12828140889 ps
CPU time 63.87 seconds
Started Aug 13 05:16:29 PM PDT 24
Finished Aug 13 05:17:33 PM PDT 24
Peak memory 217412 kb
Host smart-ccb3554c-59b9-4145-aea7-6e74a0f9d1af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994728313 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1994728313
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.973981462
Short name T620
Test name
Test status
Simulation time 68806211720 ps
CPU time 30 seconds
Started Aug 13 05:16:27 PM PDT 24
Finished Aug 13 05:16:57 PM PDT 24
Peak memory 200472 kb
Host smart-0cedb479-4cd0-4116-9837-16682f5f0b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973981462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.973981462
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1952217526
Short name T773
Test name
Test status
Simulation time 8584389653 ps
CPU time 29.86 seconds
Started Aug 13 05:16:28 PM PDT 24
Finished Aug 13 05:16:58 PM PDT 24
Peak memory 209324 kb
Host smart-0d6994c1-8ffe-48ca-bd3b-d2a7ebbec6f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952217526 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1952217526
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.2138298780
Short name T213
Test name
Test status
Simulation time 26429483482 ps
CPU time 21.1 seconds
Started Aug 13 05:16:28 PM PDT 24
Finished Aug 13 05:16:49 PM PDT 24
Peak memory 200852 kb
Host smart-1994fc23-1f46-430f-b302-7e7a976ce446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138298780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2138298780
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.793982538
Short name T565
Test name
Test status
Simulation time 15199032894 ps
CPU time 39.27 seconds
Started Aug 13 05:16:25 PM PDT 24
Finished Aug 13 05:17:04 PM PDT 24
Peak memory 210712 kb
Host smart-10d841b3-a961-424e-9344-818d90603dc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793982538 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.793982538
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.175812419
Short name T968
Test name
Test status
Simulation time 16395705276 ps
CPU time 18.43 seconds
Started Aug 13 05:16:29 PM PDT 24
Finished Aug 13 05:16:47 PM PDT 24
Peak memory 200912 kb
Host smart-52d0151d-1cdb-4d8b-9cf5-b7c75d75dc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175812419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.175812419
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2347152062
Short name T812
Test name
Test status
Simulation time 3242156660 ps
CPU time 10.97 seconds
Started Aug 13 05:16:25 PM PDT 24
Finished Aug 13 05:16:36 PM PDT 24
Peak memory 209200 kb
Host smart-a81cc2d4-0888-42f3-8973-b004f9d1ac81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347152062 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2347152062
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1968090462
Short name T1057
Test name
Test status
Simulation time 17490658 ps
CPU time 0.54 seconds
Started Aug 13 05:13:54 PM PDT 24
Finished Aug 13 05:13:54 PM PDT 24
Peak memory 195228 kb
Host smart-f6c55418-8da0-4f71-9a0f-0dbd7b971427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968090462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1968090462
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.322407623
Short name T973
Test name
Test status
Simulation time 115761031542 ps
CPU time 283.08 seconds
Started Aug 13 05:13:55 PM PDT 24
Finished Aug 13 05:18:38 PM PDT 24
Peak memory 200792 kb
Host smart-7e5bceb9-d776-4829-aeb2-ce652d51c46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322407623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.322407623
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.686162828
Short name T432
Test name
Test status
Simulation time 26922304531 ps
CPU time 11.03 seconds
Started Aug 13 05:14:03 PM PDT 24
Finished Aug 13 05:14:15 PM PDT 24
Peak memory 199404 kb
Host smart-6de254b9-1532-4b59-ac5c-ca12f43708e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686162828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.686162828
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2938000447
Short name T1122
Test name
Test status
Simulation time 30913741671 ps
CPU time 48.57 seconds
Started Aug 13 05:13:52 PM PDT 24
Finished Aug 13 05:14:40 PM PDT 24
Peak memory 200876 kb
Host smart-839bcf9f-52a5-48a0-a1a4-02a1f96699a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938000447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2938000447
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.61087231
Short name T96
Test name
Test status
Simulation time 16539322387 ps
CPU time 9.75 seconds
Started Aug 13 05:13:54 PM PDT 24
Finished Aug 13 05:14:04 PM PDT 24
Peak memory 200836 kb
Host smart-ba24df6f-64f3-430b-8532-fb4f6b082bc2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61087231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.61087231
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.350262268
Short name T1074
Test name
Test status
Simulation time 66454644060 ps
CPU time 404.76 seconds
Started Aug 13 05:13:53 PM PDT 24
Finished Aug 13 05:20:38 PM PDT 24
Peak memory 200932 kb
Host smart-8f9921d8-bf6b-489d-8d6c-93319d8ffa73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=350262268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.350262268
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1583241213
Short name T18
Test name
Test status
Simulation time 5924137648 ps
CPU time 5.65 seconds
Started Aug 13 05:14:04 PM PDT 24
Finished Aug 13 05:14:10 PM PDT 24
Peak memory 200312 kb
Host smart-e2b36025-ecbe-4264-81e0-c0351bba6668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583241213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1583241213
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.1751892212
Short name T898
Test name
Test status
Simulation time 8688713100 ps
CPU time 8.19 seconds
Started Aug 13 05:13:57 PM PDT 24
Finished Aug 13 05:14:06 PM PDT 24
Peak memory 200788 kb
Host smart-c45b4301-5b97-4cee-b9d9-8a740294a885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751892212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1751892212
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3915963268
Short name T448
Test name
Test status
Simulation time 15172094958 ps
CPU time 338.22 seconds
Started Aug 13 05:13:53 PM PDT 24
Finished Aug 13 05:19:31 PM PDT 24
Peak memory 200900 kb
Host smart-a09e42f4-970d-4a87-8527-4888d5ba193c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3915963268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3915963268
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1568631017
Short name T636
Test name
Test status
Simulation time 6089882656 ps
CPU time 50.26 seconds
Started Aug 13 05:13:53 PM PDT 24
Finished Aug 13 05:14:44 PM PDT 24
Peak memory 199892 kb
Host smart-ea07b5d1-07ae-432e-9369-bd1798deee9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1568631017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1568631017
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2331503226
Short name T392
Test name
Test status
Simulation time 52126471425 ps
CPU time 22.7 seconds
Started Aug 13 05:13:54 PM PDT 24
Finished Aug 13 05:14:17 PM PDT 24
Peak memory 200936 kb
Host smart-48f47eb1-db63-491b-a11c-ab49c86ddcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331503226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2331503226
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.568696714
Short name T446
Test name
Test status
Simulation time 42736993300 ps
CPU time 55.7 seconds
Started Aug 13 05:13:58 PM PDT 24
Finished Aug 13 05:14:54 PM PDT 24
Peak memory 197128 kb
Host smart-1e0c46dd-9902-4ecc-b69b-6cb054b6605e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568696714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.568696714
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.1849369613
Short name T576
Test name
Test status
Simulation time 712937683 ps
CPU time 2.93 seconds
Started Aug 13 05:13:53 PM PDT 24
Finished Aug 13 05:13:56 PM PDT 24
Peak memory 200440 kb
Host smart-11550e2b-ce09-4b3f-a231-12fdec432eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849369613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1849369613
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1866987570
Short name T1044
Test name
Test status
Simulation time 3509819302 ps
CPU time 42.65 seconds
Started Aug 13 05:14:00 PM PDT 24
Finished Aug 13 05:14:43 PM PDT 24
Peak memory 209380 kb
Host smart-a46ce7d4-cb94-4a38-aba9-52004871fbd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866987570 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1866987570
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.2158373565
Short name T474
Test name
Test status
Simulation time 1029194468 ps
CPU time 1.82 seconds
Started Aug 13 05:13:52 PM PDT 24
Finished Aug 13 05:13:54 PM PDT 24
Peak memory 199576 kb
Host smart-eaf4a49c-be05-4207-adb5-ef6ac6ec71d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158373565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2158373565
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.208174428
Short name T594
Test name
Test status
Simulation time 18019627690 ps
CPU time 7.08 seconds
Started Aug 13 05:13:52 PM PDT 24
Finished Aug 13 05:13:59 PM PDT 24
Peak memory 198564 kb
Host smart-98a5ae60-27d9-4c53-895b-9505cddd153c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208174428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.208174428
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.1406626808
Short name T663
Test name
Test status
Simulation time 5912638574 ps
CPU time 6.59 seconds
Started Aug 13 05:16:26 PM PDT 24
Finished Aug 13 05:16:32 PM PDT 24
Peak memory 200892 kb
Host smart-d5f3c476-0b4e-4def-b69e-617ed6b4696f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406626808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1406626808
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3484998867
Short name T1051
Test name
Test status
Simulation time 1765578645 ps
CPU time 23.98 seconds
Started Aug 13 05:16:26 PM PDT 24
Finished Aug 13 05:16:51 PM PDT 24
Peak memory 200748 kb
Host smart-abd19dec-7428-4830-9790-9b49415bbf67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484998867 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3484998867
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.890175388
Short name T551
Test name
Test status
Simulation time 27463150946 ps
CPU time 12.49 seconds
Started Aug 13 05:16:27 PM PDT 24
Finished Aug 13 05:16:40 PM PDT 24
Peak memory 200900 kb
Host smart-468c74bb-5863-4b67-9742-e36f0b043e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890175388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.890175388
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.902161915
Short name T1079
Test name
Test status
Simulation time 91224388729 ps
CPU time 39.33 seconds
Started Aug 13 05:16:24 PM PDT 24
Finished Aug 13 05:17:04 PM PDT 24
Peak memory 200900 kb
Host smart-b9b61e3c-bd55-4b31-a82e-c65d66df4d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902161915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.902161915
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.935720003
Short name T344
Test name
Test status
Simulation time 1331012440 ps
CPU time 16.77 seconds
Started Aug 13 05:16:29 PM PDT 24
Finished Aug 13 05:16:46 PM PDT 24
Peak memory 200944 kb
Host smart-e769b769-77a6-4157-8f45-4b72e954324d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935720003 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.935720003
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2539331619
Short name T751
Test name
Test status
Simulation time 3607040036 ps
CPU time 24.01 seconds
Started Aug 13 05:16:40 PM PDT 24
Finished Aug 13 05:17:04 PM PDT 24
Peak memory 217364 kb
Host smart-5d3b3501-809d-4281-a648-3a7eaf38bc14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539331619 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2539331619
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.3470013584
Short name T737
Test name
Test status
Simulation time 691091035 ps
CPU time 11.4 seconds
Started Aug 13 05:16:40 PM PDT 24
Finished Aug 13 05:16:52 PM PDT 24
Peak memory 200840 kb
Host smart-06fefadd-e332-4892-96ca-bacb08236eed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470013584 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3470013584
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2414737492
Short name T1144
Test name
Test status
Simulation time 137341570742 ps
CPU time 69.44 seconds
Started Aug 13 05:16:43 PM PDT 24
Finished Aug 13 05:17:52 PM PDT 24
Peak memory 200916 kb
Host smart-dcf0499b-13be-484e-923d-1b7cc086bb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414737492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2414737492
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2632849686
Short name T512
Test name
Test status
Simulation time 25369477176 ps
CPU time 55.61 seconds
Started Aug 13 05:16:43 PM PDT 24
Finished Aug 13 05:17:39 PM PDT 24
Peak memory 217344 kb
Host smart-1acc07a0-a343-4f71-9ced-6d10fe833818
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632849686 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2632849686
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.95622945
Short name T1038
Test name
Test status
Simulation time 23808281721 ps
CPU time 19.73 seconds
Started Aug 13 05:16:40 PM PDT 24
Finished Aug 13 05:17:00 PM PDT 24
Peak memory 200820 kb
Host smart-b2f0646e-687d-4dc3-bda8-b5f6ef616698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95622945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.95622945
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.2708397763
Short name T1164
Test name
Test status
Simulation time 6317892226 ps
CPU time 8.73 seconds
Started Aug 13 05:16:42 PM PDT 24
Finished Aug 13 05:16:51 PM PDT 24
Peak memory 216472 kb
Host smart-77f188ec-e478-4b78-b1dd-b8250801d4c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708397763 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.2708397763
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2744050745
Short name T1106
Test name
Test status
Simulation time 150539633397 ps
CPU time 19.7 seconds
Started Aug 13 05:16:39 PM PDT 24
Finished Aug 13 05:16:59 PM PDT 24
Peak memory 200936 kb
Host smart-fb7b7c31-d208-46f4-9c18-269175152188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744050745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2744050745
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.2018880049
Short name T561
Test name
Test status
Simulation time 16342731948 ps
CPU time 21.18 seconds
Started Aug 13 05:16:41 PM PDT 24
Finished Aug 13 05:17:02 PM PDT 24
Peak memory 217228 kb
Host smart-7da38e06-0168-49ac-8fdf-e24c054b3353
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018880049 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.2018880049
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2777236069
Short name T972
Test name
Test status
Simulation time 1040900799 ps
CPU time 54.57 seconds
Started Aug 13 05:16:42 PM PDT 24
Finished Aug 13 05:17:37 PM PDT 24
Peak memory 200872 kb
Host smart-cfd92a85-1f14-4f06-8823-99e16de477f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777236069 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2777236069
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.933952662
Short name T347
Test name
Test status
Simulation time 53066056650 ps
CPU time 21.09 seconds
Started Aug 13 05:16:40 PM PDT 24
Finished Aug 13 05:17:02 PM PDT 24
Peak memory 200900 kb
Host smart-6cb36875-c550-4f02-a591-2df21478c439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933952662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.933952662
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.613643627
Short name T20
Test name
Test status
Simulation time 3009015915 ps
CPU time 27.17 seconds
Started Aug 13 05:16:40 PM PDT 24
Finished Aug 13 05:17:08 PM PDT 24
Peak memory 209460 kb
Host smart-5d8be7c9-663f-43d0-9204-0e49f400f53c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613643627 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.613643627
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.2652412746
Short name T21
Test name
Test status
Simulation time 44776194 ps
CPU time 0.61 seconds
Started Aug 13 05:13:56 PM PDT 24
Finished Aug 13 05:13:57 PM PDT 24
Peak memory 196216 kb
Host smart-1a971261-fc9c-4980-9ec9-762250286bfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652412746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2652412746
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.522524088
Short name T687
Test name
Test status
Simulation time 92543381951 ps
CPU time 49.91 seconds
Started Aug 13 05:14:05 PM PDT 24
Finished Aug 13 05:14:55 PM PDT 24
Peak memory 200924 kb
Host smart-4ba47c0f-6ce0-4672-90dc-673f89c6f0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522524088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.522524088
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1107821409
Short name T166
Test name
Test status
Simulation time 80725674189 ps
CPU time 38.71 seconds
Started Aug 13 05:14:01 PM PDT 24
Finished Aug 13 05:14:40 PM PDT 24
Peak memory 200880 kb
Host smart-086e055a-494c-40c0-a19c-ec697bd4cf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107821409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1107821409
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_intr.2361357795
Short name T79
Test name
Test status
Simulation time 8321295560 ps
CPU time 7.18 seconds
Started Aug 13 05:13:56 PM PDT 24
Finished Aug 13 05:14:04 PM PDT 24
Peak memory 200916 kb
Host smart-172117e5-e307-4e81-9870-3cdf5e2e22ca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361357795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2361357795
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2948105085
Short name T588
Test name
Test status
Simulation time 44411983004 ps
CPU time 419.91 seconds
Started Aug 13 05:13:56 PM PDT 24
Finished Aug 13 05:20:56 PM PDT 24
Peak memory 200924 kb
Host smart-9878f8bc-658e-4fd3-91fc-69344dd1fa94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2948105085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2948105085
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1890198884
Short name T364
Test name
Test status
Simulation time 9078544998 ps
CPU time 12.68 seconds
Started Aug 13 05:13:54 PM PDT 24
Finished Aug 13 05:14:07 PM PDT 24
Peak memory 199248 kb
Host smart-5743bdb4-d14c-46b4-adfd-08c6e2f61191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890198884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1890198884
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.4287156946
Short name T543
Test name
Test status
Simulation time 45956207237 ps
CPU time 16.2 seconds
Started Aug 13 05:13:53 PM PDT 24
Finished Aug 13 05:14:09 PM PDT 24
Peak memory 199404 kb
Host smart-9a450d51-c1ce-41af-8a32-db0a0d6d91bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287156946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.4287156946
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.2706774652
Short name T507
Test name
Test status
Simulation time 24341422697 ps
CPU time 325.25 seconds
Started Aug 13 05:13:59 PM PDT 24
Finished Aug 13 05:19:24 PM PDT 24
Peak memory 200864 kb
Host smart-b30ecf8b-37da-4bc8-aa09-ae59d7e471a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2706774652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2706774652
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.4117745204
Short name T372
Test name
Test status
Simulation time 1593006784 ps
CPU time 6.27 seconds
Started Aug 13 05:13:54 PM PDT 24
Finished Aug 13 05:14:00 PM PDT 24
Peak memory 199436 kb
Host smart-7877c539-6db9-4c45-8c54-b62a2036dfd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4117745204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.4117745204
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.1302379574
Short name T1007
Test name
Test status
Simulation time 128494782896 ps
CPU time 53.86 seconds
Started Aug 13 05:13:52 PM PDT 24
Finished Aug 13 05:14:46 PM PDT 24
Peak memory 198852 kb
Host smart-0f1b932d-bd1b-4b8d-823e-dc1a19cc7826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302379574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1302379574
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2363650509
Short name T1031
Test name
Test status
Simulation time 6878023921 ps
CPU time 10.69 seconds
Started Aug 13 05:13:54 PM PDT 24
Finished Aug 13 05:14:04 PM PDT 24
Peak memory 197356 kb
Host smart-bf3c3bae-44c9-43b3-a3c0-e5d86fabd6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363650509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2363650509
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.3311188021
Short name T787
Test name
Test status
Simulation time 490334272 ps
CPU time 1.22 seconds
Started Aug 13 05:13:55 PM PDT 24
Finished Aug 13 05:13:57 PM PDT 24
Peak memory 200784 kb
Host smart-a6257dc9-2d4e-4620-91fd-18b6721cd735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311188021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3311188021
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.2857717100
Short name T1018
Test name
Test status
Simulation time 149444075879 ps
CPU time 1224.15 seconds
Started Aug 13 05:13:56 PM PDT 24
Finished Aug 13 05:34:20 PM PDT 24
Peak memory 209336 kb
Host smart-c6bbc037-ec6a-4360-89c4-e6df6e9497f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857717100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.2857717100
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.549966592
Short name T600
Test name
Test status
Simulation time 8256714672 ps
CPU time 29.78 seconds
Started Aug 13 05:13:53 PM PDT 24
Finished Aug 13 05:14:23 PM PDT 24
Peak memory 209348 kb
Host smart-cf81a93f-cfb0-4d2e-b289-35426def9679
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549966592 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.549966592
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.153906682
Short name T648
Test name
Test status
Simulation time 1185480052 ps
CPU time 1.92 seconds
Started Aug 13 05:13:55 PM PDT 24
Finished Aug 13 05:13:57 PM PDT 24
Peak memory 199468 kb
Host smart-f2a210bb-181b-4a36-bb39-20d5678c445e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153906682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.153906682
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2695525894
Short name T797
Test name
Test status
Simulation time 56154268395 ps
CPU time 128.98 seconds
Started Aug 13 05:13:54 PM PDT 24
Finished Aug 13 05:16:03 PM PDT 24
Peak memory 200928 kb
Host smart-ca6e9fad-148d-4d8d-86bf-d5bf39b690ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695525894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2695525894
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.266649771
Short name T624
Test name
Test status
Simulation time 119930467213 ps
CPU time 64.86 seconds
Started Aug 13 05:16:39 PM PDT 24
Finished Aug 13 05:17:44 PM PDT 24
Peak memory 201072 kb
Host smart-98665750-2ec3-46e2-9cac-f68452e97453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266649771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.266649771
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.2797127297
Short name T303
Test name
Test status
Simulation time 5342475854 ps
CPU time 74.59 seconds
Started Aug 13 05:16:40 PM PDT 24
Finished Aug 13 05:17:55 PM PDT 24
Peak memory 200984 kb
Host smart-e72c0566-66d6-44aa-a354-ede58730a14a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797127297 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2797127297
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2542742362
Short name T1147
Test name
Test status
Simulation time 103004222329 ps
CPU time 138.51 seconds
Started Aug 13 05:16:41 PM PDT 24
Finished Aug 13 05:19:00 PM PDT 24
Peak memory 200948 kb
Host smart-9f77f0f6-cf46-4246-9f12-f410c3fa0f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542742362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2542742362
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2109684420
Short name T180
Test name
Test status
Simulation time 47161353031 ps
CPU time 37.69 seconds
Started Aug 13 05:16:42 PM PDT 24
Finished Aug 13 05:17:19 PM PDT 24
Peak memory 209192 kb
Host smart-acec9283-65c1-48e0-ba1c-19303d98f09c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109684420 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2109684420
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.1059759795
Short name T217
Test name
Test status
Simulation time 75353282029 ps
CPU time 14.31 seconds
Started Aug 13 05:16:41 PM PDT 24
Finished Aug 13 05:16:56 PM PDT 24
Peak memory 200940 kb
Host smart-4d19fe73-1c87-43ce-87db-21c91d679b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059759795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1059759795
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3198064394
Short name T1098
Test name
Test status
Simulation time 8802597862 ps
CPU time 26.31 seconds
Started Aug 13 05:16:41 PM PDT 24
Finished Aug 13 05:17:07 PM PDT 24
Peak memory 217560 kb
Host smart-50bc7e7c-4609-4f15-bb8b-ffe97c5c97bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198064394 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3198064394
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.4038661768
Short name T147
Test name
Test status
Simulation time 61050439393 ps
CPU time 22.67 seconds
Started Aug 13 05:16:42 PM PDT 24
Finished Aug 13 05:17:05 PM PDT 24
Peak memory 200892 kb
Host smart-20e5f244-9238-4244-b9c9-023132848066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038661768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.4038661768
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.4158191304
Short name T677
Test name
Test status
Simulation time 3926440586 ps
CPU time 60.45 seconds
Started Aug 13 05:16:42 PM PDT 24
Finished Aug 13 05:17:43 PM PDT 24
Peak memory 210396 kb
Host smart-5af663aa-f116-4972-9650-80cd9ef6042f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158191304 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.4158191304
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1727787195
Short name T1017
Test name
Test status
Simulation time 1697450382 ps
CPU time 22.9 seconds
Started Aug 13 05:16:41 PM PDT 24
Finished Aug 13 05:17:04 PM PDT 24
Peak memory 209336 kb
Host smart-5e03b823-eccc-4f7f-b1ec-b262529d0e54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727787195 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1727787195
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1365021753
Short name T577
Test name
Test status
Simulation time 117332301136 ps
CPU time 262.53 seconds
Started Aug 13 05:16:41 PM PDT 24
Finished Aug 13 05:21:03 PM PDT 24
Peak memory 200872 kb
Host smart-c4f38338-9e25-44c8-bb12-3b00278ff60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365021753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1365021753
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.3808831953
Short name T535
Test name
Test status
Simulation time 3171693441 ps
CPU time 46.24 seconds
Started Aug 13 05:16:40 PM PDT 24
Finished Aug 13 05:17:27 PM PDT 24
Peak memory 210164 kb
Host smart-b87e45fa-88c0-4cfe-aa5d-c9728b002160
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808831953 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3808831953
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.365272859
Short name T775
Test name
Test status
Simulation time 104651544241 ps
CPU time 82.51 seconds
Started Aug 13 05:16:41 PM PDT 24
Finished Aug 13 05:18:03 PM PDT 24
Peak memory 200872 kb
Host smart-776a4fd6-571f-427e-b834-a0d09a9ef58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365272859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.365272859
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3321044518
Short name T818
Test name
Test status
Simulation time 1413690123 ps
CPU time 51.41 seconds
Started Aug 13 05:16:39 PM PDT 24
Finished Aug 13 05:17:31 PM PDT 24
Peak memory 217204 kb
Host smart-61241383-9baf-48fc-8d35-f32064bf5a9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321044518 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3321044518
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2407264083
Short name T151
Test name
Test status
Simulation time 136639844382 ps
CPU time 26.35 seconds
Started Aug 13 05:16:40 PM PDT 24
Finished Aug 13 05:17:06 PM PDT 24
Peak memory 200784 kb
Host smart-409a5f12-436c-4bf8-b32f-a66346df5d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407264083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2407264083
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.110188990
Short name T1028
Test name
Test status
Simulation time 1828520516 ps
CPU time 30.78 seconds
Started Aug 13 05:16:39 PM PDT 24
Finished Aug 13 05:17:10 PM PDT 24
Peak memory 209408 kb
Host smart-a5c9e2ae-7d5f-4ba9-80b9-76f2a2c7f5e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110188990 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.110188990
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1455058619
Short name T921
Test name
Test status
Simulation time 95323882626 ps
CPU time 134.64 seconds
Started Aug 13 05:16:43 PM PDT 24
Finished Aug 13 05:18:57 PM PDT 24
Peak memory 200912 kb
Host smart-72cb46e9-ba4f-4b23-88fb-0002bef8e755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455058619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1455058619
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.2409060641
Short name T1027
Test name
Test status
Simulation time 2788691863 ps
CPU time 32.67 seconds
Started Aug 13 05:16:43 PM PDT 24
Finished Aug 13 05:17:15 PM PDT 24
Peak memory 217488 kb
Host smart-99e0663d-237d-4da4-a161-1314b1de5196
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409060641 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.2409060641
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.2664034919
Short name T518
Test name
Test status
Simulation time 110344690018 ps
CPU time 181.66 seconds
Started Aug 13 05:16:42 PM PDT 24
Finished Aug 13 05:19:43 PM PDT 24
Peak memory 200880 kb
Host smart-71b395a7-87b4-4012-a342-393017f391b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664034919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2664034919
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.135890046
Short name T625
Test name
Test status
Simulation time 8062398368 ps
CPU time 49.95 seconds
Started Aug 13 05:16:40 PM PDT 24
Finished Aug 13 05:17:30 PM PDT 24
Peak memory 217260 kb
Host smart-a7f44ab1-918c-422f-b826-07641d9591a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135890046 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.135890046
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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