Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	89183	1			T1	26		T2	2		T3	26
all_values[1]	89183	1			T1	26		T2	2		T3	26
all_values[2]	89183	1			T1	26		T2	2		T3	26
all_values[3]	89183	1			T1	26		T2	2		T3	26
all_values[4]	89183	1			T1	26		T2	2		T3	26
all_values[5]	89183	1			T1	26		T2	2		T3	26
all_values[6]	89183	1			T1	26		T2	2		T3	26
all_values[7]	89183	1			T1	26		T2	2		T3	26
all_values[8]	89183	1			T1	26		T2	2		T3	26

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

400266

1

T1

114

T2

18

T3

137

auto[1]

402381

1

T1

120

T3

97

T4

175

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

725833

1

T1

226

T2

13

T3

179

auto[1]

76814

1

T1

8

T2

5

T3

55

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	26703	1			T1	10		T3	4		T5	5
all_values[0]	auto[0]	auto[1]	17502	1			T1	1		T2	2		T3	4
all_values[0]	auto[1]	auto[0]	24175	1			T1	13		T3	4		T6	3
all_values[0]	auto[1]	auto[1]	20803	1			T1	2		T3	14		T4	25
all_values[1]	auto[0]	auto[0]	44972	1			T1	25		T2	2		T3	7
all_values[1]	auto[0]	auto[1]	1290	1			T5	2		T6	2		T8	1
all_values[1]	auto[1]	auto[0]	41474	1			T3	5		T4	25		T6	3
all_values[1]	auto[1]	auto[1]	1447	1			T1	1		T3	14		T8	1
all_values[2]	auto[0]	auto[0]	41244	1			T1	14		T2	1		T3	24
all_values[2]	auto[0]	auto[1]	2173	1			T1	1		T2	1		T3	2
all_values[2]	auto[1]	auto[0]	43766	1			T1	11		T4	25		T5	5
all_values[2]	auto[1]	auto[1]	2000	1			T5	3		T7	3		T8	5
all_values[3]	auto[0]	auto[0]	42661	1			T1	11		T2	2		T3	10
all_values[3]	auto[0]	auto[1]	256	1			T12	1		T14	1		T128	1
all_values[3]	auto[1]	auto[0]	46002	1			T1	15		T3	12		T4	10
all_values[3]	auto[1]	auto[1]	264	1			T3	4		T8	4		T14	3
all_values[4]	auto[0]	auto[0]	46625	1			T1	16		T2	2		T3	24
all_values[4]	auto[0]	auto[1]	390	1			T14	2		T16	9		T18	6
all_values[4]	auto[1]	auto[0]	41785	1			T1	10		T3	2		T4	25
all_values[4]	auto[1]	auto[1]	383	1			T12	8		T14	4		T15	1
all_values[5]	auto[0]	auto[0]	44080	1			T1	9		T2	2		T3	21
all_values[5]	auto[0]	auto[1]	150	1			T14	2		T34	3		T83	4
all_values[5]	auto[1]	auto[0]	44813	1			T1	17		T3	5		T4	15
all_values[5]	auto[1]	auto[1]	140	1			T14	1		T15	3		T34	3
all_values[6]	auto[0]	auto[0]	42743	1			T1	10		T2	2		T3	12
all_values[6]	auto[0]	auto[1]	144	1			T14	1		T34	2		T83	1
all_values[6]	auto[1]	auto[0]	46130	1			T1	16		T3	14		T4	25
all_values[6]	auto[1]	auto[1]	166	1			T14	5		T15	1		T41	3
all_values[7]	auto[0]	auto[0]	45691	1			T1	17		T2	2		T3	17
all_values[7]	auto[0]	auto[1]	287	1			T14	1		T15	3		T16	1
all_values[7]	auto[1]	auto[0]	42857	1			T1	9		T3	9		T4	10
all_values[7]	auto[1]	auto[1]	348	1			T12	11		T14	5		T15	1
all_values[8]	auto[0]	auto[0]	28413	1			T3	9		T5	3		T6	1
all_values[8]	auto[0]	auto[1]	14942	1			T2	2		T3	3		T4	10
all_values[8]	auto[1]	auto[0]	31699	1			T1	23		T5	2		T6	6
all_values[8]	auto[1]	auto[1]	14129	1			T1	3		T3	14		T4	15