Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2535

1

T1

1

T2

1

T3

1

auto[UartRx]

2535

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4448	1			T1	2		T2	2		T3	2
values[1]	46	1			T14	1		T32	1		T34	2
values[2]	37	1			T6	1		T31	1		T32	1
values[3]	56	1			T6	1		T14	1		T22	1
values[4]	60	1			T6	1		T14	2		T15	1
values[5]	54	1			T14	1		T22	1		T15	1
values[6]	67	1			T6	1		T15	1		T30	5
values[7]	62	1			T14	1		T15	2		T33	1
values[8]	57	1			T6	2		T22	2		T33	1
values[9]	68	1			T14	1		T17	2		T31	1
values[10]	74	1			T14	2		T15	2		T17	2

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2309	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	13	1			T100	1		T337	1		T338	1
auto[UartTx]	values[2]	12	1			T31	1		T32	1		T82	1
auto[UartTx]	values[3]	16	1			T6	1		T22	1		T34	1
auto[UartTx]	values[4]	26	1			T32	3		T77	1		T339	1
auto[UartTx]	values[5]	24	1			T14	1		T22	1		T15	1
auto[UartTx]	values[6]	34	1			T6	1		T15	1		T30	2
auto[UartTx]	values[7]	26	1			T15	1		T33	1		T82	1
auto[UartTx]	values[8]	17	1			T22	1		T317	1		T99	1
auto[UartTx]	values[9]	24	1			T14	1		T33	1		T34	1
auto[UartTx]	values[10]	25	1			T14	1		T17	1		T83	2
auto[UartRx]	values[0]	2139	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	33	1			T14	1		T32	1		T34	2
auto[UartRx]	values[2]	25	1			T6	1		T34	1		T82	1
auto[UartRx]	values[3]	40	1			T14	1		T32	3		T83	1
auto[UartRx]	values[4]	34	1			T6	1		T14	2		T15	1
auto[UartRx]	values[5]	30	1			T33	1		T82	2		T83	1
auto[UartRx]	values[6]	33	1			T30	3		T82	1		T340	1
auto[UartRx]	values[7]	36	1			T14	1		T15	1		T34	2
auto[UartRx]	values[8]	40	1			T6	2		T22	1		T33	1
auto[UartRx]	values[9]	44	1			T17	2		T31	1		T33	1
auto[UartRx]	values[10]	49	1			T14	1		T15	2		T17	1