Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2004	1			T2	1		T3	1		T5	2
auto[BaudRate115200]	1473	1			T1	2		T3	1		T6	4
auto[BaudRate230400]	1589	1			T1	1		T3	3		T4	1
auto[BaudRate128Kbps]	1622	1			T1	2		T2	1		T3	1
auto[BaudRate256Kbps]	1717	1			T1	1		T3	1		T5	1
auto[BaudRate1Mbps]	1431	1			T1	1		T5	1		T6	1
auto[BaudRate1p5Mbps]	1031	1			T1	2		T6	3		T9	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1201	1			T38	8		T42	6		T18	4
freqs[25]	1031	1			T5	5		T6	18		T19	42
freqs[48]	738	1			T90	10		T263	2		T279	7
freqs[50]	424	1			T282	2		T261	5		T120	32
freqs[100]	924	1			T174	8		T22	6		T257	6

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	266	1			T42	1		T341	6		T172	1
auto[BaudRate9600]	freqs[25]	180	1			T5	2		T6	2		T19	6
auto[BaudRate9600]	freqs[48]	103	1			T90	2		T279	1		T258	2
auto[BaudRate9600]	freqs[50]	76	1			T120	5		T127	2		T223	2
auto[BaudRate9600]	freqs[100]	191	1			T174	1		T113	1		T179	1
auto[BaudRate115200]	freqs[24]	173	1			T42	3		T18	2		T342	3
auto[BaudRate115200]	freqs[25]	127	1			T6	4		T19	3		T14	1
auto[BaudRate115200]	freqs[48]	99	1			T279	1		T258	3		T237	3
auto[BaudRate115200]	freqs[50]	53	1			T261	2		T120	3		T118	1
auto[BaudRate115200]	freqs[100]	110	1			T174	3		T22	1		T257	1
auto[BaudRate230400]	freqs[24]	138	1			T18	2		T342	6		T341	6
auto[BaudRate230400]	freqs[25]	179	1			T6	2		T19	15		T14	3
auto[BaudRate230400]	freqs[48]	114	1			T90	2		T263	1		T279	1
auto[BaudRate230400]	freqs[50]	61	1			T120	2		T343	1		T118	1
auto[BaudRate230400]	freqs[100]	115	1			T174	1		T22	1		T257	1
auto[BaudRate128Kbps]	freqs[24]	172	1			T342	9		T341	9		T172	2
auto[BaudRate128Kbps]	freqs[25]	162	1			T5	1		T6	4		T19	6
auto[BaudRate128Kbps]	freqs[48]	119	1			T90	1		T344	6		T258	3
auto[BaudRate128Kbps]	freqs[50]	77	1			T261	1		T120	5		T343	1
auto[BaudRate128Kbps]	freqs[100]	120	1			T174	1		T22	2		T257	1
auto[BaudRate256Kbps]	freqs[24]	189	1			T38	4		T42	2		T342	3
auto[BaudRate256Kbps]	freqs[25]	144	1			T5	1		T6	2		T19	9
auto[BaudRate256Kbps]	freqs[48]	110	1			T90	1		T279	2		T344	6
auto[BaudRate256Kbps]	freqs[50]	45	1			T282	1		T261	1		T120	4
auto[BaudRate256Kbps]	freqs[100]	118	1			T106	1		T107	1		T113	1
auto[BaudRate1Mbps]	freqs[24]	158	1			T38	3		T342	3		T341	9
auto[BaudRate1Mbps]	freqs[25]	153	1			T5	1		T6	1		T19	3
auto[BaudRate1Mbps]	freqs[48]	93	1			T90	3		T279	1		T278	1
auto[BaudRate1Mbps]	freqs[50]	65	1			T120	7		T118	2		T223	1
auto[BaudRate1Mbps]	freqs[100]	127	1			T22	1		T257	2		T106	1
auto[BaudRate1p5Mbps]	freqs[25]	86	1			T6	3		T14	3		T76	6
auto[BaudRate1p5Mbps]	freqs[48]	100	1			T90	1		T263	1		T279	1
auto[BaudRate1p5Mbps]	freqs[50]	47	1			T282	1		T261	1		T120	6
auto[BaudRate1p5Mbps]	freqs[100]	143	1			T174	2		T22	1		T257	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded