Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.40	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	13	117	90.00

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	13	117	90.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	26473424	1			T1	13		T3	14		T4	18
all_levels[1]	136043	1			T3	4		T5	2		T6	303
all_levels[2]	1965	1			T1	1		T5	1		T6	8
all_levels[3]	870	1			T7	3		T9	5		T35	5
all_levels[4]	591	1			T9	1		T35	8		T36	1
all_levels[5]	419	1			T7	3		T10	3		T35	2
all_levels[6]	325	1			T9	1		T35	5		T29	2
all_levels[7]	267	1			T7	1		T35	1		T29	2
all_levels[8]	224	1			T3	2		T29	1		T105	1
all_levels[9]	199	1			T5	2		T29	1		T91	1
all_levels[10]	169	1			T105	1		T92	1		T106	3
all_levels[11]	172	1			T6	1		T29	1		T105	1
all_levels[12]	138	1			T6	1		T8	1		T29	1
all_levels[13]	116	1			T16	2		T107	1		T108	1
all_levels[14]	94	1			T40	1		T109	1		T106	1
all_levels[15]	88	1			T16	1		T108	1		T110	1
all_levels[16]	81	1			T36	1		T92	1		T107	1
all_levels[17]	90	1			T40	1		T16	2		T111	3
all_levels[18]	77	1			T16	1		T112	2		T110	1
all_levels[19]	60	1			T40	1		T109	1		T80	1
all_levels[20]	62	1			T105	1		T89	1		T106	1
all_levels[21]	45	1			T40	1		T113	1		T114	1
all_levels[22]	53	1			T89	1		T40	1		T110	1
all_levels[23]	53	1			T36	1		T111	2		T80	1
all_levels[24]	41	1			T5	1		T91	1		T40	2
all_levels[25]	41	1			T107	1		T110	1		T115	1
all_levels[26]	40	1			T106	1		T116	1		T93	4
all_levels[27]	40	1			T91	1		T40	2		T112	1
all_levels[28]	36	1			T117	1		T75	1		T80	2
all_levels[29]	22	1			T5	3		T10	2		T16	1
all_levels[30]	37	1			T40	1		T107	1		T110	2
all_levels[31]	21	1			T110	1		T118	1		T119	1
all_levels[32]	16	1			T111	1		T120	1		T121	1
all_levels[33]	16	1			T122	1		T123	1		T124	2
all_levels[34]	21	1			T75	1		T122	2		T125	1
all_levels[35]	15	1			T123	1		T126	1		T127	1
all_levels[36]	36	1			T128	1		T129	1		T118	3
all_levels[37]	17	1			T130	3		T131	1		T132	2
all_levels[38]	21	1			T111	4		T133	1		T134	1
all_levels[39]	9	1			T135	1		T122	1		T121	2
all_levels[40]	8	1			T10	1		T125	1		T136	1
all_levels[41]	15	1			T137	3		T138	1		T139	2
all_levels[42]	18	1			T140	1		T135	1		T118	4
all_levels[43]	7	1			T10	1		T16	1		T141	1
all_levels[44]	13	1			T16	1		T133	1		T142	1
all_levels[45]	7	1			T143	2		T144	2		T145	1
all_levels[46]	11	1			T123	2		T146	1		T147	1
all_levels[47]	10	1			T148	1		T149	1		T150	1
all_levels[48]	20	1			T112	1		T122	1		T129	1
all_levels[49]	6	1			T151	3		T152	1		T153	2
all_levels[50]	9	1			T119	1		T154	1		T155	1
all_levels[51]	10	1			T129	1		T155	1		T156	3
all_levels[52]	4	1			T142	1		T157	1		T158	1
all_levels[53]	8	1			T159	2		T150	1		T160	1
all_levels[54]	1	1			T161	1		-	-		-	-
all_levels[55]	8	1			T90	1		T117	1		T81	1
all_levels[56]	6	1			T162	5		T163	1		-	-
all_levels[57]	9	1			T90	1		T122	1		T130	2
all_levels[58]	10	1			T91	1		T164	4		T165	1
all_levels[59]	10	1			T90	1		T166	1		T167	1
all_levels[60]	4	1			T105	1		T168	2		T163	1
all_levels[61]	10	1			T120	1		T114	1		T142	1
all_levels[62]	5	1			T91	1		T169	1		T155	1
all_levels[63]	6	1			T129	1		T148	1		T170	1
all_levels[64]	99	1			T3	1		T128	1		T112	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26612498

1

T1

6

T3

15

T5

40

auto[1]

3870

1

T1

8

T3

6

T4

18

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	13	117	90.00	13

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[24] , all_levels[25]]	[auto[1]]	--	--	2
[all_levels[33]]	[auto[1]]	0	1	1
[all_levels[35]]	[auto[1]]	0	1	1
[all_levels[39] , all_levels[40]]	[auto[1]]	--	--	2
[all_levels[43]]	[auto[1]]	0	1	1
[all_levels[50]]	[auto[1]]	0	1	1
[all_levels[52]]	[auto[1]]	0	1	1
[all_levels[54]]	[auto[1]]	0	1	1
[all_levels[59]]	[auto[1]]	0	1	1
[all_levels[62] , all_levels[63]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	26469992	1			T1	5		T3	11		T5	34
all_levels[0]	auto[1]	3432	1			T1	8		T3	3		T4	18
all_levels[1]	auto[0]	135966	1			T3	2		T5	1		T6	303
all_levels[1]	auto[1]	77	1			T3	2		T5	1		T8	1
all_levels[2]	auto[0]	1937	1			T1	1		T5	1		T6	8
all_levels[2]	auto[1]	28	1			T35	1		T109	2		T107	1
all_levels[3]	auto[0]	847	1			T7	3		T9	5		T35	5
all_levels[3]	auto[1]	23	1			T171	4		T172	1		T173	6
all_levels[4]	auto[0]	567	1			T9	1		T35	8		T36	1
all_levels[4]	auto[1]	24	1			T174	1		T16	3		T107	1
all_levels[5]	auto[0]	400	1			T7	3		T10	2		T35	2
all_levels[5]	auto[1]	19	1			T10	1		T111	2		T75	1
all_levels[6]	auto[0]	309	1			T9	1		T35	2		T29	2
all_levels[6]	auto[1]	16	1			T35	3		T175	2		T176	1
all_levels[7]	auto[0]	255	1			T7	1		T35	1		T29	1
all_levels[7]	auto[1]	12	1			T29	1		T177	2		T178	2
all_levels[8]	auto[0]	207	1			T3	1		T29	1		T105	1
all_levels[8]	auto[1]	17	1			T3	1		T106	1		T108	2
all_levels[9]	auto[0]	193	1			T5	2		T29	1		T91	1
all_levels[9]	auto[1]	6	1			T179	1		T180	2		T181	1
all_levels[10]	auto[0]	160	1			T105	1		T92	1		T106	3
all_levels[10]	auto[1]	9	1			T182	2		T159	1		T183	1
all_levels[11]	auto[0]	155	1			T6	1		T29	1		T105	1
all_levels[11]	auto[1]	17	1			T109	1		T112	1		T117	2
all_levels[12]	auto[0]	127	1			T6	1		T8	1		T29	1
all_levels[12]	auto[1]	11	1			T184	1		T185	1		T186	1
all_levels[13]	auto[0]	106	1			T16	2		T107	1		T108	1
all_levels[13]	auto[1]	10	1			T187	1		T188	2		T189	1
all_levels[14]	auto[0]	87	1			T40	1		T109	1		T106	1
all_levels[14]	auto[1]	7	1			T173	1		T190	2		T191	3
all_levels[15]	auto[0]	85	1			T16	1		T108	1		T110	1
all_levels[15]	auto[1]	3	1			T146	1		T127	1		T192	1
all_levels[16]	auto[0]	72	1			T36	1		T92	1		T107	1
all_levels[16]	auto[1]	9	1			T193	2		T194	1		T195	1
all_levels[17]	auto[0]	76	1			T40	1		T16	2		T111	3
all_levels[17]	auto[1]	14	1			T196	2		T116	1		T194	1
all_levels[18]	auto[0]	70	1			T16	1		T112	1		T110	1
all_levels[18]	auto[1]	7	1			T112	1		T196	1		T184	2
all_levels[19]	auto[0]	52	1			T40	1		T109	1		T80	1
all_levels[19]	auto[1]	8	1			T197	1		T198	1		T199	6
all_levels[20]	auto[0]	59	1			T105	1		T89	1		T106	1
all_levels[20]	auto[1]	3	1			T152	1		T200	1		T201	1
all_levels[21]	auto[0]	40	1			T40	1		T113	1		T114	1
all_levels[21]	auto[1]	5	1			T202	2		T203	1		T204	1
all_levels[22]	auto[0]	49	1			T89	1		T40	1		T110	1
all_levels[22]	auto[1]	4	1			T81	1		T205	1		T206	2
all_levels[23]	auto[0]	42	1			T36	1		T111	1		T80	1
all_levels[23]	auto[1]	11	1			T111	1		T180	2		T207	1
all_levels[24]	auto[0]	41	1			T5	1		T91	1		T40	2
all_levels[25]	auto[0]	41	1			T107	1		T110	1		T115	1
all_levels[26]	auto[0]	32	1			T106	1		T116	1		T93	2
all_levels[26]	auto[1]	8	1			T93	2		T208	2		T168	1
all_levels[27]	auto[0]	34	1			T91	1		T40	2		T112	1
all_levels[27]	auto[1]	6	1			T209	1		T195	2		T210	1
all_levels[28]	auto[0]	29	1			T117	1		T75	1		T80	2
all_levels[28]	auto[1]	7	1			T203	1		T211	1		T212	3
all_levels[29]	auto[0]	19	1			T5	1		T10	1		T16	1
all_levels[29]	auto[1]	3	1			T5	2		T10	1		-	-
all_levels[30]	auto[0]	33	1			T40	1		T107	1		T110	2
all_levels[30]	auto[1]	4	1			T172	2		T213	1		T214	1
all_levels[31]	auto[0]	20	1			T110	1		T118	1		T119	1
all_levels[31]	auto[1]	1	1			T184	1		-	-		-	-
all_levels[32]	auto[0]	15	1			T111	1		T120	1		T121	1
all_levels[32]	auto[1]	1	1			T215	1		-	-		-	-
all_levels[33]	auto[0]	16	1			T122	1		T123	1		T124	2
all_levels[34]	auto[0]	19	1			T75	1		T122	1		T125	1
all_levels[34]	auto[1]	2	1			T122	1		T216	1		-	-
all_levels[35]	auto[0]	15	1			T123	1		T126	1		T127	1
all_levels[36]	auto[0]	34	1			T128	1		T129	1		T118	2
all_levels[36]	auto[1]	2	1			T118	1		T217	1		-	-
all_levels[37]	auto[0]	13	1			T130	1		T131	1		T132	2
all_levels[37]	auto[1]	4	1			T130	2		T218	2		-	-
all_levels[38]	auto[0]	17	1			T111	3		T133	1		T134	1
all_levels[38]	auto[1]	4	1			T111	1		T219	1		T220	1
all_levels[39]	auto[0]	9	1			T135	1		T122	1		T121	2
all_levels[40]	auto[0]	8	1			T10	1		T125	1		T136	1
all_levels[41]	auto[0]	12	1			T137	1		T138	1		T139	1
all_levels[41]	auto[1]	3	1			T137	2		T139	1		-	-
all_levels[42]	auto[0]	14	1			T140	1		T135	1		T118	1
all_levels[42]	auto[1]	4	1			T118	3		T221	1		-	-
all_levels[43]	auto[0]	7	1			T10	1		T16	1		T141	1
all_levels[44]	auto[0]	12	1			T16	1		T133	1		T142	1
all_levels[44]	auto[1]	1	1			T178	1		-	-		-	-
all_levels[45]	auto[0]	6	1			T143	1		T144	2		T145	1
all_levels[45]	auto[1]	1	1			T143	1		-	-		-	-
all_levels[46]	auto[0]	8	1			T123	2		T146	1		T147	1
all_levels[46]	auto[1]	3	1			T124	1		T203	2		-	-
all_levels[47]	auto[0]	8	1			T148	1		T149	1		T150	1
all_levels[47]	auto[1]	2	1			T222	2		-	-		-	-
all_levels[48]	auto[0]	11	1			T112	1		T122	1		T129	1
all_levels[48]	auto[1]	9	1			T223	4		T224	1		T225	2
all_levels[49]	auto[0]	3	1			T151	1		T152	1		T153	1
all_levels[49]	auto[1]	3	1			T151	2		T153	1		-	-
all_levels[50]	auto[0]	9	1			T119	1		T154	1		T155	1
all_levels[51]	auto[0]	8	1			T129	1		T155	1		T156	1
all_levels[51]	auto[1]	2	1			T156	2		-	-		-	-
all_levels[52]	auto[0]	4	1			T142	1		T157	1		T158	1
all_levels[53]	auto[0]	7	1			T159	1		T150	1		T160	1
all_levels[53]	auto[1]	1	1			T159	1		-	-		-	-
all_levels[54]	auto[0]	1	1			T161	1		-	-		-	-
all_levels[55]	auto[0]	7	1			T90	1		T117	1		T81	1
all_levels[55]	auto[1]	1	1			T226	1		-	-		-	-
all_levels[56]	auto[0]	3	1			T162	2		T163	1		-	-
all_levels[56]	auto[1]	3	1			T162	3		-	-		-	-
all_levels[57]	auto[0]	8	1			T90	1		T122	1		T130	1
all_levels[57]	auto[1]	1	1			T130	1		-	-		-	-
all_levels[58]	auto[0]	7	1			T91	1		T164	1		T165	1
all_levels[58]	auto[1]	3	1			T164	3		-	-		-	-
all_levels[59]	auto[0]	10	1			T90	1		T166	1		T167	1
all_levels[60]	auto[0]	3	1			T105	1		T168	1		T163	1
all_levels[60]	auto[1]	1	1			T168	1		-	-		-	-
all_levels[61]	auto[0]	9	1			T120	1		T114	1		T142	1
all_levels[61]	auto[1]	1	1			T227	1		-	-		-	-
all_levels[62]	auto[0]	5	1			T91	1		T169	1		T155	1
all_levels[63]	auto[0]	6	1			T129	1		T148	1		T170	1
all_levels[64]	auto[0]	82	1			T3	1		T128	1		T112	1
all_levels[64]	auto[1]	17	1			T133	3		T122	1		T228	1