Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
8 |
1 |
7 |
87.50 |
Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_watermark_lvl |
8 |
1 |
7 |
87.50 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_watermark_lvl
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
1 |
7 |
87.50 |
User Defined Bins for cp_watermark_lvl
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
all_levels[7] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_levels[0] |
1282 |
1 |
|
|
T6 |
2 |
|
T8 |
1 |
|
T10 |
2 |
all_levels[1] |
546 |
1 |
|
|
T35 |
18 |
|
T90 |
14 |
|
T91 |
1 |
all_levels[2] |
393 |
1 |
|
|
T1 |
1 |
|
T3 |
14 |
|
T8 |
1 |
all_levels[3] |
208 |
1 |
|
|
T5 |
2 |
|
T89 |
1 |
|
T16 |
23 |
all_levels[4] |
151 |
1 |
|
|
T40 |
1 |
|
T93 |
8 |
|
T94 |
4 |
all_levels[5] |
129 |
1 |
|
|
T12 |
4 |
|
T18 |
4 |
|
T95 |
8 |
all_levels[6] |
22 |
1 |
|
|
T96 |
2 |
|
T97 |
2 |
|
T98 |
4 |
0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |