Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	89183	1			T1	26		T2	2		T3	26
all_pins[1]	89183	1			T1	26		T2	2		T3	26
all_pins[2]	89183	1			T1	26		T2	2		T3	26
all_pins[3]	89183	1			T1	26		T2	2		T3	26
all_pins[4]	89183	1			T1	26		T2	2		T3	26
all_pins[5]	89183	1			T1	26		T2	2		T3	26
all_pins[6]	89183	1			T1	26		T2	2		T3	26
all_pins[7]	89183	1			T1	26		T2	2		T3	26
all_pins[8]	89183	1			T1	26		T2	2		T3	26

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	762163	1			T1	227		T2	18		T3	177
values[0x1]	40484	1			T1	7		T3	57		T4	40
transitions[0x0=>0x1]	32587	1			T1	6		T3	30		T4	25
transitions[0x1=>0x0]	32413	1			T1	6		T3	30		T4	24

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	68338	1			T1	24		T2	2		T3	12
all_pins[0]	values[0x1]	20845	1			T1	2		T3	14		T4	25
all_pins[0]	transitions[0x0=>0x1]	20379	1			T1	2		T4	25		T6	4
all_pins[0]	transitions[0x1=>0x0]	980	1			T1	1		T8	1		T37	8
all_pins[1]	values[0x0]	87737	1			T1	25		T2	2		T3	12
all_pins[1]	values[0x1]	1446	1			T1	1		T3	14		T8	1
all_pins[1]	transitions[0x0=>0x1]	1350	1			T1	1		T3	14		T8	1
all_pins[1]	transitions[0x1=>0x0]	1945	1			T5	3		T7	3		T8	5
all_pins[2]	values[0x0]	87142	1			T1	26		T2	2		T3	26
all_pins[2]	values[0x1]	2041	1			T5	3		T7	3		T8	5
all_pins[2]	transitions[0x0=>0x1]	1981	1			T5	3		T7	3		T8	4
all_pins[2]	transitions[0x1=>0x0]	204	1			T3	4		T8	3		T14	2
all_pins[3]	values[0x0]	88919	1			T1	26		T2	2		T3	22
all_pins[3]	values[0x1]	264	1			T3	4		T8	4		T14	3
all_pins[3]	transitions[0x0=>0x1]	221	1			T3	4		T8	4		T14	3
all_pins[3]	transitions[0x1=>0x0]	340	1			T12	8		T14	4		T17	1
all_pins[4]	values[0x0]	88800	1			T1	26		T2	2		T3	26
all_pins[4]	values[0x1]	383	1			T12	8		T14	4		T15	1
all_pins[4]	transitions[0x0=>0x1]	326	1			T12	8		T14	4		T17	1
all_pins[4]	transitions[0x1=>0x0]	128	1			T14	1		T15	2		T18	1
all_pins[5]	values[0x0]	88998	1			T1	26		T2	2		T3	26
all_pins[5]	values[0x1]	185	1			T14	1		T15	3		T18	2
all_pins[5]	transitions[0x0=>0x1]	154	1			T14	1		T15	2		T18	2
all_pins[5]	transitions[0x1=>0x0]	770	1			T1	1		T3	11		T9	2
all_pins[6]	values[0x0]	88382	1			T1	25		T2	2		T3	15
all_pins[6]	values[0x1]	801	1			T1	1		T3	11		T9	2
all_pins[6]	transitions[0x0=>0x1]	734	1			T1	1		T3	11		T9	2
all_pins[6]	transitions[0x1=>0x0]	281	1			T12	11		T14	5		T114	3
all_pins[7]	values[0x0]	88835	1			T1	26		T2	2		T3	26
all_pins[7]	values[0x1]	348	1			T12	11		T14	5		T15	1
all_pins[7]	transitions[0x0=>0x1]	221	1			T12	11		T14	4		T229	3
all_pins[7]	transitions[0x1=>0x0]	14044	1			T1	3		T3	14		T4	15
all_pins[8]	values[0x0]	75012	1			T1	23		T2	2		T3	12
all_pins[8]	values[0x1]	14171	1			T1	3		T3	14		T4	15
all_pins[8]	transitions[0x0=>0x1]	7221	1			T1	2		T3	1		T6	1
all_pins[8]	transitions[0x1=>0x0]	13721	1			T1	1		T3	1		T4	9