Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7232788	1			T1	6		T3	5		T4	18
all_levels[1]	2135604	1			T3	3		T6	3		T7	88
all_levels[2]	459835	1			T5	1		T7	2		T9	6
all_levels[3]	170135	1			T6	2		T8	1		T9	14
all_levels[4]	825020	1			T5	2		T6	2		T9	7
all_levels[5]	322008	1			T3	8		T7	1		T8	2
all_levels[6]	158676	1			T8	1		T9	3		T11	5349
all_levels[7]	158604	1			T5	1		T6	1		T7	2
all_levels[8]	173720	1			T5	2		T6	1		T7	2
all_levels[9]	256563	1			T5	1		T7	6		T8	2
all_levels[10]	155684	1			T5	2		T7	1		T8	4
all_levels[11]	375761	1			T6	4		T7	1		T9	1
all_levels[12]	526642	1			T5	1		T6	4		T7	3
all_levels[13]	303628	1			T5	3		T7	83		T9	32
all_levels[14]	231439	1			T5	2		T7	3		T9	3
all_levels[15]	189444	1			T1	1		T3	3		T7	2
all_levels[16]	397362	1			T9	1		T10	1		T11	5316
all_levels[17]	201314	1			T7	2		T9	4		T10	1
all_levels[18]	140684	1			T7	27		T9	2		T11	5335
all_levels[19]	234411	1			T6	1		T8	2		T11	5333
all_levels[20]	147357	1			T7	1		T9	4		T10	2
all_levels[21]	134331	1			T9	3		T11	5628		T12	2084
all_levels[22]	140913	1			T11	9603		T12	2117		T29	1
all_levels[23]	290895	1			T7	1		T8	1		T10	1
all_levels[24]	171333	1			T6	1		T7	1		T8	1
all_levels[25]	240954	1			T11	9577		T12	2377		T37	1
all_levels[26]	157500	1			T11	9518		T12	2759		T174	7
all_levels[27]	424687	1			T3	2		T11	9603		T12	2337
all_levels[28]	164359	1			T11	9157		T12	1455		T29	5
all_levels[29]	207886	1			T11	5358		T12	1411		T29	3
all_levels[30]	196273	1			T6	1		T11	5346		T12	1439
all_levels[31]	577470	1			T6	100		T11	26036		T12	4488
all_levels[32]	9112887	1			T1	3		T5	21		T6	817

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26612498

1

T1

6

T3

15

T5

40

auto[1]

3669

1

T1

4

T3

6

T4

18

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7230636	1			T1	3		T3	4		T5	7
all_levels[0]	auto[1]	2152	1			T1	3		T3	1		T4	18
all_levels[1]	auto[0]	2135379	1			T3	3		T6	3		T7	88
all_levels[1]	auto[1]	225	1			T8	1		T174	2		T15	1
all_levels[2]	auto[0]	459809	1			T5	1		T7	2		T9	6
all_levels[2]	auto[1]	26	1			T108	1		T79	1		T247	2
all_levels[3]	auto[0]	170014	1			T6	2		T8	1		T9	14
all_levels[3]	auto[1]	121	1			T91	1		T42	1		T18	21
all_levels[4]	auto[0]	824987	1			T5	1		T6	2		T9	7
all_levels[4]	auto[1]	33	1			T5	1		T239	1		T135	1
all_levels[5]	auto[0]	321976	1			T3	5		T7	1		T8	2
all_levels[5]	auto[1]	32	1			T3	3		T108	1		T346	1
all_levels[6]	auto[0]	158648	1			T8	1		T9	3		T11	5349
all_levels[6]	auto[1]	28	1			T35	1		T130	2		T301	1
all_levels[7]	auto[0]	158537	1			T5	1		T6	1		T7	2
all_levels[7]	auto[1]	67	1			T106	2		T171	1		T247	1
all_levels[8]	auto[0]	173687	1			T5	2		T6	1		T7	2
all_levels[8]	auto[1]	33	1			T128	1		T279	1		T112	4
all_levels[9]	auto[0]	256544	1			T5	1		T7	6		T8	2
all_levels[9]	auto[1]	19	1			T347	1		T127	1		T348	1
all_levels[10]	auto[0]	155655	1			T5	2		T7	1		T8	3
all_levels[10]	auto[1]	29	1			T8	1		T174	1		T109	2
all_levels[11]	auto[0]	375745	1			T6	4		T7	1		T9	1
all_levels[11]	auto[1]	16	1			T182	3		T314	1		T267	1
all_levels[12]	auto[0]	526614	1			T5	1		T6	4		T7	3
all_levels[12]	auto[1]	28	1			T246	1		T122	1		T267	1
all_levels[13]	auto[0]	303604	1			T5	3		T7	83		T9	32
all_levels[13]	auto[1]	24	1			T29	1		T234	1		T330	2
all_levels[14]	auto[0]	231419	1			T5	2		T7	3		T9	3
all_levels[14]	auto[1]	20	1			T246	1		T247	1		T313	1
all_levels[15]	auto[0]	189367	1			T1	1		T3	2		T7	2
all_levels[15]	auto[1]	77	1			T3	1		T107	2		T196	1
all_levels[16]	auto[0]	397349	1			T9	1		T10	1		T11	5316
all_levels[16]	auto[1]	13	1			T171	1		T196	1		T349	1
all_levels[17]	auto[0]	201290	1			T7	2		T9	4		T10	1
all_levels[17]	auto[1]	24	1			T135	1		T173	2		T350	1
all_levels[18]	auto[0]	140659	1			T7	27		T9	2		T11	5335
all_levels[18]	auto[1]	25	1			T228	1		T351	1		T352	4
all_levels[19]	auto[0]	234391	1			T6	1		T8	2		T11	5333
all_levels[19]	auto[1]	20	1			T249	1		T271	1		T313	1
all_levels[20]	auto[0]	147341	1			T7	1		T9	4		T10	2
all_levels[20]	auto[1]	16	1			T128	1		T334	1		T353	1
all_levels[21]	auto[0]	134310	1			T9	3		T11	5628		T12	2084
all_levels[21]	auto[1]	21	1			T254	3		T231	1		T146	1
all_levels[22]	auto[0]	140903	1			T11	9603		T12	2117		T29	1
all_levels[22]	auto[1]	10	1			T354	1		T326	1		T290	1
all_levels[23]	auto[0]	290883	1			T7	1		T8	1		T10	1
all_levels[23]	auto[1]	12	1			T109	2		T355	1		T127	1
all_levels[24]	auto[0]	171310	1			T6	1		T7	1		T8	1
all_levels[24]	auto[1]	23	1			T36	1		T262	1		T126	1
all_levels[25]	auto[0]	240935	1			T11	9577		T12	2377		T37	1
all_levels[25]	auto[1]	19	1			T115	1		T75	1		T293	1
all_levels[26]	auto[0]	157482	1			T11	9518		T12	2759		T174	4
all_levels[26]	auto[1]	18	1			T174	3		T125	1		T356	2
all_levels[27]	auto[0]	424663	1			T3	1		T11	9603		T12	2337
all_levels[27]	auto[1]	24	1			T3	1		T107	2		T244	2
all_levels[28]	auto[0]	164339	1			T11	9157		T12	1455		T29	4
all_levels[28]	auto[1]	20	1			T29	1		T119	1		T180	2
all_levels[29]	auto[0]	207869	1			T11	5358		T12	1411		T29	3
all_levels[29]	auto[1]	17	1			T228	2		T313	3		T357	2
all_levels[30]	auto[0]	196255	1			T6	1		T11	5346		T12	1439
all_levels[30]	auto[1]	18	1			T261	1		T75	2		T130	1
all_levels[31]	auto[0]	577453	1			T6	100		T11	26036		T12	4488
all_levels[31]	auto[1]	17	1			T106	1		T279	1		T111	2
all_levels[32]	auto[0]	9112445	1			T1	2		T5	19		T6	817
all_levels[32]	auto[1]	442	1			T1	1		T5	2		T8	1