Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	673	1			T14	11		T15	4		T41	4
all_values[1]	673	1			T14	11		T15	4		T41	4
all_values[2]	673	1			T14	11		T15	4		T41	4
all_values[3]	673	1			T14	11		T15	4		T41	4
all_values[4]	673	1			T14	11		T15	4		T41	4
all_values[5]	673	1			T14	11		T15	4		T41	4
all_values[6]	673	1			T14	11		T15	4		T41	4
all_values[7]	673	1			T14	11		T15	4		T41	4
all_values[8]	673	1			T14	11		T15	4		T41	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3267

1

T14

52

T15

17

T41

24

auto[1]

2790

1

T14

47

T15

19

T41

12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1970

1

T14

34

T15

7

T41

16

auto[1]

4087

1

T14

65

T15

29

T41

20

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3563

1

T14

58

T15

16

T41

25

auto[1]

2494

1

T14

41

T15

20

T41

11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	227	1			T14	4		T15	3		T83	2
all_values[0]	auto[0]	auto[1]	auto[1]	171	1			T14	2		T41	1		T34	3
all_values[0]	auto[1]	auto[0]	auto[1]	142	1			T14	3		T15	1		T41	2
all_values[0]	auto[1]	auto[1]	auto[1]	133	1			T14	2		T41	1		T34	3
all_values[1]	auto[0]	auto[0]	auto[0]	242	1			T14	4		T15	1		T41	3
all_values[1]	auto[0]	auto[1]	auto[0]	179	1			T14	2		T83	2		T99	1
all_values[1]	auto[1]	auto[0]	auto[1]	133	1			T14	1		T15	1		T41	1
all_values[1]	auto[1]	auto[1]	auto[1]	119	1			T14	4		T15	2		T34	2
all_values[2]	auto[0]	auto[0]	auto[0]	154	1			T14	2		T83	2		T99	1
all_values[2]	auto[0]	auto[0]	auto[1]	57	1			T14	1		T41	1		T34	1
all_values[2]	auto[0]	auto[1]	auto[0]	104	1			T14	2		T15	2		T34	3
all_values[2]	auto[0]	auto[1]	auto[1]	76	1			T41	1		T34	1		T83	2
all_values[2]	auto[1]	auto[0]	auto[1]	159	1			T14	3		T15	1		T41	1
all_values[2]	auto[1]	auto[1]	auto[1]	123	1			T14	3		T15	1		T41	1
all_values[3]	auto[0]	auto[0]	auto[0]	154	1			T14	5		T41	3		T34	3
all_values[3]	auto[0]	auto[0]	auto[1]	70	1			T14	1		T83	1		T100	2
all_values[3]	auto[0]	auto[1]	auto[0]	102	1			T14	1		T41	1		T34	3
all_values[3]	auto[0]	auto[1]	auto[1]	73	1			T14	1		T15	2		T101	2
all_values[3]	auto[1]	auto[0]	auto[1]	153	1			T14	2		T15	1		T83	1
all_values[3]	auto[1]	auto[1]	auto[1]	121	1			T14	1		T15	1		T34	1
all_values[4]	auto[0]	auto[0]	auto[0]	156	1			T14	1		T41	3		T83	4
all_values[4]	auto[0]	auto[0]	auto[1]	63	1			T14	1		T34	1		T83	2
all_values[4]	auto[0]	auto[1]	auto[0]	105	1			T14	3		T15	2		T41	1
all_values[4]	auto[0]	auto[1]	auto[1]	64	1			T14	1		T34	1		T83	1
all_values[4]	auto[1]	auto[0]	auto[1]	164	1			T14	2		T15	1		T34	1
all_values[4]	auto[1]	auto[1]	auto[1]	121	1			T14	3		T15	1		T34	4
all_values[5]	auto[0]	auto[0]	auto[0]	146	1			T14	6		T41	4		T34	1
all_values[5]	auto[0]	auto[0]	auto[1]	67	1			T14	1		T34	2		T83	2
all_values[5]	auto[0]	auto[1]	auto[0]	121	1			T14	1		T83	3		T99	2
all_values[5]	auto[0]	auto[1]	auto[1]	58	1			T15	2		T34	1		T101	3
all_values[5]	auto[1]	auto[0]	auto[1]	143	1			T15	1		T34	1		T83	3
all_values[5]	auto[1]	auto[1]	auto[1]	138	1			T14	3		T15	1		T34	2
all_values[6]	auto[0]	auto[0]	auto[0]	132	1			T14	3		T15	2		T41	1
all_values[6]	auto[0]	auto[0]	auto[1]	62	1			T14	2		T34	1		T99	1
all_values[6]	auto[0]	auto[1]	auto[0]	120	1			T14	1		T34	2		T83	4
all_values[6]	auto[0]	auto[1]	auto[1]	67	1			T14	1		T41	1		T83	2
all_values[6]	auto[1]	auto[0]	auto[1]	146	1			T15	1		T34	1		T83	3
all_values[6]	auto[1]	auto[1]	auto[1]	146	1			T14	4		T15	1		T41	2
all_values[7]	auto[0]	auto[0]	auto[0]	135	1			T14	1		T83	1		T99	1
all_values[7]	auto[0]	auto[0]	auto[1]	61	1			T15	1		T41	2		T34	1
all_values[7]	auto[0]	auto[1]	auto[0]	120	1			T14	2		T83	3		T99	3
all_values[7]	auto[0]	auto[1]	auto[1]	74	1			T14	3		T83	2		T100	1
all_values[7]	auto[1]	auto[0]	auto[1]	151	1			T14	2		T15	2		T41	2
all_values[7]	auto[1]	auto[1]	auto[1]	132	1			T14	3		T15	1		T83	4
all_values[8]	auto[0]	auto[0]	auto[1]	203	1			T14	3		T34	3		T83	4
all_values[8]	auto[0]	auto[1]	auto[1]	200	1			T14	3		T15	1		T41	3
all_values[8]	auto[1]	auto[0]	auto[1]	147	1			T14	4		T15	1		T41	1
all_values[8]	auto[1]	auto[1]	auto[1]	123	1			T14	1		T15	2		T83	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal