Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.10 99.10 97.65 100.00 98.38 100.00 99.48


Total test records in report: 1319
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T1259 /workspace/coverage/cover_reg_top/11.uart_csr_rw.1774203893 Aug 14 04:38:19 PM PDT 24 Aug 14 04:38:20 PM PDT 24 19812943 ps
T1260 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.927503813 Aug 14 04:38:38 PM PDT 24 Aug 14 04:38:39 PM PDT 24 126802942 ps
T1261 /workspace/coverage/cover_reg_top/4.uart_tl_errors.2463569611 Aug 14 04:38:17 PM PDT 24 Aug 14 04:38:19 PM PDT 24 98240415 ps
T1262 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2222816853 Aug 14 04:38:11 PM PDT 24 Aug 14 04:38:17 PM PDT 24 63853624 ps
T1263 /workspace/coverage/cover_reg_top/0.uart_intr_test.1422738912 Aug 14 04:38:10 PM PDT 24 Aug 14 04:38:11 PM PDT 24 48602532 ps
T1264 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2172698043 Aug 14 04:38:11 PM PDT 24 Aug 14 04:38:11 PM PDT 24 49861885 ps
T1265 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4101833584 Aug 14 04:38:20 PM PDT 24 Aug 14 04:38:20 PM PDT 24 50279080 ps
T1266 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.603010799 Aug 14 04:38:19 PM PDT 24 Aug 14 04:38:21 PM PDT 24 135497423 ps
T1267 /workspace/coverage/cover_reg_top/7.uart_csr_rw.744316359 Aug 14 04:38:39 PM PDT 24 Aug 14 04:38:40 PM PDT 24 199906329 ps
T1268 /workspace/coverage/cover_reg_top/17.uart_intr_test.3168440114 Aug 14 04:38:35 PM PDT 24 Aug 14 04:38:35 PM PDT 24 49336851 ps
T1269 /workspace/coverage/cover_reg_top/25.uart_intr_test.2224698949 Aug 14 04:38:31 PM PDT 24 Aug 14 04:38:31 PM PDT 24 25805687 ps
T1270 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3533306908 Aug 14 04:38:14 PM PDT 24 Aug 14 04:38:15 PM PDT 24 12841363 ps
T1271 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1897267106 Aug 14 04:38:13 PM PDT 24 Aug 14 04:38:14 PM PDT 24 128833764 ps
T1272 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2640321859 Aug 14 04:38:08 PM PDT 24 Aug 14 04:38:09 PM PDT 24 30280247 ps
T1273 /workspace/coverage/cover_reg_top/31.uart_intr_test.129293668 Aug 14 04:38:33 PM PDT 24 Aug 14 04:38:33 PM PDT 24 22318530 ps
T1274 /workspace/coverage/cover_reg_top/46.uart_intr_test.505294447 Aug 14 04:38:41 PM PDT 24 Aug 14 04:38:41 PM PDT 24 45890575 ps
T1275 /workspace/coverage/cover_reg_top/12.uart_intr_test.3118612034 Aug 14 04:38:17 PM PDT 24 Aug 14 04:38:18 PM PDT 24 16841822 ps
T1276 /workspace/coverage/cover_reg_top/3.uart_intr_test.953689490 Aug 14 04:38:13 PM PDT 24 Aug 14 04:38:14 PM PDT 24 18154734 ps
T1277 /workspace/coverage/cover_reg_top/15.uart_csr_rw.3587696114 Aug 14 04:38:50 PM PDT 24 Aug 14 04:38:51 PM PDT 24 26782169 ps
T1278 /workspace/coverage/cover_reg_top/35.uart_intr_test.2387341489 Aug 14 04:38:34 PM PDT 24 Aug 14 04:38:35 PM PDT 24 12019807 ps
T1279 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.4196738315 Aug 14 04:38:31 PM PDT 24 Aug 14 04:38:32 PM PDT 24 46728811 ps
T71 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.490694115 Aug 14 04:37:57 PM PDT 24 Aug 14 04:37:58 PM PDT 24 366046729 ps
T1280 /workspace/coverage/cover_reg_top/48.uart_intr_test.2856522671 Aug 14 04:38:38 PM PDT 24 Aug 14 04:38:39 PM PDT 24 14282547 ps
T1281 /workspace/coverage/cover_reg_top/23.uart_intr_test.3037520131 Aug 14 04:38:20 PM PDT 24 Aug 14 04:38:21 PM PDT 24 25069399 ps
T1282 /workspace/coverage/cover_reg_top/9.uart_tl_errors.2423894078 Aug 14 04:38:25 PM PDT 24 Aug 14 04:38:27 PM PDT 24 203743690 ps
T49 /workspace/coverage/cover_reg_top/12.uart_csr_rw.2078874221 Aug 14 04:38:26 PM PDT 24 Aug 14 04:38:27 PM PDT 24 13534270 ps
T1283 /workspace/coverage/cover_reg_top/49.uart_intr_test.3944562883 Aug 14 04:38:38 PM PDT 24 Aug 14 04:38:39 PM PDT 24 15075477 ps
T50 /workspace/coverage/cover_reg_top/0.uart_csr_rw.617723521 Aug 14 04:38:03 PM PDT 24 Aug 14 04:38:04 PM PDT 24 12916959 ps
T1284 /workspace/coverage/cover_reg_top/14.uart_tl_errors.2260866753 Aug 14 04:38:22 PM PDT 24 Aug 14 04:38:24 PM PDT 24 83508916 ps
T54 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3833620950 Aug 14 04:38:18 PM PDT 24 Aug 14 04:38:19 PM PDT 24 34716668 ps
T1285 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.436280709 Aug 14 04:37:52 PM PDT 24 Aug 14 04:37:53 PM PDT 24 20472125 ps
T1286 /workspace/coverage/cover_reg_top/5.uart_csr_rw.3832452073 Aug 14 04:38:18 PM PDT 24 Aug 14 04:38:19 PM PDT 24 15580667 ps
T1287 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1748162911 Aug 14 04:38:18 PM PDT 24 Aug 14 04:38:24 PM PDT 24 162093723 ps
T1288 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1315664920 Aug 14 04:38:31 PM PDT 24 Aug 14 04:38:32 PM PDT 24 26283652 ps
T51 /workspace/coverage/cover_reg_top/1.uart_csr_rw.1429392229 Aug 14 04:38:22 PM PDT 24 Aug 14 04:38:23 PM PDT 24 55694969 ps
T1289 /workspace/coverage/cover_reg_top/4.uart_csr_rw.3422056904 Aug 14 04:38:20 PM PDT 24 Aug 14 04:38:21 PM PDT 24 13125804 ps
T1290 /workspace/coverage/cover_reg_top/13.uart_intr_test.2174950788 Aug 14 04:38:16 PM PDT 24 Aug 14 04:38:16 PM PDT 24 31725924 ps
T104 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.488599867 Aug 14 04:38:23 PM PDT 24 Aug 14 04:38:24 PM PDT 24 88573822 ps
T1291 /workspace/coverage/cover_reg_top/37.uart_intr_test.732587489 Aug 14 04:38:24 PM PDT 24 Aug 14 04:38:24 PM PDT 24 36094022 ps
T1292 /workspace/coverage/cover_reg_top/18.uart_tl_errors.1768561263 Aug 14 04:38:27 PM PDT 24 Aug 14 04:38:29 PM PDT 24 73161292 ps
T1293 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2213867945 Aug 14 04:38:37 PM PDT 24 Aug 14 04:38:38 PM PDT 24 122208678 ps
T1294 /workspace/coverage/cover_reg_top/2.uart_intr_test.1398637857 Aug 14 04:38:14 PM PDT 24 Aug 14 04:38:15 PM PDT 24 89931892 ps
T1295 /workspace/coverage/cover_reg_top/16.uart_intr_test.3141644099 Aug 14 04:38:39 PM PDT 24 Aug 14 04:38:40 PM PDT 24 48724462 ps
T1296 /workspace/coverage/cover_reg_top/15.uart_tl_errors.2889349214 Aug 14 04:38:39 PM PDT 24 Aug 14 04:38:40 PM PDT 24 389562256 ps
T1297 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2862153221 Aug 14 04:38:35 PM PDT 24 Aug 14 04:38:35 PM PDT 24 76040288 ps
T1298 /workspace/coverage/cover_reg_top/15.uart_intr_test.1082569784 Aug 14 04:38:24 PM PDT 24 Aug 14 04:38:25 PM PDT 24 25086190 ps
T1299 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3532702276 Aug 14 04:38:20 PM PDT 24 Aug 14 04:38:21 PM PDT 24 91714806 ps
T1300 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2454229287 Aug 14 04:38:30 PM PDT 24 Aug 14 04:38:30 PM PDT 24 23021137 ps
T1301 /workspace/coverage/cover_reg_top/26.uart_intr_test.1129461874 Aug 14 04:38:37 PM PDT 24 Aug 14 04:38:38 PM PDT 24 11487339 ps
T1302 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.773472849 Aug 14 04:38:22 PM PDT 24 Aug 14 04:38:23 PM PDT 24 161739483 ps
T1303 /workspace/coverage/cover_reg_top/33.uart_intr_test.648034346 Aug 14 04:38:39 PM PDT 24 Aug 14 04:38:40 PM PDT 24 24610596 ps
T1304 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1129837631 Aug 14 04:38:20 PM PDT 24 Aug 14 04:38:21 PM PDT 24 117629603 ps
T1305 /workspace/coverage/cover_reg_top/45.uart_intr_test.2885874499 Aug 14 04:38:41 PM PDT 24 Aug 14 04:38:42 PM PDT 24 28834276 ps
T52 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.113841731 Aug 14 04:37:59 PM PDT 24 Aug 14 04:37:59 PM PDT 24 60694903 ps
T53 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1041793343 Aug 14 04:38:22 PM PDT 24 Aug 14 04:38:25 PM PDT 24 266598265 ps
T1306 /workspace/coverage/cover_reg_top/39.uart_intr_test.2345502932 Aug 14 04:38:36 PM PDT 24 Aug 14 04:38:37 PM PDT 24 38741743 ps
T1307 /workspace/coverage/cover_reg_top/3.uart_tl_errors.4009292823 Aug 14 04:38:16 PM PDT 24 Aug 14 04:38:18 PM PDT 24 431144155 ps
T1308 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1059084127 Aug 14 04:38:35 PM PDT 24 Aug 14 04:38:37 PM PDT 24 103280747 ps
T1309 /workspace/coverage/cover_reg_top/24.uart_intr_test.3763048376 Aug 14 04:38:37 PM PDT 24 Aug 14 04:38:38 PM PDT 24 29426722 ps
T1310 /workspace/coverage/cover_reg_top/30.uart_intr_test.489919138 Aug 14 04:38:25 PM PDT 24 Aug 14 04:38:25 PM PDT 24 55479639 ps
T1311 /workspace/coverage/cover_reg_top/10.uart_tl_errors.2026336082 Aug 14 04:38:18 PM PDT 24 Aug 14 04:38:19 PM PDT 24 297985393 ps
T1312 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3074731813 Aug 14 04:38:15 PM PDT 24 Aug 14 04:38:16 PM PDT 24 89208219 ps
T1313 /workspace/coverage/cover_reg_top/4.uart_intr_test.3530337605 Aug 14 04:38:20 PM PDT 24 Aug 14 04:38:20 PM PDT 24 48153868 ps
T1314 /workspace/coverage/cover_reg_top/11.uart_intr_test.3983492842 Aug 14 04:38:19 PM PDT 24 Aug 14 04:38:20 PM PDT 24 11843206 ps
T1315 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1391633033 Aug 14 04:37:50 PM PDT 24 Aug 14 04:37:51 PM PDT 24 11701252 ps
T1316 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.17317991 Aug 14 04:38:19 PM PDT 24 Aug 14 04:38:20 PM PDT 24 69418309 ps
T1317 /workspace/coverage/cover_reg_top/10.uart_csr_rw.2412396866 Aug 14 04:38:31 PM PDT 24 Aug 14 04:38:32 PM PDT 24 22666540 ps
T1318 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3238322895 Aug 14 04:38:31 PM PDT 24 Aug 14 04:38:32 PM PDT 24 23626623 ps
T1319 /workspace/coverage/cover_reg_top/5.uart_intr_test.974153545 Aug 14 04:38:26 PM PDT 24 Aug 14 04:38:27 PM PDT 24 14733277 ps

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1586600427
Short name T6
Test name
Test status
Simulation time 13589644587 ps
CPU time 60.11 seconds
Started Aug 14 05:00:01 PM PDT 24
Finished Aug 14 05:01:01 PM PDT 24
Peak memory 217140 kb
Host smart-9632d339-b734-45a9-85f4-d85be4e622f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586600427 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1586600427
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2673649295
Short name T14
Test name
Test status
Simulation time 12981489011 ps
CPU time 67.56 seconds
Started Aug 14 05:03:08 PM PDT 24
Finished Aug 14 05:04:16 PM PDT 24
Peak memory 217624 kb
Host smart-09449069-ca00-40ff-aa53-31da9c431f26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673649295 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2673649295
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_stress_all.3288049484
Short name T120
Test name
Test status
Simulation time 444512409627 ps
CPU time 737.51 seconds
Started Aug 14 05:01:37 PM PDT 24
Finished Aug 14 05:13:55 PM PDT 24
Peak memory 200856 kb
Host smart-ca5c83db-2e33-4486-a75e-d1bad36ad499
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288049484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.3288049484
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all.286560362
Short name T12
Test name
Test status
Simulation time 152814023060 ps
CPU time 337.95 seconds
Started Aug 14 05:01:51 PM PDT 24
Finished Aug 14 05:07:29 PM PDT 24
Peak memory 200960 kb
Host smart-88beaf29-1eac-4a72-800d-71e39f256508
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286560362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.286560362
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all.656820113
Short name T16
Test name
Test status
Simulation time 460722802029 ps
CPU time 93.51 seconds
Started Aug 14 05:02:17 PM PDT 24
Finished Aug 14 05:03:51 PM PDT 24
Peak memory 200956 kb
Host smart-a3dfda1d-5931-43d1-ba65-6eb8e90c8151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656820113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.656820113
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.3239433751
Short name T38
Test name
Test status
Simulation time 161405706071 ps
CPU time 219.4 seconds
Started Aug 14 05:01:21 PM PDT 24
Finished Aug 14 05:05:01 PM PDT 24
Peak memory 200896 kb
Host smart-d0fcddff-ad15-4be0-a5cb-94c411f68ac2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3239433751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3239433751
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3927326648
Short name T10
Test name
Test status
Simulation time 230076912631 ps
CPU time 62.92 seconds
Started Aug 14 05:03:26 PM PDT 24
Finished Aug 14 05:04:29 PM PDT 24
Peak memory 200932 kb
Host smart-8f9cc755-c302-42e3-b31c-fb228798344c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927326648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3927326648
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.9792275
Short name T228
Test name
Test status
Simulation time 75449830574 ps
CPU time 39.17 seconds
Started Aug 14 05:04:09 PM PDT 24
Finished Aug 14 05:04:49 PM PDT 24
Peak memory 200868 kb
Host smart-bccbbddf-f650-4c56-81b7-8f085c84ec86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9792275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.9792275
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1145405123
Short name T27
Test name
Test status
Simulation time 133930171 ps
CPU time 0.78 seconds
Started Aug 14 04:58:47 PM PDT 24
Finished Aug 14 04:58:48 PM PDT 24
Peak memory 218756 kb
Host smart-7c659793-d900-40c0-947b-91108236a6ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145405123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1145405123
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/31.uart_stress_all.623020786
Short name T154
Test name
Test status
Simulation time 214070714052 ps
CPU time 1013.63 seconds
Started Aug 14 05:01:21 PM PDT 24
Finished Aug 14 05:18:15 PM PDT 24
Peak memory 200884 kb
Host smart-da6c45f1-2feb-4840-8563-07ab5d8fe345
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623020786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.623020786
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_perf.2713766840
Short name T11
Test name
Test status
Simulation time 21006783304 ps
CPU time 1087.83 seconds
Started Aug 14 05:02:02 PM PDT 24
Finished Aug 14 05:20:10 PM PDT 24
Peak memory 200944 kb
Host smart-a01fb87a-113f-43c2-aa97-90b8ea800eeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713766840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2713766840
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/45.uart_perf.4195541711
Short name T288
Test name
Test status
Simulation time 27637544905 ps
CPU time 363.45 seconds
Started Aug 14 05:02:26 PM PDT 24
Finished Aug 14 05:08:30 PM PDT 24
Peak memory 200888 kb
Host smart-c1e822f4-60df-4155-8005-303dc3fe97a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4195541711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.4195541711
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1592626351
Short name T44
Test name
Test status
Simulation time 28212682 ps
CPU time 0.59 seconds
Started Aug 14 04:38:25 PM PDT 24
Finished Aug 14 04:38:25 PM PDT 24
Peak memory 195760 kb
Host smart-ca818f78-4b9d-4e1a-8986-2af1d163a030
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592626351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1592626351
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.298530742
Short name T29
Test name
Test status
Simulation time 62395791377 ps
CPU time 143.56 seconds
Started Aug 14 05:03:05 PM PDT 24
Finished Aug 14 05:05:28 PM PDT 24
Peak memory 200896 kb
Host smart-5cf70cc8-505a-4f2d-a14d-36f8f7ce704d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298530742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.298530742
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_stress_all.3460717834
Short name T246
Test name
Test status
Simulation time 178382602429 ps
CPU time 89.25 seconds
Started Aug 14 05:01:02 PM PDT 24
Finished Aug 14 05:02:31 PM PDT 24
Peak memory 217488 kb
Host smart-4af712fa-c01c-498d-aa43-9f444336591e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460717834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3460717834
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all.1021963488
Short name T259
Test name
Test status
Simulation time 184277161586 ps
CPU time 110.08 seconds
Started Aug 14 05:00:35 PM PDT 24
Finished Aug 14 05:02:26 PM PDT 24
Peak memory 200856 kb
Host smart-4f772abd-7e98-4f20-8817-3c07a6f5a6c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021963488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1021963488
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_perf.4078366626
Short name T253
Test name
Test status
Simulation time 16067637577 ps
CPU time 367.47 seconds
Started Aug 14 05:00:47 PM PDT 24
Finished Aug 14 05:06:55 PM PDT 24
Peak memory 200816 kb
Host smart-3a7b25e6-62e2-4fec-ab8e-0fedbb29222e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4078366626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.4078366626
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/22.uart_tx_rx.928174513
Short name T283
Test name
Test status
Simulation time 198328917640 ps
CPU time 364.17 seconds
Started Aug 14 05:00:26 PM PDT 24
Finished Aug 14 05:06:31 PM PDT 24
Peak memory 200900 kb
Host smart-9d250123-99a0-4996-b53e-8b6c400bfc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928174513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.928174513
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.1165453956
Short name T32
Test name
Test status
Simulation time 3353104964 ps
CPU time 59.74 seconds
Started Aug 14 05:02:09 PM PDT 24
Finished Aug 14 05:03:09 PM PDT 24
Peak memory 210428 kb
Host smart-837059fa-bdcd-4757-bf14-4f51d15bf43e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165453956 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.1165453956
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_stress_all.1309777091
Short name T238
Test name
Test status
Simulation time 445503311996 ps
CPU time 348.53 seconds
Started Aug 14 05:01:14 PM PDT 24
Finished Aug 14 05:07:03 PM PDT 24
Peak memory 200992 kb
Host smart-720def4c-66ed-433d-beee-fc331941d5e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309777091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1309777091
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.161399195
Short name T68
Test name
Test status
Simulation time 678541208 ps
CPU time 1.39 seconds
Started Aug 14 04:38:25 PM PDT 24
Finished Aug 14 04:38:31 PM PDT 24
Peak memory 199340 kb
Host smart-8d30bab1-737f-4054-ad28-5fb05aac09f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161399195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.161399195
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.577111267
Short name T130
Test name
Test status
Simulation time 334314208572 ps
CPU time 415.31 seconds
Started Aug 14 05:03:25 PM PDT 24
Finished Aug 14 05:10:21 PM PDT 24
Peak memory 200896 kb
Host smart-cebe2f1b-56ec-401e-81ef-1d4312cfe045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577111267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.577111267
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3814947646
Short name T121
Test name
Test status
Simulation time 91748581666 ps
CPU time 43.43 seconds
Started Aug 14 05:01:08 PM PDT 24
Finished Aug 14 05:01:51 PM PDT 24
Peak memory 200848 kb
Host smart-0bdda96f-0352-4960-bb44-fcad986150fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814947646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3814947646
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.645918382
Short name T245
Test name
Test status
Simulation time 117199877721 ps
CPU time 921.78 seconds
Started Aug 14 05:00:37 PM PDT 24
Finished Aug 14 05:15:59 PM PDT 24
Peak memory 200952 kb
Host smart-20af242c-8c06-405a-8092-0ad9f5ba98d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=645918382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.645918382
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_alert_test.1305680681
Short name T389
Test name
Test status
Simulation time 30449745 ps
CPU time 0.59 seconds
Started Aug 14 04:59:36 PM PDT 24
Finished Aug 14 04:59:36 PM PDT 24
Peak memory 196204 kb
Host smart-50b6db43-dbf5-4437-b542-b26259318722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305680681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.1305680681
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3221369585
Short name T109
Test name
Test status
Simulation time 50612918267 ps
CPU time 51.17 seconds
Started Aug 14 04:58:51 PM PDT 24
Finished Aug 14 04:59:42 PM PDT 24
Peak memory 200916 kb
Host smart-23424d61-1370-49db-ab4d-2ca4daac5900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221369585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3221369585
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3894288111
Short name T146
Test name
Test status
Simulation time 67246812193 ps
CPU time 66.93 seconds
Started Aug 14 05:00:00 PM PDT 24
Finished Aug 14 05:01:08 PM PDT 24
Peak memory 200948 kb
Host smart-9b39cc44-fc3a-431f-a914-d6881d5238a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894288111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3894288111
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.492942815
Short name T117
Test name
Test status
Simulation time 17750434864 ps
CPU time 27.39 seconds
Started Aug 14 05:01:58 PM PDT 24
Finished Aug 14 05:02:25 PM PDT 24
Peak memory 200964 kb
Host smart-43dfd5fb-cafa-416a-93de-8cfadf04c036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492942815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.492942815
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1491802100
Short name T265
Test name
Test status
Simulation time 198675767752 ps
CPU time 278.41 seconds
Started Aug 14 04:59:27 PM PDT 24
Finished Aug 14 05:04:05 PM PDT 24
Peak memory 200932 kb
Host smart-af0135d2-dbfa-4e74-989f-c76d5c33bc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491802100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1491802100
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3404094964
Short name T40
Test name
Test status
Simulation time 51920256934 ps
CPU time 45.19 seconds
Started Aug 14 05:02:17 PM PDT 24
Finished Aug 14 05:03:02 PM PDT 24
Peak memory 200804 kb
Host smart-3784abed-ef8b-4203-b170-3eb402a3a348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404094964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3404094964
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.3492689501
Short name T148
Test name
Test status
Simulation time 49200176632 ps
CPU time 24.07 seconds
Started Aug 14 05:03:34 PM PDT 24
Finished Aug 14 05:03:58 PM PDT 24
Peak memory 200976 kb
Host smart-ae2d3e47-2db9-4a05-b02c-8e8a300f784e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492689501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.3492689501
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_stress_all.423760396
Short name T97
Test name
Test status
Simulation time 343410021123 ps
CPU time 606.77 seconds
Started Aug 14 05:01:02 PM PDT 24
Finished Aug 14 05:11:09 PM PDT 24
Peak memory 200896 kb
Host smart-2a107a73-0d25-480c-aefe-03cd9be893b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423760396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.423760396
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2889670779
Short name T231
Test name
Test status
Simulation time 87984105266 ps
CPU time 173.66 seconds
Started Aug 14 05:00:37 PM PDT 24
Finished Aug 14 05:03:30 PM PDT 24
Peak memory 201292 kb
Host smart-1c21a8a1-4a14-4bfb-a219-1f3df3fa3e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889670779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2889670779
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1636048015
Short name T184
Test name
Test status
Simulation time 36528790201 ps
CPU time 74.09 seconds
Started Aug 14 05:03:43 PM PDT 24
Finished Aug 14 05:04:57 PM PDT 24
Peak memory 200884 kb
Host smart-cb8b6782-26d8-449c-8a5f-3c89d7a07ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636048015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1636048015
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3453129583
Short name T385
Test name
Test status
Simulation time 68570934459 ps
CPU time 32.48 seconds
Started Aug 14 05:01:40 PM PDT 24
Finished Aug 14 05:02:13 PM PDT 24
Peak memory 200972 kb
Host smart-d220f433-550c-490d-836a-9e26bbc4a8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453129583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3453129583
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1588011697
Short name T194
Test name
Test status
Simulation time 91203475886 ps
CPU time 43.1 seconds
Started Aug 14 05:04:01 PM PDT 24
Finished Aug 14 05:04:44 PM PDT 24
Peak memory 200876 kb
Host smart-901609c3-4762-438c-9b59-3793a18415e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588011697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1588011697
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.2247492557
Short name T79
Test name
Test status
Simulation time 172300663762 ps
CPU time 78.68 seconds
Started Aug 14 05:04:00 PM PDT 24
Finished Aug 14 05:05:18 PM PDT 24
Peak memory 200952 kb
Host smart-243b5b10-3a16-4745-b65d-8755519739f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247492557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2247492557
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3255009974
Short name T229
Test name
Test status
Simulation time 144440067408 ps
CPU time 250.52 seconds
Started Aug 14 04:59:07 PM PDT 24
Finished Aug 14 05:03:18 PM PDT 24
Peak memory 200712 kb
Host smart-70f2ac86-bd1b-4701-8894-6faeb23c624e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255009974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3255009974
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.488599867
Short name T104
Test name
Test status
Simulation time 88573822 ps
CPU time 0.97 seconds
Started Aug 14 04:38:23 PM PDT 24
Finished Aug 14 04:38:24 PM PDT 24
Peak memory 198832 kb
Host smart-a28706d0-8def-4fc4-a9e3-d583de6321d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488599867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.488599867
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_stress_all.3989631227
Short name T124
Test name
Test status
Simulation time 307294814166 ps
CPU time 467.09 seconds
Started Aug 14 04:58:48 PM PDT 24
Finished Aug 14 05:06:36 PM PDT 24
Peak memory 209284 kb
Host smart-b352b7fd-8b36-4657-a829-b3cdae605888
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989631227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.3989631227
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.169234888
Short name T83
Test name
Test status
Simulation time 5819821093 ps
CPU time 66.95 seconds
Started Aug 14 05:00:12 PM PDT 24
Finished Aug 14 05:01:19 PM PDT 24
Peak memory 209424 kb
Host smart-a3de1161-8d51-4981-b868-8300037b1ad0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169234888 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.169234888
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3896087079
Short name T151
Test name
Test status
Simulation time 19281761503 ps
CPU time 18.64 seconds
Started Aug 14 05:04:04 PM PDT 24
Finished Aug 14 05:04:23 PM PDT 24
Peak memory 200972 kb
Host smart-d5d31e9a-6234-45b1-b15a-032f110050f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896087079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3896087079
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2124141323
Short name T979
Test name
Test status
Simulation time 314126165708 ps
CPU time 381.46 seconds
Started Aug 14 05:01:50 PM PDT 24
Finished Aug 14 05:08:12 PM PDT 24
Peak memory 200760 kb
Host smart-ac36a216-8883-4580-b6ad-8cec45167aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124141323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2124141323
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_stress_all.1629555227
Short name T252
Test name
Test status
Simulation time 86294361310 ps
CPU time 43.34 seconds
Started Aug 14 05:02:36 PM PDT 24
Finished Aug 14 05:03:20 PM PDT 24
Peak memory 200956 kb
Host smart-e9fe1532-cdc6-4de6-8f2a-cfe795c44321
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629555227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1629555227
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.1272511856
Short name T158
Test name
Test status
Simulation time 107205330069 ps
CPU time 109.21 seconds
Started Aug 14 04:58:49 PM PDT 24
Finished Aug 14 05:00:38 PM PDT 24
Peak memory 200876 kb
Host smart-153b7cb8-2b0d-4214-8b76-16f076804d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272511856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1272511856
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3733330307
Short name T207
Test name
Test status
Simulation time 176837936581 ps
CPU time 153.85 seconds
Started Aug 14 05:03:15 PM PDT 24
Finished Aug 14 05:05:49 PM PDT 24
Peak memory 200936 kb
Host smart-ef9ebb82-b8c2-4d62-b167-7802d9c7eb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733330307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3733330307
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.1969135775
Short name T112
Test name
Test status
Simulation time 163360859870 ps
CPU time 115.97 seconds
Started Aug 14 05:03:46 PM PDT 24
Finished Aug 14 05:05:42 PM PDT 24
Peak memory 200900 kb
Host smart-f0e13a81-0d96-4ef9-874d-ffc01b52ca68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969135775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1969135775
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.2826498052
Short name T163
Test name
Test status
Simulation time 39137027621 ps
CPU time 17.74 seconds
Started Aug 14 05:04:21 PM PDT 24
Finished Aug 14 05:04:39 PM PDT 24
Peak memory 200948 kb
Host smart-3e480ba6-41a6-4c34-9125-c028e2a26131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826498052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2826498052
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_stress_all.3414238885
Short name T195
Test name
Test status
Simulation time 456238144313 ps
CPU time 69.63 seconds
Started Aug 14 05:02:10 PM PDT 24
Finished Aug 14 05:03:20 PM PDT 24
Peak memory 200976 kb
Host smart-1a0493ed-a3aa-41be-9bfd-6f9e92e5dd35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414238885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3414238885
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3152495413
Short name T152
Test name
Test status
Simulation time 92463103764 ps
CPU time 107.72 seconds
Started Aug 14 05:03:05 PM PDT 24
Finished Aug 14 05:04:53 PM PDT 24
Peak memory 200904 kb
Host smart-abdd422e-5ee3-442f-9210-bfc0f0b9f459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152495413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3152495413
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3974780725
Short name T317
Test name
Test status
Simulation time 7426327652 ps
CPU time 33.69 seconds
Started Aug 14 05:03:06 PM PDT 24
Finished Aug 14 05:03:40 PM PDT 24
Peak memory 217296 kb
Host smart-32685f88-93a3-4ce5-8a3d-66da30ebe5a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974780725 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3974780725
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.2731697856
Short name T159
Test name
Test status
Simulation time 214440388812 ps
CPU time 25.8 seconds
Started Aug 14 05:03:18 PM PDT 24
Finished Aug 14 05:03:44 PM PDT 24
Peak memory 200960 kb
Host smart-b0319d0e-cb34-4df1-a293-2177b58f651d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731697856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2731697856
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.580216130
Short name T1181
Test name
Test status
Simulation time 10506170989 ps
CPU time 20.86 seconds
Started Aug 14 05:03:32 PM PDT 24
Finished Aug 14 05:03:53 PM PDT 24
Peak memory 200924 kb
Host smart-9107e17d-98a0-4692-a41c-5eebccc9b334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580216130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.580216130
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.4264353962
Short name T226
Test name
Test status
Simulation time 142041809210 ps
CPU time 60.18 seconds
Started Aug 14 05:04:14 PM PDT 24
Finished Aug 14 05:05:14 PM PDT 24
Peak memory 200900 kb
Host smart-94e48361-768c-4341-98da-7cd4553cfd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264353962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.4264353962
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_noise_filter.3785197993
Short name T286
Test name
Test status
Simulation time 95995474502 ps
CPU time 168.91 seconds
Started Aug 14 04:58:50 PM PDT 24
Finished Aug 14 05:01:39 PM PDT 24
Peak memory 200348 kb
Host smart-b3e05e63-0a02-4b0e-a426-eb78a7ffb4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785197993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3785197993
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.502599699
Short name T161
Test name
Test status
Simulation time 117958518982 ps
CPU time 174.11 seconds
Started Aug 14 05:03:24 PM PDT 24
Finished Aug 14 05:06:18 PM PDT 24
Peak memory 200944 kb
Host smart-cce03c93-259a-442d-b677-54c7c05ac8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502599699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.502599699
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3608642186
Short name T1039
Test name
Test status
Simulation time 58874205139 ps
CPU time 12.31 seconds
Started Aug 14 05:03:33 PM PDT 24
Finished Aug 14 05:03:46 PM PDT 24
Peak memory 200868 kb
Host smart-8ff71dd5-d6e2-4309-be5b-9f9517980188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608642186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3608642186
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2790053015
Short name T891
Test name
Test status
Simulation time 104251954482 ps
CPU time 45.68 seconds
Started Aug 14 05:03:35 PM PDT 24
Finished Aug 14 05:04:21 PM PDT 24
Peak memory 200856 kb
Host smart-b40810d1-8d21-4a23-ba23-6e8bfe4b71b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790053015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2790053015
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2230976578
Short name T203
Test name
Test status
Simulation time 276805287705 ps
CPU time 87.06 seconds
Started Aug 14 05:03:37 PM PDT 24
Finished Aug 14 05:05:04 PM PDT 24
Peak memory 200968 kb
Host smart-592b8abf-de19-451c-85c8-c5bbd20f1029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230976578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2230976578
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3260301358
Short name T190
Test name
Test status
Simulation time 46340192693 ps
CPU time 124.95 seconds
Started Aug 14 05:03:44 PM PDT 24
Finished Aug 14 05:05:50 PM PDT 24
Peak memory 200964 kb
Host smart-b31b7466-f298-4412-b6ea-4958a34d1669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260301358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3260301358
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.749657480
Short name T118
Test name
Test status
Simulation time 30026131817 ps
CPU time 28.76 seconds
Started Aug 14 04:58:57 PM PDT 24
Finished Aug 14 04:59:27 PM PDT 24
Peak memory 200892 kb
Host smart-71181112-5876-4367-80fe-7e3ed93cfa82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749657480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.749657480
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2748779287
Short name T187
Test name
Test status
Simulation time 57019984104 ps
CPU time 20.46 seconds
Started Aug 14 05:03:58 PM PDT 24
Finished Aug 14 05:04:19 PM PDT 24
Peak memory 200860 kb
Host smart-9cf8cfd4-f06d-40c6-b1b5-c419522e1709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748779287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2748779287
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3232711336
Short name T128
Test name
Test status
Simulation time 69521105786 ps
CPU time 26.64 seconds
Started Aug 14 05:04:03 PM PDT 24
Finished Aug 14 05:04:30 PM PDT 24
Peak memory 200968 kb
Host smart-7b998a49-3b43-49d1-839d-63fa68f59b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232711336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3232711336
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1533942127
Short name T205
Test name
Test status
Simulation time 55848437264 ps
CPU time 26 seconds
Started Aug 14 05:04:22 PM PDT 24
Finished Aug 14 05:04:48 PM PDT 24
Peak memory 200952 kb
Host smart-215e5aff-ba92-48ec-aca0-c55de0167e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533942127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1533942127
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.152090611
Short name T428
Test name
Test status
Simulation time 3053754433 ps
CPU time 42.05 seconds
Started Aug 14 05:01:50 PM PDT 24
Finished Aug 14 05:02:32 PM PDT 24
Peak memory 217292 kb
Host smart-f82fd71a-482c-49f0-84d3-5ab70821c8e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152090611 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.152090611
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3197544084
Short name T168
Test name
Test status
Simulation time 95073568986 ps
CPU time 36.71 seconds
Started Aug 14 05:02:57 PM PDT 24
Finished Aug 14 05:03:34 PM PDT 24
Peak memory 200892 kb
Host smart-67ca0ba7-b447-4835-9b92-d4f39c7d4f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197544084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3197544084
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2389972245
Short name T413
Test name
Test status
Simulation time 83376766532 ps
CPU time 211.85 seconds
Started Aug 14 04:58:49 PM PDT 24
Finished Aug 14 05:02:21 PM PDT 24
Peak memory 200952 kb
Host smart-bf7c5ce6-bdb1-4192-b9d5-4be198ed2d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389972245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2389972245
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1346004727
Short name T199
Test name
Test status
Simulation time 89967357168 ps
CPU time 46.18 seconds
Started Aug 14 04:59:24 PM PDT 24
Finished Aug 14 05:00:10 PM PDT 24
Peak memory 200812 kb
Host smart-4b576339-9d24-4b78-aed9-cde874eaea54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346004727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1346004727
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.539505600
Short name T122
Test name
Test status
Simulation time 37688963820 ps
CPU time 13.18 seconds
Started Aug 14 05:03:15 PM PDT 24
Finished Aug 14 05:03:28 PM PDT 24
Peak memory 200948 kb
Host smart-1141fdc8-17f2-4010-bcd1-f3508897e5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539505600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.539505600
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3657721915
Short name T100
Test name
Test status
Simulation time 46831807670 ps
CPU time 34.11 seconds
Started Aug 14 04:59:35 PM PDT 24
Finished Aug 14 05:00:09 PM PDT 24
Peak memory 217328 kb
Host smart-445adecc-c059-4e56-9191-1b48c9fa8937
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657721915 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3657721915
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.89805618
Short name T222
Test name
Test status
Simulation time 17442033419 ps
CPU time 58.72 seconds
Started Aug 14 05:03:24 PM PDT 24
Finished Aug 14 05:04:23 PM PDT 24
Peak memory 200816 kb
Host smart-4a094b85-55b1-4ff6-a8a2-81533285b12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89805618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.89805618
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1856900854
Short name T169
Test name
Test status
Simulation time 119055560432 ps
CPU time 41.75 seconds
Started Aug 14 05:03:23 PM PDT 24
Finished Aug 14 05:04:04 PM PDT 24
Peak memory 200940 kb
Host smart-f8d82b2c-4cd6-4fcd-86e9-8dd0e7484786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856900854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1856900854
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1115969015
Short name T111
Test name
Test status
Simulation time 27068611068 ps
CPU time 49.99 seconds
Started Aug 14 05:03:43 PM PDT 24
Finished Aug 14 05:04:34 PM PDT 24
Peak memory 200876 kb
Host smart-8185c85b-2394-4e4e-99f9-63f56230fe15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115969015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1115969015
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.2866598474
Short name T172
Test name
Test status
Simulation time 72380313625 ps
CPU time 25.63 seconds
Started Aug 14 05:04:01 PM PDT 24
Finished Aug 14 05:04:26 PM PDT 24
Peak memory 200824 kb
Host smart-1b1de7f7-5c8e-49d7-b183-a83fc4b02c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866598474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2866598474
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3100451087
Short name T137
Test name
Test status
Simulation time 57739521953 ps
CPU time 15.95 seconds
Started Aug 14 05:04:09 PM PDT 24
Finished Aug 14 05:04:26 PM PDT 24
Peak memory 199524 kb
Host smart-e2a21827-1cd6-4744-9a2a-3742d8ffcede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100451087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3100451087
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3712791655
Short name T225
Test name
Test status
Simulation time 89431875766 ps
CPU time 144.69 seconds
Started Aug 14 05:04:05 PM PDT 24
Finished Aug 14 05:06:29 PM PDT 24
Peak memory 200952 kb
Host smart-8b3e954c-64ba-41f0-aa79-4f9dbd909217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712791655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3712791655
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3383078933
Short name T215
Test name
Test status
Simulation time 22096813125 ps
CPU time 12 seconds
Started Aug 14 05:04:04 PM PDT 24
Finished Aug 14 05:04:16 PM PDT 24
Peak memory 200856 kb
Host smart-f02966fd-b41d-4c54-95f2-57e30c241bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383078933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3383078933
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.990545075
Short name T178
Test name
Test status
Simulation time 56161856107 ps
CPU time 35.81 seconds
Started Aug 14 05:04:15 PM PDT 24
Finished Aug 14 05:04:51 PM PDT 24
Peak memory 200928 kb
Host smart-cc46cfdd-9041-4718-a045-56638b3d60b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990545075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.990545075
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1892141932
Short name T227
Test name
Test status
Simulation time 108675957122 ps
CPU time 80.35 seconds
Started Aug 14 05:04:21 PM PDT 24
Finished Aug 14 05:05:41 PM PDT 24
Peak memory 199980 kb
Host smart-c669157c-6250-4700-80fd-e9ed816bb6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892141932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1892141932
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.2360000045
Short name T156
Test name
Test status
Simulation time 16876226063 ps
CPU time 11.63 seconds
Started Aug 14 05:04:20 PM PDT 24
Finished Aug 14 05:04:31 PM PDT 24
Peak memory 200880 kb
Host smart-f6c38e97-8ced-49a7-b257-286799418fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360000045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.2360000045
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.744090844
Short name T143
Test name
Test status
Simulation time 33912556008 ps
CPU time 20.49 seconds
Started Aug 14 05:01:05 PM PDT 24
Finished Aug 14 05:01:25 PM PDT 24
Peak memory 200980 kb
Host smart-1a2e14e6-a6eb-4d29-96c2-96a434f8e676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744090844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.744090844
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2283608492
Short name T162
Test name
Test status
Simulation time 41030955092 ps
CPU time 21.8 seconds
Started Aug 14 05:02:08 PM PDT 24
Finished Aug 14 05:02:30 PM PDT 24
Peak memory 200928 kb
Host smart-bf04d14e-34ba-45ae-91a5-2a1d218b9836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283608492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2283608492
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.4286050685
Short name T164
Test name
Test status
Simulation time 140325589974 ps
CPU time 65.92 seconds
Started Aug 14 05:03:06 PM PDT 24
Finished Aug 14 05:04:12 PM PDT 24
Peak memory 200980 kb
Host smart-f60342cc-bdb6-4607-b9d7-26bb59021e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286050685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.4286050685
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1638892654
Short name T48
Test name
Test status
Simulation time 17857051 ps
CPU time 0.76 seconds
Started Aug 14 04:38:16 PM PDT 24
Finished Aug 14 04:38:17 PM PDT 24
Peak memory 196432 kb
Host smart-64ec09d2-ea20-4fbb-a050-e1cf9d6cdbce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638892654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1638892654
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1211461598
Short name T1256
Test name
Test status
Simulation time 192225206 ps
CPU time 1.48 seconds
Started Aug 14 04:37:56 PM PDT 24
Finished Aug 14 04:37:58 PM PDT 24
Peak memory 197836 kb
Host smart-3aba2e34-5ea1-4b4b-8067-12daad385ce4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211461598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1211461598
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4101833584
Short name T1265
Test name
Test status
Simulation time 50279080 ps
CPU time 0.6 seconds
Started Aug 14 04:38:20 PM PDT 24
Finished Aug 14 04:38:20 PM PDT 24
Peak memory 195384 kb
Host smart-d21a8f8e-5f52-4f44-a3d9-c51a6d7319e6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101833584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.4101833584
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.289289568
Short name T1243
Test name
Test status
Simulation time 18286900 ps
CPU time 0.65 seconds
Started Aug 14 04:38:26 PM PDT 24
Finished Aug 14 04:38:27 PM PDT 24
Peak memory 197976 kb
Host smart-b1005e33-bcc1-45d1-b860-20fe5793708d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289289568 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.289289568
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.617723521
Short name T50
Test name
Test status
Simulation time 12916959 ps
CPU time 0.57 seconds
Started Aug 14 04:38:03 PM PDT 24
Finished Aug 14 04:38:04 PM PDT 24
Peak memory 195392 kb
Host smart-1cc7ca26-cc38-4cca-b2c1-3d11363ae854
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617723521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.617723521
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1422738912
Short name T1263
Test name
Test status
Simulation time 48602532 ps
CPU time 0.55 seconds
Started Aug 14 04:38:10 PM PDT 24
Finished Aug 14 04:38:11 PM PDT 24
Peak memory 194520 kb
Host smart-f53767d6-bebf-49da-9d90-bf891bc406e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422738912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1422738912
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.82730471
Short name T1247
Test name
Test status
Simulation time 53718504 ps
CPU time 0.73 seconds
Started Aug 14 04:38:04 PM PDT 24
Finished Aug 14 04:38:05 PM PDT 24
Peak memory 196312 kb
Host smart-01e34acd-8e6e-4f4f-b35f-60512f212897
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82730471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_o
utstanding.82730471
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.1114186107
Short name T1257
Test name
Test status
Simulation time 217334342 ps
CPU time 1.37 seconds
Started Aug 14 04:38:20 PM PDT 24
Finished Aug 14 04:38:22 PM PDT 24
Peak memory 200168 kb
Host smart-3b6bee9b-3802-4702-8443-b8d6fdbe8d3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114186107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.1114186107
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.316745308
Short name T64
Test name
Test status
Simulation time 51306184 ps
CPU time 0.88 seconds
Started Aug 14 04:38:12 PM PDT 24
Finished Aug 14 04:38:13 PM PDT 24
Peak memory 198916 kb
Host smart-b25ccd22-852f-4759-bc50-b872b56f371c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316745308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.316745308
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2109001492
Short name T1188
Test name
Test status
Simulation time 57570935 ps
CPU time 0.66 seconds
Started Aug 14 04:38:16 PM PDT 24
Finished Aug 14 04:38:17 PM PDT 24
Peak memory 195040 kb
Host smart-853e1af4-6aac-4fda-b447-cf65384b65b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109001492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2109001492
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1059084127
Short name T1308
Test name
Test status
Simulation time 103280747 ps
CPU time 2.25 seconds
Started Aug 14 04:38:35 PM PDT 24
Finished Aug 14 04:38:37 PM PDT 24
Peak memory 198060 kb
Host smart-426f235f-f442-4135-95f2-a719366df8cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059084127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1059084127
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1391633033
Short name T1315
Test name
Test status
Simulation time 11701252 ps
CPU time 0.57 seconds
Started Aug 14 04:37:50 PM PDT 24
Finished Aug 14 04:37:51 PM PDT 24
Peak memory 195412 kb
Host smart-6c370fdc-1566-4a86-8ca4-064f47e79a4a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391633033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1391633033
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3076649626
Short name T1191
Test name
Test status
Simulation time 22716372 ps
CPU time 1.08 seconds
Started Aug 14 04:38:08 PM PDT 24
Finished Aug 14 04:38:09 PM PDT 24
Peak memory 200236 kb
Host smart-d9660223-d0ff-4657-ae57-ec2a7041df68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076649626 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3076649626
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.1429392229
Short name T51
Test name
Test status
Simulation time 55694969 ps
CPU time 0.61 seconds
Started Aug 14 04:38:22 PM PDT 24
Finished Aug 14 04:38:23 PM PDT 24
Peak memory 195564 kb
Host smart-b2256a37-fe2c-4ee8-a0ee-35051c2530f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429392229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1429392229
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3246204530
Short name T1193
Test name
Test status
Simulation time 18837002 ps
CPU time 0.58 seconds
Started Aug 14 04:38:29 PM PDT 24
Finished Aug 14 04:38:30 PM PDT 24
Peak memory 194496 kb
Host smart-f0b574a4-9db4-442e-bc6d-0beca223ce61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246204530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3246204530
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1585071732
Short name T1224
Test name
Test status
Simulation time 41769684 ps
CPU time 0.67 seconds
Started Aug 14 04:38:20 PM PDT 24
Finished Aug 14 04:38:25 PM PDT 24
Peak memory 194608 kb
Host smart-60c05008-fa16-44a4-94c6-8d239757c043
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585071732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1585071732
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.2465608150
Short name T1216
Test name
Test status
Simulation time 155212909 ps
CPU time 1.52 seconds
Started Aug 14 04:38:34 PM PDT 24
Finished Aug 14 04:38:35 PM PDT 24
Peak memory 200144 kb
Host smart-d79cf442-4354-4605-93a5-53aa8465bce6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465608150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2465608150
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3625197971
Short name T65
Test name
Test status
Simulation time 106755955 ps
CPU time 1.33 seconds
Started Aug 14 04:38:22 PM PDT 24
Finished Aug 14 04:38:24 PM PDT 24
Peak memory 199544 kb
Host smart-ce2e0551-c503-455a-9c84-88296fb22815
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625197971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3625197971
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2172698043
Short name T1264
Test name
Test status
Simulation time 49861885 ps
CPU time 0.66 seconds
Started Aug 14 04:38:11 PM PDT 24
Finished Aug 14 04:38:11 PM PDT 24
Peak memory 198480 kb
Host smart-96bf9b28-a25d-43b3-9df9-59438f154cc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172698043 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2172698043
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2412396866
Short name T1317
Test name
Test status
Simulation time 22666540 ps
CPU time 0.57 seconds
Started Aug 14 04:38:31 PM PDT 24
Finished Aug 14 04:38:32 PM PDT 24
Peak memory 195444 kb
Host smart-8b0b21e9-6789-4176-b5a7-0fd8c0409870
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412396866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2412396866
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2717070108
Short name T1204
Test name
Test status
Simulation time 13323059 ps
CPU time 0.55 seconds
Started Aug 14 04:38:14 PM PDT 24
Finished Aug 14 04:38:15 PM PDT 24
Peak memory 194552 kb
Host smart-a335f19a-aaa3-4c1d-b820-d56a2aa4859e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717070108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2717070108
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.436280709
Short name T1285
Test name
Test status
Simulation time 20472125 ps
CPU time 0.64 seconds
Started Aug 14 04:37:52 PM PDT 24
Finished Aug 14 04:37:53 PM PDT 24
Peak memory 195052 kb
Host smart-e85e4b23-ace8-4f2f-a08d-b63c4a126558
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436280709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.436280709
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2026336082
Short name T1311
Test name
Test status
Simulation time 297985393 ps
CPU time 1.31 seconds
Started Aug 14 04:38:18 PM PDT 24
Finished Aug 14 04:38:19 PM PDT 24
Peak memory 200148 kb
Host smart-a85591ad-f88a-4234-8c59-db4452ccdcbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026336082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2026336082
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.323709738
Short name T1205
Test name
Test status
Simulation time 106391113 ps
CPU time 0.87 seconds
Started Aug 14 04:38:27 PM PDT 24
Finished Aug 14 04:38:28 PM PDT 24
Peak memory 198788 kb
Host smart-52c465fe-2919-4a22-9fac-77b0bf9411e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323709738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.323709738
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2222816853
Short name T1262
Test name
Test status
Simulation time 63853624 ps
CPU time 0.87 seconds
Started Aug 14 04:38:11 PM PDT 24
Finished Aug 14 04:38:17 PM PDT 24
Peak memory 199932 kb
Host smart-b44ca2d8-f93f-43da-ae05-25e78a0e95c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222816853 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2222816853
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.1774203893
Short name T1259
Test name
Test status
Simulation time 19812943 ps
CPU time 0.6 seconds
Started Aug 14 04:38:19 PM PDT 24
Finished Aug 14 04:38:20 PM PDT 24
Peak memory 195712 kb
Host smart-827b2cbc-e9dc-48cf-84b6-de113b323912
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774203893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1774203893
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.3983492842
Short name T1314
Test name
Test status
Simulation time 11843206 ps
CPU time 0.6 seconds
Started Aug 14 04:38:19 PM PDT 24
Finished Aug 14 04:38:20 PM PDT 24
Peak memory 194492 kb
Host smart-764f08e9-7d39-49d6-8a38-75be011586ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983492842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3983492842
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1183763733
Short name T1250
Test name
Test status
Simulation time 43268736 ps
CPU time 0.61 seconds
Started Aug 14 04:38:20 PM PDT 24
Finished Aug 14 04:38:21 PM PDT 24
Peak memory 195836 kb
Host smart-1c317bd7-878b-4b73-8250-e10aa044f645
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183763733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1183763733
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.60270684
Short name T1235
Test name
Test status
Simulation time 167408440 ps
CPU time 2.2 seconds
Started Aug 14 04:38:06 PM PDT 24
Finished Aug 14 04:38:08 PM PDT 24
Peak memory 200240 kb
Host smart-3b5a157d-2dcf-43c2-bb4b-6a6197371d69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60270684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.60270684
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3460139311
Short name T70
Test name
Test status
Simulation time 359973246 ps
CPU time 1.3 seconds
Started Aug 14 04:38:19 PM PDT 24
Finished Aug 14 04:38:20 PM PDT 24
Peak memory 199636 kb
Host smart-bff262ee-36ef-4991-bd64-1fb48a623d28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460139311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3460139311
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3532702276
Short name T1299
Test name
Test status
Simulation time 91714806 ps
CPU time 1.24 seconds
Started Aug 14 04:38:20 PM PDT 24
Finished Aug 14 04:38:21 PM PDT 24
Peak memory 200172 kb
Host smart-1dd4e0f3-eaf8-4711-9801-24a01362e187
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532702276 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3532702276
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2078874221
Short name T49
Test name
Test status
Simulation time 13534270 ps
CPU time 0.6 seconds
Started Aug 14 04:38:26 PM PDT 24
Finished Aug 14 04:38:27 PM PDT 24
Peak memory 195448 kb
Host smart-1369a629-b758-4a89-bf67-dd0d446fbdaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078874221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2078874221
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3118612034
Short name T1275
Test name
Test status
Simulation time 16841822 ps
CPU time 0.58 seconds
Started Aug 14 04:38:17 PM PDT 24
Finished Aug 14 04:38:18 PM PDT 24
Peak memory 194488 kb
Host smart-4f5d9ed8-023f-468a-82f3-5e1ea2a43de3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118612034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3118612034
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2893618597
Short name T55
Test name
Test status
Simulation time 25194932 ps
CPU time 0.72 seconds
Started Aug 14 04:38:07 PM PDT 24
Finished Aug 14 04:38:08 PM PDT 24
Peak memory 197144 kb
Host smart-9d0e364d-cd62-4f5a-bd05-1834078d43d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893618597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2893618597
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.782163983
Short name T1240
Test name
Test status
Simulation time 34647857 ps
CPU time 1.74 seconds
Started Aug 14 04:38:27 PM PDT 24
Finished Aug 14 04:38:29 PM PDT 24
Peak memory 200244 kb
Host smart-d427daf3-c251-4d7d-842a-092dc2d3702e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782163983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.782163983
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3074731813
Short name T1312
Test name
Test status
Simulation time 89208219 ps
CPU time 0.97 seconds
Started Aug 14 04:38:15 PM PDT 24
Finished Aug 14 04:38:16 PM PDT 24
Peak memory 199300 kb
Host smart-9ec173ba-5d76-4730-8595-6bb613925305
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074731813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3074731813
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.962366106
Short name T1248
Test name
Test status
Simulation time 37584845 ps
CPU time 1.01 seconds
Started Aug 14 04:38:17 PM PDT 24
Finished Aug 14 04:38:18 PM PDT 24
Peak memory 199924 kb
Host smart-78144841-b1d3-441d-9e11-c7f3b5ab4ed9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962366106 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.962366106
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.2174950788
Short name T1290
Test name
Test status
Simulation time 31725924 ps
CPU time 0.57 seconds
Started Aug 14 04:38:16 PM PDT 24
Finished Aug 14 04:38:16 PM PDT 24
Peak memory 194472 kb
Host smart-79ba5671-5a78-4f37-b74e-9ed4e0e94bae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174950788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2174950788
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2992609930
Short name T1241
Test name
Test status
Simulation time 31059446 ps
CPU time 0.76 seconds
Started Aug 14 04:38:31 PM PDT 24
Finished Aug 14 04:38:32 PM PDT 24
Peak memory 197236 kb
Host smart-68221881-4a91-44c6-9e5c-92f8b783ce82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992609930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.2992609930
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3177962205
Short name T1213
Test name
Test status
Simulation time 178219643 ps
CPU time 1.28 seconds
Started Aug 14 04:38:19 PM PDT 24
Finished Aug 14 04:38:21 PM PDT 24
Peak memory 200184 kb
Host smart-0f907160-cc60-4c11-922a-d96ecb3f792f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177962205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3177962205
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.205690584
Short name T66
Test name
Test status
Simulation time 467546053 ps
CPU time 1.44 seconds
Started Aug 14 04:38:45 PM PDT 24
Finished Aug 14 04:38:46 PM PDT 24
Peak memory 199392 kb
Host smart-25766d95-eaac-4fde-99a4-0398adbfe98e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205690584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.205690584
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.17317991
Short name T1316
Test name
Test status
Simulation time 69418309 ps
CPU time 0.94 seconds
Started Aug 14 04:38:19 PM PDT 24
Finished Aug 14 04:38:20 PM PDT 24
Peak memory 199780 kb
Host smart-53a5c39b-b04d-4bc3-9142-ded95193c382
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17317991 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.17317991
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.74087305
Short name T1225
Test name
Test status
Simulation time 56242693 ps
CPU time 0.61 seconds
Started Aug 14 04:38:27 PM PDT 24
Finished Aug 14 04:38:28 PM PDT 24
Peak memory 195624 kb
Host smart-4b01a3fe-0522-47c0-907e-f1023e09c965
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74087305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.74087305
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.311391845
Short name T1236
Test name
Test status
Simulation time 31698649 ps
CPU time 0.57 seconds
Started Aug 14 04:38:28 PM PDT 24
Finished Aug 14 04:38:29 PM PDT 24
Peak memory 194592 kb
Host smart-11871b0a-bfed-4415-9e1c-15c15f6bac9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311391845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.311391845
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.773472849
Short name T1302
Test name
Test status
Simulation time 161739483 ps
CPU time 0.63 seconds
Started Aug 14 04:38:22 PM PDT 24
Finished Aug 14 04:38:23 PM PDT 24
Peak memory 195732 kb
Host smart-5b45389e-6067-4ffc-9f79-60bb63bc554d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773472849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr
_outstanding.773472849
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2260866753
Short name T1284
Test name
Test status
Simulation time 83508916 ps
CPU time 2.28 seconds
Started Aug 14 04:38:22 PM PDT 24
Finished Aug 14 04:38:24 PM PDT 24
Peak memory 200172 kb
Host smart-0748a9ef-0f8b-409a-bfca-6b39d2a0a40b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260866753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2260866753
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.4089133429
Short name T103
Test name
Test status
Simulation time 77806202 ps
CPU time 1.27 seconds
Started Aug 14 04:38:33 PM PDT 24
Finished Aug 14 04:38:34 PM PDT 24
Peak memory 199688 kb
Host smart-e6d35944-a5b9-40ef-a4a9-ba45af8700e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089133429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.4089133429
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3003004536
Short name T1221
Test name
Test status
Simulation time 32120826 ps
CPU time 0.86 seconds
Started Aug 14 04:38:28 PM PDT 24
Finished Aug 14 04:38:29 PM PDT 24
Peak memory 199940 kb
Host smart-d23855ee-b408-406e-95a5-60faed25d1c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003004536 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3003004536
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3587696114
Short name T1277
Test name
Test status
Simulation time 26782169 ps
CPU time 0.63 seconds
Started Aug 14 04:38:50 PM PDT 24
Finished Aug 14 04:38:51 PM PDT 24
Peak memory 195432 kb
Host smart-858e0cfa-6646-4684-b632-3c269b5ee445
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587696114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3587696114
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.1082569784
Short name T1298
Test name
Test status
Simulation time 25086190 ps
CPU time 0.57 seconds
Started Aug 14 04:38:24 PM PDT 24
Finished Aug 14 04:38:25 PM PDT 24
Peak memory 194516 kb
Host smart-b119669e-f0b1-48ec-bd63-5458cd2b8b6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082569784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.1082569784
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1222915290
Short name T61
Test name
Test status
Simulation time 23083070 ps
CPU time 0.67 seconds
Started Aug 14 04:38:34 PM PDT 24
Finished Aug 14 04:38:35 PM PDT 24
Peak memory 194624 kb
Host smart-31698c96-cbc9-4cde-903a-cbe6cac737d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222915290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1222915290
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2889349214
Short name T1296
Test name
Test status
Simulation time 389562256 ps
CPU time 1.59 seconds
Started Aug 14 04:38:39 PM PDT 24
Finished Aug 14 04:38:40 PM PDT 24
Peak memory 200136 kb
Host smart-b1cdabfb-aff2-4da7-9f8d-d03461042bfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889349214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2889349214
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3109197862
Short name T1251
Test name
Test status
Simulation time 148209921 ps
CPU time 1.01 seconds
Started Aug 14 04:38:27 PM PDT 24
Finished Aug 14 04:38:28 PM PDT 24
Peak memory 198952 kb
Host smart-01e6d8b5-10b2-440d-ac0f-a8be1d4a92a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109197862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3109197862
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1176084609
Short name T1227
Test name
Test status
Simulation time 24062977 ps
CPU time 0.81 seconds
Started Aug 14 04:38:17 PM PDT 24
Finished Aug 14 04:38:23 PM PDT 24
Peak memory 199008 kb
Host smart-1dff2a9d-7700-4368-ac0b-190cf90c11d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176084609 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1176084609
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1265302161
Short name T56
Test name
Test status
Simulation time 58109130 ps
CPU time 0.57 seconds
Started Aug 14 04:38:14 PM PDT 24
Finished Aug 14 04:38:15 PM PDT 24
Peak memory 195432 kb
Host smart-6ff4c6c9-f819-427a-aedc-fb57c511f77c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265302161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1265302161
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.3141644099
Short name T1295
Test name
Test status
Simulation time 48724462 ps
CPU time 0.55 seconds
Started Aug 14 04:38:39 PM PDT 24
Finished Aug 14 04:38:40 PM PDT 24
Peak memory 194496 kb
Host smart-ea5c6753-7bb1-4088-a024-6d749d4f3282
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141644099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3141644099
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1315664920
Short name T1288
Test name
Test status
Simulation time 26283652 ps
CPU time 0.76 seconds
Started Aug 14 04:38:31 PM PDT 24
Finished Aug 14 04:38:32 PM PDT 24
Peak memory 197176 kb
Host smart-f236de47-acdf-4009-acd0-42d2650531d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315664920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1315664920
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3519449786
Short name T1203
Test name
Test status
Simulation time 780737809 ps
CPU time 1.95 seconds
Started Aug 14 04:38:33 PM PDT 24
Finished Aug 14 04:38:36 PM PDT 24
Peak memory 200172 kb
Host smart-66e85fda-066b-4639-baaf-28ebee941fbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519449786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3519449786
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1748162911
Short name T1287
Test name
Test status
Simulation time 162093723 ps
CPU time 1.3 seconds
Started Aug 14 04:38:18 PM PDT 24
Finished Aug 14 04:38:24 PM PDT 24
Peak memory 199600 kb
Host smart-866aea1a-bb31-429f-936f-6466b0c10c42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748162911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.1748162911
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3044246706
Short name T1186
Test name
Test status
Simulation time 61156514 ps
CPU time 0.68 seconds
Started Aug 14 04:38:17 PM PDT 24
Finished Aug 14 04:38:18 PM PDT 24
Peak memory 198244 kb
Host smart-b360104c-5c81-45c4-a51c-1fdd1c5e2b82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044246706 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3044246706
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3897996368
Short name T1231
Test name
Test status
Simulation time 13364948 ps
CPU time 0.62 seconds
Started Aug 14 04:38:25 PM PDT 24
Finished Aug 14 04:38:31 PM PDT 24
Peak memory 195696 kb
Host smart-b995ecc7-1a7f-4cca-bd6a-5a92c2ac6ebb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897996368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3897996368
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3168440114
Short name T1268
Test name
Test status
Simulation time 49336851 ps
CPU time 0.54 seconds
Started Aug 14 04:38:35 PM PDT 24
Finished Aug 14 04:38:35 PM PDT 24
Peak memory 194552 kb
Host smart-df6d1d7a-1eef-486e-85ac-9329e2269acb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168440114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3168440114
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1129837631
Short name T1304
Test name
Test status
Simulation time 117629603 ps
CPU time 0.69 seconds
Started Aug 14 04:38:20 PM PDT 24
Finished Aug 14 04:38:21 PM PDT 24
Peak memory 194984 kb
Host smart-d6ed0d22-d09e-467e-979f-92c9f3367c70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129837631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.1129837631
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.4165941086
Short name T1255
Test name
Test status
Simulation time 99357792 ps
CPU time 2.08 seconds
Started Aug 14 04:38:26 PM PDT 24
Finished Aug 14 04:38:28 PM PDT 24
Peak memory 200284 kb
Host smart-b7736870-144b-444f-8fcf-956ee408098d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165941086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.4165941086
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.371542608
Short name T67
Test name
Test status
Simulation time 339710258 ps
CPU time 0.88 seconds
Started Aug 14 04:38:17 PM PDT 24
Finished Aug 14 04:38:18 PM PDT 24
Peak memory 198888 kb
Host smart-d7d65f78-a46f-44df-90b3-6a4d15093081
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371542608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.371542608
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2213867945
Short name T1293
Test name
Test status
Simulation time 122208678 ps
CPU time 0.83 seconds
Started Aug 14 04:38:37 PM PDT 24
Finished Aug 14 04:38:38 PM PDT 24
Peak memory 199908 kb
Host smart-3e23be98-d24a-43cc-a9bf-d3ae0a379816
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213867945 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2213867945
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3432971462
Short name T1237
Test name
Test status
Simulation time 15588154 ps
CPU time 0.65 seconds
Started Aug 14 04:38:33 PM PDT 24
Finished Aug 14 04:38:34 PM PDT 24
Peak memory 195532 kb
Host smart-0966981a-1611-459d-9c4f-37532f040a96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432971462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3432971462
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3641815590
Short name T1187
Test name
Test status
Simulation time 10916218 ps
CPU time 0.54 seconds
Started Aug 14 04:38:33 PM PDT 24
Finished Aug 14 04:38:33 PM PDT 24
Peak memory 194468 kb
Host smart-719ac658-5dd1-4ef4-882c-ce02f250fe12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641815590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3641815590
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.129155354
Short name T1228
Test name
Test status
Simulation time 43551527 ps
CPU time 0.63 seconds
Started Aug 14 04:38:43 PM PDT 24
Finished Aug 14 04:38:43 PM PDT 24
Peak memory 194968 kb
Host smart-ed0f1167-36ba-423e-ba6d-2e318896acc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129155354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr
_outstanding.129155354
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.1768561263
Short name T1292
Test name
Test status
Simulation time 73161292 ps
CPU time 1.96 seconds
Started Aug 14 04:38:27 PM PDT 24
Finished Aug 14 04:38:29 PM PDT 24
Peak memory 200172 kb
Host smart-df8dff2b-8289-46eb-9c29-d3d6aee86079
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768561263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1768561263
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1289480952
Short name T1238
Test name
Test status
Simulation time 30269133 ps
CPU time 0.79 seconds
Started Aug 14 04:38:18 PM PDT 24
Finished Aug 14 04:38:18 PM PDT 24
Peak memory 199916 kb
Host smart-08f93d8c-2d12-4715-ae19-8114f194f74e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289480952 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1289480952
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2932281916
Short name T1246
Test name
Test status
Simulation time 149561194 ps
CPU time 0.6 seconds
Started Aug 14 04:38:26 PM PDT 24
Finished Aug 14 04:38:27 PM PDT 24
Peak memory 195456 kb
Host smart-7186d6e5-b330-40dc-a6fb-376f462a0cf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932281916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2932281916
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.2815593053
Short name T1253
Test name
Test status
Simulation time 37159036 ps
CPU time 0.55 seconds
Started Aug 14 04:38:44 PM PDT 24
Finished Aug 14 04:38:45 PM PDT 24
Peak memory 194560 kb
Host smart-670ebed3-a9b3-4757-ad76-9466c51b5c11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815593053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2815593053
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2862153221
Short name T1297
Test name
Test status
Simulation time 76040288 ps
CPU time 0.64 seconds
Started Aug 14 04:38:35 PM PDT 24
Finished Aug 14 04:38:35 PM PDT 24
Peak memory 196676 kb
Host smart-83d315bc-3bc9-4a73-abf5-63a220c3dac3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862153221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2862153221
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3001661072
Short name T1192
Test name
Test status
Simulation time 345390740 ps
CPU time 1.84 seconds
Started Aug 14 04:38:30 PM PDT 24
Finished Aug 14 04:38:32 PM PDT 24
Peak memory 200168 kb
Host smart-ae9ad654-1a8c-4d83-8bcb-aea6b0835217
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001661072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3001661072
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.501887786
Short name T1222
Test name
Test status
Simulation time 52637816 ps
CPU time 0.91 seconds
Started Aug 14 04:38:15 PM PDT 24
Finished Aug 14 04:38:16 PM PDT 24
Peak memory 199260 kb
Host smart-5ca902c6-8966-48a0-8786-b378e5caba34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501887786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.501887786
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2436422919
Short name T1226
Test name
Test status
Simulation time 51837213 ps
CPU time 0.62 seconds
Started Aug 14 04:38:21 PM PDT 24
Finished Aug 14 04:38:22 PM PDT 24
Peak memory 194888 kb
Host smart-3c01b8b1-3c8f-46b4-9792-13a68b48e9e7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436422919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2436422919
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1041793343
Short name T53
Test name
Test status
Simulation time 266598265 ps
CPU time 2.48 seconds
Started Aug 14 04:38:22 PM PDT 24
Finished Aug 14 04:38:25 PM PDT 24
Peak memory 197760 kb
Host smart-51373a5f-ed5b-4a17-b0f3-b0abc848ed1c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041793343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1041793343
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3533306908
Short name T1270
Test name
Test status
Simulation time 12841363 ps
CPU time 0.58 seconds
Started Aug 14 04:38:14 PM PDT 24
Finished Aug 14 04:38:15 PM PDT 24
Peak memory 195512 kb
Host smart-92b39eaf-7709-4eb2-8338-c5555db1e86e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533306908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3533306908
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2945729224
Short name T1214
Test name
Test status
Simulation time 58800669 ps
CPU time 0.92 seconds
Started Aug 14 04:38:35 PM PDT 24
Finished Aug 14 04:38:36 PM PDT 24
Peak memory 199924 kb
Host smart-a3ab61b6-ca20-4c37-bffc-2ecb15424225
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945729224 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2945729224
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.241319588
Short name T45
Test name
Test status
Simulation time 15230462 ps
CPU time 0.61 seconds
Started Aug 14 04:37:57 PM PDT 24
Finished Aug 14 04:37:58 PM PDT 24
Peak memory 195780 kb
Host smart-79860cc6-783e-451f-9a6a-6173932b519e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241319588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.241319588
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.1398637857
Short name T1294
Test name
Test status
Simulation time 89931892 ps
CPU time 0.55 seconds
Started Aug 14 04:38:14 PM PDT 24
Finished Aug 14 04:38:15 PM PDT 24
Peak memory 194532 kb
Host smart-073ed62d-4854-438a-b0ae-ace4626f9aa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398637857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1398637857
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3851238081
Short name T57
Test name
Test status
Simulation time 62049789 ps
CPU time 0.75 seconds
Started Aug 14 04:38:35 PM PDT 24
Finished Aug 14 04:38:36 PM PDT 24
Peak memory 197176 kb
Host smart-119e9b26-7507-4863-84dd-cb0e18c439fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851238081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3851238081
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.264812254
Short name T1234
Test name
Test status
Simulation time 64026865 ps
CPU time 1.3 seconds
Started Aug 14 04:38:24 PM PDT 24
Finished Aug 14 04:38:26 PM PDT 24
Peak memory 200144 kb
Host smart-762eef33-4e7e-44b5-8d9f-f0220a839ddf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264812254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.264812254
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.490694115
Short name T71
Test name
Test status
Simulation time 366046729 ps
CPU time 1.28 seconds
Started Aug 14 04:37:57 PM PDT 24
Finished Aug 14 04:37:58 PM PDT 24
Peak memory 199552 kb
Host smart-15aaf176-3c02-4655-8a1e-10a26ecd8cfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490694115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.490694115
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3369181550
Short name T1208
Test name
Test status
Simulation time 68634712 ps
CPU time 0.55 seconds
Started Aug 14 04:38:21 PM PDT 24
Finished Aug 14 04:38:21 PM PDT 24
Peak memory 194576 kb
Host smart-4d4cf871-c7ca-42f0-9cfc-6056a6a093ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369181550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3369181550
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2958941665
Short name T1202
Test name
Test status
Simulation time 59565824 ps
CPU time 0.59 seconds
Started Aug 14 04:38:22 PM PDT 24
Finished Aug 14 04:38:23 PM PDT 24
Peak memory 194388 kb
Host smart-d48272b7-3e86-4331-a45b-9eee2b6b75ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958941665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2958941665
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2779875609
Short name T1210
Test name
Test status
Simulation time 25574027 ps
CPU time 0.57 seconds
Started Aug 14 04:38:34 PM PDT 24
Finished Aug 14 04:38:35 PM PDT 24
Peak memory 194492 kb
Host smart-12b0bc1c-db06-41c6-b9a6-8a04a559629a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779875609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2779875609
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.3037520131
Short name T1281
Test name
Test status
Simulation time 25069399 ps
CPU time 0.6 seconds
Started Aug 14 04:38:20 PM PDT 24
Finished Aug 14 04:38:21 PM PDT 24
Peak memory 194564 kb
Host smart-e40ae7a8-02ef-4302-bd7f-41870d2a8def
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037520131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3037520131
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.3763048376
Short name T1309
Test name
Test status
Simulation time 29426722 ps
CPU time 0.59 seconds
Started Aug 14 04:38:37 PM PDT 24
Finished Aug 14 04:38:38 PM PDT 24
Peak memory 194516 kb
Host smart-29867ac7-6f47-4f30-9788-521d1f721762
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763048376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3763048376
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2224698949
Short name T1269
Test name
Test status
Simulation time 25805687 ps
CPU time 0.54 seconds
Started Aug 14 04:38:31 PM PDT 24
Finished Aug 14 04:38:31 PM PDT 24
Peak memory 194576 kb
Host smart-db26a9a5-fb39-4752-bee1-b93fe19a2891
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224698949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2224698949
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1129461874
Short name T1301
Test name
Test status
Simulation time 11487339 ps
CPU time 0.55 seconds
Started Aug 14 04:38:37 PM PDT 24
Finished Aug 14 04:38:38 PM PDT 24
Peak memory 194576 kb
Host smart-3a9efb6c-1e11-410b-bd28-3a67fa2efc09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129461874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1129461874
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3881517105
Short name T1254
Test name
Test status
Simulation time 36882106 ps
CPU time 0.56 seconds
Started Aug 14 04:38:37 PM PDT 24
Finished Aug 14 04:38:38 PM PDT 24
Peak memory 194392 kb
Host smart-963f68dc-08cf-4031-ac3a-70d48c750f12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881517105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3881517105
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.1871002517
Short name T1232
Test name
Test status
Simulation time 20880835 ps
CPU time 0.59 seconds
Started Aug 14 04:38:38 PM PDT 24
Finished Aug 14 04:38:38 PM PDT 24
Peak memory 193544 kb
Host smart-db0679af-542b-4fa1-ab3b-16b7642502b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871002517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1871002517
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.765693846
Short name T1201
Test name
Test status
Simulation time 14547734 ps
CPU time 0.57 seconds
Started Aug 14 04:38:29 PM PDT 24
Finished Aug 14 04:38:30 PM PDT 24
Peak memory 193540 kb
Host smart-24ef7956-5d7a-41af-ad9f-29af2e95f6f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765693846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.765693846
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.294104564
Short name T46
Test name
Test status
Simulation time 18605073 ps
CPU time 0.67 seconds
Started Aug 14 04:38:16 PM PDT 24
Finished Aug 14 04:38:17 PM PDT 24
Peak memory 195432 kb
Host smart-d5f9e0c2-9277-47d5-b3e0-54c431802be1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294104564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.294104564
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.603010799
Short name T1266
Test name
Test status
Simulation time 135497423 ps
CPU time 1.48 seconds
Started Aug 14 04:38:19 PM PDT 24
Finished Aug 14 04:38:21 PM PDT 24
Peak memory 197812 kb
Host smart-4bc5ad8a-5b7b-4ce6-99fd-3f3e7a877c99
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603010799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.603010799
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3234659152
Short name T47
Test name
Test status
Simulation time 62738548 ps
CPU time 0.59 seconds
Started Aug 14 04:38:15 PM PDT 24
Finished Aug 14 04:38:15 PM PDT 24
Peak memory 195428 kb
Host smart-ca8c61bd-1a03-43ce-a2d9-8869ad492ad8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234659152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3234659152
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.448426598
Short name T1215
Test name
Test status
Simulation time 92977690 ps
CPU time 1.16 seconds
Started Aug 14 04:38:34 PM PDT 24
Finished Aug 14 04:38:35 PM PDT 24
Peak memory 200240 kb
Host smart-1a9573f4-89a9-4f94-b51a-72c80f1183b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448426598 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.448426598
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.1462429531
Short name T1217
Test name
Test status
Simulation time 18179039 ps
CPU time 0.62 seconds
Started Aug 14 04:38:16 PM PDT 24
Finished Aug 14 04:38:27 PM PDT 24
Peak memory 195588 kb
Host smart-d4dadaa8-b86c-4c34-a2c2-87fd8ea014f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462429531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1462429531
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.953689490
Short name T1276
Test name
Test status
Simulation time 18154734 ps
CPU time 0.58 seconds
Started Aug 14 04:38:13 PM PDT 24
Finished Aug 14 04:38:14 PM PDT 24
Peak memory 194572 kb
Host smart-d39e7ec5-c2c2-49ad-831d-fcda81108336
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953689490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.953689490
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1310007617
Short name T59
Test name
Test status
Simulation time 15003660 ps
CPU time 0.67 seconds
Started Aug 14 04:38:10 PM PDT 24
Finished Aug 14 04:38:11 PM PDT 24
Peak memory 195840 kb
Host smart-53d105c1-92ba-4164-abe3-1bc356b2cbb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310007617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1310007617
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.4009292823
Short name T1307
Test name
Test status
Simulation time 431144155 ps
CPU time 1.92 seconds
Started Aug 14 04:38:16 PM PDT 24
Finished Aug 14 04:38:18 PM PDT 24
Peak memory 200172 kb
Host smart-8458fffe-7fea-4a48-8942-5a464925a050
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009292823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.4009292823
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1897267106
Short name T1271
Test name
Test status
Simulation time 128833764 ps
CPU time 1.32 seconds
Started Aug 14 04:38:13 PM PDT 24
Finished Aug 14 04:38:14 PM PDT 24
Peak memory 199520 kb
Host smart-b34e23b4-e796-4a15-933d-52dedecb4dfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897267106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1897267106
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.489919138
Short name T1310
Test name
Test status
Simulation time 55479639 ps
CPU time 0.57 seconds
Started Aug 14 04:38:25 PM PDT 24
Finished Aug 14 04:38:25 PM PDT 24
Peak memory 194580 kb
Host smart-eaaf050d-7e42-41ea-bd21-0c10488106d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489919138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.489919138
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.129293668
Short name T1273
Test name
Test status
Simulation time 22318530 ps
CPU time 0.53 seconds
Started Aug 14 04:38:33 PM PDT 24
Finished Aug 14 04:38:33 PM PDT 24
Peak memory 194500 kb
Host smart-94f2627f-306d-447c-83d0-ad759e87a770
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129293668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.129293668
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.164419132
Short name T1195
Test name
Test status
Simulation time 25958530 ps
CPU time 0.56 seconds
Started Aug 14 04:38:20 PM PDT 24
Finished Aug 14 04:38:21 PM PDT 24
Peak memory 194584 kb
Host smart-50c69a04-8b79-4c77-af65-4370ae37215e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164419132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.164419132
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.648034346
Short name T1303
Test name
Test status
Simulation time 24610596 ps
CPU time 0.54 seconds
Started Aug 14 04:38:39 PM PDT 24
Finished Aug 14 04:38:40 PM PDT 24
Peak memory 194580 kb
Host smart-672123c8-6b78-40d4-a4b9-c227700d66e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648034346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.648034346
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.51612588
Short name T1200
Test name
Test status
Simulation time 29562278 ps
CPU time 0.55 seconds
Started Aug 14 04:38:22 PM PDT 24
Finished Aug 14 04:38:23 PM PDT 24
Peak memory 194576 kb
Host smart-80443e48-31e8-4bc4-b850-b0a41e49e50c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51612588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.51612588
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.2387341489
Short name T1278
Test name
Test status
Simulation time 12019807 ps
CPU time 0.59 seconds
Started Aug 14 04:38:34 PM PDT 24
Finished Aug 14 04:38:35 PM PDT 24
Peak memory 194548 kb
Host smart-8f24aeff-a190-4162-8f6b-a6f9f9c8f15c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387341489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2387341489
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1677321444
Short name T1190
Test name
Test status
Simulation time 26795371 ps
CPU time 0.57 seconds
Started Aug 14 04:38:33 PM PDT 24
Finished Aug 14 04:38:33 PM PDT 24
Peak memory 194552 kb
Host smart-b346a367-caf3-496e-a4e4-694453a566e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677321444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1677321444
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.732587489
Short name T1291
Test name
Test status
Simulation time 36094022 ps
CPU time 0.58 seconds
Started Aug 14 04:38:24 PM PDT 24
Finished Aug 14 04:38:24 PM PDT 24
Peak memory 194568 kb
Host smart-147a0812-b7d8-4806-af50-aa5fe42414f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732587489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.732587489
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3889542360
Short name T1245
Test name
Test status
Simulation time 14747687 ps
CPU time 0.66 seconds
Started Aug 14 04:38:27 PM PDT 24
Finished Aug 14 04:38:28 PM PDT 24
Peak memory 194460 kb
Host smart-92ec0c01-70af-4c35-ba6f-216d1f108bf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889542360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3889542360
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.2345502932
Short name T1306
Test name
Test status
Simulation time 38741743 ps
CPU time 0.57 seconds
Started Aug 14 04:38:36 PM PDT 24
Finished Aug 14 04:38:37 PM PDT 24
Peak memory 194428 kb
Host smart-f8336b31-9b43-4528-b333-5ab9796acb8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345502932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2345502932
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.113841731
Short name T52
Test name
Test status
Simulation time 60694903 ps
CPU time 0.76 seconds
Started Aug 14 04:37:59 PM PDT 24
Finished Aug 14 04:37:59 PM PDT 24
Peak memory 196492 kb
Host smart-0809f055-07c4-4cc1-a0de-28a89615d143
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113841731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.113841731
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3833620950
Short name T54
Test name
Test status
Simulation time 34716668 ps
CPU time 1.42 seconds
Started Aug 14 04:38:18 PM PDT 24
Finished Aug 14 04:38:19 PM PDT 24
Peak memory 197700 kb
Host smart-fbb62bed-c2c7-4d14-8960-d7e3d7583ec7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833620950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3833620950
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3759099304
Short name T1233
Test name
Test status
Simulation time 45243097 ps
CPU time 0.57 seconds
Started Aug 14 04:38:12 PM PDT 24
Finished Aug 14 04:38:13 PM PDT 24
Peak memory 195428 kb
Host smart-3d5bed71-b25b-4a60-870a-14db57bc77bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759099304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3759099304
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2454229287
Short name T1300
Test name
Test status
Simulation time 23021137 ps
CPU time 0.7 seconds
Started Aug 14 04:38:30 PM PDT 24
Finished Aug 14 04:38:30 PM PDT 24
Peak memory 197648 kb
Host smart-0b1dd5fb-c4dc-45d3-a63b-86ec0d524e44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454229287 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2454229287
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3422056904
Short name T1289
Test name
Test status
Simulation time 13125804 ps
CPU time 0.58 seconds
Started Aug 14 04:38:20 PM PDT 24
Finished Aug 14 04:38:21 PM PDT 24
Peak memory 195452 kb
Host smart-93980904-4a2b-45ce-bc36-966af1a232e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422056904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3422056904
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.3530337605
Short name T1313
Test name
Test status
Simulation time 48153868 ps
CPU time 0.58 seconds
Started Aug 14 04:38:20 PM PDT 24
Finished Aug 14 04:38:20 PM PDT 24
Peak memory 194460 kb
Host smart-62f4a1a8-0e76-4e54-979a-2067d0d6a202
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530337605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3530337605
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.774482241
Short name T60
Test name
Test status
Simulation time 23170514 ps
CPU time 0.65 seconds
Started Aug 14 04:38:03 PM PDT 24
Finished Aug 14 04:38:04 PM PDT 24
Peak memory 195652 kb
Host smart-4ec589f3-6e08-4dcf-b48f-0756af277b3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774482241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_
outstanding.774482241
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.2463569611
Short name T1261
Test name
Test status
Simulation time 98240415 ps
CPU time 1.2 seconds
Started Aug 14 04:38:17 PM PDT 24
Finished Aug 14 04:38:19 PM PDT 24
Peak memory 200096 kb
Host smart-cd57481a-cef9-4a7b-97ae-316d34cca48f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463569611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2463569611
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.124268686
Short name T102
Test name
Test status
Simulation time 73212285 ps
CPU time 1.27 seconds
Started Aug 14 04:38:23 PM PDT 24
Finished Aug 14 04:38:25 PM PDT 24
Peak memory 199472 kb
Host smart-2295d00f-1144-482e-bc1c-b6e0358d10ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124268686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.124268686
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.1298311202
Short name T1199
Test name
Test status
Simulation time 41375363 ps
CPU time 0.62 seconds
Started Aug 14 04:38:27 PM PDT 24
Finished Aug 14 04:38:28 PM PDT 24
Peak memory 194476 kb
Host smart-a807b60c-c0af-4d47-9939-9a1b73687be0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298311202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1298311202
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.4248328110
Short name T1244
Test name
Test status
Simulation time 26318820 ps
CPU time 0.54 seconds
Started Aug 14 04:38:33 PM PDT 24
Finished Aug 14 04:38:33 PM PDT 24
Peak memory 194480 kb
Host smart-3edfdccd-e603-4565-9410-3583ebb50d09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248328110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.4248328110
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1783411716
Short name T1198
Test name
Test status
Simulation time 50978936 ps
CPU time 0.56 seconds
Started Aug 14 04:38:41 PM PDT 24
Finished Aug 14 04:38:46 PM PDT 24
Peak memory 194440 kb
Host smart-4913f99d-5180-4f38-ab3d-bb35871577a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783411716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1783411716
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.753164051
Short name T1239
Test name
Test status
Simulation time 13427201 ps
CPU time 0.57 seconds
Started Aug 14 04:38:42 PM PDT 24
Finished Aug 14 04:38:43 PM PDT 24
Peak memory 194584 kb
Host smart-ac5e61f5-1b84-4f88-b51d-425d2e86d864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753164051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.753164051
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2821346031
Short name T1252
Test name
Test status
Simulation time 38878942 ps
CPU time 0.62 seconds
Started Aug 14 04:38:39 PM PDT 24
Finished Aug 14 04:38:40 PM PDT 24
Peak memory 194616 kb
Host smart-b644140b-9b30-4b0e-abe3-9e1c0aa453f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821346031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2821346031
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2885874499
Short name T1305
Test name
Test status
Simulation time 28834276 ps
CPU time 0.58 seconds
Started Aug 14 04:38:41 PM PDT 24
Finished Aug 14 04:38:42 PM PDT 24
Peak memory 194588 kb
Host smart-a792fafa-dea0-4491-a381-4f116644f322
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885874499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2885874499
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.505294447
Short name T1274
Test name
Test status
Simulation time 45890575 ps
CPU time 0.58 seconds
Started Aug 14 04:38:41 PM PDT 24
Finished Aug 14 04:38:41 PM PDT 24
Peak memory 194572 kb
Host smart-6312eefa-532c-4402-af55-de417360ff09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505294447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.505294447
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3975321079
Short name T1206
Test name
Test status
Simulation time 37292852 ps
CPU time 0.56 seconds
Started Aug 14 04:38:40 PM PDT 24
Finished Aug 14 04:38:41 PM PDT 24
Peak memory 194440 kb
Host smart-f78e2cc5-5dba-4bbe-94ae-160af18b1826
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975321079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3975321079
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2856522671
Short name T1280
Test name
Test status
Simulation time 14282547 ps
CPU time 0.58 seconds
Started Aug 14 04:38:38 PM PDT 24
Finished Aug 14 04:38:39 PM PDT 24
Peak memory 194476 kb
Host smart-846df10a-eb5f-4298-9d5b-825731ec46da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856522671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2856522671
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3944562883
Short name T1283
Test name
Test status
Simulation time 15075477 ps
CPU time 0.56 seconds
Started Aug 14 04:38:38 PM PDT 24
Finished Aug 14 04:38:39 PM PDT 24
Peak memory 194552 kb
Host smart-43dc4830-8632-4024-a766-fcbf557ad000
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944562883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3944562883
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1936762447
Short name T1212
Test name
Test status
Simulation time 73882806 ps
CPU time 1.04 seconds
Started Aug 14 04:38:38 PM PDT 24
Finished Aug 14 04:38:40 PM PDT 24
Peak memory 200192 kb
Host smart-e2710476-fe77-4320-93f1-e70254b791fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936762447 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1936762447
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3832452073
Short name T1286
Test name
Test status
Simulation time 15580667 ps
CPU time 0.59 seconds
Started Aug 14 04:38:18 PM PDT 24
Finished Aug 14 04:38:19 PM PDT 24
Peak memory 195456 kb
Host smart-b5e806be-a7c2-42d6-96b2-b8dd2eb6b241
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832452073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3832452073
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.974153545
Short name T1319
Test name
Test status
Simulation time 14733277 ps
CPU time 0.56 seconds
Started Aug 14 04:38:26 PM PDT 24
Finished Aug 14 04:38:27 PM PDT 24
Peak memory 194496 kb
Host smart-95ad7c6e-e4ad-4424-9d09-9bdbe1da6c87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974153545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.974153545
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.306833281
Short name T58
Test name
Test status
Simulation time 56813428 ps
CPU time 0.63 seconds
Started Aug 14 04:38:10 PM PDT 24
Finished Aug 14 04:38:11 PM PDT 24
Peak memory 195868 kb
Host smart-1d870f73-3936-4a9b-88b3-01a40ca961f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306833281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_
outstanding.306833281
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.4013331425
Short name T1209
Test name
Test status
Simulation time 857981029 ps
CPU time 1.3 seconds
Started Aug 14 04:38:33 PM PDT 24
Finished Aug 14 04:38:35 PM PDT 24
Peak memory 200156 kb
Host smart-8bfc3875-0284-4b72-b2ae-3d1c9f459306
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013331425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.4013331425
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3089267253
Short name T63
Test name
Test status
Simulation time 85496241 ps
CPU time 0.97 seconds
Started Aug 14 04:38:26 PM PDT 24
Finished Aug 14 04:38:27 PM PDT 24
Peak memory 199248 kb
Host smart-ed838eab-4dc6-41ea-8078-1c95e535f39a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089267253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3089267253
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3238322895
Short name T1318
Test name
Test status
Simulation time 23626623 ps
CPU time 0.76 seconds
Started Aug 14 04:38:31 PM PDT 24
Finished Aug 14 04:38:32 PM PDT 24
Peak memory 199372 kb
Host smart-0ca7d7a9-49c6-4b46-a214-f7e2c3075d11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238322895 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.3238322895
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3803237164
Short name T1220
Test name
Test status
Simulation time 40553705 ps
CPU time 0.59 seconds
Started Aug 14 04:38:16 PM PDT 24
Finished Aug 14 04:38:17 PM PDT 24
Peak memory 195508 kb
Host smart-d05cca08-0994-4854-9eb3-17223451f4cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803237164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3803237164
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1605869473
Short name T1211
Test name
Test status
Simulation time 41450343 ps
CPU time 0.55 seconds
Started Aug 14 04:38:35 PM PDT 24
Finished Aug 14 04:38:36 PM PDT 24
Peak memory 194484 kb
Host smart-2ff58e44-9bf8-4c07-b97f-a7b4f4ac2dee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605869473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1605869473
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.927503813
Short name T1260
Test name
Test status
Simulation time 126802942 ps
CPU time 0.76 seconds
Started Aug 14 04:38:38 PM PDT 24
Finished Aug 14 04:38:39 PM PDT 24
Peak memory 197588 kb
Host smart-9b52df78-7018-4a5f-8dbe-15a6f8b38425
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927503813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.927503813
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.307946447
Short name T1219
Test name
Test status
Simulation time 128479518 ps
CPU time 1.81 seconds
Started Aug 14 04:38:06 PM PDT 24
Finished Aug 14 04:38:08 PM PDT 24
Peak memory 200180 kb
Host smart-ab2917c5-784a-453b-b43e-e4ee1fefa8c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307946447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.307946447
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.9082956
Short name T1242
Test name
Test status
Simulation time 187884089 ps
CPU time 0.98 seconds
Started Aug 14 04:38:12 PM PDT 24
Finished Aug 14 04:38:13 PM PDT 24
Peak memory 199364 kb
Host smart-85fe1c7b-5df2-4961-b6af-d782553e8ff7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9082956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.9082956
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2136874425
Short name T1207
Test name
Test status
Simulation time 39196349 ps
CPU time 0.78 seconds
Started Aug 14 04:38:18 PM PDT 24
Finished Aug 14 04:38:19 PM PDT 24
Peak memory 198952 kb
Host smart-b1f3cd41-82fc-417b-83e8-fd397b2b66c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136874425 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2136874425
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.744316359
Short name T1267
Test name
Test status
Simulation time 199906329 ps
CPU time 0.65 seconds
Started Aug 14 04:38:39 PM PDT 24
Finished Aug 14 04:38:40 PM PDT 24
Peak memory 195996 kb
Host smart-a75a8df7-5881-4cf1-a380-ca062bf43372
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744316359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.744316359
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1344253039
Short name T1249
Test name
Test status
Simulation time 26516614 ps
CPU time 0.54 seconds
Started Aug 14 04:38:19 PM PDT 24
Finished Aug 14 04:38:20 PM PDT 24
Peak memory 194560 kb
Host smart-474b593a-da9f-450c-82fc-cff3824de34f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344253039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1344253039
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.785065242
Short name T62
Test name
Test status
Simulation time 94222878 ps
CPU time 0.75 seconds
Started Aug 14 04:38:22 PM PDT 24
Finished Aug 14 04:38:23 PM PDT 24
Peak memory 197644 kb
Host smart-b2c3301f-dc61-4c48-9557-74d6ca811078
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785065242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_
outstanding.785065242
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2236346974
Short name T1197
Test name
Test status
Simulation time 22229967 ps
CPU time 1.04 seconds
Started Aug 14 04:38:12 PM PDT 24
Finished Aug 14 04:38:13 PM PDT 24
Peak memory 199908 kb
Host smart-f4bda933-76fb-46b3-92b2-4ecb8d2393b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236346974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2236346974
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3341237844
Short name T69
Test name
Test status
Simulation time 750040135 ps
CPU time 0.93 seconds
Started Aug 14 04:38:22 PM PDT 24
Finished Aug 14 04:38:23 PM PDT 24
Peak memory 198980 kb
Host smart-52ae8746-8a84-4d62-b075-60ede3792b0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341237844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3341237844
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.4196738315
Short name T1279
Test name
Test status
Simulation time 46728811 ps
CPU time 0.99 seconds
Started Aug 14 04:38:31 PM PDT 24
Finished Aug 14 04:38:32 PM PDT 24
Peak memory 199888 kb
Host smart-1656607f-4358-41c2-9fe0-a72fec4dbe7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196738315 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.4196738315
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1872775232
Short name T1196
Test name
Test status
Simulation time 39745420 ps
CPU time 0.63 seconds
Started Aug 14 04:38:32 PM PDT 24
Finished Aug 14 04:38:32 PM PDT 24
Peak memory 195460 kb
Host smart-886af57b-7ece-4872-af78-b63c36cefdd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872775232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1872775232
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.210273962
Short name T1229
Test name
Test status
Simulation time 41235383 ps
CPU time 0.59 seconds
Started Aug 14 04:38:29 PM PDT 24
Finished Aug 14 04:38:30 PM PDT 24
Peak memory 194552 kb
Host smart-98a85cd4-29a9-4585-8a55-0e89997c1b05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210273962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.210273962
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2598466434
Short name T1218
Test name
Test status
Simulation time 18651165 ps
CPU time 0.71 seconds
Started Aug 14 04:38:14 PM PDT 24
Finished Aug 14 04:38:14 PM PDT 24
Peak memory 197908 kb
Host smart-511da74b-fd99-4506-b9c0-ffc4e33bbe25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598466434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.2598466434
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2264431967
Short name T1194
Test name
Test status
Simulation time 138390976 ps
CPU time 1.29 seconds
Started Aug 14 04:38:21 PM PDT 24
Finished Aug 14 04:38:22 PM PDT 24
Peak memory 200152 kb
Host smart-7567abe3-d60a-41e5-ae81-8d3e8c3c0047
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264431967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2264431967
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2407764973
Short name T1258
Test name
Test status
Simulation time 273973560 ps
CPU time 1.24 seconds
Started Aug 14 04:38:16 PM PDT 24
Finished Aug 14 04:38:17 PM PDT 24
Peak memory 199348 kb
Host smart-e8c74e00-a1f4-4004-9743-f567e5518eb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407764973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2407764973
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.453768938
Short name T1189
Test name
Test status
Simulation time 99303096 ps
CPU time 0.65 seconds
Started Aug 14 04:38:20 PM PDT 24
Finished Aug 14 04:38:21 PM PDT 24
Peak memory 197856 kb
Host smart-f3b27140-b950-48c4-94c4-f45930fe6a55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453768938 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.453768938
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3185293648
Short name T1223
Test name
Test status
Simulation time 23979832 ps
CPU time 0.63 seconds
Started Aug 14 04:38:14 PM PDT 24
Finished Aug 14 04:38:15 PM PDT 24
Peak memory 195668 kb
Host smart-8f4b27a3-1783-44bd-b14a-e38e4b097b3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185293648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3185293648
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.4023223092
Short name T1230
Test name
Test status
Simulation time 96574181 ps
CPU time 0.55 seconds
Started Aug 14 04:38:29 PM PDT 24
Finished Aug 14 04:38:29 PM PDT 24
Peak memory 194580 kb
Host smart-77aa6ea9-0e38-4f73-bd9f-9102ae0a5bd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023223092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.4023223092
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2640321859
Short name T1272
Test name
Test status
Simulation time 30280247 ps
CPU time 0.74 seconds
Started Aug 14 04:38:08 PM PDT 24
Finished Aug 14 04:38:09 PM PDT 24
Peak memory 197616 kb
Host smart-635ecefa-63e0-4b1f-8357-d0960402a688
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640321859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2640321859
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.2423894078
Short name T1282
Test name
Test status
Simulation time 203743690 ps
CPU time 1.92 seconds
Started Aug 14 04:38:25 PM PDT 24
Finished Aug 14 04:38:27 PM PDT 24
Peak memory 200144 kb
Host smart-9a3235b0-fed8-4cad-a0b6-146daeab5ddb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423894078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2423894078
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/default/0.uart_alert_test.1911484337
Short name T486
Test name
Test status
Simulation time 14965493 ps
CPU time 0.59 seconds
Started Aug 14 04:58:50 PM PDT 24
Finished Aug 14 04:58:51 PM PDT 24
Peak memory 196564 kb
Host smart-93ca6ba3-a040-4444-8e3b-ae9e50550328
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911484337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1911484337
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.548544490
Short name T554
Test name
Test status
Simulation time 87800701964 ps
CPU time 121.55 seconds
Started Aug 14 04:58:49 PM PDT 24
Finished Aug 14 05:00:51 PM PDT 24
Peak memory 200964 kb
Host smart-6235ff04-80cd-4c6c-98c5-c307d425fbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548544490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.548544490
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.891295548
Short name T687
Test name
Test status
Simulation time 104851374547 ps
CPU time 153.41 seconds
Started Aug 14 04:58:48 PM PDT 24
Finished Aug 14 05:01:22 PM PDT 24
Peak memory 200564 kb
Host smart-a1074ac9-7bfb-4edc-83f0-d0661880bc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891295548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.891295548
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.2324980165
Short name T553
Test name
Test status
Simulation time 185531505190 ps
CPU time 560.34 seconds
Started Aug 14 04:58:47 PM PDT 24
Finished Aug 14 05:08:07 PM PDT 24
Peak memory 200800 kb
Host smart-002168e6-c83f-48a7-9f21-22e9a9db44a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324980165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2324980165
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.1572559640
Short name T656
Test name
Test status
Simulation time 15918964003 ps
CPU time 26.61 seconds
Started Aug 14 04:58:49 PM PDT 24
Finished Aug 14 04:59:16 PM PDT 24
Peak memory 200744 kb
Host smart-976f838c-ab0a-4443-ad64-f5de26ea0140
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572559640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1572559640
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2441420709
Short name T415
Test name
Test status
Simulation time 116063680285 ps
CPU time 337.65 seconds
Started Aug 14 04:58:51 PM PDT 24
Finished Aug 14 05:04:29 PM PDT 24
Peak memory 200896 kb
Host smart-07d60389-02ed-43a8-8dad-0d475b4e704a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2441420709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2441420709
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.3193007757
Short name T1015
Test name
Test status
Simulation time 286603720 ps
CPU time 0.64 seconds
Started Aug 14 04:58:47 PM PDT 24
Finished Aug 14 04:58:47 PM PDT 24
Peak memory 196556 kb
Host smart-844dc18e-af67-42f9-9fd9-2b72682c733d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193007757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.3193007757
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_perf.31276470
Short name T492
Test name
Test status
Simulation time 21736625788 ps
CPU time 972.32 seconds
Started Aug 14 04:58:48 PM PDT 24
Finished Aug 14 05:15:01 PM PDT 24
Peak memory 200896 kb
Host smart-ce4df181-711a-4306-b3bd-bec3a52e0220
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=31276470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.31276470
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.4279416408
Short name T380
Test name
Test status
Simulation time 1375577496 ps
CPU time 2.68 seconds
Started Aug 14 04:58:50 PM PDT 24
Finished Aug 14 04:58:53 PM PDT 24
Peak memory 199160 kb
Host smart-c26e140a-9d86-4978-976b-9687253e548a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4279416408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.4279416408
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.691184548
Short name T1139
Test name
Test status
Simulation time 39063345032 ps
CPU time 11.65 seconds
Started Aug 14 04:58:48 PM PDT 24
Finished Aug 14 04:59:00 PM PDT 24
Peak memory 196788 kb
Host smart-5a89dddf-8379-4d45-b9b0-880b19a47971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691184548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.691184548
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.997146549
Short name T731
Test name
Test status
Simulation time 6243148388 ps
CPU time 22.59 seconds
Started Aug 14 04:58:47 PM PDT 24
Finished Aug 14 04:59:10 PM PDT 24
Peak memory 200900 kb
Host smart-0df7c0e9-eaaf-4973-9acc-ab43c7e3b28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997146549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.997146549
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.4281046561
Short name T784
Test name
Test status
Simulation time 7169056929 ps
CPU time 14.8 seconds
Started Aug 14 04:58:50 PM PDT 24
Finished Aug 14 04:59:05 PM PDT 24
Peak memory 201136 kb
Host smart-662e22f4-4825-47d7-abc9-bc691e4632c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281046561 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.4281046561
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.4004594969
Short name T879
Test name
Test status
Simulation time 1168088511 ps
CPU time 1.66 seconds
Started Aug 14 04:58:49 PM PDT 24
Finished Aug 14 04:58:51 PM PDT 24
Peak memory 199756 kb
Host smart-82b7f7b0-8d20-45ab-ba36-ad877f8fae3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004594969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.4004594969
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.540463935
Short name T315
Test name
Test status
Simulation time 103888185232 ps
CPU time 71.65 seconds
Started Aug 14 04:58:47 PM PDT 24
Finished Aug 14 04:59:59 PM PDT 24
Peak memory 200812 kb
Host smart-db5496e0-85f5-4087-82e1-6506be2b0226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540463935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.540463935
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.3461305794
Short name T1110
Test name
Test status
Simulation time 15274136 ps
CPU time 0.59 seconds
Started Aug 14 04:58:58 PM PDT 24
Finished Aug 14 04:58:59 PM PDT 24
Peak memory 196548 kb
Host smart-b4e3561d-0b81-4416-88c3-8bbcdda7c7ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461305794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3461305794
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3555054596
Short name T319
Test name
Test status
Simulation time 224585378930 ps
CPU time 147.33 seconds
Started Aug 14 04:58:49 PM PDT 24
Finished Aug 14 05:01:17 PM PDT 24
Peak memory 200988 kb
Host smart-3b8e6732-7f51-44ba-b2d3-c6c5375e3c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555054596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3555054596
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_intr.4143495675
Short name T1112
Test name
Test status
Simulation time 8360980202 ps
CPU time 24.01 seconds
Started Aug 14 04:58:47 PM PDT 24
Finished Aug 14 04:59:11 PM PDT 24
Peak memory 200496 kb
Host smart-413b5982-6eb3-4592-853f-5a9a9fb8cb8e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143495675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.4143495675
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1506963984
Short name T678
Test name
Test status
Simulation time 48415220554 ps
CPU time 141.14 seconds
Started Aug 14 04:58:56 PM PDT 24
Finished Aug 14 05:01:17 PM PDT 24
Peak memory 200960 kb
Host smart-6ab069ea-67bb-47a8-84f0-a79fd937c504
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1506963984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1506963984
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.674745179
Short name T980
Test name
Test status
Simulation time 7089307204 ps
CPU time 2.75 seconds
Started Aug 14 04:59:01 PM PDT 24
Finished Aug 14 04:59:04 PM PDT 24
Peak memory 200100 kb
Host smart-f62b8fc7-38e0-45a9-a1f8-9f455d8c9434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674745179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.674745179
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.1688424470
Short name T631
Test name
Test status
Simulation time 40576070640 ps
CPU time 114.67 seconds
Started Aug 14 04:58:50 PM PDT 24
Finished Aug 14 05:00:45 PM PDT 24
Peak memory 199084 kb
Host smart-4c77f020-cf74-4f6a-8b57-cc20a9d2bf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688424470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1688424470
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.484935125
Short name T452
Test name
Test status
Simulation time 21047349094 ps
CPU time 327.49 seconds
Started Aug 14 04:58:57 PM PDT 24
Finished Aug 14 05:04:25 PM PDT 24
Peak memory 200948 kb
Host smart-7432b826-e110-4832-9409-29f57087d2a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=484935125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.484935125
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.210447018
Short name T862
Test name
Test status
Simulation time 3938509782 ps
CPU time 4.52 seconds
Started Aug 14 04:58:48 PM PDT 24
Finished Aug 14 04:58:52 PM PDT 24
Peak memory 199408 kb
Host smart-75566bbe-5a62-4a6e-9524-6ef83a3dd5ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=210447018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.210447018
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.3647228002
Short name T716
Test name
Test status
Simulation time 103443242274 ps
CPU time 35.82 seconds
Started Aug 14 04:58:49 PM PDT 24
Finished Aug 14 04:59:25 PM PDT 24
Peak memory 200840 kb
Host smart-0dbe32bb-c1b8-4bf8-aef8-6be3455e7acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647228002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3647228002
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.2510710965
Short name T939
Test name
Test status
Simulation time 5388118548 ps
CPU time 9.84 seconds
Started Aug 14 04:58:47 PM PDT 24
Finished Aug 14 04:58:57 PM PDT 24
Peak memory 197072 kb
Host smart-0b8cd77e-0519-44bb-b7e2-80eaada803b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510710965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2510710965
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.2052356262
Short name T72
Test name
Test status
Simulation time 36845281 ps
CPU time 0.8 seconds
Started Aug 14 04:58:56 PM PDT 24
Finished Aug 14 04:58:57 PM PDT 24
Peak memory 219004 kb
Host smart-3bd4cc9a-49c8-40cc-bb74-22e0b0b986c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052356262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2052356262
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3641526976
Short name T297
Test name
Test status
Simulation time 5308868113 ps
CPU time 32.22 seconds
Started Aug 14 04:58:46 PM PDT 24
Finished Aug 14 04:59:19 PM PDT 24
Peak memory 200848 kb
Host smart-265792d7-aa47-43a4-9883-95083c8b9bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641526976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3641526976
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.938760874
Short name T1010
Test name
Test status
Simulation time 302134759784 ps
CPU time 716.52 seconds
Started Aug 14 04:58:56 PM PDT 24
Finished Aug 14 05:10:53 PM PDT 24
Peak memory 217184 kb
Host smart-e2dbb0c4-5161-4094-a409-a3f1cfdca8d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938760874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.938760874
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.457129294
Short name T449
Test name
Test status
Simulation time 11275849265 ps
CPU time 40.84 seconds
Started Aug 14 04:59:01 PM PDT 24
Finished Aug 14 04:59:42 PM PDT 24
Peak memory 216704 kb
Host smart-b28a5005-8f1b-47ed-be47-1116b50df67b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457129294 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.457129294
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2526944848
Short name T515
Test name
Test status
Simulation time 4508463022 ps
CPU time 2.46 seconds
Started Aug 14 04:58:59 PM PDT 24
Finished Aug 14 04:59:02 PM PDT 24
Peak memory 200240 kb
Host smart-62b0ea50-3c38-45dc-b3ae-671cbdae0786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526944848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2526944848
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1229490417
Short name T582
Test name
Test status
Simulation time 130915984061 ps
CPU time 34.17 seconds
Started Aug 14 04:58:47 PM PDT 24
Finished Aug 14 04:59:22 PM PDT 24
Peak memory 200956 kb
Host smart-05800cb4-711f-4d3a-b0fa-46b7fd3467df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229490417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1229490417
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.810788701
Short name T693
Test name
Test status
Simulation time 10304239 ps
CPU time 0.56 seconds
Started Aug 14 04:59:37 PM PDT 24
Finished Aug 14 04:59:37 PM PDT 24
Peak memory 195248 kb
Host smart-ca052113-4f85-4ae0-9891-2d90e18652ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810788701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.810788701
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.420532263
Short name T960
Test name
Test status
Simulation time 40424965393 ps
CPU time 70.68 seconds
Started Aug 14 04:59:25 PM PDT 24
Finished Aug 14 05:00:36 PM PDT 24
Peak memory 200952 kb
Host smart-d210a598-aa8c-4a26-9cf8-7d276cad2d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420532263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.420532263
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.840761352
Short name T1175
Test name
Test status
Simulation time 29136124189 ps
CPU time 36.76 seconds
Started Aug 14 04:59:26 PM PDT 24
Finished Aug 14 05:00:03 PM PDT 24
Peak memory 200992 kb
Host smart-5de57b41-3cc6-45d1-ac82-b148b98dad04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840761352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.840761352
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_intr.2413914457
Short name T345
Test name
Test status
Simulation time 165693532047 ps
CPU time 254.45 seconds
Started Aug 14 04:59:26 PM PDT 24
Finished Aug 14 05:03:41 PM PDT 24
Peak memory 200632 kb
Host smart-16781ff5-e7a2-4e58-923e-3fb054433deb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413914457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2413914457
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3381396538
Short name T1094
Test name
Test status
Simulation time 58417779359 ps
CPU time 404.4 seconds
Started Aug 14 04:59:41 PM PDT 24
Finished Aug 14 05:06:25 PM PDT 24
Peak memory 200792 kb
Host smart-0d834ceb-2792-44c0-9136-49c29cc543bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3381396538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3381396538
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.4226955787
Short name T838
Test name
Test status
Simulation time 8075531574 ps
CPU time 11.28 seconds
Started Aug 14 04:59:35 PM PDT 24
Finished Aug 14 04:59:46 PM PDT 24
Peak memory 200656 kb
Host smart-7751da1c-7f86-4988-a4ae-d9834b0c5c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226955787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.4226955787
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.3203337611
Short name T616
Test name
Test status
Simulation time 50484456659 ps
CPU time 58.11 seconds
Started Aug 14 04:59:25 PM PDT 24
Finished Aug 14 05:00:23 PM PDT 24
Peak memory 201092 kb
Host smart-6773fa06-4480-428f-be47-3aef05dd55bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203337611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3203337611
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.279928945
Short name T1071
Test name
Test status
Simulation time 18526790889 ps
CPU time 488.05 seconds
Started Aug 14 04:59:35 PM PDT 24
Finished Aug 14 05:07:43 PM PDT 24
Peak memory 200956 kb
Host smart-2581c950-3adf-430d-8956-234aafe2eeb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=279928945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.279928945
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2754855876
Short name T962
Test name
Test status
Simulation time 5779120860 ps
CPU time 53.74 seconds
Started Aug 14 04:59:28 PM PDT 24
Finished Aug 14 05:00:22 PM PDT 24
Peak memory 199216 kb
Host smart-09c935ef-0e2c-4ae2-aba3-16fb3dc5d346
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2754855876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2754855876
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2906004690
Short name T414
Test name
Test status
Simulation time 7617628020 ps
CPU time 11.5 seconds
Started Aug 14 04:59:26 PM PDT 24
Finished Aug 14 04:59:38 PM PDT 24
Peak memory 199568 kb
Host smart-8fe3b8d4-fafd-418a-b796-c832784dc063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906004690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2906004690
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1889692089
Short name T983
Test name
Test status
Simulation time 37457193373 ps
CPU time 56.67 seconds
Started Aug 14 04:59:26 PM PDT 24
Finished Aug 14 05:00:23 PM PDT 24
Peak memory 197632 kb
Host smart-f1e97916-c5c4-4220-98ce-a5f9089ec878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889692089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1889692089
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.1271113452
Short name T950
Test name
Test status
Simulation time 295445683 ps
CPU time 1.46 seconds
Started Aug 14 04:59:25 PM PDT 24
Finished Aug 14 04:59:26 PM PDT 24
Peak memory 200516 kb
Host smart-0754bab9-16d1-4fc6-83d1-d73b92ad503c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271113452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1271113452
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.1012476676
Short name T869
Test name
Test status
Simulation time 201629774515 ps
CPU time 612.54 seconds
Started Aug 14 04:59:36 PM PDT 24
Finished Aug 14 05:09:49 PM PDT 24
Peak memory 200960 kb
Host smart-e56e7e6a-80c6-419b-9803-0c56ef7252ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012476676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.1012476676
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.122168271
Short name T825
Test name
Test status
Simulation time 13866586222 ps
CPU time 44.84 seconds
Started Aug 14 04:59:39 PM PDT 24
Finished Aug 14 05:00:24 PM PDT 24
Peak memory 209116 kb
Host smart-6900c1fa-923b-4920-9f92-4d12c89ee510
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122168271 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.122168271
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3832222750
Short name T243
Test name
Test status
Simulation time 1692365527 ps
CPU time 2.31 seconds
Started Aug 14 04:59:35 PM PDT 24
Finished Aug 14 04:59:38 PM PDT 24
Peak memory 200744 kb
Host smart-5f0f8b82-1b7d-4106-b018-0c3870217090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832222750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3832222750
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2041150575
Short name T1179
Test name
Test status
Simulation time 1340712674 ps
CPU time 1.29 seconds
Started Aug 14 04:59:26 PM PDT 24
Finished Aug 14 04:59:27 PM PDT 24
Peak memory 199992 kb
Host smart-065c3a21-2d68-4f2a-8884-3e57dd44830c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041150575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2041150575
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3353124153
Short name T94
Test name
Test status
Simulation time 19059991593 ps
CPU time 31.95 seconds
Started Aug 14 05:03:17 PM PDT 24
Finished Aug 14 05:03:49 PM PDT 24
Peak memory 200932 kb
Host smart-ddcbfa82-7fda-4cda-9584-f6dbfc882394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353124153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3353124153
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.3844620360
Short name T667
Test name
Test status
Simulation time 44196939511 ps
CPU time 32.9 seconds
Started Aug 14 05:03:16 PM PDT 24
Finished Aug 14 05:03:49 PM PDT 24
Peak memory 200880 kb
Host smart-2305a418-0843-424c-80b8-accdf7541e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844620360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3844620360
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.2269259902
Short name T545
Test name
Test status
Simulation time 71071331557 ps
CPU time 150.99 seconds
Started Aug 14 05:03:20 PM PDT 24
Finished Aug 14 05:05:51 PM PDT 24
Peak memory 200964 kb
Host smart-95e1afce-b05e-49ec-ace4-eb6a849a21cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269259902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2269259902
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.401589294
Short name T1035
Test name
Test status
Simulation time 93495182131 ps
CPU time 67.04 seconds
Started Aug 14 05:03:17 PM PDT 24
Finished Aug 14 05:04:24 PM PDT 24
Peak memory 200912 kb
Host smart-ecc9b399-0c30-432f-a98f-fc5d4c977066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401589294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.401589294
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.2994377045
Short name T919
Test name
Test status
Simulation time 16185441215 ps
CPU time 7.94 seconds
Started Aug 14 05:03:14 PM PDT 24
Finished Aug 14 05:03:22 PM PDT 24
Peak memory 200832 kb
Host smart-05ebdea2-58cf-480b-9da4-df3087d49fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994377045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2994377045
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2940439328
Short name T262
Test name
Test status
Simulation time 4428230042 ps
CPU time 8.56 seconds
Started Aug 14 05:03:15 PM PDT 24
Finished Aug 14 05:03:23 PM PDT 24
Peak memory 200964 kb
Host smart-7d2b5c07-36e7-44c9-b704-648735aee906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940439328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2940439328
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.3086623631
Short name T1049
Test name
Test status
Simulation time 17437515684 ps
CPU time 26.51 seconds
Started Aug 14 05:03:15 PM PDT 24
Finished Aug 14 05:03:42 PM PDT 24
Peak memory 200876 kb
Host smart-0ab34d25-9dbc-4d00-a2d9-9862fabb58fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086623631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3086623631
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.171399149
Short name T856
Test name
Test status
Simulation time 263456125211 ps
CPU time 84.41 seconds
Started Aug 14 05:03:17 PM PDT 24
Finished Aug 14 05:04:41 PM PDT 24
Peak memory 200984 kb
Host smart-06966569-0ba3-4aab-a461-91585d089c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171399149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.171399149
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_full.1357027126
Short name T517
Test name
Test status
Simulation time 48399545477 ps
CPU time 13.65 seconds
Started Aug 14 04:59:39 PM PDT 24
Finished Aug 14 04:59:52 PM PDT 24
Peak memory 201012 kb
Host smart-85f5ec69-7f3d-40f7-8f33-d3a5f9688f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357027126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.1357027126
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3529471543
Short name T864
Test name
Test status
Simulation time 126534507539 ps
CPU time 131.6 seconds
Started Aug 14 04:59:35 PM PDT 24
Finished Aug 14 05:01:47 PM PDT 24
Peak memory 200972 kb
Host smart-075e9cd5-c27b-4fc8-858b-2e236e5d6027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529471543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3529471543
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1693679663
Short name T839
Test name
Test status
Simulation time 72833471073 ps
CPU time 136.22 seconds
Started Aug 14 04:59:35 PM PDT 24
Finished Aug 14 05:01:51 PM PDT 24
Peak memory 200816 kb
Host smart-fe1a8f50-736c-45c4-8d80-54494f8dac00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693679663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1693679663
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.3368319019
Short name T818
Test name
Test status
Simulation time 56788298587 ps
CPU time 19.31 seconds
Started Aug 14 04:59:36 PM PDT 24
Finished Aug 14 04:59:56 PM PDT 24
Peak memory 200176 kb
Host smart-897e63a6-3cd1-46eb-864f-fa7fe418ffcb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368319019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.3368319019
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3192374060
Short name T1056
Test name
Test status
Simulation time 163830249000 ps
CPU time 752.12 seconds
Started Aug 14 04:59:40 PM PDT 24
Finished Aug 14 05:12:13 PM PDT 24
Peak memory 200792 kb
Host smart-a71de354-08cb-4e17-982b-c2935d2e054a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3192374060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3192374060
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2222004213
Short name T342
Test name
Test status
Simulation time 3577726555 ps
CPU time 2.32 seconds
Started Aug 14 04:59:35 PM PDT 24
Finished Aug 14 04:59:38 PM PDT 24
Peak memory 199500 kb
Host smart-97850747-5228-4286-b894-e8dc211b2c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222004213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2222004213
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1019971197
Short name T249
Test name
Test status
Simulation time 72828140334 ps
CPU time 114.78 seconds
Started Aug 14 04:59:38 PM PDT 24
Finished Aug 14 05:01:33 PM PDT 24
Peak memory 208880 kb
Host smart-d2c6db71-95b7-4e68-9cb5-982f647ed0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019971197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1019971197
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.2747290382
Short name T642
Test name
Test status
Simulation time 22260632520 ps
CPU time 204.97 seconds
Started Aug 14 04:59:36 PM PDT 24
Finished Aug 14 05:03:01 PM PDT 24
Peak memory 200956 kb
Host smart-13c2dd66-24a8-418d-95fa-498c85bf3b90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2747290382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2747290382
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3607894647
Short name T494
Test name
Test status
Simulation time 3476379285 ps
CPU time 7.5 seconds
Started Aug 14 04:59:34 PM PDT 24
Finished Aug 14 04:59:42 PM PDT 24
Peak memory 200036 kb
Host smart-8f24ad0f-55fd-4f78-9a51-5a988931fc52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3607894647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3607894647
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3470168342
Short name T606
Test name
Test status
Simulation time 29859436019 ps
CPU time 20.7 seconds
Started Aug 14 04:59:38 PM PDT 24
Finished Aug 14 04:59:58 PM PDT 24
Peak memory 200820 kb
Host smart-5c82b78b-8f4f-4e3d-95c5-a3ed2fc67323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470168342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3470168342
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.4176630151
Short name T505
Test name
Test status
Simulation time 44497281195 ps
CPU time 10.35 seconds
Started Aug 14 04:59:36 PM PDT 24
Finished Aug 14 04:59:47 PM PDT 24
Peak memory 197244 kb
Host smart-f1f00af4-7b3b-4fc4-ab8d-db8b394c3d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176630151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.4176630151
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2585938405
Short name T496
Test name
Test status
Simulation time 5995757821 ps
CPU time 17.2 seconds
Started Aug 14 04:59:36 PM PDT 24
Finished Aug 14 04:59:53 PM PDT 24
Peak memory 200784 kb
Host smart-943b1239-6af9-4f90-936a-082eee2afb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585938405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2585938405
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.2390423766
Short name T160
Test name
Test status
Simulation time 97785848067 ps
CPU time 180.19 seconds
Started Aug 14 04:59:39 PM PDT 24
Finished Aug 14 05:02:39 PM PDT 24
Peak memory 200856 kb
Host smart-ab3235e8-4207-4d75-9d4a-04d6fafc369b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390423766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2390423766
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.1965576230
Short name T984
Test name
Test status
Simulation time 748607329 ps
CPU time 2.61 seconds
Started Aug 14 04:59:36 PM PDT 24
Finished Aug 14 04:59:39 PM PDT 24
Peak memory 200552 kb
Host smart-d2d8ba6f-b296-4430-9ebf-936e9f127e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965576230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.1965576230
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.604067876
Short name T1052
Test name
Test status
Simulation time 58277507489 ps
CPU time 53.6 seconds
Started Aug 14 04:59:35 PM PDT 24
Finished Aug 14 05:00:29 PM PDT 24
Peak memory 200960 kb
Host smart-bdb03e50-e659-4475-8d61-46a33c8ec022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604067876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.604067876
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.2473821775
Short name T861
Test name
Test status
Simulation time 103470620604 ps
CPU time 236.38 seconds
Started Aug 14 05:03:26 PM PDT 24
Finished Aug 14 05:07:22 PM PDT 24
Peak memory 200968 kb
Host smart-5fdd53c7-345b-40a6-89e1-a4ca596701b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473821775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2473821775
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1636092294
Short name T963
Test name
Test status
Simulation time 193839833966 ps
CPU time 55.44 seconds
Started Aug 14 05:03:23 PM PDT 24
Finished Aug 14 05:04:19 PM PDT 24
Peak memory 200864 kb
Host smart-76f69446-1b26-47c9-832a-b8e8de5b4411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636092294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1636092294
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.1164756765
Short name T349
Test name
Test status
Simulation time 184723401617 ps
CPU time 80.24 seconds
Started Aug 14 05:03:24 PM PDT 24
Finished Aug 14 05:04:45 PM PDT 24
Peak memory 200908 kb
Host smart-c060b8ce-d977-4b81-b7dc-4f828a17a2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164756765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1164756765
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.818091314
Short name T742
Test name
Test status
Simulation time 19511883540 ps
CPU time 27.66 seconds
Started Aug 14 05:03:24 PM PDT 24
Finished Aug 14 05:03:51 PM PDT 24
Peak memory 200956 kb
Host smart-7c9802f9-8230-45c5-962d-17ea4e67a297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818091314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.818091314
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.302315157
Short name T525
Test name
Test status
Simulation time 133516324140 ps
CPU time 102.49 seconds
Started Aug 14 05:03:24 PM PDT 24
Finished Aug 14 05:05:07 PM PDT 24
Peak memory 200876 kb
Host smart-4f529b41-5215-46e1-80ed-37729e35841a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302315157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.302315157
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2456844566
Short name T893
Test name
Test status
Simulation time 48139209292 ps
CPU time 88.79 seconds
Started Aug 14 05:03:25 PM PDT 24
Finished Aug 14 05:04:54 PM PDT 24
Peak memory 200960 kb
Host smart-49f39341-5477-4407-8bea-28d8fd57c47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456844566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2456844566
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.1814110530
Short name T1055
Test name
Test status
Simulation time 120072053411 ps
CPU time 88.67 seconds
Started Aug 14 05:03:25 PM PDT 24
Finished Aug 14 05:04:54 PM PDT 24
Peak memory 200924 kb
Host smart-72a7bb36-ed77-4f87-b065-001f4bb51ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814110530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1814110530
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2832247289
Short name T586
Test name
Test status
Simulation time 19048404735 ps
CPU time 30.93 seconds
Started Aug 14 05:03:24 PM PDT 24
Finished Aug 14 05:03:55 PM PDT 24
Peak memory 199948 kb
Host smart-b243f2e0-caae-435b-abc8-4d8dd90572b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832247289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2832247289
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.509595524
Short name T799
Test name
Test status
Simulation time 13145758 ps
CPU time 0.56 seconds
Started Aug 14 04:59:45 PM PDT 24
Finished Aug 14 04:59:46 PM PDT 24
Peak memory 195728 kb
Host smart-75c48443-d499-4fd8-a084-96f6a3f425a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509595524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.509595524
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.1718803992
Short name T603
Test name
Test status
Simulation time 38039623201 ps
CPU time 63.79 seconds
Started Aug 14 04:59:37 PM PDT 24
Finished Aug 14 05:00:41 PM PDT 24
Peak memory 200888 kb
Host smart-b7029302-37dc-4dcd-8e4a-3020c1390559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718803992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1718803992
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.1179511894
Short name T644
Test name
Test status
Simulation time 44672184793 ps
CPU time 60.95 seconds
Started Aug 14 04:59:36 PM PDT 24
Finished Aug 14 05:00:37 PM PDT 24
Peak memory 200876 kb
Host smart-171dd27c-f96c-4874-bf6d-1b332ed62524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179511894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1179511894
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.3009419850
Short name T805
Test name
Test status
Simulation time 81239177706 ps
CPU time 30.35 seconds
Started Aug 14 04:59:39 PM PDT 24
Finished Aug 14 05:00:10 PM PDT 24
Peak memory 200864 kb
Host smart-c32e1c95-cd38-4203-853f-2b8383933d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009419850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.3009419850
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.2358103262
Short name T724
Test name
Test status
Simulation time 13170121037 ps
CPU time 22.75 seconds
Started Aug 14 04:59:36 PM PDT 24
Finished Aug 14 04:59:59 PM PDT 24
Peak memory 200908 kb
Host smart-12243f01-a219-4a42-b039-1c5cdd97bac5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358103262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2358103262
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2960634269
Short name T851
Test name
Test status
Simulation time 43223182518 ps
CPU time 321.05 seconds
Started Aug 14 04:59:44 PM PDT 24
Finished Aug 14 05:05:05 PM PDT 24
Peak memory 200792 kb
Host smart-ce9fb6f6-fd91-492c-bc69-c4a80bc3a0b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2960634269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2960634269
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.2457953624
Short name T722
Test name
Test status
Simulation time 8032457283 ps
CPU time 5.72 seconds
Started Aug 14 04:59:38 PM PDT 24
Finished Aug 14 04:59:44 PM PDT 24
Peak memory 199652 kb
Host smart-485c67fd-0f78-4682-9a2f-b113cad5d561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457953624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2457953624
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.125189644
Short name T548
Test name
Test status
Simulation time 106682569480 ps
CPU time 92.14 seconds
Started Aug 14 04:59:34 PM PDT 24
Finished Aug 14 05:01:06 PM PDT 24
Peak memory 201116 kb
Host smart-1377fbe9-0b16-4d81-9edf-6cff9603d8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125189644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.125189644
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.957872852
Short name T570
Test name
Test status
Simulation time 29496555367 ps
CPU time 1388.38 seconds
Started Aug 14 04:59:33 PM PDT 24
Finished Aug 14 05:22:42 PM PDT 24
Peak memory 200976 kb
Host smart-30f094fe-4f22-4feb-90f4-564b465c254a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=957872852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.957872852
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.876535922
Short name T765
Test name
Test status
Simulation time 3404250066 ps
CPU time 27.49 seconds
Started Aug 14 04:59:37 PM PDT 24
Finished Aug 14 05:00:04 PM PDT 24
Peak memory 199920 kb
Host smart-9893da04-e157-4dfc-8474-d1cd782d1da5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=876535922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.876535922
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2149066905
Short name T989
Test name
Test status
Simulation time 173901811240 ps
CPU time 73.88 seconds
Started Aug 14 04:59:41 PM PDT 24
Finished Aug 14 05:00:55 PM PDT 24
Peak memory 200796 kb
Host smart-2d98d60b-7fab-4137-b840-3b1809903c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149066905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2149066905
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.3815786388
Short name T810
Test name
Test status
Simulation time 7913862332 ps
CPU time 1.31 seconds
Started Aug 14 04:59:35 PM PDT 24
Finished Aug 14 04:59:36 PM PDT 24
Peak memory 197076 kb
Host smart-cd5d3326-2b9f-4f56-9d31-a853033b21d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815786388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3815786388
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2914080176
Short name T485
Test name
Test status
Simulation time 503202879 ps
CPU time 1.45 seconds
Started Aug 14 04:59:36 PM PDT 24
Finished Aug 14 04:59:38 PM PDT 24
Peak memory 200808 kb
Host smart-ae8f84ba-8fec-470d-8f95-936e1eb16203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914080176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2914080176
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.655681463
Short name T1093
Test name
Test status
Simulation time 79263467543 ps
CPU time 294.16 seconds
Started Aug 14 04:59:44 PM PDT 24
Finished Aug 14 05:04:39 PM PDT 24
Peak memory 200976 kb
Host smart-4c4ec92b-3646-4445-88e7-e943baaa6529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655681463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.655681463
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.2306592313
Short name T339
Test name
Test status
Simulation time 11572065695 ps
CPU time 29.76 seconds
Started Aug 14 04:59:47 PM PDT 24
Finished Aug 14 05:00:16 PM PDT 24
Peak memory 216616 kb
Host smart-7c58cb23-7373-4fb9-aad2-8152aed65b52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306592313 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.2306592313
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1607767462
Short name T420
Test name
Test status
Simulation time 1173819722 ps
CPU time 2.07 seconds
Started Aug 14 04:59:36 PM PDT 24
Finished Aug 14 04:59:38 PM PDT 24
Peak memory 199820 kb
Host smart-395adc28-3121-43f6-ac91-636312dbbdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607767462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1607767462
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1230130743
Short name T826
Test name
Test status
Simulation time 94789782983 ps
CPU time 93.98 seconds
Started Aug 14 04:59:38 PM PDT 24
Finished Aug 14 05:01:12 PM PDT 24
Peak memory 200920 kb
Host smart-ce696d67-71f6-4532-a60f-73748defaab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230130743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1230130743
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3168738591
Short name T1004
Test name
Test status
Simulation time 138901883795 ps
CPU time 36.66 seconds
Started Aug 14 05:03:25 PM PDT 24
Finished Aug 14 05:04:02 PM PDT 24
Peak memory 200932 kb
Host smart-a475bfd5-ae4b-4454-88a2-6a047489cce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168738591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3168738591
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.151719602
Short name T290
Test name
Test status
Simulation time 100489289421 ps
CPU time 86.62 seconds
Started Aug 14 05:03:25 PM PDT 24
Finished Aug 14 05:04:52 PM PDT 24
Peak memory 200912 kb
Host smart-fb77e4f9-743a-4620-bd6b-7cb727001165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151719602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.151719602
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2305455855
Short name T107
Test name
Test status
Simulation time 22137834752 ps
CPU time 45.45 seconds
Started Aug 14 05:03:26 PM PDT 24
Finished Aug 14 05:04:11 PM PDT 24
Peak memory 200952 kb
Host smart-dc50500d-0d74-44a2-9162-d452f9e704d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305455855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2305455855
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3681584872
Short name T126
Test name
Test status
Simulation time 49543722104 ps
CPU time 21.31 seconds
Started Aug 14 05:03:26 PM PDT 24
Finished Aug 14 05:03:48 PM PDT 24
Peak memory 200664 kb
Host smart-98120694-9875-4407-9182-6d42f968a041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681584872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3681584872
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1103368162
Short name T959
Test name
Test status
Simulation time 53585634258 ps
CPU time 50.68 seconds
Started Aug 14 05:03:25 PM PDT 24
Finished Aug 14 05:04:16 PM PDT 24
Peak memory 200828 kb
Host smart-3f5aafa3-b75d-4ac7-808f-cdefb96cb4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103368162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1103368162
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.268909634
Short name T876
Test name
Test status
Simulation time 9994376987 ps
CPU time 14.84 seconds
Started Aug 14 05:03:26 PM PDT 24
Finished Aug 14 05:03:41 PM PDT 24
Peak memory 200652 kb
Host smart-8f7eb7b3-e36b-4910-8280-130808c4b4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268909634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.268909634
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1388351596
Short name T719
Test name
Test status
Simulation time 52403677080 ps
CPU time 36.36 seconds
Started Aug 14 05:03:26 PM PDT 24
Finished Aug 14 05:04:03 PM PDT 24
Peak memory 200896 kb
Host smart-fbeebfdd-7f96-4706-9b55-bd502fdb8fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388351596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1388351596
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.116646080
Short name T247
Test name
Test status
Simulation time 112974031748 ps
CPU time 112.02 seconds
Started Aug 14 05:03:26 PM PDT 24
Finished Aug 14 05:05:18 PM PDT 24
Peak memory 200868 kb
Host smart-8194b985-4cef-4fd5-88d4-33383f1768ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116646080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.116646080
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2232106891
Short name T81
Test name
Test status
Simulation time 78815569691 ps
CPU time 30.46 seconds
Started Aug 14 05:03:26 PM PDT 24
Finished Aug 14 05:03:57 PM PDT 24
Peak memory 200956 kb
Host smart-2a9873a6-bc96-41ec-81d5-9477ff631b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232106891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2232106891
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.439875334
Short name T748
Test name
Test status
Simulation time 22994001 ps
CPU time 0.56 seconds
Started Aug 14 04:59:45 PM PDT 24
Finished Aug 14 04:59:46 PM PDT 24
Peak memory 195536 kb
Host smart-3a195fee-c50f-4df2-a745-c0f3697d4707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439875334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.439875334
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.18940879
Short name T132
Test name
Test status
Simulation time 261430312392 ps
CPU time 72.81 seconds
Started Aug 14 04:59:45 PM PDT 24
Finished Aug 14 05:00:57 PM PDT 24
Peak memory 200864 kb
Host smart-ea158904-5df1-4abc-b804-f4a3b150d480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18940879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.18940879
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.957269671
Short name T537
Test name
Test status
Simulation time 146689504347 ps
CPU time 137.73 seconds
Started Aug 14 04:59:49 PM PDT 24
Finished Aug 14 05:02:07 PM PDT 24
Peak memory 200848 kb
Host smart-0c830bd1-9e5e-4870-97dc-01bbe7dd5cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957269671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.957269671
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.574038103
Short name T932
Test name
Test status
Simulation time 10817514739 ps
CPU time 14.89 seconds
Started Aug 14 04:59:49 PM PDT 24
Finished Aug 14 05:00:04 PM PDT 24
Peak memory 200616 kb
Host smart-b12f7b6f-bea9-47d4-8746-431383c9e177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574038103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.574038103
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2885725944
Short name T438
Test name
Test status
Simulation time 7596744883 ps
CPU time 18.75 seconds
Started Aug 14 04:59:45 PM PDT 24
Finished Aug 14 05:00:04 PM PDT 24
Peak memory 200868 kb
Host smart-21957f45-6adf-4ed6-8a0c-c792bc653bd3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885725944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2885725944
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.4227955540
Short name T1155
Test name
Test status
Simulation time 71415996622 ps
CPU time 284.13 seconds
Started Aug 14 04:59:46 PM PDT 24
Finished Aug 14 05:04:30 PM PDT 24
Peak memory 200920 kb
Host smart-efe9e7d0-d33a-4e6b-9d25-61961c051335
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4227955540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.4227955540
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.2768148578
Short name T367
Test name
Test status
Simulation time 6971074654 ps
CPU time 7.38 seconds
Started Aug 14 04:59:46 PM PDT 24
Finished Aug 14 04:59:53 PM PDT 24
Peak memory 200288 kb
Host smart-9a4841ae-a358-4169-8785-20d409658866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768148578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.2768148578
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.1572892108
Short name T751
Test name
Test status
Simulation time 69772509852 ps
CPU time 112.26 seconds
Started Aug 14 04:59:44 PM PDT 24
Finished Aug 14 05:01:36 PM PDT 24
Peak memory 199756 kb
Host smart-23ff8cbb-3228-41c5-8b71-04e167017170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572892108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.1572892108
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.2009263990
Short name T690
Test name
Test status
Simulation time 19535644123 ps
CPU time 1163.81 seconds
Started Aug 14 04:59:58 PM PDT 24
Finished Aug 14 05:19:22 PM PDT 24
Peak memory 200892 kb
Host smart-c290af23-16b3-4816-a536-d0a185029b40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2009263990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2009263990
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.2188039672
Short name T619
Test name
Test status
Simulation time 7688841051 ps
CPU time 17.37 seconds
Started Aug 14 04:59:46 PM PDT 24
Finished Aug 14 05:00:03 PM PDT 24
Peak memory 199720 kb
Host smart-4396f648-95e4-436b-9e35-5394a603569b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2188039672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2188039672
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.612692509
Short name T808
Test name
Test status
Simulation time 112616080172 ps
CPU time 66.01 seconds
Started Aug 14 04:59:45 PM PDT 24
Finished Aug 14 05:00:51 PM PDT 24
Peak memory 200564 kb
Host smart-697c8d09-76fe-4240-ab53-0205fe668b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612692509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.612692509
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.793800867
Short name T1002
Test name
Test status
Simulation time 4038617633 ps
CPU time 1.59 seconds
Started Aug 14 04:59:46 PM PDT 24
Finished Aug 14 04:59:48 PM PDT 24
Peak memory 197820 kb
Host smart-eb428dd5-a2ae-4efd-8fcb-367e9265ccf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793800867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.793800867
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3283867557
Short name T770
Test name
Test status
Simulation time 265468174 ps
CPU time 1.34 seconds
Started Aug 14 04:59:45 PM PDT 24
Finished Aug 14 04:59:46 PM PDT 24
Peak memory 199104 kb
Host smart-18196110-00b4-4dd5-875f-f76b46a35fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283867557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3283867557
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.944554552
Short name T977
Test name
Test status
Simulation time 308206982773 ps
CPU time 346.31 seconds
Started Aug 14 04:59:45 PM PDT 24
Finished Aug 14 05:05:32 PM PDT 24
Peak memory 216796 kb
Host smart-e7d3cb8e-5e2e-42e5-a621-851c72de62e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944554552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.944554552
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.3573016
Short name T1079
Test name
Test status
Simulation time 3793475563 ps
CPU time 25.37 seconds
Started Aug 14 04:59:48 PM PDT 24
Finished Aug 14 05:00:13 PM PDT 24
Peak memory 209464 kb
Host smart-b09421e4-80d6-4d5f-9e80-d41f37f3bf64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573016 -assert nopostproc
+UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.3573016
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.1761650983
Short name T661
Test name
Test status
Simulation time 507456144 ps
CPU time 1.22 seconds
Started Aug 14 04:59:46 PM PDT 24
Finished Aug 14 04:59:47 PM PDT 24
Peak memory 199696 kb
Host smart-d3ba94a2-c2b6-4862-a9a9-38c4fe077ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761650983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.1761650983
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3999118402
Short name T830
Test name
Test status
Simulation time 22090451397 ps
CPU time 10.85 seconds
Started Aug 14 04:59:58 PM PDT 24
Finished Aug 14 05:00:09 PM PDT 24
Peak memory 200884 kb
Host smart-5d2514a4-0790-402f-9d1f-363e2bc62c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999118402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3999118402
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.3663867522
Short name T1170
Test name
Test status
Simulation time 35772706715 ps
CPU time 92.87 seconds
Started Aug 14 05:03:24 PM PDT 24
Finished Aug 14 05:04:57 PM PDT 24
Peak memory 200980 kb
Host smart-29ed251f-3ddc-44c5-a261-86104d31e7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663867522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3663867522
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1048913400
Short name T439
Test name
Test status
Simulation time 105907426646 ps
CPU time 41.43 seconds
Started Aug 14 05:03:26 PM PDT 24
Finished Aug 14 05:04:08 PM PDT 24
Peak memory 200968 kb
Host smart-618c2b30-6ed8-4dd8-8dfc-062906d2b108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048913400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1048913400
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.2960309842
Short name T684
Test name
Test status
Simulation time 145661848993 ps
CPU time 239.59 seconds
Started Aug 14 05:03:24 PM PDT 24
Finished Aug 14 05:07:24 PM PDT 24
Peak memory 200864 kb
Host smart-0d5b8736-db8f-4daa-bc61-c6d49f20e420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960309842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2960309842
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3612167257
Short name T1082
Test name
Test status
Simulation time 21014351799 ps
CPU time 28.39 seconds
Started Aug 14 05:03:26 PM PDT 24
Finished Aug 14 05:03:55 PM PDT 24
Peak memory 200908 kb
Host smart-6288f6c5-9889-48b7-a1c0-6c8f125d4406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612167257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3612167257
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.111109766
Short name T700
Test name
Test status
Simulation time 224508458867 ps
CPU time 23.36 seconds
Started Aug 14 05:03:26 PM PDT 24
Finished Aug 14 05:03:50 PM PDT 24
Peak memory 200900 kb
Host smart-3c8cbae3-00ba-48f8-bb30-5ade6da7eb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111109766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.111109766
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1534141138
Short name T221
Test name
Test status
Simulation time 44008760486 ps
CPU time 24.46 seconds
Started Aug 14 05:03:26 PM PDT 24
Finished Aug 14 05:03:50 PM PDT 24
Peak memory 200812 kb
Host smart-ea965f2f-4015-4ddd-ac3a-3e43cd2aab5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534141138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1534141138
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.557965171
Short name T75
Test name
Test status
Simulation time 14441473095 ps
CPU time 30.1 seconds
Started Aug 14 05:03:25 PM PDT 24
Finished Aug 14 05:03:55 PM PDT 24
Peak memory 200900 kb
Host smart-ac5fb970-77e8-4da6-ad61-3ab9cd22e8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557965171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.557965171
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1323586632
Short name T844
Test name
Test status
Simulation time 87633179630 ps
CPU time 36.04 seconds
Started Aug 14 05:03:25 PM PDT 24
Finished Aug 14 05:04:02 PM PDT 24
Peak memory 200884 kb
Host smart-36a88cda-f9b5-4083-9fd2-6b6bd77b9197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323586632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1323586632
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3521354651
Short name T815
Test name
Test status
Simulation time 144849327 ps
CPU time 0.58 seconds
Started Aug 14 04:59:53 PM PDT 24
Finished Aug 14 04:59:54 PM PDT 24
Peak memory 196560 kb
Host smart-d4c2417c-af4c-4422-a562-967253a2337d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521354651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3521354651
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.1286543589
Short name T115
Test name
Test status
Simulation time 21360306561 ps
CPU time 9.69 seconds
Started Aug 14 04:59:49 PM PDT 24
Finished Aug 14 04:59:59 PM PDT 24
Peak memory 200632 kb
Host smart-bacba2c5-47a0-44dc-b12d-9e7e64780cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286543589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1286543589
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2955141940
Short name T816
Test name
Test status
Simulation time 61770969275 ps
CPU time 52.72 seconds
Started Aug 14 04:59:44 PM PDT 24
Finished Aug 14 05:00:37 PM PDT 24
Peak memory 200868 kb
Host smart-d21572c7-b023-49c2-9385-b07860f18429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955141940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2955141940
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.1603191269
Short name T822
Test name
Test status
Simulation time 20191677270 ps
CPU time 12.35 seconds
Started Aug 14 04:59:46 PM PDT 24
Finished Aug 14 04:59:58 PM PDT 24
Peak memory 200908 kb
Host smart-1d7d23a7-9d63-42e8-bc12-13edbfb88a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603191269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1603191269
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.2530592444
Short name T669
Test name
Test status
Simulation time 3767872741 ps
CPU time 2.47 seconds
Started Aug 14 04:59:47 PM PDT 24
Finished Aug 14 04:59:49 PM PDT 24
Peak memory 197800 kb
Host smart-1a3b4916-bbfa-45c1-8408-a8e6473257c9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530592444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2530592444
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1684878099
Short name T43
Test name
Test status
Simulation time 101324205773 ps
CPU time 340.41 seconds
Started Aug 14 04:59:52 PM PDT 24
Finished Aug 14 05:05:32 PM PDT 24
Peak memory 200844 kb
Host smart-5ce32e4b-176c-4c62-a3e2-34e7479555da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1684878099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1684878099
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2926458664
Short name T448
Test name
Test status
Simulation time 4360659280 ps
CPU time 9.96 seconds
Started Aug 14 04:59:45 PM PDT 24
Finished Aug 14 04:59:55 PM PDT 24
Peak memory 200244 kb
Host smart-1a6f4577-858f-41c0-8c86-4631e2cf5b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926458664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2926458664
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.1293128407
Short name T709
Test name
Test status
Simulation time 88097914587 ps
CPU time 140.95 seconds
Started Aug 14 04:59:45 PM PDT 24
Finished Aug 14 05:02:06 PM PDT 24
Peak memory 201048 kb
Host smart-64043ead-6284-4d06-9d40-d4309f27687b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293128407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1293128407
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.1793194815
Short name T571
Test name
Test status
Simulation time 2428979044 ps
CPU time 63.48 seconds
Started Aug 14 05:00:07 PM PDT 24
Finished Aug 14 05:01:10 PM PDT 24
Peak memory 200896 kb
Host smart-95673fae-da38-4518-9970-f11b84dba0a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1793194815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1793194815
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.46079508
Short name T854
Test name
Test status
Simulation time 2116517907 ps
CPU time 9.36 seconds
Started Aug 14 04:59:58 PM PDT 24
Finished Aug 14 05:00:08 PM PDT 24
Peak memory 199564 kb
Host smart-876ee221-4ea7-4c05-9ea3-3706d0705303
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=46079508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.46079508
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.3881675006
Short name T398
Test name
Test status
Simulation time 32668696783 ps
CPU time 13.15 seconds
Started Aug 14 04:59:45 PM PDT 24
Finished Aug 14 04:59:59 PM PDT 24
Peak memory 199012 kb
Host smart-5980f448-c26f-4c74-9626-ae0091969871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881675006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3881675006
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.4091721224
Short name T584
Test name
Test status
Simulation time 37240271232 ps
CPU time 27.31 seconds
Started Aug 14 04:59:46 PM PDT 24
Finished Aug 14 05:00:13 PM PDT 24
Peak memory 196988 kb
Host smart-45362f2e-380c-49de-9fd6-8a8fc8c26a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091721224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.4091721224
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.1812772461
Short name T890
Test name
Test status
Simulation time 471862473 ps
CPU time 1.87 seconds
Started Aug 14 04:59:45 PM PDT 24
Finished Aug 14 04:59:47 PM PDT 24
Peak memory 199596 kb
Host smart-4f9b5e1c-4a07-4c3c-8263-9c056dd48eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812772461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1812772461
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.2176899840
Short name T551
Test name
Test status
Simulation time 270935419510 ps
CPU time 2863.19 seconds
Started Aug 14 04:59:52 PM PDT 24
Finished Aug 14 05:47:35 PM PDT 24
Peak memory 200916 kb
Host smart-0d7a4f75-132f-4e24-9c0b-7b05008a7859
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176899840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2176899840
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.978615276
Short name T1047
Test name
Test status
Simulation time 8342009344 ps
CPU time 57.4 seconds
Started Aug 14 04:59:53 PM PDT 24
Finished Aug 14 05:00:50 PM PDT 24
Peak memory 217372 kb
Host smart-879f40a8-52bd-4d83-8c69-dcad5dec591a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978615276 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.978615276
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.4051878755
Short name T969
Test name
Test status
Simulation time 956046529 ps
CPU time 3.1 seconds
Started Aug 14 04:59:45 PM PDT 24
Finished Aug 14 04:59:48 PM PDT 24
Peak memory 199812 kb
Host smart-5ea36c58-8f06-4388-a60d-70e05f011cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051878755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.4051878755
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3552756526
Short name T326
Test name
Test status
Simulation time 217380867017 ps
CPU time 34.55 seconds
Started Aug 14 04:59:46 PM PDT 24
Finished Aug 14 05:00:20 PM PDT 24
Peak memory 200968 kb
Host smart-ac2a5b37-e12a-4f4c-9e2d-87389a6aea76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552756526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3552756526
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1338564953
Short name T914
Test name
Test status
Simulation time 11097956148 ps
CPU time 10.21 seconds
Started Aug 14 05:03:22 PM PDT 24
Finished Aug 14 05:03:33 PM PDT 24
Peak memory 200952 kb
Host smart-ef2f59ed-1bde-4e4a-afc9-adf8f98921e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338564953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1338564953
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1429202795
Short name T1012
Test name
Test status
Simulation time 31795945647 ps
CPU time 12.42 seconds
Started Aug 14 05:03:33 PM PDT 24
Finished Aug 14 05:03:46 PM PDT 24
Peak memory 199232 kb
Host smart-75ead66f-8501-4568-80dc-16af099324c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429202795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1429202795
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1807158148
Short name T707
Test name
Test status
Simulation time 23405436776 ps
CPU time 17.94 seconds
Started Aug 14 05:03:35 PM PDT 24
Finished Aug 14 05:03:53 PM PDT 24
Peak memory 200688 kb
Host smart-1b487e89-d9c9-4245-ae88-c3109524e6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807158148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1807158148
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.385266592
Short name T557
Test name
Test status
Simulation time 28414728724 ps
CPU time 11.61 seconds
Started Aug 14 05:03:35 PM PDT 24
Finished Aug 14 05:03:47 PM PDT 24
Peak memory 200968 kb
Host smart-4b12fc22-aea5-45e7-adfc-862aa2f58006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385266592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.385266592
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.837498645
Short name T1127
Test name
Test status
Simulation time 51006177508 ps
CPU time 18.31 seconds
Started Aug 14 05:03:35 PM PDT 24
Finished Aug 14 05:03:53 PM PDT 24
Peak memory 200964 kb
Host smart-c9d36a56-ed6a-4686-9bf3-7131a0bc3f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837498645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.837498645
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3010354904
Short name T174
Test name
Test status
Simulation time 26004850671 ps
CPU time 41.22 seconds
Started Aug 14 05:03:37 PM PDT 24
Finished Aug 14 05:04:18 PM PDT 24
Peak memory 200852 kb
Host smart-a1a2fc3b-ae27-4770-a716-d416213224e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010354904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3010354904
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1545433795
Short name T200
Test name
Test status
Simulation time 61239606398 ps
CPU time 26.25 seconds
Started Aug 14 05:03:34 PM PDT 24
Finished Aug 14 05:04:01 PM PDT 24
Peak memory 200852 kb
Host smart-8082ab74-c9c8-4f82-bdd9-2cf42512ba3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545433795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1545433795
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.3799904711
Short name T1040
Test name
Test status
Simulation time 25953525187 ps
CPU time 23.02 seconds
Started Aug 14 05:03:35 PM PDT 24
Finished Aug 14 05:03:58 PM PDT 24
Peak memory 200108 kb
Host smart-48807a64-e110-4612-b2a6-d53260dd0102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799904711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3799904711
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.3962843020
Short name T1011
Test name
Test status
Simulation time 43813269009 ps
CPU time 16.62 seconds
Started Aug 14 05:03:36 PM PDT 24
Finished Aug 14 05:03:53 PM PDT 24
Peak memory 200836 kb
Host smart-35d68ac4-c016-4851-a5f5-ac5624ef8844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962843020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.3962843020
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1896514005
Short name T25
Test name
Test status
Simulation time 44884917 ps
CPU time 0.58 seconds
Started Aug 14 04:59:58 PM PDT 24
Finished Aug 14 04:59:59 PM PDT 24
Peak memory 196476 kb
Host smart-aac08f6e-8c4a-4734-9bc8-8b6a2e79ddbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896514005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1896514005
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1315017906
Short name T232
Test name
Test status
Simulation time 144945616932 ps
CPU time 230.3 seconds
Started Aug 14 04:59:55 PM PDT 24
Finished Aug 14 05:03:45 PM PDT 24
Peak memory 200964 kb
Host smart-141be239-9432-4fe0-8fe2-a7ee99c74b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315017906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1315017906
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.45740375
Short name T639
Test name
Test status
Simulation time 147913293861 ps
CPU time 15.99 seconds
Started Aug 14 04:59:58 PM PDT 24
Finished Aug 14 05:00:14 PM PDT 24
Peak memory 200820 kb
Host smart-fd4183c5-0ef3-44ac-a2ac-ebd92ac81c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45740375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.45740375
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.1081079300
Short name T416
Test name
Test status
Simulation time 42494660030 ps
CPU time 39.04 seconds
Started Aug 14 04:59:52 PM PDT 24
Finished Aug 14 05:00:31 PM PDT 24
Peak memory 200772 kb
Host smart-f343c93e-b087-41e4-9d48-bb774e00be72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081079300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1081079300
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.2549551540
Short name T611
Test name
Test status
Simulation time 26244195151 ps
CPU time 9.35 seconds
Started Aug 14 04:59:53 PM PDT 24
Finished Aug 14 05:00:03 PM PDT 24
Peak memory 199288 kb
Host smart-0e443bfb-7980-4a0d-8c52-712cd70df30d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549551540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2549551540
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.333111984
Short name T907
Test name
Test status
Simulation time 58175948510 ps
CPU time 503.49 seconds
Started Aug 14 04:59:53 PM PDT 24
Finished Aug 14 05:08:16 PM PDT 24
Peak memory 200788 kb
Host smart-775ef022-5048-45a0-bb04-acb80d585786
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=333111984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.333111984
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3971249687
Short name T474
Test name
Test status
Simulation time 3829263394 ps
CPU time 8.43 seconds
Started Aug 14 04:59:55 PM PDT 24
Finished Aug 14 05:00:04 PM PDT 24
Peak memory 199756 kb
Host smart-b1538b4f-58de-437b-a87d-067cefeef972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971249687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3971249687
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1334627235
Short name T1131
Test name
Test status
Simulation time 79471749289 ps
CPU time 36.15 seconds
Started Aug 14 04:59:53 PM PDT 24
Finished Aug 14 05:00:29 PM PDT 24
Peak memory 201168 kb
Host smart-572920ef-223b-4840-a4ac-a8f33f01fc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334627235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1334627235
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.3083996445
Short name T284
Test name
Test status
Simulation time 23532163242 ps
CPU time 1051.46 seconds
Started Aug 14 04:59:54 PM PDT 24
Finished Aug 14 05:17:25 PM PDT 24
Peak memory 200840 kb
Host smart-21917644-334f-4999-a95f-c102613f8fca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3083996445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3083996445
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.2599131209
Short name T1006
Test name
Test status
Simulation time 7662243760 ps
CPU time 3.94 seconds
Started Aug 14 04:59:55 PM PDT 24
Finished Aug 14 04:59:59 PM PDT 24
Peak memory 199956 kb
Host smart-52f4d31e-f3c3-4410-b2ed-9f0f4d31d451
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2599131209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2599131209
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.934388655
Short name T976
Test name
Test status
Simulation time 167967709164 ps
CPU time 228.73 seconds
Started Aug 14 04:59:58 PM PDT 24
Finished Aug 14 05:03:47 PM PDT 24
Peak memory 200832 kb
Host smart-25ac32eb-d6b2-43f1-89b3-96797d3c7443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934388655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.934388655
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.4155058122
Short name T483
Test name
Test status
Simulation time 42560126417 ps
CPU time 15.99 seconds
Started Aug 14 04:59:53 PM PDT 24
Finished Aug 14 05:00:09 PM PDT 24
Peak memory 196772 kb
Host smart-1e3b4c51-c813-426b-b600-d24c99d32caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155058122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.4155058122
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.4121316081
Short name T1106
Test name
Test status
Simulation time 642979544 ps
CPU time 1.89 seconds
Started Aug 14 04:59:53 PM PDT 24
Finished Aug 14 04:59:55 PM PDT 24
Peak memory 200848 kb
Host smart-ba5c2176-bf7a-43e2-b639-a5e0d24e9e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121316081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.4121316081
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.1070262333
Short name T1069
Test name
Test status
Simulation time 421897827593 ps
CPU time 358.41 seconds
Started Aug 14 04:59:52 PM PDT 24
Finished Aug 14 05:05:51 PM PDT 24
Peak memory 217144 kb
Host smart-d4698016-c1d7-42cf-9718-80aa18928eb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070262333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1070262333
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.4108230888
Short name T85
Test name
Test status
Simulation time 6509109413 ps
CPU time 23.29 seconds
Started Aug 14 04:59:53 PM PDT 24
Finished Aug 14 05:00:16 PM PDT 24
Peak memory 217520 kb
Host smart-902490a3-d88f-4246-be4e-f1efd55fe209
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108230888 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.4108230888
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3490186375
Short name T399
Test name
Test status
Simulation time 2083496642 ps
CPU time 3.09 seconds
Started Aug 14 04:59:52 PM PDT 24
Finished Aug 14 04:59:55 PM PDT 24
Peak memory 199392 kb
Host smart-5e333c54-3e0c-4d5c-bfc4-d77bc60fb5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490186375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3490186375
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3669610409
Short name T1183
Test name
Test status
Simulation time 33313363285 ps
CPU time 50.77 seconds
Started Aug 14 04:59:52 PM PDT 24
Finished Aug 14 05:00:43 PM PDT 24
Peak memory 200964 kb
Host smart-f2f50cd1-c80c-425f-ad8a-f94cf9c675d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669610409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3669610409
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.1114851729
Short name T210
Test name
Test status
Simulation time 7250215124 ps
CPU time 7.87 seconds
Started Aug 14 05:03:38 PM PDT 24
Finished Aug 14 05:03:46 PM PDT 24
Peak memory 200812 kb
Host smart-048aaa07-e4c8-47e0-ad5c-ac7fd52e3319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114851729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1114851729
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1641873846
Short name T180
Test name
Test status
Simulation time 99458964823 ps
CPU time 48.71 seconds
Started Aug 14 05:03:35 PM PDT 24
Finished Aug 14 05:04:24 PM PDT 24
Peak memory 200864 kb
Host smart-b3a1a321-9b0f-404b-86b8-d4d724d4ee52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641873846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1641873846
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1006396327
Short name T462
Test name
Test status
Simulation time 22972433312 ps
CPU time 36.18 seconds
Started Aug 14 05:03:34 PM PDT 24
Finished Aug 14 05:04:11 PM PDT 24
Peak memory 200968 kb
Host smart-d31f21d2-3b03-48ca-b995-3ce7fbda8041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006396327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1006396327
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2066376404
Short name T177
Test name
Test status
Simulation time 84116742459 ps
CPU time 101.75 seconds
Started Aug 14 05:03:34 PM PDT 24
Finished Aug 14 05:05:16 PM PDT 24
Peak memory 200864 kb
Host smart-e7f66cd3-2c17-431b-99bb-0f8b6798a676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066376404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2066376404
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.4050012598
Short name T422
Test name
Test status
Simulation time 15980041701 ps
CPU time 13.81 seconds
Started Aug 14 05:03:33 PM PDT 24
Finished Aug 14 05:03:47 PM PDT 24
Peak memory 200984 kb
Host smart-3ef94011-7585-4566-a405-a0889aec9edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050012598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.4050012598
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.2731385099
Short name T354
Test name
Test status
Simulation time 16612676182 ps
CPU time 38.87 seconds
Started Aug 14 05:03:39 PM PDT 24
Finished Aug 14 05:04:18 PM PDT 24
Peak memory 200796 kb
Host smart-70ff74a5-e47e-4044-8ecb-06a05344dded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731385099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2731385099
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1667930900
Short name T658
Test name
Test status
Simulation time 109007940900 ps
CPU time 157.82 seconds
Started Aug 14 05:03:34 PM PDT 24
Finished Aug 14 05:06:12 PM PDT 24
Peak memory 200932 kb
Host smart-9cd60005-a20f-4a62-867d-ee1c6b59e444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667930900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1667930900
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.4127827095
Short name T911
Test name
Test status
Simulation time 22675147294 ps
CPU time 37.16 seconds
Started Aug 14 05:03:33 PM PDT 24
Finished Aug 14 05:04:10 PM PDT 24
Peak memory 200972 kb
Host smart-a8e12982-3261-44cd-81f3-bff64bc2dac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127827095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.4127827095
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.1594078785
Short name T903
Test name
Test status
Simulation time 34379562485 ps
CPU time 11.95 seconds
Started Aug 14 05:03:34 PM PDT 24
Finished Aug 14 05:03:46 PM PDT 24
Peak memory 200860 kb
Host smart-f60196a1-4e48-4664-8684-b9b026d1e5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594078785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1594078785
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.1720499129
Short name T956
Test name
Test status
Simulation time 17114659 ps
CPU time 0.55 seconds
Started Aug 14 05:00:00 PM PDT 24
Finished Aug 14 05:00:01 PM PDT 24
Peak memory 195236 kb
Host smart-8fbfd32a-2f76-4053-bf1e-3bcfdf0549f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720499129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1720499129
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.113403005
Short name T235
Test name
Test status
Simulation time 81919992894 ps
CPU time 154.2 seconds
Started Aug 14 05:00:02 PM PDT 24
Finished Aug 14 05:02:40 PM PDT 24
Peak memory 200968 kb
Host smart-9665ea94-28b3-4e76-b807-1fd2ca985487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113403005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.113403005
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3978573712
Short name T432
Test name
Test status
Simulation time 43869656198 ps
CPU time 75.07 seconds
Started Aug 14 05:00:02 PM PDT 24
Finished Aug 14 05:01:21 PM PDT 24
Peak memory 200972 kb
Host smart-b2a68e04-a525-4183-bb93-b694cfcc4059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978573712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3978573712
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_intr.2338568024
Short name T1172
Test name
Test status
Simulation time 30402461781 ps
CPU time 45.52 seconds
Started Aug 14 05:00:00 PM PDT 24
Finished Aug 14 05:00:46 PM PDT 24
Peak memory 200816 kb
Host smart-f6e616ac-f12f-44a6-b2c6-e026b2f90fce
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338568024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2338568024
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.3402165568
Short name T1157
Test name
Test status
Simulation time 90631447607 ps
CPU time 282.14 seconds
Started Aug 14 05:00:04 PM PDT 24
Finished Aug 14 05:04:48 PM PDT 24
Peak memory 200916 kb
Host smart-d8f6e3eb-2fcb-4e4f-8398-130742fce11f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3402165568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3402165568
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3628376304
Short name T812
Test name
Test status
Simulation time 5416373382 ps
CPU time 10.65 seconds
Started Aug 14 05:00:03 PM PDT 24
Finished Aug 14 05:00:16 PM PDT 24
Peak memory 200460 kb
Host smart-e9d41ac9-98bf-4fc8-aaa8-049aed8c36d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628376304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3628376304
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.2870844866
Short name T1107
Test name
Test status
Simulation time 29176946032 ps
CPU time 46.25 seconds
Started Aug 14 05:00:03 PM PDT 24
Finished Aug 14 05:00:52 PM PDT 24
Peak memory 200896 kb
Host smart-93d0dd1d-f47b-47f7-80c0-8c32031776ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870844866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2870844866
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.615696763
Short name T1134
Test name
Test status
Simulation time 27040096588 ps
CPU time 598.09 seconds
Started Aug 14 05:00:02 PM PDT 24
Finished Aug 14 05:10:04 PM PDT 24
Peak memory 200976 kb
Host smart-875890af-a085-4ead-bbd8-f0c1ac7f25fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=615696763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.615696763
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2773673005
Short name T699
Test name
Test status
Simulation time 6303530275 ps
CPU time 53.01 seconds
Started Aug 14 05:00:00 PM PDT 24
Finished Aug 14 05:00:53 PM PDT 24
Peak memory 199012 kb
Host smart-714e9441-80b6-4d44-b944-ac05579f8866
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2773673005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2773673005
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2927206252
Short name T843
Test name
Test status
Simulation time 124656253483 ps
CPU time 170.77 seconds
Started Aug 14 05:00:04 PM PDT 24
Finished Aug 14 05:02:56 PM PDT 24
Peak memory 200900 kb
Host smart-19002f2e-bea3-44bb-90ab-c62d051a59ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927206252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2927206252
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2141697340
Short name T819
Test name
Test status
Simulation time 2957495557 ps
CPU time 1.92 seconds
Started Aug 14 05:00:00 PM PDT 24
Finished Aug 14 05:00:02 PM PDT 24
Peak memory 196756 kb
Host smart-0f20d1fb-a716-4ecb-86bf-de715b84bc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141697340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2141697340
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.2026470463
Short name T705
Test name
Test status
Simulation time 894888693 ps
CPU time 2.82 seconds
Started Aug 14 05:00:03 PM PDT 24
Finished Aug 14 05:00:08 PM PDT 24
Peak memory 200356 kb
Host smart-c62d888e-9d1f-463d-bf22-25875ec0c60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026470463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2026470463
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.1692242043
Short name T472
Test name
Test status
Simulation time 40040689320 ps
CPU time 139.6 seconds
Started Aug 14 05:00:02 PM PDT 24
Finished Aug 14 05:02:25 PM PDT 24
Peak memory 200968 kb
Host smart-e82d8924-e136-4a5a-ba32-93248d3ab340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692242043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.1692242043
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.1430120476
Short name T15
Test name
Test status
Simulation time 8612176644 ps
CPU time 83.58 seconds
Started Aug 14 05:00:00 PM PDT 24
Finished Aug 14 05:01:24 PM PDT 24
Peak memory 216948 kb
Host smart-815cff8f-8843-4f66-a13e-d8fc843ea068
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430120476 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.1430120476
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1953252409
Short name T455
Test name
Test status
Simulation time 6761632511 ps
CPU time 13.19 seconds
Started Aug 14 05:00:00 PM PDT 24
Finished Aug 14 05:00:13 PM PDT 24
Peak memory 200888 kb
Host smart-e2c73e43-1dd2-4389-a7b0-6ada147695a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953252409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1953252409
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2849921142
Short name T698
Test name
Test status
Simulation time 80639393619 ps
CPU time 123.8 seconds
Started Aug 14 05:00:01 PM PDT 24
Finished Aug 14 05:02:05 PM PDT 24
Peak memory 200960 kb
Host smart-41c12a0b-274b-4d31-aeeb-5a5754467afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849921142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2849921142
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.2714416004
Short name T775
Test name
Test status
Simulation time 230801447146 ps
CPU time 388.39 seconds
Started Aug 14 05:03:38 PM PDT 24
Finished Aug 14 05:10:07 PM PDT 24
Peak memory 200872 kb
Host smart-b86f2bf2-68aa-408d-83c8-f9c99b4c52e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714416004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2714416004
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.1304563810
Short name T529
Test name
Test status
Simulation time 118685938832 ps
CPU time 45.99 seconds
Started Aug 14 05:03:33 PM PDT 24
Finished Aug 14 05:04:19 PM PDT 24
Peak memory 200956 kb
Host smart-5c83772e-8fe6-49a8-a4aa-8273349527c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304563810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.1304563810
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.4092576467
Short name T916
Test name
Test status
Simulation time 93254676498 ps
CPU time 133.81 seconds
Started Aug 14 05:03:35 PM PDT 24
Finished Aug 14 05:05:49 PM PDT 24
Peak memory 200484 kb
Host smart-7d2f8869-ac66-46c1-a5cd-8170d3035633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092576467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.4092576467
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.3396560625
Short name T171
Test name
Test status
Simulation time 77138466540 ps
CPU time 31.63 seconds
Started Aug 14 05:03:35 PM PDT 24
Finished Aug 14 05:04:07 PM PDT 24
Peak memory 200972 kb
Host smart-8f41b9e7-e844-4986-9d60-9ca1935984da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396560625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3396560625
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1683874068
Short name T204
Test name
Test status
Simulation time 55637551270 ps
CPU time 96.95 seconds
Started Aug 14 05:03:35 PM PDT 24
Finished Aug 14 05:05:12 PM PDT 24
Peak memory 200952 kb
Host smart-d2eda371-bb9e-433e-b41c-2f823fdf885b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683874068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1683874068
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1459506959
Short name T1043
Test name
Test status
Simulation time 17689456748 ps
CPU time 31.88 seconds
Started Aug 14 05:03:33 PM PDT 24
Finished Aug 14 05:04:05 PM PDT 24
Peak memory 200964 kb
Host smart-ea6122bf-946b-4baf-acab-55d02a1d0bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459506959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1459506959
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.239034518
Short name T357
Test name
Test status
Simulation time 37160157967 ps
CPU time 16.77 seconds
Started Aug 14 05:03:34 PM PDT 24
Finished Aug 14 05:03:51 PM PDT 24
Peak memory 200976 kb
Host smart-3fe9b236-a3a8-4342-b3c2-22ef912a5b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239034518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.239034518
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1023327672
Short name T811
Test name
Test status
Simulation time 120762449 ps
CPU time 0.54 seconds
Started Aug 14 05:00:01 PM PDT 24
Finished Aug 14 05:00:06 PM PDT 24
Peak memory 195648 kb
Host smart-d7747391-4f0e-4c6e-b4c5-46dbca4d93a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023327672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1023327672
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.751018162
Short name T155
Test name
Test status
Simulation time 37585413976 ps
CPU time 4.91 seconds
Started Aug 14 05:00:03 PM PDT 24
Finished Aug 14 05:00:10 PM PDT 24
Peak memory 200660 kb
Host smart-f5bdaedc-8302-4c78-902d-911e529858a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751018162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.751018162
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.3413834692
Short name T947
Test name
Test status
Simulation time 21438214224 ps
CPU time 14.7 seconds
Started Aug 14 05:00:04 PM PDT 24
Finished Aug 14 05:00:20 PM PDT 24
Peak memory 200888 kb
Host smart-f3cd2b21-627b-4a9e-a4d1-8790d803087a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413834692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3413834692
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2357419850
Short name T1125
Test name
Test status
Simulation time 78553228908 ps
CPU time 30.82 seconds
Started Aug 14 05:00:03 PM PDT 24
Finished Aug 14 05:00:36 PM PDT 24
Peak memory 200884 kb
Host smart-231d6395-e135-4f4d-b705-09332e0c5607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357419850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2357419850
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.600945605
Short name T1142
Test name
Test status
Simulation time 11496912140 ps
CPU time 17.05 seconds
Started Aug 14 05:00:01 PM PDT 24
Finished Aug 14 05:00:22 PM PDT 24
Peak memory 200916 kb
Host smart-ba8113ef-b28e-4a65-8379-fd405e6a8f2f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600945605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.600945605
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.4201436212
Short name T671
Test name
Test status
Simulation time 66549593695 ps
CPU time 173.77 seconds
Started Aug 14 05:00:02 PM PDT 24
Finished Aug 14 05:02:59 PM PDT 24
Peak memory 200904 kb
Host smart-2969aedd-6f71-417e-aaee-1e8788dcf5fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4201436212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.4201436212
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.3561786182
Short name T360
Test name
Test status
Simulation time 4028813934 ps
CPU time 5.11 seconds
Started Aug 14 05:00:01 PM PDT 24
Finished Aug 14 05:00:10 PM PDT 24
Peak memory 200264 kb
Host smart-15a4f5b0-f017-4321-b926-bb8ad9d29867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561786182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3561786182
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.933589651
Short name T298
Test name
Test status
Simulation time 165936818287 ps
CPU time 69.49 seconds
Started Aug 14 05:00:00 PM PDT 24
Finished Aug 14 05:01:10 PM PDT 24
Peak memory 201076 kb
Host smart-60d2cea5-494d-456c-967c-8579dcf05fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933589651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.933589651
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.2498904915
Short name T877
Test name
Test status
Simulation time 7285101825 ps
CPU time 359.66 seconds
Started Aug 14 05:00:02 PM PDT 24
Finished Aug 14 05:06:05 PM PDT 24
Peak memory 200972 kb
Host smart-2787d4e5-117f-45f4-9b51-7e0e8f7c5251
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2498904915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2498904915
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.1144181960
Short name T451
Test name
Test status
Simulation time 2947554195 ps
CPU time 19.78 seconds
Started Aug 14 05:00:02 PM PDT 24
Finished Aug 14 05:00:25 PM PDT 24
Peak memory 199296 kb
Host smart-42cd9548-3552-4c40-b288-759251e03c72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1144181960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.1144181960
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.686879153
Short name T679
Test name
Test status
Simulation time 12842884986 ps
CPU time 19.86 seconds
Started Aug 14 05:00:00 PM PDT 24
Finished Aug 14 05:00:20 PM PDT 24
Peak memory 200820 kb
Host smart-0d71fa9c-ee50-47be-b171-013a07352182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686879153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.686879153
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.1037810275
Short name T1136
Test name
Test status
Simulation time 4262663074 ps
CPU time 3.95 seconds
Started Aug 14 05:00:01 PM PDT 24
Finished Aug 14 05:00:05 PM PDT 24
Peak memory 197248 kb
Host smart-987b3015-5cfe-4bb7-8dcd-14eb75b726d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037810275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1037810275
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1240310401
Short name T401
Test name
Test status
Simulation time 661529860 ps
CPU time 3.97 seconds
Started Aug 14 05:00:01 PM PDT 24
Finished Aug 14 05:00:05 PM PDT 24
Peak memory 200524 kb
Host smart-279e22fc-01c5-450a-b3ff-f63afb05d03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240310401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1240310401
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.187715738
Short name T790
Test name
Test status
Simulation time 18689333099 ps
CPU time 635.31 seconds
Started Aug 14 05:00:04 PM PDT 24
Finished Aug 14 05:10:41 PM PDT 24
Peak memory 200896 kb
Host smart-310ed1e9-39fb-4346-9130-d09e3c01f183
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187715738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.187715738
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.2282670306
Short name T803
Test name
Test status
Simulation time 3457683753 ps
CPU time 2.11 seconds
Started Aug 14 05:00:00 PM PDT 24
Finished Aug 14 05:00:02 PM PDT 24
Peak memory 200536 kb
Host smart-bc525ac6-7722-4b51-b027-d74f56c7da27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282670306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2282670306
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2806524747
Short name T434
Test name
Test status
Simulation time 2461133576 ps
CPU time 4.43 seconds
Started Aug 14 05:00:01 PM PDT 24
Finished Aug 14 05:00:05 PM PDT 24
Peak memory 197596 kb
Host smart-87ebf126-cd08-403e-ab04-c193f42f5e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806524747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2806524747
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.437258917
Short name T1174
Test name
Test status
Simulation time 52940220646 ps
CPU time 81.45 seconds
Started Aug 14 05:03:33 PM PDT 24
Finished Aug 14 05:04:55 PM PDT 24
Peak memory 200880 kb
Host smart-d96243e3-eb6c-4cc8-89c6-7e0e0af14f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437258917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.437258917
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2579706793
Short name T127
Test name
Test status
Simulation time 115242991318 ps
CPU time 89.8 seconds
Started Aug 14 05:03:38 PM PDT 24
Finished Aug 14 05:05:08 PM PDT 24
Peak memory 200876 kb
Host smart-9935138f-b466-42fb-96ea-848963858937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579706793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2579706793
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.920172010
Short name T261
Test name
Test status
Simulation time 24577991901 ps
CPU time 17.35 seconds
Started Aug 14 05:03:43 PM PDT 24
Finished Aug 14 05:04:01 PM PDT 24
Peak memory 200896 kb
Host smart-ed0e1629-d61e-4b88-83b5-e803b50bbc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920172010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.920172010
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2747131639
Short name T680
Test name
Test status
Simulation time 58589212871 ps
CPU time 103.31 seconds
Started Aug 14 05:03:45 PM PDT 24
Finished Aug 14 05:05:28 PM PDT 24
Peak memory 200964 kb
Host smart-ff4483ff-af8d-460d-b089-57d4c15a9f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747131639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2747131639
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.1482757008
Short name T620
Test name
Test status
Simulation time 88131773198 ps
CPU time 143.48 seconds
Started Aug 14 05:03:44 PM PDT 24
Finished Aug 14 05:06:08 PM PDT 24
Peak memory 200908 kb
Host smart-5ffcde66-3e2c-4e2f-9214-6a836efb8879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482757008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1482757008
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.1310390695
Short name T346
Test name
Test status
Simulation time 44420266427 ps
CPU time 37.69 seconds
Started Aug 14 05:03:48 PM PDT 24
Finished Aug 14 05:04:26 PM PDT 24
Peak memory 200964 kb
Host smart-e1db3a83-c5a4-4b22-be48-cac41ca5fb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310390695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1310390695
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1366668490
Short name T502
Test name
Test status
Simulation time 27662477301 ps
CPU time 19.78 seconds
Started Aug 14 05:03:44 PM PDT 24
Finished Aug 14 05:04:03 PM PDT 24
Peak memory 200736 kb
Host smart-fe7b8945-feaa-4083-ac7f-60271c8a3eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366668490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1366668490
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.922194536
Short name T206
Test name
Test status
Simulation time 44039647070 ps
CPU time 33.26 seconds
Started Aug 14 05:03:43 PM PDT 24
Finished Aug 14 05:04:16 PM PDT 24
Peak memory 200932 kb
Host smart-b8719d64-e11a-4067-ad47-bd3720b8a429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922194536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.922194536
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3564966685
Short name T386
Test name
Test status
Simulation time 12963507 ps
CPU time 0.57 seconds
Started Aug 14 05:00:12 PM PDT 24
Finished Aug 14 05:00:13 PM PDT 24
Peak memory 196272 kb
Host smart-855ca93c-cce5-4460-944d-17320d7dfebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564966685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3564966685
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.137974086
Short name T1145
Test name
Test status
Simulation time 56185362158 ps
CPU time 14.06 seconds
Started Aug 14 05:00:03 PM PDT 24
Finished Aug 14 05:00:19 PM PDT 24
Peak memory 200888 kb
Host smart-6e9647fb-ff71-45b3-ad58-5437f172234e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137974086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.137974086
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3598589288
Short name T1111
Test name
Test status
Simulation time 95780110584 ps
CPU time 118.26 seconds
Started Aug 14 05:00:02 PM PDT 24
Finished Aug 14 05:02:04 PM PDT 24
Peak memory 200920 kb
Host smart-7b8ae9b7-4fa6-49ab-9096-269c39314f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598589288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3598589288
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2280685654
Short name T695
Test name
Test status
Simulation time 69666971943 ps
CPU time 119.5 seconds
Started Aug 14 05:00:11 PM PDT 24
Finished Aug 14 05:02:11 PM PDT 24
Peak memory 200788 kb
Host smart-5c105308-9d74-4afa-a3a6-8de1657f4354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280685654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2280685654
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.3962619474
Short name T501
Test name
Test status
Simulation time 48870151019 ps
CPU time 22.69 seconds
Started Aug 14 05:00:12 PM PDT 24
Finished Aug 14 05:00:35 PM PDT 24
Peak memory 200916 kb
Host smart-008249d4-1622-4a88-bdfb-841562d96725
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962619474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3962619474
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.4108540679
Short name T1045
Test name
Test status
Simulation time 103091154373 ps
CPU time 121.33 seconds
Started Aug 14 05:00:11 PM PDT 24
Finished Aug 14 05:02:13 PM PDT 24
Peak memory 200852 kb
Host smart-9eb1d6dd-ac51-479b-b76f-8b63a77f5f22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4108540679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.4108540679
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.789915948
Short name T484
Test name
Test status
Simulation time 6404136799 ps
CPU time 12.79 seconds
Started Aug 14 05:00:12 PM PDT 24
Finished Aug 14 05:00:25 PM PDT 24
Peak memory 200928 kb
Host smart-e0a276f0-79de-410a-90d6-44e278dccc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789915948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.789915948
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.1179486188
Short name T295
Test name
Test status
Simulation time 74294549982 ps
CPU time 125.27 seconds
Started Aug 14 05:00:15 PM PDT 24
Finished Aug 14 05:02:20 PM PDT 24
Peak memory 201248 kb
Host smart-a510628d-3a87-4395-942d-c6de624902dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179486188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.1179486188
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.4235344542
Short name T712
Test name
Test status
Simulation time 12334191129 ps
CPU time 139.94 seconds
Started Aug 14 05:00:12 PM PDT 24
Finished Aug 14 05:02:33 PM PDT 24
Peak memory 200944 kb
Host smart-7db7f11e-c880-4032-a159-31aa1bf6d32a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4235344542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.4235344542
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.1774056318
Short name T375
Test name
Test status
Simulation time 1911683646 ps
CPU time 3.52 seconds
Started Aug 14 05:00:13 PM PDT 24
Finished Aug 14 05:00:17 PM PDT 24
Peak memory 199124 kb
Host smart-2991c5b7-5df1-4f2b-b45b-83a2b635fcae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1774056318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1774056318
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2761604460
Short name T1144
Test name
Test status
Simulation time 44004060796 ps
CPU time 71.41 seconds
Started Aug 14 05:00:13 PM PDT 24
Finished Aug 14 05:01:24 PM PDT 24
Peak memory 200992 kb
Host smart-4323d001-065f-41d6-bbb4-5cb4395eaea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761604460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2761604460
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2748031837
Short name T568
Test name
Test status
Simulation time 3403714413 ps
CPU time 1.85 seconds
Started Aug 14 05:00:15 PM PDT 24
Finished Aug 14 05:00:17 PM PDT 24
Peak memory 197452 kb
Host smart-c5db1836-a4b7-4aaa-949f-7563644b0fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748031837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2748031837
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2773370825
Short name T848
Test name
Test status
Simulation time 533656770 ps
CPU time 3.41 seconds
Started Aug 14 05:00:00 PM PDT 24
Finished Aug 14 05:00:04 PM PDT 24
Peak memory 199932 kb
Host smart-ee9a7118-ed35-41db-9065-2cbb611a61f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773370825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2773370825
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.766468681
Short name T706
Test name
Test status
Simulation time 122765352020 ps
CPU time 191.35 seconds
Started Aug 14 05:00:13 PM PDT 24
Finished Aug 14 05:03:25 PM PDT 24
Peak memory 200952 kb
Host smart-5ccb0ab8-0404-4071-9d6a-908d2f10d472
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766468681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.766468681
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2540045681
Short name T101
Test name
Test status
Simulation time 5154044905 ps
CPU time 51.32 seconds
Started Aug 14 05:00:12 PM PDT 24
Finished Aug 14 05:01:03 PM PDT 24
Peak memory 217316 kb
Host smart-02754e0b-a524-4444-9f1f-fbb7ed1769f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540045681 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2540045681
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3476346150
Short name T507
Test name
Test status
Simulation time 6408586297 ps
CPU time 18.79 seconds
Started Aug 14 05:00:13 PM PDT 24
Finished Aug 14 05:00:32 PM PDT 24
Peak memory 200964 kb
Host smart-d58abfca-e92a-4bb0-b927-e02b54d8170c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476346150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3476346150
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.294290598
Short name T1129
Test name
Test status
Simulation time 216746558615 ps
CPU time 90.99 seconds
Started Aug 14 05:00:00 PM PDT 24
Finished Aug 14 05:01:32 PM PDT 24
Peak memory 200956 kb
Host smart-90cb007b-2e5d-4226-bd92-3db0eedc92aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294290598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.294290598
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.4094166714
Short name T539
Test name
Test status
Simulation time 25610133577 ps
CPU time 38.16 seconds
Started Aug 14 05:03:48 PM PDT 24
Finished Aug 14 05:04:26 PM PDT 24
Peak memory 200964 kb
Host smart-e106f2c4-cc3e-458a-a75d-0839c7559654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094166714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.4094166714
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.3201866531
Short name T435
Test name
Test status
Simulation time 72594734733 ps
CPU time 77.2 seconds
Started Aug 14 05:03:46 PM PDT 24
Finished Aug 14 05:05:03 PM PDT 24
Peak memory 200968 kb
Host smart-89ab8c6d-f57d-4c15-84f9-bbca3d931485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201866531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3201866531
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3447352034
Short name T949
Test name
Test status
Simulation time 18398465775 ps
CPU time 29.86 seconds
Started Aug 14 05:03:45 PM PDT 24
Finished Aug 14 05:04:14 PM PDT 24
Peak memory 200560 kb
Host smart-15b5d0e5-f721-4bb8-90be-e9ba447e2fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447352034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3447352034
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.419488801
Short name T1065
Test name
Test status
Simulation time 84047059987 ps
CPU time 85.64 seconds
Started Aug 14 05:03:44 PM PDT 24
Finished Aug 14 05:05:10 PM PDT 24
Peak memory 200972 kb
Host smart-f586f7c3-be09-4998-8035-76f18a29f557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419488801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.419488801
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1332756673
Short name T490
Test name
Test status
Simulation time 75572753866 ps
CPU time 220.4 seconds
Started Aug 14 05:03:44 PM PDT 24
Finished Aug 14 05:07:25 PM PDT 24
Peak memory 200888 kb
Host smart-aec42469-8664-4432-a811-3dddabafd20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332756673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1332756673
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3664976088
Short name T135
Test name
Test status
Simulation time 52274467119 ps
CPU time 39.71 seconds
Started Aug 14 05:03:45 PM PDT 24
Finished Aug 14 05:04:25 PM PDT 24
Peak memory 200892 kb
Host smart-9c6998d4-4a09-48a7-8534-62351df6be15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664976088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3664976088
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.969407400
Short name T196
Test name
Test status
Simulation time 51398171689 ps
CPU time 80.95 seconds
Started Aug 14 05:03:45 PM PDT 24
Finished Aug 14 05:05:06 PM PDT 24
Peak memory 200788 kb
Host smart-b77844d9-45ef-4fdf-813b-c1ccca80e136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969407400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.969407400
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1300936137
Short name T637
Test name
Test status
Simulation time 123691368567 ps
CPU time 189.38 seconds
Started Aug 14 05:03:44 PM PDT 24
Finished Aug 14 05:06:53 PM PDT 24
Peak memory 200948 kb
Host smart-2eb1f16a-d93e-4883-8cc9-97422c3f07c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300936137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1300936137
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1036178279
Short name T24
Test name
Test status
Simulation time 46132306 ps
CPU time 0.57 seconds
Started Aug 14 05:00:15 PM PDT 24
Finished Aug 14 05:00:16 PM PDT 24
Peak memory 196480 kb
Host smart-c8ec1a7d-36fc-4858-8685-3f07ef15a729
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036178279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1036178279
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.1823452382
Short name T720
Test name
Test status
Simulation time 97742639187 ps
CPU time 38.7 seconds
Started Aug 14 05:00:12 PM PDT 24
Finished Aug 14 05:00:51 PM PDT 24
Peak memory 200888 kb
Host smart-d1d36812-6717-4987-85ef-31e31c84a5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823452382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1823452382
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.1155821867
Short name T927
Test name
Test status
Simulation time 21385151013 ps
CPU time 26.3 seconds
Started Aug 14 05:00:17 PM PDT 24
Finished Aug 14 05:00:43 PM PDT 24
Peak memory 200652 kb
Host smart-ae319343-846e-4598-bfe6-873e1ebe091e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155821867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1155821867
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.153114577
Short name T646
Test name
Test status
Simulation time 185168811338 ps
CPU time 90.99 seconds
Started Aug 14 05:00:12 PM PDT 24
Finished Aug 14 05:01:44 PM PDT 24
Peak memory 200948 kb
Host smart-d030e6f0-94c4-4595-8679-55468ef87109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153114577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.153114577
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3831699908
Short name T896
Test name
Test status
Simulation time 36490168480 ps
CPU time 16.44 seconds
Started Aug 14 05:00:13 PM PDT 24
Finished Aug 14 05:00:30 PM PDT 24
Peak memory 200440 kb
Host smart-a97744a0-757f-4c13-a6d0-5e7d0e11521a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831699908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3831699908
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.2056281199
Short name T292
Test name
Test status
Simulation time 127435626016 ps
CPU time 512.81 seconds
Started Aug 14 05:00:11 PM PDT 24
Finished Aug 14 05:08:44 PM PDT 24
Peak memory 200976 kb
Host smart-46b1ee8c-1be5-4bb6-8d03-fd95eb430933
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2056281199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2056281199
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.174764520
Short name T20
Test name
Test status
Simulation time 9847318738 ps
CPU time 5.02 seconds
Started Aug 14 05:00:13 PM PDT 24
Finished Aug 14 05:00:18 PM PDT 24
Peak memory 199620 kb
Host smart-19a23e25-5759-48f6-b20c-11052181a21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174764520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.174764520
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.1914674988
Short name T565
Test name
Test status
Simulation time 186570081169 ps
CPU time 22.45 seconds
Started Aug 14 05:00:16 PM PDT 24
Finished Aug 14 05:00:39 PM PDT 24
Peak memory 201060 kb
Host smart-61542de0-0b11-4772-a70a-489f3b2fb734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914674988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1914674988
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.907769172
Short name T429
Test name
Test status
Simulation time 5102653637 ps
CPU time 276.94 seconds
Started Aug 14 05:00:13 PM PDT 24
Finished Aug 14 05:04:50 PM PDT 24
Peak memory 200848 kb
Host smart-1ca64d6c-8e63-495f-b77b-bee84e35d7ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=907769172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.907769172
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.4068482525
Short name T464
Test name
Test status
Simulation time 3902070529 ps
CPU time 37.55 seconds
Started Aug 14 05:00:14 PM PDT 24
Finished Aug 14 05:00:52 PM PDT 24
Peak memory 199236 kb
Host smart-480b13f6-9cb9-484f-a42f-92f66dc97e33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4068482525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.4068482525
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.579632872
Short name T136
Test name
Test status
Simulation time 22094689019 ps
CPU time 5.85 seconds
Started Aug 14 05:00:14 PM PDT 24
Finished Aug 14 05:00:20 PM PDT 24
Peak memory 200788 kb
Host smart-afe3b069-dad0-4064-a21e-e59cf0b82bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579632872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.579632872
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1011531660
Short name T274
Test name
Test status
Simulation time 5266735623 ps
CPU time 2.64 seconds
Started Aug 14 05:00:15 PM PDT 24
Finished Aug 14 05:00:18 PM PDT 24
Peak memory 197356 kb
Host smart-06d84ced-62c2-464a-b6f4-778470f6d104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011531660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1011531660
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.476004482
Short name T660
Test name
Test status
Simulation time 650255669 ps
CPU time 3.1 seconds
Started Aug 14 05:00:12 PM PDT 24
Finished Aug 14 05:00:15 PM PDT 24
Peak memory 200584 kb
Host smart-284fe51b-3f10-45c6-b0ae-e11be557a309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476004482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.476004482
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1022081929
Short name T913
Test name
Test status
Simulation time 407593685261 ps
CPU time 931.69 seconds
Started Aug 14 05:00:11 PM PDT 24
Finished Aug 14 05:15:43 PM PDT 24
Peak memory 209516 kb
Host smart-792f3726-a085-4d98-aa68-0578df12236f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022081929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1022081929
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.2195480297
Short name T78
Test name
Test status
Simulation time 1615448443 ps
CPU time 1.65 seconds
Started Aug 14 05:00:17 PM PDT 24
Finished Aug 14 05:00:19 PM PDT 24
Peak memory 198884 kb
Host smart-d4e16672-c7da-4142-9650-a399778dca69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195480297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2195480297
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2075926151
Short name T580
Test name
Test status
Simulation time 53485315940 ps
CPU time 93.8 seconds
Started Aug 14 05:00:12 PM PDT 24
Finished Aug 14 05:01:46 PM PDT 24
Peak memory 200964 kb
Host smart-27f2a8cc-913d-4bc2-883a-b1062fdab27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075926151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2075926151
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3132283249
Short name T133
Test name
Test status
Simulation time 36069869764 ps
CPU time 20.02 seconds
Started Aug 14 05:03:44 PM PDT 24
Finished Aug 14 05:04:04 PM PDT 24
Peak memory 200944 kb
Host smart-381d6de8-fe94-49a6-a871-0f57a3d51b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132283249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3132283249
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2442905838
Short name T905
Test name
Test status
Simulation time 106957307012 ps
CPU time 86.37 seconds
Started Aug 14 05:04:00 PM PDT 24
Finished Aug 14 05:05:26 PM PDT 24
Peak memory 200872 kb
Host smart-b26c8f0c-111e-4fb4-bc2f-e357f462e642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442905838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2442905838
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.170645063
Short name T233
Test name
Test status
Simulation time 30120894632 ps
CPU time 14.56 seconds
Started Aug 14 05:04:00 PM PDT 24
Finished Aug 14 05:04:14 PM PDT 24
Peak memory 200880 kb
Host smart-5e4240f3-cb56-48ae-aa58-4d78ebf10bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170645063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.170645063
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1069753010
Short name T996
Test name
Test status
Simulation time 65178373211 ps
CPU time 25.66 seconds
Started Aug 14 05:04:00 PM PDT 24
Finished Aug 14 05:04:26 PM PDT 24
Peak memory 200892 kb
Host smart-267b4fff-8dd3-4f7b-b2e6-e98697748a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069753010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1069753010
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.1227563196
Short name T1176
Test name
Test status
Simulation time 208376650789 ps
CPU time 41.23 seconds
Started Aug 14 05:04:02 PM PDT 24
Finished Aug 14 05:04:44 PM PDT 24
Peak memory 200916 kb
Host smart-ce9dbb6d-e6b7-42de-a596-a505815d8c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227563196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1227563196
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.4020054670
Short name T1054
Test name
Test status
Simulation time 54748922912 ps
CPU time 46.26 seconds
Started Aug 14 05:04:04 PM PDT 24
Finished Aug 14 05:04:50 PM PDT 24
Peak memory 200944 kb
Host smart-8f4b6f36-3a3c-4d23-a5e8-d0737de05434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020054670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.4020054670
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.1551283073
Short name T332
Test name
Test status
Simulation time 246323379417 ps
CPU time 180.13 seconds
Started Aug 14 05:04:01 PM PDT 24
Finished Aug 14 05:07:01 PM PDT 24
Peak memory 200872 kb
Host smart-73c1c8fb-5677-42cc-b7c9-2e6d1f03458b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551283073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.1551283073
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3020290833
Short name T313
Test name
Test status
Simulation time 76089745389 ps
CPU time 34.3 seconds
Started Aug 14 05:04:03 PM PDT 24
Finished Aug 14 05:04:38 PM PDT 24
Peak memory 200964 kb
Host smart-e626bed8-9702-4311-8a05-01caab2a981e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020290833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3020290833
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.4165022107
Short name T108
Test name
Test status
Simulation time 141556801395 ps
CPU time 213.06 seconds
Started Aug 14 05:04:00 PM PDT 24
Finished Aug 14 05:07:33 PM PDT 24
Peak memory 200904 kb
Host smart-7b4eabe6-3688-4a79-8bdd-1d959662be68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165022107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.4165022107
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.4118245930
Short name T607
Test name
Test status
Simulation time 13693592 ps
CPU time 0.55 seconds
Started Aug 14 04:58:57 PM PDT 24
Finished Aug 14 04:58:58 PM PDT 24
Peak memory 196204 kb
Host smart-9720c01e-838b-42eb-a2be-a945d6ac674d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118245930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.4118245930
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2638628773
Short name T306
Test name
Test status
Simulation time 88074788589 ps
CPU time 40.05 seconds
Started Aug 14 04:58:56 PM PDT 24
Finished Aug 14 04:59:37 PM PDT 24
Peak memory 200440 kb
Host smart-f5df6ee4-025c-49e5-901c-7ebe8da6971e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638628773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2638628773
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.2287726493
Short name T463
Test name
Test status
Simulation time 245044009267 ps
CPU time 205.96 seconds
Started Aug 14 04:58:59 PM PDT 24
Finished Aug 14 05:02:25 PM PDT 24
Peak memory 200864 kb
Host smart-67bcd964-447e-49ed-acdc-d0b52ad39d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287726493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2287726493
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_intr.3369945762
Short name T909
Test name
Test status
Simulation time 19922651370 ps
CPU time 4.48 seconds
Started Aug 14 04:58:57 PM PDT 24
Finished Aug 14 04:59:02 PM PDT 24
Peak memory 197888 kb
Host smart-537b2ff2-766e-4d80-9f86-87644b2e2fd9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369945762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3369945762
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.2772978689
Short name T740
Test name
Test status
Simulation time 264409089928 ps
CPU time 229.15 seconds
Started Aug 14 04:59:01 PM PDT 24
Finished Aug 14 05:02:50 PM PDT 24
Peak memory 200852 kb
Host smart-2a98ec71-4c3f-4459-8603-a146ae1d0adb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2772978689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2772978689
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.3255866932
Short name T986
Test name
Test status
Simulation time 899322561 ps
CPU time 1.98 seconds
Started Aug 14 04:58:59 PM PDT 24
Finished Aug 14 04:59:01 PM PDT 24
Peak memory 198300 kb
Host smart-43c483fa-4dfa-46cc-90f8-3abe4f02aa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255866932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3255866932
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.1747654460
Short name T531
Test name
Test status
Simulation time 61918074202 ps
CPU time 158.3 seconds
Started Aug 14 04:59:02 PM PDT 24
Finished Aug 14 05:01:40 PM PDT 24
Peak memory 200968 kb
Host smart-83cbd9cb-45e4-4558-8b1e-777229cc4e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747654460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1747654460
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.995631887
Short name T1148
Test name
Test status
Simulation time 16600150923 ps
CPU time 211.73 seconds
Started Aug 14 04:58:58 PM PDT 24
Finished Aug 14 05:02:30 PM PDT 24
Peak memory 200880 kb
Host smart-5fb9abcd-5d20-45b3-b692-4acc2519ad79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=995631887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.995631887
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.1093472332
Short name T460
Test name
Test status
Simulation time 1705087804 ps
CPU time 3.98 seconds
Started Aug 14 04:58:55 PM PDT 24
Finished Aug 14 04:59:00 PM PDT 24
Peak memory 199048 kb
Host smart-90db8869-6108-4ec8-beed-6c142e31712a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1093472332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1093472332
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1515373138
Short name T945
Test name
Test status
Simulation time 8215747703 ps
CPU time 8.93 seconds
Started Aug 14 04:58:57 PM PDT 24
Finished Aug 14 04:59:06 PM PDT 24
Peak memory 200852 kb
Host smart-90522355-95a0-4172-80be-b5f973b8c745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515373138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1515373138
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2111785076
Short name T752
Test name
Test status
Simulation time 45337578709 ps
CPU time 66.75 seconds
Started Aug 14 04:58:57 PM PDT 24
Finished Aug 14 05:00:03 PM PDT 24
Peak memory 197472 kb
Host smart-05fda200-2180-4256-ae85-cd15228d75ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111785076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2111785076
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2798215920
Short name T73
Test name
Test status
Simulation time 39633668 ps
CPU time 0.77 seconds
Started Aug 14 04:58:56 PM PDT 24
Finished Aug 14 04:58:56 PM PDT 24
Peak memory 218892 kb
Host smart-9626908c-0db7-4534-8da2-516268c49774
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798215920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2798215920
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2442746907
Short name T559
Test name
Test status
Simulation time 5810300654 ps
CPU time 20.55 seconds
Started Aug 14 04:58:57 PM PDT 24
Finished Aug 14 04:59:18 PM PDT 24
Peak memory 200792 kb
Host smart-229d24b6-3852-4fb7-ab4e-eedbc1dc26ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442746907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2442746907
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.2391471789
Short name T654
Test name
Test status
Simulation time 390623329410 ps
CPU time 923.65 seconds
Started Aug 14 04:58:58 PM PDT 24
Finished Aug 14 05:14:22 PM PDT 24
Peak memory 200972 kb
Host smart-e0cb0566-e6af-42d7-bb52-15bbc91e17fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391471789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2391471789
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1759010029
Short name T348
Test name
Test status
Simulation time 5917849568 ps
CPU time 43.67 seconds
Started Aug 14 04:58:59 PM PDT 24
Finished Aug 14 04:59:42 PM PDT 24
Peak memory 216776 kb
Host smart-3cd63f30-fdd1-4b0d-9c92-25a0cc5ca1cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759010029 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1759010029
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.2541747262
Short name T39
Test name
Test status
Simulation time 1000640790 ps
CPU time 4.71 seconds
Started Aug 14 04:58:59 PM PDT 24
Finished Aug 14 04:59:04 PM PDT 24
Peak memory 199480 kb
Host smart-7c18e94b-3bc8-4afc-bd50-0c4130cedf8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541747262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2541747262
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3489839433
Short name T1013
Test name
Test status
Simulation time 65902158436 ps
CPU time 27.99 seconds
Started Aug 14 04:58:56 PM PDT 24
Finished Aug 14 04:59:25 PM PDT 24
Peak memory 200960 kb
Host smart-517021b2-a996-4ea8-99ed-a07082987bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489839433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3489839433
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.2763751878
Short name T871
Test name
Test status
Simulation time 14620328 ps
CPU time 0.58 seconds
Started Aug 14 05:00:23 PM PDT 24
Finished Aug 14 05:00:24 PM PDT 24
Peak memory 196272 kb
Host smart-050da771-67a5-483e-a4e4-28a4c83402e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763751878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2763751878
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.393856319
Short name T1158
Test name
Test status
Simulation time 37291666313 ps
CPU time 28.16 seconds
Started Aug 14 05:00:23 PM PDT 24
Finished Aug 14 05:00:51 PM PDT 24
Peak memory 200872 kb
Host smart-41946102-07cd-49da-acef-9b15a056c2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393856319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.393856319
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2498473024
Short name T140
Test name
Test status
Simulation time 27907683595 ps
CPU time 45.16 seconds
Started Aug 14 05:00:22 PM PDT 24
Finished Aug 14 05:01:08 PM PDT 24
Peak memory 200844 kb
Host smart-09a6ee16-ffab-40c7-a44e-d16474bf13d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498473024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2498473024
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1801124705
Short name T351
Test name
Test status
Simulation time 41249159370 ps
CPU time 65.09 seconds
Started Aug 14 05:00:21 PM PDT 24
Finished Aug 14 05:01:27 PM PDT 24
Peak memory 200856 kb
Host smart-0cc96f84-4531-4093-891c-2a3076f8d4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801124705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1801124705
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.543016089
Short name T305
Test name
Test status
Simulation time 71353938865 ps
CPU time 69.51 seconds
Started Aug 14 05:00:24 PM PDT 24
Finished Aug 14 05:01:34 PM PDT 24
Peak memory 200924 kb
Host smart-ff908a57-7b45-4764-8498-82bc97968ee4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543016089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.543016089
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2325381138
Short name T576
Test name
Test status
Simulation time 173606823914 ps
CPU time 902.4 seconds
Started Aug 14 05:00:23 PM PDT 24
Finished Aug 14 05:15:26 PM PDT 24
Peak memory 201008 kb
Host smart-6e1cf811-2504-47e3-a60c-bd01f0d49263
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2325381138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2325381138
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1820739398
Short name T76
Test name
Test status
Simulation time 9080933640 ps
CPU time 6.55 seconds
Started Aug 14 05:00:24 PM PDT 24
Finished Aug 14 05:00:30 PM PDT 24
Peak memory 200196 kb
Host smart-873bce16-d879-45de-b587-74151da55117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820739398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1820739398
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.2558550778
Short name T759
Test name
Test status
Simulation time 34771304342 ps
CPU time 17.76 seconds
Started Aug 14 05:00:24 PM PDT 24
Finished Aug 14 05:00:42 PM PDT 24
Peak memory 200936 kb
Host smart-6c75069a-e51d-4644-961d-f74f635e6f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558550778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2558550778
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.3200335141
Short name T627
Test name
Test status
Simulation time 13152028563 ps
CPU time 718.47 seconds
Started Aug 14 05:00:24 PM PDT 24
Finished Aug 14 05:12:22 PM PDT 24
Peak memory 200892 kb
Host smart-52b32073-71ed-4c80-9f30-8e06eb8ef6b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3200335141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3200335141
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.3425127962
Short name T629
Test name
Test status
Simulation time 6404931977 ps
CPU time 62.72 seconds
Started Aug 14 05:00:24 PM PDT 24
Finished Aug 14 05:01:27 PM PDT 24
Peak memory 199092 kb
Host smart-90b248c9-09ed-4818-8853-293252190ab6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3425127962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3425127962
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1740335076
Short name T604
Test name
Test status
Simulation time 97555912566 ps
CPU time 48.51 seconds
Started Aug 14 05:00:22 PM PDT 24
Finished Aug 14 05:01:11 PM PDT 24
Peak memory 200820 kb
Host smart-822bf511-7436-4f7c-99db-c9adfbbb301e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740335076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1740335076
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.636521379
Short name T934
Test name
Test status
Simulation time 35039555597 ps
CPU time 12.23 seconds
Started Aug 14 05:00:22 PM PDT 24
Finished Aug 14 05:00:35 PM PDT 24
Peak memory 197656 kb
Host smart-43f7b56c-524d-4e1a-8be4-05741c1a75a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636521379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.636521379
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3822567349
Short name T1033
Test name
Test status
Simulation time 542255459 ps
CPU time 2.08 seconds
Started Aug 14 05:00:12 PM PDT 24
Finished Aug 14 05:00:15 PM PDT 24
Peak memory 199368 kb
Host smart-a8379921-177c-4aa5-b9e1-59882a4827cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822567349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3822567349
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.765714712
Short name T835
Test name
Test status
Simulation time 99285952316 ps
CPU time 95.51 seconds
Started Aug 14 05:00:23 PM PDT 24
Finished Aug 14 05:01:59 PM PDT 24
Peak memory 201056 kb
Host smart-6d9aeb90-a223-420b-bb10-e9f35f0854bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765714712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.765714712
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.2767633979
Short name T588
Test name
Test status
Simulation time 3986730946 ps
CPU time 24.75 seconds
Started Aug 14 05:00:24 PM PDT 24
Finished Aug 14 05:00:49 PM PDT 24
Peak memory 217352 kb
Host smart-ff5fa1d1-c2ff-4eda-bc94-b05752e9a1c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767633979 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.2767633979
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2453235
Short name T282
Test name
Test status
Simulation time 820386389 ps
CPU time 1.74 seconds
Started Aug 14 05:00:29 PM PDT 24
Finished Aug 14 05:00:31 PM PDT 24
Peak memory 200444 kb
Host smart-15cf4d9c-4fe9-4de8-8100-911307af25b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2453235
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3218127342
Short name T628
Test name
Test status
Simulation time 75760031589 ps
CPU time 29.44 seconds
Started Aug 14 05:00:24 PM PDT 24
Finished Aug 14 05:00:53 PM PDT 24
Peak memory 200964 kb
Host smart-49a0e6ca-6ce6-4428-807b-b040e7f03b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218127342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3218127342
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3646373792
Short name T201
Test name
Test status
Simulation time 104804039994 ps
CPU time 139.8 seconds
Started Aug 14 05:03:59 PM PDT 24
Finished Aug 14 05:06:19 PM PDT 24
Peak memory 200928 kb
Host smart-28e0bfa7-81ad-483d-b246-7343623d9d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646373792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3646373792
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1677298486
Short name T217
Test name
Test status
Simulation time 36217189224 ps
CPU time 58.16 seconds
Started Aug 14 05:04:02 PM PDT 24
Finished Aug 14 05:05:01 PM PDT 24
Peak memory 200964 kb
Host smart-e06d0efe-1f2f-43e4-b1ed-d52d281e4ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677298486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1677298486
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1984203403
Short name T219
Test name
Test status
Simulation time 19009465767 ps
CPU time 30.03 seconds
Started Aug 14 05:04:00 PM PDT 24
Finished Aug 14 05:04:31 PM PDT 24
Peak memory 200836 kb
Host smart-f3a1414a-b028-4738-a472-3a7ace238387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984203403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1984203403
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.58333384
Short name T1005
Test name
Test status
Simulation time 21082529156 ps
CPU time 26.42 seconds
Started Aug 14 05:04:00 PM PDT 24
Finished Aug 14 05:04:26 PM PDT 24
Peak memory 200980 kb
Host smart-7fd6db04-840d-44be-bece-77244b2f70c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58333384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.58333384
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3078796653
Short name T521
Test name
Test status
Simulation time 149611207104 ps
CPU time 255.15 seconds
Started Aug 14 05:04:00 PM PDT 24
Finished Aug 14 05:08:16 PM PDT 24
Peak memory 200956 kb
Host smart-8c205ebc-d059-406d-8810-17bcfefac830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078796653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3078796653
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.952666175
Short name T1
Test name
Test status
Simulation time 56349838006 ps
CPU time 24.22 seconds
Started Aug 14 05:04:01 PM PDT 24
Finished Aug 14 05:04:26 PM PDT 24
Peak memory 200856 kb
Host smart-1c46b68d-9200-4005-a285-53ca109b4541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952666175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.952666175
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.492219458
Short name T1074
Test name
Test status
Simulation time 46046190 ps
CPU time 0.53 seconds
Started Aug 14 05:00:24 PM PDT 24
Finished Aug 14 05:00:24 PM PDT 24
Peak memory 196268 kb
Host smart-26bac05f-a40a-4f15-a0d0-ae1c5cbb4e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492219458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.492219458
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2021513130
Short name T36
Test name
Test status
Simulation time 17581318274 ps
CPU time 28.96 seconds
Started Aug 14 05:00:22 PM PDT 24
Finished Aug 14 05:00:52 PM PDT 24
Peak memory 200960 kb
Host smart-efc522dd-e401-4151-96d9-8b78a6e6eb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021513130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2021513130
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.546598742
Short name T762
Test name
Test status
Simulation time 181157276205 ps
CPU time 18.16 seconds
Started Aug 14 05:00:24 PM PDT 24
Finished Aug 14 05:00:43 PM PDT 24
Peak memory 200980 kb
Host smart-3ff25784-7049-4cae-af89-81dbec4abe9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546598742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.546598742
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2648823584
Short name T1038
Test name
Test status
Simulation time 87290250703 ps
CPU time 44.99 seconds
Started Aug 14 05:00:24 PM PDT 24
Finished Aug 14 05:01:09 PM PDT 24
Peak memory 200924 kb
Host smart-026b16e1-dbeb-488c-a155-6fb450eb5152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648823584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2648823584
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.4219636298
Short name T388
Test name
Test status
Simulation time 22225671944 ps
CPU time 18 seconds
Started Aug 14 05:00:24 PM PDT 24
Finished Aug 14 05:00:42 PM PDT 24
Peak memory 199176 kb
Host smart-5ebec575-9700-47ad-841b-21d0f8095270
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219636298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.4219636298
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.2416532056
Short name T1080
Test name
Test status
Simulation time 54784460841 ps
CPU time 304.99 seconds
Started Aug 14 05:00:24 PM PDT 24
Finished Aug 14 05:05:29 PM PDT 24
Peak memory 200896 kb
Host smart-3bf89b6c-2b86-47e6-ace6-ea53ae6bc373
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2416532056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2416532056
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2218088205
Short name T359
Test name
Test status
Simulation time 5510197790 ps
CPU time 5.89 seconds
Started Aug 14 05:00:26 PM PDT 24
Finished Aug 14 05:00:32 PM PDT 24
Peak memory 200200 kb
Host smart-d2c876b0-6016-4528-8996-617f64fa5dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218088205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2218088205
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.958996174
Short name T781
Test name
Test status
Simulation time 19444369315 ps
CPU time 16.21 seconds
Started Aug 14 05:00:22 PM PDT 24
Finished Aug 14 05:00:38 PM PDT 24
Peak memory 200952 kb
Host smart-e8863832-5a22-4377-8de1-277163f77357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958996174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.958996174
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.394508254
Short name T347
Test name
Test status
Simulation time 19862656982 ps
CPU time 282.37 seconds
Started Aug 14 05:00:26 PM PDT 24
Finished Aug 14 05:05:09 PM PDT 24
Peak memory 200912 kb
Host smart-d32a4d29-4eec-4ee8-a98d-38810cee3116
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=394508254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.394508254
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.1140926079
Short name T590
Test name
Test status
Simulation time 4830200985 ps
CPU time 20.26 seconds
Started Aug 14 05:00:26 PM PDT 24
Finished Aug 14 05:00:46 PM PDT 24
Peak memory 198712 kb
Host smart-4323077a-31e9-48f6-abda-01e69c1bc2df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1140926079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1140926079
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.3629416043
Short name T638
Test name
Test status
Simulation time 168559589102 ps
CPU time 553.72 seconds
Started Aug 14 05:00:24 PM PDT 24
Finished Aug 14 05:09:38 PM PDT 24
Peak memory 200908 kb
Host smart-d7d56af5-6df0-4302-8998-e3f0d79acb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629416043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3629416043
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1214552448
Short name T970
Test name
Test status
Simulation time 1301429418 ps
CPU time 2.78 seconds
Started Aug 14 05:00:23 PM PDT 24
Finished Aug 14 05:00:26 PM PDT 24
Peak memory 196448 kb
Host smart-b33a91a0-247f-4999-9ba3-a09e1f7719c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214552448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1214552448
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3481793336
Short name T376
Test name
Test status
Simulation time 911705424 ps
CPU time 2.03 seconds
Started Aug 14 05:00:22 PM PDT 24
Finished Aug 14 05:00:24 PM PDT 24
Peak memory 199256 kb
Host smart-2e46e88e-7be3-4307-b140-4479bb1b9266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481793336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3481793336
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.3101540573
Short name T743
Test name
Test status
Simulation time 8741092334 ps
CPU time 10.88 seconds
Started Aug 14 05:00:23 PM PDT 24
Finished Aug 14 05:00:34 PM PDT 24
Peak memory 200880 kb
Host smart-6f4a5106-0b8a-4d1a-a82e-22da8c46d7c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101540573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.3101540573
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.332416521
Short name T730
Test name
Test status
Simulation time 4038000042 ps
CPU time 55.98 seconds
Started Aug 14 05:00:25 PM PDT 24
Finished Aug 14 05:01:21 PM PDT 24
Peak memory 209220 kb
Host smart-9d456a01-7a35-4a32-88a1-fb9c11925c72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332416521 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.332416521
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.1371993902
Short name T465
Test name
Test status
Simulation time 1128844885 ps
CPU time 1.29 seconds
Started Aug 14 05:00:23 PM PDT 24
Finished Aug 14 05:00:24 PM PDT 24
Peak memory 199308 kb
Host smart-71e8372b-a6eb-4ad7-8138-22d0d3ce9cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371993902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1371993902
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2587740256
Short name T240
Test name
Test status
Simulation time 101192623514 ps
CPU time 92.29 seconds
Started Aug 14 05:00:23 PM PDT 24
Finished Aug 14 05:01:56 PM PDT 24
Peak memory 200892 kb
Host smart-db1baebe-7b38-4121-a4cc-87111309a94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587740256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2587740256
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3335307139
Short name T1031
Test name
Test status
Simulation time 24364256732 ps
CPU time 35.56 seconds
Started Aug 14 05:04:00 PM PDT 24
Finished Aug 14 05:04:35 PM PDT 24
Peak memory 200900 kb
Host smart-b9ac6999-bb2e-4cfa-b7f7-3f0b1c82743b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335307139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3335307139
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.4221760146
Short name T461
Test name
Test status
Simulation time 53043733719 ps
CPU time 86.52 seconds
Started Aug 14 05:04:01 PM PDT 24
Finished Aug 14 05:05:28 PM PDT 24
Peak memory 201108 kb
Host smart-00fad97e-49ad-4c49-be19-a73be002333d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221760146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.4221760146
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2125582978
Short name T301
Test name
Test status
Simulation time 63353536964 ps
CPU time 69.74 seconds
Started Aug 14 05:04:00 PM PDT 24
Finished Aug 14 05:05:10 PM PDT 24
Peak memory 200900 kb
Host smart-e4f942c3-483f-4ea8-864d-2f9677f6b2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125582978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2125582978
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.1671666989
Short name T254
Test name
Test status
Simulation time 20106930647 ps
CPU time 8.31 seconds
Started Aug 14 05:04:00 PM PDT 24
Finished Aug 14 05:04:08 PM PDT 24
Peak memory 200592 kb
Host smart-237e9ffa-381b-43ff-a0d8-df160f025a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671666989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.1671666989
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.3955413280
Short name T442
Test name
Test status
Simulation time 118584011433 ps
CPU time 40.84 seconds
Started Aug 14 05:04:01 PM PDT 24
Finished Aug 14 05:04:42 PM PDT 24
Peak memory 200904 kb
Host smart-4a7d57e7-2f5f-4aef-80f3-d0fbdd447ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955413280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3955413280
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.787007311
Short name T933
Test name
Test status
Simulation time 44527382924 ps
CPU time 96.07 seconds
Started Aug 14 05:04:00 PM PDT 24
Finished Aug 14 05:05:36 PM PDT 24
Peak memory 200916 kb
Host smart-baf60031-65bf-4d6b-97a9-bf85169ee9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787007311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.787007311
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1777851763
Short name T711
Test name
Test status
Simulation time 182202546175 ps
CPU time 145.44 seconds
Started Aug 14 05:04:00 PM PDT 24
Finished Aug 14 05:06:26 PM PDT 24
Peak memory 200956 kb
Host smart-ccae93e9-678e-44b8-96d2-c91dee00bbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777851763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1777851763
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1260310102
Short name T1087
Test name
Test status
Simulation time 167606822148 ps
CPU time 71.17 seconds
Started Aug 14 05:04:04 PM PDT 24
Finished Aug 14 05:05:15 PM PDT 24
Peak memory 200968 kb
Host smart-f695e3b7-a263-49d2-898c-dfcc62a2baf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260310102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1260310102
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.1355679676
Short name T1007
Test name
Test status
Simulation time 67711198345 ps
CPU time 138.76 seconds
Started Aug 14 05:04:01 PM PDT 24
Finished Aug 14 05:06:19 PM PDT 24
Peak memory 200880 kb
Host smart-17e2cfb2-c0e9-4f5f-9714-384138bb2667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355679676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1355679676
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1715476397
Short name T1085
Test name
Test status
Simulation time 40883645360 ps
CPU time 59.38 seconds
Started Aug 14 05:04:02 PM PDT 24
Finished Aug 14 05:05:01 PM PDT 24
Peak memory 200584 kb
Host smart-197d6b8b-800b-4025-b8c2-56fb8db4efbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715476397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1715476397
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3643136840
Short name T609
Test name
Test status
Simulation time 30799924 ps
CPU time 0.58 seconds
Started Aug 14 05:00:37 PM PDT 24
Finished Aug 14 05:00:38 PM PDT 24
Peak memory 196196 kb
Host smart-bc3b53b0-0b2b-47ee-b6f3-c362bddafa23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643136840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3643136840
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.881863394
Short name T998
Test name
Test status
Simulation time 39630509267 ps
CPU time 18.29 seconds
Started Aug 14 05:00:35 PM PDT 24
Finished Aug 14 05:00:53 PM PDT 24
Peak memory 200944 kb
Host smart-77a68806-f9a5-4b17-a069-e4e57d54e814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881863394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.881863394
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2784683541
Short name T726
Test name
Test status
Simulation time 209286072630 ps
CPU time 203.23 seconds
Started Aug 14 05:00:34 PM PDT 24
Finished Aug 14 05:03:58 PM PDT 24
Peak memory 201048 kb
Host smart-6647012b-9b82-4dd9-a2a3-a7e445b91d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784683541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2784683541
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2288681102
Short name T1053
Test name
Test status
Simulation time 20502016529 ps
CPU time 31.41 seconds
Started Aug 14 05:00:35 PM PDT 24
Finished Aug 14 05:01:06 PM PDT 24
Peak memory 200956 kb
Host smart-e681923a-e00b-449f-bad4-4bf4aa387de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288681102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2288681102
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.2247089505
Short name T458
Test name
Test status
Simulation time 18060731511 ps
CPU time 11.7 seconds
Started Aug 14 05:00:36 PM PDT 24
Finished Aug 14 05:00:47 PM PDT 24
Peak memory 200696 kb
Host smart-267aac1b-9ff2-41da-a3f8-5c771ce9eb1c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247089505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2247089505
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_loopback.1634686616
Short name T368
Test name
Test status
Simulation time 6439285662 ps
CPU time 10.9 seconds
Started Aug 14 05:00:35 PM PDT 24
Finished Aug 14 05:00:46 PM PDT 24
Peak memory 200364 kb
Host smart-dc3b9ae4-bedc-4710-9d11-ee415e49878f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634686616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1634686616
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.2102848182
Short name T768
Test name
Test status
Simulation time 137771447269 ps
CPU time 97.23 seconds
Started Aug 14 05:00:33 PM PDT 24
Finished Aug 14 05:02:11 PM PDT 24
Peak memory 209336 kb
Host smart-95896dbe-3b21-4769-9c62-273809b6638f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102848182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2102848182
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.869323446
Short name T824
Test name
Test status
Simulation time 13216618911 ps
CPU time 157.74 seconds
Started Aug 14 05:00:35 PM PDT 24
Finished Aug 14 05:03:13 PM PDT 24
Peak memory 200972 kb
Host smart-c1a4974e-7b56-4188-b659-27fd61bc964e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=869323446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.869323446
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.903941173
Short name T882
Test name
Test status
Simulation time 4649693816 ps
CPU time 10.11 seconds
Started Aug 14 05:00:34 PM PDT 24
Finished Aug 14 05:00:45 PM PDT 24
Peak memory 199664 kb
Host smart-af7805cc-fb3d-4ac4-a907-b8967a46a702
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=903941173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.903941173
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2276878076
Short name T477
Test name
Test status
Simulation time 31197732133 ps
CPU time 49.15 seconds
Started Aug 14 05:00:37 PM PDT 24
Finished Aug 14 05:01:26 PM PDT 24
Peak memory 200900 kb
Host smart-d860c3cc-9ff3-45fb-9c5a-43d1137556f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276878076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2276878076
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.3746450027
Short name T802
Test name
Test status
Simulation time 3929107401 ps
CPU time 7.06 seconds
Started Aug 14 05:00:37 PM PDT 24
Finished Aug 14 05:00:44 PM PDT 24
Peak memory 197040 kb
Host smart-73b2a62e-659c-42e3-af6d-946f8aba20b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746450027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3746450027
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.115861203
Short name T535
Test name
Test status
Simulation time 278304389 ps
CPU time 0.95 seconds
Started Aug 14 05:00:23 PM PDT 24
Finished Aug 14 05:00:24 PM PDT 24
Peak memory 199180 kb
Host smart-c45baa25-55b8-43c9-8c29-70e16614ddab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115861203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.115861203
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.4061847077
Short name T1027
Test name
Test status
Simulation time 1412330152 ps
CPU time 16.93 seconds
Started Aug 14 05:00:37 PM PDT 24
Finished Aug 14 05:00:54 PM PDT 24
Peak memory 200964 kb
Host smart-c737131e-fc6b-4a14-95a1-538e7c2ce8d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061847077 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.4061847077
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.1370721660
Short name T457
Test name
Test status
Simulation time 1123891065 ps
CPU time 1.66 seconds
Started Aug 14 05:00:34 PM PDT 24
Finished Aug 14 05:00:36 PM PDT 24
Peak memory 199204 kb
Host smart-3ae79d7c-7b9d-4b14-8186-bee9c4e91f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370721660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1370721660
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3762669660
Short name T958
Test name
Test status
Simulation time 105999524974 ps
CPU time 156.22 seconds
Started Aug 14 05:03:59 PM PDT 24
Finished Aug 14 05:06:36 PM PDT 24
Peak memory 200860 kb
Host smart-4eccfc24-ade1-4c81-ac79-7820f20078d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762669660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3762669660
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3709069571
Short name T940
Test name
Test status
Simulation time 9165912143 ps
CPU time 14.05 seconds
Started Aug 14 05:04:03 PM PDT 24
Finished Aug 14 05:04:17 PM PDT 24
Peak memory 200964 kb
Host smart-3b8576fa-1dee-4f3b-94b3-df19944bc098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709069571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3709069571
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.770541619
Short name T649
Test name
Test status
Simulation time 134639148331 ps
CPU time 191.94 seconds
Started Aug 14 05:04:02 PM PDT 24
Finished Aug 14 05:07:14 PM PDT 24
Peak memory 200892 kb
Host smart-cd8558c5-edf2-4160-907e-607f0d4941a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770541619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.770541619
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3771476728
Short name T1105
Test name
Test status
Simulation time 58581785049 ps
CPU time 24.88 seconds
Started Aug 14 05:03:59 PM PDT 24
Finished Aug 14 05:04:24 PM PDT 24
Peak memory 200868 kb
Host smart-ca2206a9-59ca-439e-a1ba-42c72c76fe53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771476728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3771476728
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2480561729
Short name T131
Test name
Test status
Simulation time 87822538087 ps
CPU time 39.51 seconds
Started Aug 14 05:04:01 PM PDT 24
Finished Aug 14 05:04:41 PM PDT 24
Peak memory 200908 kb
Host smart-b2e20c12-556a-49bd-9aae-15b6cf34e486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480561729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2480561729
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2504152870
Short name T202
Test name
Test status
Simulation time 93122178523 ps
CPU time 209.14 seconds
Started Aug 14 05:04:02 PM PDT 24
Finished Aug 14 05:07:31 PM PDT 24
Peak memory 200956 kb
Host smart-8d6721e3-66db-41e2-b1a6-cb6a1a2ace44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504152870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2504152870
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1602444406
Short name T106
Test name
Test status
Simulation time 20951502450 ps
CPU time 37.57 seconds
Started Aug 14 05:04:02 PM PDT 24
Finished Aug 14 05:04:39 PM PDT 24
Peak memory 200880 kb
Host smart-3a6ccf50-8d01-4b66-b858-1f7396e1bd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602444406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1602444406
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.76327223
Short name T361
Test name
Test status
Simulation time 15566064 ps
CPU time 0.57 seconds
Started Aug 14 05:00:34 PM PDT 24
Finished Aug 14 05:00:35 PM PDT 24
Peak memory 196484 kb
Host smart-f9cc5cfd-6b7a-467f-ba60-d383144e0162
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76327223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.76327223
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.3305743820
Short name T1037
Test name
Test status
Simulation time 84284651825 ps
CPU time 212.78 seconds
Started Aug 14 05:00:36 PM PDT 24
Finished Aug 14 05:04:09 PM PDT 24
Peak memory 200864 kb
Host smart-60f3f65d-3c46-4e37-92b2-ffaf7d6055ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305743820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3305743820
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.1971524552
Short name T1026
Test name
Test status
Simulation time 323305523981 ps
CPU time 31.93 seconds
Started Aug 14 05:00:36 PM PDT 24
Finished Aug 14 05:01:08 PM PDT 24
Peak memory 200608 kb
Host smart-b6226c48-489e-480e-a8a9-9208b2779e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971524552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.1971524552
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.692117986
Short name T241
Test name
Test status
Simulation time 56239317597 ps
CPU time 44.79 seconds
Started Aug 14 05:00:35 PM PDT 24
Finished Aug 14 05:01:20 PM PDT 24
Peak memory 200976 kb
Host smart-6d5d4c94-785a-4e96-84d0-028dd87bfa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692117986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.692117986
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.2689299443
Short name T746
Test name
Test status
Simulation time 16959089182 ps
CPU time 22.97 seconds
Started Aug 14 05:00:35 PM PDT 24
Finished Aug 14 05:00:58 PM PDT 24
Peak memory 198132 kb
Host smart-6f430e6c-70f9-4007-980e-1986ecf90efa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689299443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2689299443
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1187409764
Short name T1088
Test name
Test status
Simulation time 83715197040 ps
CPU time 218.88 seconds
Started Aug 14 05:00:36 PM PDT 24
Finished Aug 14 05:04:15 PM PDT 24
Peak memory 200888 kb
Host smart-a5acd40a-067a-4969-957e-25413232d4eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1187409764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1187409764
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.2471845710
Short name T697
Test name
Test status
Simulation time 9768426611 ps
CPU time 16.66 seconds
Started Aug 14 05:00:38 PM PDT 24
Finished Aug 14 05:00:54 PM PDT 24
Peak memory 200940 kb
Host smart-d43c8db0-a299-4b7f-8b54-33b05d70f82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471845710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2471845710
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1016916436
Short name T923
Test name
Test status
Simulation time 98825781984 ps
CPU time 14.31 seconds
Started Aug 14 05:00:34 PM PDT 24
Finished Aug 14 05:00:49 PM PDT 24
Peak memory 196564 kb
Host smart-cd4579d3-4193-4b56-8637-85909b990121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016916436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1016916436
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.66394288
Short name T310
Test name
Test status
Simulation time 19086993502 ps
CPU time 263.34 seconds
Started Aug 14 05:00:37 PM PDT 24
Finished Aug 14 05:05:00 PM PDT 24
Peak memory 200940 kb
Host smart-63666df6-4fea-4d31-9755-ee447491b63b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=66394288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.66394288
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1634256779
Short name T708
Test name
Test status
Simulation time 6826126910 ps
CPU time 4.63 seconds
Started Aug 14 05:00:35 PM PDT 24
Finished Aug 14 05:00:40 PM PDT 24
Peak memory 199308 kb
Host smart-4c0127e6-f6a5-442c-b678-7d34ef7f932e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1634256779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1634256779
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.2614971102
Short name T150
Test name
Test status
Simulation time 122184025238 ps
CPU time 13.36 seconds
Started Aug 14 05:00:39 PM PDT 24
Finished Aug 14 05:00:53 PM PDT 24
Peak memory 201012 kb
Host smart-60948858-bae6-4f5a-882a-aeee5af99d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614971102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2614971102
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.411281475
Short name T459
Test name
Test status
Simulation time 1683438926 ps
CPU time 1.98 seconds
Started Aug 14 05:00:35 PM PDT 24
Finished Aug 14 05:00:37 PM PDT 24
Peak memory 196440 kb
Host smart-10655314-02a2-4d82-a434-691de3546110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411281475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.411281475
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1395387175
Short name T937
Test name
Test status
Simulation time 809181173 ps
CPU time 3.13 seconds
Started Aug 14 05:00:36 PM PDT 24
Finished Aug 14 05:00:40 PM PDT 24
Peak memory 199836 kb
Host smart-1bbfa08f-df80-480d-8663-ee0bfda6efac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395387175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1395387175
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.2129949292
Short name T1169
Test name
Test status
Simulation time 450909220023 ps
CPU time 923.67 seconds
Started Aug 14 05:00:38 PM PDT 24
Finished Aug 14 05:16:02 PM PDT 24
Peak memory 201016 kb
Host smart-89451978-93b6-4bb4-a270-7d498f337f8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129949292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2129949292
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.2984988116
Short name T1022
Test name
Test status
Simulation time 9809139584 ps
CPU time 31.53 seconds
Started Aug 14 05:00:35 PM PDT 24
Finished Aug 14 05:01:07 PM PDT 24
Peak memory 209472 kb
Host smart-77133997-b7af-46c6-a667-4054c8a1da35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984988116 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2984988116
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1168820400
Short name T390
Test name
Test status
Simulation time 2308103153 ps
CPU time 2.12 seconds
Started Aug 14 05:00:34 PM PDT 24
Finished Aug 14 05:00:36 PM PDT 24
Peak memory 200844 kb
Host smart-fb7ce6c9-4c47-4ce7-b155-1773e08e8f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168820400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1168820400
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1501338629
Short name T853
Test name
Test status
Simulation time 45910628742 ps
CPU time 32.5 seconds
Started Aug 14 05:00:35 PM PDT 24
Finished Aug 14 05:01:08 PM PDT 24
Peak memory 200876 kb
Host smart-0e36b4bd-6cce-4db8-a96f-6ea1de230a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501338629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1501338629
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2002395732
Short name T185
Test name
Test status
Simulation time 80238252272 ps
CPU time 19.35 seconds
Started Aug 14 05:04:05 PM PDT 24
Finished Aug 14 05:04:24 PM PDT 24
Peak memory 200960 kb
Host smart-a83df5db-c762-4551-80c6-b80322c3162f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002395732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2002395732
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3001353202
Short name T287
Test name
Test status
Simulation time 71679453053 ps
CPU time 32.67 seconds
Started Aug 14 05:04:05 PM PDT 24
Finished Aug 14 05:04:37 PM PDT 24
Peak memory 200968 kb
Host smart-1719e333-05b7-409a-a587-2916142b3130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001353202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3001353202
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.1500683205
Short name T1099
Test name
Test status
Simulation time 36351638601 ps
CPU time 26.72 seconds
Started Aug 14 05:04:04 PM PDT 24
Finished Aug 14 05:04:31 PM PDT 24
Peak memory 200824 kb
Host smart-d37b84c7-9089-4df9-bacc-2bc8deff04b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500683205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1500683205
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.462589622
Short name T353
Test name
Test status
Simulation time 54388434196 ps
CPU time 76.56 seconds
Started Aug 14 05:04:02 PM PDT 24
Finished Aug 14 05:05:18 PM PDT 24
Peak memory 200728 kb
Host smart-7370000c-d9e8-4b2c-8a2a-a6a12f0bc910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462589622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.462589622
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.1778793684
Short name T197
Test name
Test status
Simulation time 15574575569 ps
CPU time 37.02 seconds
Started Aug 14 05:04:03 PM PDT 24
Finished Aug 14 05:04:40 PM PDT 24
Peak memory 200896 kb
Host smart-6bdbbbd2-5301-45e2-b3b8-0de4b030441e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778793684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1778793684
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.2530912807
Short name T1140
Test name
Test status
Simulation time 84982767796 ps
CPU time 125.02 seconds
Started Aug 14 05:04:04 PM PDT 24
Finished Aug 14 05:06:10 PM PDT 24
Peak memory 200904 kb
Host smart-72b315a7-4032-4d95-bae2-0d86621fc008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530912807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2530912807
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.18977049
Short name T952
Test name
Test status
Simulation time 56627691603 ps
CPU time 19.34 seconds
Started Aug 14 05:04:09 PM PDT 24
Finished Aug 14 05:04:28 PM PDT 24
Peak memory 200456 kb
Host smart-c8d36a2f-ca0c-4dd9-a0a6-c4889cfebf5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18977049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.18977049
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.2537183733
Short name T975
Test name
Test status
Simulation time 182197849105 ps
CPU time 236.98 seconds
Started Aug 14 05:04:02 PM PDT 24
Finished Aug 14 05:08:00 PM PDT 24
Peak memory 200772 kb
Host smart-870708e3-4266-4d84-818d-d62a281b9450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537183733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2537183733
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2354994609
Short name T173
Test name
Test status
Simulation time 336215846130 ps
CPU time 30.47 seconds
Started Aug 14 05:04:03 PM PDT 24
Finished Aug 14 05:04:34 PM PDT 24
Peak memory 200900 kb
Host smart-2fe8ff89-37b6-4617-b4ca-34163ff29208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354994609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2354994609
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3935008485
Short name T652
Test name
Test status
Simulation time 29889270 ps
CPU time 0.55 seconds
Started Aug 14 05:00:46 PM PDT 24
Finished Aug 14 05:00:47 PM PDT 24
Peak memory 195148 kb
Host smart-8469cc1a-be58-4f7a-9701-d2683349d948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935008485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3935008485
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1106801655
Short name T917
Test name
Test status
Simulation time 245814632656 ps
CPU time 409.37 seconds
Started Aug 14 05:00:37 PM PDT 24
Finished Aug 14 05:07:27 PM PDT 24
Peak memory 200884 kb
Host smart-e1b0c72d-9ac8-4beb-9cc5-89ac30e83c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106801655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1106801655
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.4134707768
Short name T294
Test name
Test status
Simulation time 77858824813 ps
CPU time 85.92 seconds
Started Aug 14 05:00:38 PM PDT 24
Finished Aug 14 05:02:04 PM PDT 24
Peak memory 200896 kb
Host smart-40c9cc15-1568-4170-848b-301d8b8be080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134707768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.4134707768
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.4278518895
Short name T218
Test name
Test status
Simulation time 41433931231 ps
CPU time 28.59 seconds
Started Aug 14 05:00:33 PM PDT 24
Finished Aug 14 05:01:02 PM PDT 24
Peak memory 200636 kb
Host smart-e445431a-862b-44bc-8fd6-19dbcbf2c706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278518895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.4278518895
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3395590481
Short name T302
Test name
Test status
Simulation time 27738599363 ps
CPU time 43.12 seconds
Started Aug 14 05:00:44 PM PDT 24
Finished Aug 14 05:01:27 PM PDT 24
Peak memory 199984 kb
Host smart-ef9fdc73-4bd7-4541-befc-46befe406b9d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395590481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3395590481
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1541504279
Short name T703
Test name
Test status
Simulation time 103453129782 ps
CPU time 651.04 seconds
Started Aug 14 05:00:46 PM PDT 24
Finished Aug 14 05:11:37 PM PDT 24
Peak memory 200904 kb
Host smart-1e862271-d975-461a-94d8-bd32a09e4b83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1541504279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1541504279
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.2447389326
Short name T344
Test name
Test status
Simulation time 1884347605 ps
CPU time 2.3 seconds
Started Aug 14 05:00:46 PM PDT 24
Finished Aug 14 05:00:48 PM PDT 24
Peak memory 198412 kb
Host smart-4b6f9b5a-2182-4f73-891b-1ab3c7c0e01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447389326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2447389326
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3287772331
Short name T954
Test name
Test status
Simulation time 4261463248 ps
CPU time 17.88 seconds
Started Aug 14 05:00:37 PM PDT 24
Finished Aug 14 05:00:55 PM PDT 24
Peak memory 199368 kb
Host smart-25a63a9d-706a-4193-8ef0-2033d7b41ba7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3287772331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3287772331
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.3506375383
Short name T633
Test name
Test status
Simulation time 55629639551 ps
CPU time 93.24 seconds
Started Aug 14 05:00:44 PM PDT 24
Finished Aug 14 05:02:17 PM PDT 24
Peak memory 200932 kb
Host smart-0be51329-c77b-4403-9bc4-86ce2038be0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506375383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3506375383
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.896687206
Short name T423
Test name
Test status
Simulation time 47054256526 ps
CPU time 62.89 seconds
Started Aug 14 05:00:34 PM PDT 24
Finished Aug 14 05:01:37 PM PDT 24
Peak memory 196940 kb
Host smart-2f708e4a-7b73-4caf-aaf6-35892221fb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896687206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.896687206
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2293689970
Short name T263
Test name
Test status
Simulation time 279707731 ps
CPU time 1.17 seconds
Started Aug 14 05:00:35 PM PDT 24
Finished Aug 14 05:00:36 PM PDT 24
Peak memory 199556 kb
Host smart-947055de-f0e9-4fcc-8424-c862b6ee8941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293689970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2293689970
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.1794554520
Short name T1143
Test name
Test status
Simulation time 646657191399 ps
CPU time 1338.22 seconds
Started Aug 14 05:00:46 PM PDT 24
Finished Aug 14 05:23:05 PM PDT 24
Peak memory 209340 kb
Host smart-ea31e3e4-df04-42bc-a119-617a692fffaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794554520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1794554520
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3142402266
Short name T454
Test name
Test status
Simulation time 12483653492 ps
CPU time 52.67 seconds
Started Aug 14 05:00:43 PM PDT 24
Finished Aug 14 05:01:36 PM PDT 24
Peak memory 209156 kb
Host smart-d711cd13-ea9a-456a-bcd4-21ec904f3e9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142402266 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3142402266
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2300512991
Short name T991
Test name
Test status
Simulation time 7414584216 ps
CPU time 7.45 seconds
Started Aug 14 05:00:44 PM PDT 24
Finished Aug 14 05:00:52 PM PDT 24
Peak memory 200896 kb
Host smart-4f4db0d3-5adb-42c2-9e5e-38c4f08c85a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300512991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2300512991
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.4275656004
Short name T266
Test name
Test status
Simulation time 153099904166 ps
CPU time 131.13 seconds
Started Aug 14 05:00:38 PM PDT 24
Finished Aug 14 05:02:49 PM PDT 24
Peak memory 200884 kb
Host smart-c2afaffd-a5d6-4a03-82b7-a007b6130a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275656004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.4275656004
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2627760404
Short name T1121
Test name
Test status
Simulation time 104692898345 ps
CPU time 29.21 seconds
Started Aug 14 05:04:05 PM PDT 24
Finished Aug 14 05:04:34 PM PDT 24
Peak memory 200908 kb
Host smart-d9e1a11b-f538-43c9-a1ff-3d784d32cee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627760404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2627760404
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1469192182
Short name T1165
Test name
Test status
Simulation time 18105920583 ps
CPU time 27.53 seconds
Started Aug 14 05:04:06 PM PDT 24
Finished Aug 14 05:04:34 PM PDT 24
Peak memory 200868 kb
Host smart-b6909a48-9daf-4cec-97b7-ef7e60c3892a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469192182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1469192182
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1399728708
Short name T688
Test name
Test status
Simulation time 82990205005 ps
CPU time 34.56 seconds
Started Aug 14 05:04:06 PM PDT 24
Finished Aug 14 05:04:41 PM PDT 24
Peak memory 200892 kb
Host smart-db782cc9-ac66-485d-87b4-3048a23e5604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399728708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1399728708
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2125559267
Short name T503
Test name
Test status
Simulation time 58803851312 ps
CPU time 93.33 seconds
Started Aug 14 05:04:04 PM PDT 24
Finished Aug 14 05:05:37 PM PDT 24
Peak memory 200956 kb
Host smart-634d46d0-0db7-4aec-b80d-4de806a764f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125559267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2125559267
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.3106672799
Short name T1147
Test name
Test status
Simulation time 129445680409 ps
CPU time 11.43 seconds
Started Aug 14 05:04:03 PM PDT 24
Finished Aug 14 05:04:15 PM PDT 24
Peak memory 199916 kb
Host smart-27fd3563-f3a5-4eb6-9f33-63eed0c7e649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106672799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3106672799
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.241315151
Short name T239
Test name
Test status
Simulation time 24784683627 ps
CPU time 43.51 seconds
Started Aug 14 05:04:05 PM PDT 24
Finished Aug 14 05:04:49 PM PDT 24
Peak memory 200892 kb
Host smart-b6aa0252-73db-43c1-b0f9-b847000bdb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241315151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.241315151
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1373300619
Short name T211
Test name
Test status
Simulation time 122478062835 ps
CPU time 142.45 seconds
Started Aug 14 05:04:04 PM PDT 24
Finished Aug 14 05:06:27 PM PDT 24
Peak memory 200864 kb
Host smart-ae590089-3da5-4509-8856-f68287994d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373300619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1373300619
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.4247792872
Short name T747
Test name
Test status
Simulation time 88286983807 ps
CPU time 64.06 seconds
Started Aug 14 05:04:04 PM PDT 24
Finished Aug 14 05:05:08 PM PDT 24
Peak memory 200732 kb
Host smart-6f641793-efd4-46a0-ae26-c78cebc8136c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247792872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.4247792872
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.3898184894
Short name T139
Test name
Test status
Simulation time 171145300796 ps
CPU time 130.72 seconds
Started Aug 14 05:04:05 PM PDT 24
Finished Aug 14 05:06:16 PM PDT 24
Peak memory 200964 kb
Host smart-0edc244e-90cd-4885-9613-f9182c091af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898184894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3898184894
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2786322399
Short name T1141
Test name
Test status
Simulation time 38620575738 ps
CPU time 24.37 seconds
Started Aug 14 05:04:09 PM PDT 24
Finished Aug 14 05:04:34 PM PDT 24
Peak memory 200860 kb
Host smart-25120b28-d1c9-483f-bab1-b24aa8debc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786322399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2786322399
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2413591559
Short name T1161
Test name
Test status
Simulation time 13589110 ps
CPU time 0.61 seconds
Started Aug 14 05:00:46 PM PDT 24
Finished Aug 14 05:00:47 PM PDT 24
Peak memory 196448 kb
Host smart-619201c5-792f-40fb-90cc-1995ea199db1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413591559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2413591559
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.471337922
Short name T717
Test name
Test status
Simulation time 28456257115 ps
CPU time 42.3 seconds
Started Aug 14 05:00:45 PM PDT 24
Finished Aug 14 05:01:28 PM PDT 24
Peak memory 200964 kb
Host smart-0b3b27da-5b74-4796-abf9-7a160a1fbe90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471337922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.471337922
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2235757869
Short name T1126
Test name
Test status
Simulation time 151069518503 ps
CPU time 127.13 seconds
Started Aug 14 05:00:45 PM PDT 24
Finished Aug 14 05:02:52 PM PDT 24
Peak memory 200956 kb
Host smart-0a2241b5-4f3c-4053-a6bd-ccd0357547c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235757869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2235757869
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2670415759
Short name T179
Test name
Test status
Simulation time 53209927460 ps
CPU time 82.43 seconds
Started Aug 14 05:00:45 PM PDT 24
Finished Aug 14 05:02:07 PM PDT 24
Peak memory 200960 kb
Host smart-4bef4275-9b9f-4706-8c18-968173e3acd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670415759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2670415759
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.252228349
Short name T441
Test name
Test status
Simulation time 34277355632 ps
CPU time 17.34 seconds
Started Aug 14 05:00:45 PM PDT 24
Finished Aug 14 05:01:03 PM PDT 24
Peak memory 200980 kb
Host smart-fe1dd7c2-5cf0-4687-8762-3972789bf460
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252228349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.252228349
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2013202295
Short name T1051
Test name
Test status
Simulation time 78205881004 ps
CPU time 453 seconds
Started Aug 14 05:00:46 PM PDT 24
Finished Aug 14 05:08:19 PM PDT 24
Peak memory 200876 kb
Host smart-1b07bcbc-2f8a-456c-85d1-9184e4fa87a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2013202295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2013202295
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2702171101
Short name T872
Test name
Test status
Simulation time 4300135940 ps
CPU time 2.45 seconds
Started Aug 14 05:00:45 PM PDT 24
Finished Aug 14 05:00:48 PM PDT 24
Peak memory 197124 kb
Host smart-ee2a8b2c-9fd0-4d4d-b004-89aee5cd8b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702171101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2702171101
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2938873655
Short name T456
Test name
Test status
Simulation time 59153975664 ps
CPU time 37.48 seconds
Started Aug 14 05:00:46 PM PDT 24
Finished Aug 14 05:01:24 PM PDT 24
Peak memory 200532 kb
Host smart-a8da4eba-c4ec-4be2-bba0-370d740780bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938873655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2938873655
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3548251296
Short name T640
Test name
Test status
Simulation time 7346406624 ps
CPU time 211.19 seconds
Started Aug 14 05:00:45 PM PDT 24
Finished Aug 14 05:04:17 PM PDT 24
Peak memory 200972 kb
Host smart-9bd5fd75-0ed6-425e-ad66-12f250f08b05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3548251296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3548251296
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1797279047
Short name T915
Test name
Test status
Simulation time 6717369537 ps
CPU time 63.41 seconds
Started Aug 14 05:00:45 PM PDT 24
Finished Aug 14 05:01:49 PM PDT 24
Peak memory 198976 kb
Host smart-3718574e-c5c9-4766-8723-c4ab8dfe5bb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1797279047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1797279047
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2632761832
Short name T1075
Test name
Test status
Simulation time 88067945120 ps
CPU time 16.52 seconds
Started Aug 14 05:00:46 PM PDT 24
Finished Aug 14 05:01:03 PM PDT 24
Peak memory 200328 kb
Host smart-f479e007-ad3d-4f4e-94ef-2e4ccf31e0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632761832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2632761832
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.513209658
Short name T444
Test name
Test status
Simulation time 3427610260 ps
CPU time 6.01 seconds
Started Aug 14 05:00:44 PM PDT 24
Finished Aug 14 05:00:50 PM PDT 24
Peak memory 197276 kb
Host smart-8e01bcaf-0990-4da9-ab3c-820f443dc05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513209658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.513209658
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.205371263
Short name T852
Test name
Test status
Simulation time 6193441510 ps
CPU time 10.09 seconds
Started Aug 14 05:00:46 PM PDT 24
Finished Aug 14 05:00:56 PM PDT 24
Peak memory 200936 kb
Host smart-ca5713c9-4097-4ca7-a1c0-80fb44610565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205371263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.205371263
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.3961663300
Short name T971
Test name
Test status
Simulation time 172910179972 ps
CPU time 257.56 seconds
Started Aug 14 05:00:47 PM PDT 24
Finished Aug 14 05:05:04 PM PDT 24
Peak memory 216792 kb
Host smart-fa33c0f3-36c1-4da8-829c-9fa0f8ce23bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961663300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3961663300
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.1953382282
Short name T22
Test name
Test status
Simulation time 1511466765 ps
CPU time 53.34 seconds
Started Aug 14 05:00:47 PM PDT 24
Finished Aug 14 05:01:41 PM PDT 24
Peak memory 201144 kb
Host smart-8b7153d8-5b41-4040-a52b-42118c2ba29e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953382282 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1953382282
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.8005674
Short name T328
Test name
Test status
Simulation time 436555312 ps
CPU time 1.62 seconds
Started Aug 14 05:00:48 PM PDT 24
Finished Aug 14 05:00:50 PM PDT 24
Peak memory 199156 kb
Host smart-c0e3cf40-8c5d-4642-bedc-2b5cbb99cfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8005674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.8005674
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.426221988
Short name T308
Test name
Test status
Simulation time 105891766020 ps
CPU time 30.63 seconds
Started Aug 14 05:00:49 PM PDT 24
Finished Aug 14 05:01:19 PM PDT 24
Peak memory 200888 kb
Host smart-c9d0e00f-721c-44fd-9148-b56ead7a0933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426221988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.426221988
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.542824031
Short name T763
Test name
Test status
Simulation time 72753418744 ps
CPU time 23.57 seconds
Started Aug 14 05:04:10 PM PDT 24
Finished Aug 14 05:04:34 PM PDT 24
Peak memory 200844 kb
Host smart-804e7a83-0e0f-4961-90d3-68787ea462cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542824031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.542824031
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2450090359
Short name T546
Test name
Test status
Simulation time 14324350315 ps
CPU time 18 seconds
Started Aug 14 05:04:03 PM PDT 24
Finished Aug 14 05:04:21 PM PDT 24
Peak memory 200472 kb
Host smart-302e579e-3d98-47a5-a74f-198068ef2cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450090359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2450090359
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.650350767
Short name T922
Test name
Test status
Simulation time 103995509035 ps
CPU time 107.74 seconds
Started Aug 14 05:04:04 PM PDT 24
Finished Aug 14 05:05:52 PM PDT 24
Peak memory 200828 kb
Host smart-0319844f-83f1-4a52-ac11-d60980554085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650350767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.650350767
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.207570328
Short name T330
Test name
Test status
Simulation time 78414836827 ps
CPU time 33.96 seconds
Started Aug 14 05:04:04 PM PDT 24
Finished Aug 14 05:04:38 PM PDT 24
Peak memory 200912 kb
Host smart-8f0fb9d3-1e4f-4c59-830c-d71968819720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207570328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.207570328
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2785701113
Short name T948
Test name
Test status
Simulation time 12685043875 ps
CPU time 23.51 seconds
Started Aug 14 05:04:12 PM PDT 24
Finished Aug 14 05:04:35 PM PDT 24
Peak memory 200960 kb
Host smart-94fefa0f-3bda-4d56-baf1-1b333de88316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785701113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2785701113
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.3870869518
Short name T795
Test name
Test status
Simulation time 72410916126 ps
CPU time 18.38 seconds
Started Aug 14 05:04:11 PM PDT 24
Finished Aug 14 05:04:29 PM PDT 24
Peak memory 200640 kb
Host smart-b790ac7a-57ee-43a7-a8e2-e2ba7a80039f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870869518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3870869518
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.236149631
Short name T750
Test name
Test status
Simulation time 17449014776 ps
CPU time 12.93 seconds
Started Aug 14 05:04:17 PM PDT 24
Finished Aug 14 05:04:30 PM PDT 24
Peak memory 201016 kb
Host smart-574f9034-3ae8-4592-b8c4-266c5d61ee08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236149631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.236149631
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2869841548
Short name T683
Test name
Test status
Simulation time 29527805698 ps
CPU time 41.13 seconds
Started Aug 14 05:04:13 PM PDT 24
Finished Aug 14 05:04:54 PM PDT 24
Peak memory 200892 kb
Host smart-73dfa7eb-c3e0-416a-9acb-770b7abd2977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869841548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2869841548
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2009325324
Short name T372
Test name
Test status
Simulation time 24335141 ps
CPU time 0.56 seconds
Started Aug 14 05:00:59 PM PDT 24
Finished Aug 14 05:01:00 PM PDT 24
Peak memory 196196 kb
Host smart-7fc8b5ae-2b5c-48bf-a75f-9c6bc025f645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009325324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2009325324
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.544445785
Short name T80
Test name
Test status
Simulation time 18646556042 ps
CPU time 14.7 seconds
Started Aug 14 05:01:00 PM PDT 24
Finished Aug 14 05:01:15 PM PDT 24
Peak memory 200884 kb
Host smart-59c28c84-0f48-4e00-a7dd-c4ab3d1bd95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544445785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.544445785
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.3518258907
Short name T431
Test name
Test status
Simulation time 61224988903 ps
CPU time 32.07 seconds
Started Aug 14 05:00:54 PM PDT 24
Finished Aug 14 05:01:26 PM PDT 24
Peak memory 200920 kb
Host smart-6dbbfcad-4805-4940-8ff1-76d177f70797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518258907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3518258907
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.2865747593
Short name T224
Test name
Test status
Simulation time 30127508894 ps
CPU time 13.12 seconds
Started Aug 14 05:00:58 PM PDT 24
Finished Aug 14 05:01:11 PM PDT 24
Peak memory 200892 kb
Host smart-2783d69f-bfe2-4ed1-bb92-10d862b8c944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865747593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2865747593
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.2518166486
Short name T702
Test name
Test status
Simulation time 26558190244 ps
CPU time 11.87 seconds
Started Aug 14 05:01:00 PM PDT 24
Finished Aug 14 05:01:12 PM PDT 24
Peak memory 200276 kb
Host smart-f4c464f3-8821-439e-afd4-349b7b8bb5e2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518166486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2518166486
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.2437533015
Short name T369
Test name
Test status
Simulation time 81623100387 ps
CPU time 142.31 seconds
Started Aug 14 05:00:54 PM PDT 24
Finished Aug 14 05:03:17 PM PDT 24
Peak memory 200796 kb
Host smart-06ab5259-006b-41df-99f7-883cae2d4976
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2437533015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2437533015
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.253373883
Short name T1113
Test name
Test status
Simulation time 2678749703 ps
CPU time 2.3 seconds
Started Aug 14 05:00:55 PM PDT 24
Finished Aug 14 05:00:57 PM PDT 24
Peak memory 200844 kb
Host smart-e57906d1-f09a-47a0-946b-423b0f846396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253373883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.253373883
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.3514898139
Short name T758
Test name
Test status
Simulation time 118199525680 ps
CPU time 279.34 seconds
Started Aug 14 05:00:59 PM PDT 24
Finished Aug 14 05:05:38 PM PDT 24
Peak memory 201084 kb
Host smart-c40d2df5-e8e4-44ff-94cb-bf49a6e2cc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514898139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3514898139
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.2772401670
Short name T783
Test name
Test status
Simulation time 13625290832 ps
CPU time 366.49 seconds
Started Aug 14 05:00:54 PM PDT 24
Finished Aug 14 05:07:00 PM PDT 24
Peak memory 200912 kb
Host smart-cbdc3c2a-5b72-415f-8aa6-3c63c0b0b85e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2772401670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2772401670
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.4044307077
Short name T421
Test name
Test status
Simulation time 6410921272 ps
CPU time 13.26 seconds
Started Aug 14 05:00:54 PM PDT 24
Finished Aug 14 05:01:07 PM PDT 24
Peak memory 199224 kb
Host smart-347ac5b8-ae0a-4094-b739-07bb97295791
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4044307077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.4044307077
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2176653143
Short name T912
Test name
Test status
Simulation time 189253396994 ps
CPU time 136.67 seconds
Started Aug 14 05:00:55 PM PDT 24
Finished Aug 14 05:03:12 PM PDT 24
Peak memory 200976 kb
Host smart-ca1ebc79-17a9-4940-800d-4d8dbca84ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176653143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2176653143
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.893114188
Short name T857
Test name
Test status
Simulation time 3372472212 ps
CPU time 3 seconds
Started Aug 14 05:00:53 PM PDT 24
Finished Aug 14 05:00:56 PM PDT 24
Peak memory 197432 kb
Host smart-8c5ee6ef-ee55-46fa-8a6e-5be7d5a5dd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893114188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.893114188
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.3726135048
Short name T846
Test name
Test status
Simulation time 710099710 ps
CPU time 2.39 seconds
Started Aug 14 05:00:47 PM PDT 24
Finished Aug 14 05:00:49 PM PDT 24
Peak memory 199652 kb
Host smart-ee455a86-846b-45da-b2a8-5e2f1c6a9032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726135048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3726135048
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.1099383981
Short name T889
Test name
Test status
Simulation time 26212045357 ps
CPU time 58.86 seconds
Started Aug 14 05:00:53 PM PDT 24
Finished Aug 14 05:01:52 PM PDT 24
Peak memory 200876 kb
Host smart-9878aa9f-56cf-4712-9045-8f40724efd5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099383981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.1099383981
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2554043091
Short name T581
Test name
Test status
Simulation time 6093653735 ps
CPU time 25.27 seconds
Started Aug 14 05:00:59 PM PDT 24
Finished Aug 14 05:01:25 PM PDT 24
Peak memory 217316 kb
Host smart-e090fc3a-5265-40d2-b9c5-dc9d13052943
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554043091 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2554043091
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.22195482
Short name T323
Test name
Test status
Simulation time 6386839051 ps
CPU time 33.39 seconds
Started Aug 14 05:00:57 PM PDT 24
Finished Aug 14 05:01:30 PM PDT 24
Peak memory 200860 kb
Host smart-1292cb69-1293-4928-b56a-5b3718ef3b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22195482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.22195482
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2779412011
Short name T260
Test name
Test status
Simulation time 39239840766 ps
CPU time 71.05 seconds
Started Aug 14 05:00:57 PM PDT 24
Finished Aug 14 05:02:08 PM PDT 24
Peak memory 200960 kb
Host smart-437db002-bf43-4644-bd08-ffb4b2e4dfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779412011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2779412011
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2679336271
Short name T188
Test name
Test status
Simulation time 53634120877 ps
CPU time 24.65 seconds
Started Aug 14 05:04:17 PM PDT 24
Finished Aug 14 05:04:42 PM PDT 24
Peak memory 200976 kb
Host smart-636129c6-900c-4ef6-a639-2b83602c55c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679336271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2679336271
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1628200854
Short name T213
Test name
Test status
Simulation time 77240589389 ps
CPU time 125.47 seconds
Started Aug 14 05:04:15 PM PDT 24
Finished Aug 14 05:06:20 PM PDT 24
Peak memory 200808 kb
Host smart-fcf0e673-11d0-4023-bcca-d3200c494b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628200854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1628200854
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.2386389536
Short name T772
Test name
Test status
Simulation time 110704403778 ps
CPU time 48.49 seconds
Started Aug 14 05:04:13 PM PDT 24
Finished Aug 14 05:05:01 PM PDT 24
Peak memory 200956 kb
Host smart-0c6dd372-d1e9-44fd-9c6d-e83d58aed741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386389536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2386389536
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1190834870
Short name T739
Test name
Test status
Simulation time 125284938236 ps
CPU time 97.92 seconds
Started Aug 14 05:04:15 PM PDT 24
Finished Aug 14 05:05:53 PM PDT 24
Peak memory 200888 kb
Host smart-eebbc849-6e37-4235-90bc-8bf934ceb2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190834870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1190834870
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2393352627
Short name T1171
Test name
Test status
Simulation time 8356449689 ps
CPU time 6.51 seconds
Started Aug 14 05:04:13 PM PDT 24
Finished Aug 14 05:04:19 PM PDT 24
Peak memory 200744 kb
Host smart-88c2e3ac-7505-44ce-916d-eaa4433577c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393352627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2393352627
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1407609264
Short name T191
Test name
Test status
Simulation time 16287082409 ps
CPU time 25.43 seconds
Started Aug 14 05:04:14 PM PDT 24
Finished Aug 14 05:04:39 PM PDT 24
Peak memory 200976 kb
Host smart-228ba601-c0f5-4a27-b2c4-33fb085a1a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407609264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1407609264
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.1590184433
Short name T214
Test name
Test status
Simulation time 50077114068 ps
CPU time 87.45 seconds
Started Aug 14 05:04:14 PM PDT 24
Finished Aug 14 05:05:41 PM PDT 24
Peak memory 200864 kb
Host smart-a1b9c673-512b-4de6-a218-05040881195c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590184433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.1590184433
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.185316010
Short name T356
Test name
Test status
Simulation time 101658122213 ps
CPU time 219.04 seconds
Started Aug 14 05:04:13 PM PDT 24
Finished Aug 14 05:07:52 PM PDT 24
Peak memory 200976 kb
Host smart-afefc3c4-4ab7-4dd3-a9ec-40d9f745586c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185316010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.185316010
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.652396171
Short name T189
Test name
Test status
Simulation time 93495663906 ps
CPU time 151.34 seconds
Started Aug 14 05:04:16 PM PDT 24
Finished Aug 14 05:06:48 PM PDT 24
Peak memory 200924 kb
Host smart-69d3c675-012d-4543-9959-91a96aeb4caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652396171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.652396171
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2277764109
Short name T755
Test name
Test status
Simulation time 19774376968 ps
CPU time 47.97 seconds
Started Aug 14 05:04:15 PM PDT 24
Finished Aug 14 05:05:03 PM PDT 24
Peak memory 200780 kb
Host smart-9d768647-dc52-4e8e-850c-03c86fc7cb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277764109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2277764109
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.586287594
Short name T541
Test name
Test status
Simulation time 41343899 ps
CPU time 0.59 seconds
Started Aug 14 05:00:54 PM PDT 24
Finished Aug 14 05:00:54 PM PDT 24
Peak memory 196488 kb
Host smart-a6e68617-0be6-45e7-97e8-0af034cce98b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586287594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.586287594
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.1000292160
Short name T275
Test name
Test status
Simulation time 89355685842 ps
CPU time 59.02 seconds
Started Aug 14 05:00:54 PM PDT 24
Finished Aug 14 05:01:53 PM PDT 24
Peak memory 200828 kb
Host smart-8b117ea8-5a98-490d-855f-66c683ba74ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000292160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1000292160
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.4196286779
Short name T653
Test name
Test status
Simulation time 27156424148 ps
CPU time 45.88 seconds
Started Aug 14 05:00:54 PM PDT 24
Finished Aug 14 05:01:40 PM PDT 24
Peak memory 200948 kb
Host smart-6597d5ed-c624-4961-94f6-e2789f573166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196286779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.4196286779
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.3032974440
Short name T978
Test name
Test status
Simulation time 215397896055 ps
CPU time 434.39 seconds
Started Aug 14 05:00:58 PM PDT 24
Finished Aug 14 05:08:12 PM PDT 24
Peak memory 200944 kb
Host smart-7831e6ab-f560-4daf-bb85-9341c3bcdfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032974440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3032974440
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.530838982
Short name T538
Test name
Test status
Simulation time 7582198005 ps
CPU time 11.12 seconds
Started Aug 14 05:00:55 PM PDT 24
Finished Aug 14 05:01:06 PM PDT 24
Peak memory 197648 kb
Host smart-ad2d2513-9b61-4502-8790-9188c8f3c5d1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530838982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.530838982
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.3488682875
Short name T832
Test name
Test status
Simulation time 59609927531 ps
CPU time 348.09 seconds
Started Aug 14 05:00:56 PM PDT 24
Finished Aug 14 05:06:44 PM PDT 24
Peak memory 200952 kb
Host smart-eda27ae3-de77-4fb9-8079-01ba112bc68d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3488682875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3488682875
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.3252917812
Short name T1150
Test name
Test status
Simulation time 6920300346 ps
CPU time 4.48 seconds
Started Aug 14 05:01:00 PM PDT 24
Finished Aug 14 05:01:05 PM PDT 24
Peak memory 200704 kb
Host smart-a64f68eb-e116-48ec-a36f-315527390692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252917812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3252917812
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.2034329984
Short name T258
Test name
Test status
Simulation time 80232382603 ps
CPU time 68.92 seconds
Started Aug 14 05:00:55 PM PDT 24
Finished Aug 14 05:02:04 PM PDT 24
Peak memory 209276 kb
Host smart-fcfa8f56-4c16-4b33-9b08-2751ee380ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034329984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2034329984
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2747185513
Short name T242
Test name
Test status
Simulation time 23608112425 ps
CPU time 976.5 seconds
Started Aug 14 05:00:57 PM PDT 24
Finished Aug 14 05:17:14 PM PDT 24
Peak memory 200900 kb
Host smart-67d45c09-619b-4246-996f-5035d6dd8e28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2747185513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2747185513
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.3640898618
Short name T929
Test name
Test status
Simulation time 7328641223 ps
CPU time 61.83 seconds
Started Aug 14 05:00:59 PM PDT 24
Finished Aug 14 05:02:01 PM PDT 24
Peak memory 199068 kb
Host smart-131bb36a-3428-44f5-94bf-6d1d5c277908
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3640898618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3640898618
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.4278049900
Short name T809
Test name
Test status
Simulation time 36116591646 ps
CPU time 86.21 seconds
Started Aug 14 05:00:55 PM PDT 24
Finished Aug 14 05:02:21 PM PDT 24
Peak memory 200912 kb
Host smart-5ce07043-5f29-45c9-879c-eaa45129da5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278049900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.4278049900
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1515910362
Short name T1089
Test name
Test status
Simulation time 94387556818 ps
CPU time 137.42 seconds
Started Aug 14 05:00:56 PM PDT 24
Finished Aug 14 05:03:13 PM PDT 24
Peak memory 196916 kb
Host smart-84db4f15-8af1-4a3e-8635-820f0ee3c574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515910362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1515910362
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.3562679540
Short name T676
Test name
Test status
Simulation time 660633901 ps
CPU time 1.87 seconds
Started Aug 14 05:00:55 PM PDT 24
Finished Aug 14 05:00:57 PM PDT 24
Peak memory 200548 kb
Host smart-d3ae889b-11a2-46ae-ba46-be052f268255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562679540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3562679540
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3757440043
Short name T738
Test name
Test status
Simulation time 101126032098 ps
CPU time 143.79 seconds
Started Aug 14 05:00:56 PM PDT 24
Finished Aug 14 05:03:20 PM PDT 24
Peak memory 200880 kb
Host smart-31c74b99-d69c-4afa-a841-9514762debcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757440043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3757440043
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.980553085
Short name T1066
Test name
Test status
Simulation time 8490032959 ps
CPU time 40.78 seconds
Started Aug 14 05:00:57 PM PDT 24
Finished Aug 14 05:01:38 PM PDT 24
Peak memory 217504 kb
Host smart-ad86d0ad-a770-49ca-870f-1bb70d942bf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980553085 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.980553085
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1546587536
Short name T419
Test name
Test status
Simulation time 1856383601 ps
CPU time 2.53 seconds
Started Aug 14 05:00:57 PM PDT 24
Finished Aug 14 05:01:00 PM PDT 24
Peak memory 199380 kb
Host smart-8e736a54-7519-4724-8e38-0d5b7e9400f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546587536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1546587536
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.4087494000
Short name T931
Test name
Test status
Simulation time 81236828019 ps
CPU time 213.4 seconds
Started Aug 14 05:00:57 PM PDT 24
Finished Aug 14 05:04:30 PM PDT 24
Peak memory 200888 kb
Host smart-0f32e2ed-0bf0-4e42-ba36-2642542bda5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087494000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.4087494000
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3615435957
Short name T223
Test name
Test status
Simulation time 16094383074 ps
CPU time 16.03 seconds
Started Aug 14 05:04:16 PM PDT 24
Finished Aug 14 05:04:33 PM PDT 24
Peak memory 201000 kb
Host smart-4538c095-41b2-422f-83c5-74f892281dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615435957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3615435957
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3684247340
Short name T186
Test name
Test status
Simulation time 32377042048 ps
CPU time 50.77 seconds
Started Aug 14 05:04:12 PM PDT 24
Finished Aug 14 05:05:03 PM PDT 24
Peak memory 200900 kb
Host smart-114bbee3-0b2a-46b7-950e-dc0acf882472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684247340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3684247340
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1140692010
Short name T279
Test name
Test status
Simulation time 98512512801 ps
CPU time 74.81 seconds
Started Aug 14 05:04:13 PM PDT 24
Finished Aug 14 05:05:28 PM PDT 24
Peak memory 200848 kb
Host smart-5b52c4fa-0368-4348-a207-9504d31c98a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140692010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1140692010
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.4206630223
Short name T618
Test name
Test status
Simulation time 156285720019 ps
CPU time 67.11 seconds
Started Aug 14 05:04:13 PM PDT 24
Finished Aug 14 05:05:20 PM PDT 24
Peak memory 200932 kb
Host smart-f901b54c-4757-44e1-8475-14541835dbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206630223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.4206630223
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.214364518
Short name T721
Test name
Test status
Simulation time 25820679377 ps
CPU time 11.9 seconds
Started Aug 14 05:04:13 PM PDT 24
Finished Aug 14 05:04:24 PM PDT 24
Peak memory 200956 kb
Host smart-2b3110f7-d3ae-417a-aa02-adb5bf364898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214364518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.214364518
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.385682552
Short name T1041
Test name
Test status
Simulation time 116251495558 ps
CPU time 168.71 seconds
Started Aug 14 05:04:13 PM PDT 24
Finished Aug 14 05:07:02 PM PDT 24
Peak memory 200968 kb
Host smart-58e6bc38-004c-41d5-b2e5-32e28f46af08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385682552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.385682552
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.11435835
Short name T314
Test name
Test status
Simulation time 17181968908 ps
CPU time 15.88 seconds
Started Aug 14 05:04:14 PM PDT 24
Finished Aug 14 05:04:30 PM PDT 24
Peak memory 200976 kb
Host smart-7679d7e3-8780-4761-bbf9-b4019ae7b363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11435835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.11435835
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2283110435
Short name T1180
Test name
Test status
Simulation time 46087917114 ps
CPU time 28.1 seconds
Started Aug 14 05:04:16 PM PDT 24
Finished Aug 14 05:04:45 PM PDT 24
Peak memory 200996 kb
Host smart-bfaff0ea-d1db-46d4-9868-af8ffe855fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283110435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2283110435
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.290091239
Short name T309
Test name
Test status
Simulation time 118365204301 ps
CPU time 80.99 seconds
Started Aug 14 05:04:12 PM PDT 24
Finished Aug 14 05:05:33 PM PDT 24
Peak memory 200888 kb
Host smart-1de2543b-a803-4e1c-bb08-8bb57c45cb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290091239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.290091239
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.968584500
Short name T425
Test name
Test status
Simulation time 40492900 ps
CPU time 0.56 seconds
Started Aug 14 05:01:04 PM PDT 24
Finished Aug 14 05:01:04 PM PDT 24
Peak memory 196236 kb
Host smart-9cb40690-4329-4532-b2dd-904e93aea19e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968584500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.968584500
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3403907616
Short name T938
Test name
Test status
Simulation time 88868311272 ps
CPU time 39.1 seconds
Started Aug 14 05:00:56 PM PDT 24
Finished Aug 14 05:01:35 PM PDT 24
Peak memory 200824 kb
Host smart-23bbce53-46e9-417f-adb8-ddd6057b1ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403907616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3403907616
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.2236527277
Short name T655
Test name
Test status
Simulation time 18763870789 ps
CPU time 27.58 seconds
Started Aug 14 05:00:57 PM PDT 24
Finished Aug 14 05:01:25 PM PDT 24
Peak memory 199720 kb
Host smart-3c55c812-6aae-45dc-be7a-02145aa8c77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236527277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2236527277
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.682018260
Short name T737
Test name
Test status
Simulation time 97573507166 ps
CPU time 34.53 seconds
Started Aug 14 05:00:57 PM PDT 24
Finished Aug 14 05:01:32 PM PDT 24
Peak memory 200836 kb
Host smart-91f38f34-a1f5-4045-8b30-87a02b01e496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682018260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.682018260
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.3572118146
Short name T1084
Test name
Test status
Simulation time 33458834867 ps
CPU time 16.35 seconds
Started Aug 14 05:00:54 PM PDT 24
Finished Aug 14 05:01:11 PM PDT 24
Peak memory 200960 kb
Host smart-a602bac8-5af0-4773-adae-e591c3461494
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572118146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3572118146
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.3221601391
Short name T964
Test name
Test status
Simulation time 244959626497 ps
CPU time 403.54 seconds
Started Aug 14 05:01:04 PM PDT 24
Finished Aug 14 05:07:48 PM PDT 24
Peak memory 200984 kb
Host smart-90669eee-9e44-4711-8f54-172adc4cd58a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3221601391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3221601391
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.3273793019
Short name T516
Test name
Test status
Simulation time 7778728273 ps
CPU time 5.96 seconds
Started Aug 14 05:01:00 PM PDT 24
Finished Aug 14 05:01:06 PM PDT 24
Peak memory 200792 kb
Host smart-8aa9113d-f485-4791-98ce-aac1482fd4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273793019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3273793019
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.941601239
Short name T573
Test name
Test status
Simulation time 96234154520 ps
CPU time 45.59 seconds
Started Aug 14 05:00:56 PM PDT 24
Finished Aug 14 05:01:41 PM PDT 24
Peak memory 201204 kb
Host smart-d8947e3b-d526-4d92-94c7-016603f72500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941601239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.941601239
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.2938515361
Short name T897
Test name
Test status
Simulation time 18231830055 ps
CPU time 188.06 seconds
Started Aug 14 05:01:04 PM PDT 24
Finished Aug 14 05:04:12 PM PDT 24
Peak memory 200832 kb
Host smart-40bad5ec-87d3-4876-baf3-75be63b87c7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2938515361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2938515361
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.591120555
Short name T371
Test name
Test status
Simulation time 6192688319 ps
CPU time 6.51 seconds
Started Aug 14 05:00:58 PM PDT 24
Finished Aug 14 05:01:05 PM PDT 24
Peak memory 200304 kb
Host smart-add10ce4-c00a-4bac-a389-b33b18069e97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=591120555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.591120555
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3323633165
Short name T943
Test name
Test status
Simulation time 6899717332 ps
CPU time 11.66 seconds
Started Aug 14 05:01:00 PM PDT 24
Finished Aug 14 05:01:12 PM PDT 24
Peak memory 201012 kb
Host smart-23d52a22-5129-4682-9409-6cdc6af663c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323633165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3323633165
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2183017969
Short name T370
Test name
Test status
Simulation time 5441510257 ps
CPU time 8.79 seconds
Started Aug 14 05:00:53 PM PDT 24
Finished Aug 14 05:01:02 PM PDT 24
Peak memory 197024 kb
Host smart-538449bf-2e94-4645-9a14-8621e657e010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183017969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2183017969
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3241115737
Short name T928
Test name
Test status
Simulation time 527972269 ps
CPU time 1.37 seconds
Started Aug 14 05:01:00 PM PDT 24
Finished Aug 14 05:01:02 PM PDT 24
Peak memory 199656 kb
Host smart-54839f19-45bf-45fd-960a-eb01288ecef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241115737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3241115737
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.483916949
Short name T926
Test name
Test status
Simulation time 1630453010 ps
CPU time 11.54 seconds
Started Aug 14 05:01:03 PM PDT 24
Finished Aug 14 05:01:14 PM PDT 24
Peak memory 200960 kb
Host smart-9024c92f-3ca6-47a9-9c2b-87f987dc0e8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483916949 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.483916949
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.355596890
Short name T278
Test name
Test status
Simulation time 600070300 ps
CPU time 1.34 seconds
Started Aug 14 05:00:54 PM PDT 24
Finished Aug 14 05:00:56 PM PDT 24
Peak memory 198752 kb
Host smart-b35a6720-99dc-469f-b3dc-b1df10753b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355596890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.355596890
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.1723727598
Short name T987
Test name
Test status
Simulation time 3858690853 ps
CPU time 5.49 seconds
Started Aug 14 05:01:00 PM PDT 24
Finished Aug 14 05:01:06 PM PDT 24
Peak memory 198416 kb
Host smart-31fec603-3b62-4b51-ae5e-0adf446bc39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723727598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1723727598
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.1878142392
Short name T1091
Test name
Test status
Simulation time 19098962282 ps
CPU time 37.09 seconds
Started Aug 14 05:04:16 PM PDT 24
Finished Aug 14 05:04:53 PM PDT 24
Peak memory 200804 kb
Host smart-2e459238-96db-4023-bc27-522db41b6f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878142392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1878142392
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3534887419
Short name T858
Test name
Test status
Simulation time 119397017850 ps
CPU time 50.29 seconds
Started Aug 14 05:04:12 PM PDT 24
Finished Aug 14 05:05:03 PM PDT 24
Peak memory 200968 kb
Host smart-6a40a5ef-bda9-40aa-ab47-03f4af18e96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534887419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3534887419
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3560181973
Short name T466
Test name
Test status
Simulation time 35816588080 ps
CPU time 16.68 seconds
Started Aug 14 05:04:15 PM PDT 24
Finished Aug 14 05:04:32 PM PDT 24
Peak memory 200972 kb
Host smart-8436d3b1-1ebe-43de-9437-eea02b9d1b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560181973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3560181973
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.244144927
Short name T175
Test name
Test status
Simulation time 122258724523 ps
CPU time 47.13 seconds
Started Aug 14 05:04:20 PM PDT 24
Finished Aug 14 05:05:07 PM PDT 24
Peak memory 200848 kb
Host smart-9a0349fd-2eec-4386-9e27-dff24d8b2664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244144927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.244144927
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.392352196
Short name T836
Test name
Test status
Simulation time 51889787213 ps
CPU time 76.83 seconds
Started Aug 14 05:04:19 PM PDT 24
Finished Aug 14 05:05:36 PM PDT 24
Peak memory 200900 kb
Host smart-cf5bf1a3-c28d-4c10-a119-ab44878022ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392352196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.392352196
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.386438654
Short name T788
Test name
Test status
Simulation time 17751222745 ps
CPU time 13.83 seconds
Started Aug 14 05:04:21 PM PDT 24
Finished Aug 14 05:04:35 PM PDT 24
Peak memory 200784 kb
Host smart-b95451e5-f816-4e96-9498-3047b8bdbc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386438654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.386438654
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3980762771
Short name T508
Test name
Test status
Simulation time 104650820896 ps
CPU time 162.05 seconds
Started Aug 14 05:04:22 PM PDT 24
Finished Aug 14 05:07:04 PM PDT 24
Peak memory 200976 kb
Host smart-91aecbcc-9832-4de3-b23c-1952bd981179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980762771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3980762771
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.1426740182
Short name T497
Test name
Test status
Simulation time 76788283494 ps
CPU time 66.9 seconds
Started Aug 14 05:04:21 PM PDT 24
Finished Aug 14 05:05:28 PM PDT 24
Peak memory 200864 kb
Host smart-e8980aa6-b5ac-439d-9743-ebca422ef9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426740182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1426740182
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2715662122
Short name T512
Test name
Test status
Simulation time 19862669 ps
CPU time 0.6 seconds
Started Aug 14 05:01:07 PM PDT 24
Finished Aug 14 05:01:08 PM PDT 24
Peak memory 196556 kb
Host smart-6c769150-a5fa-4799-b753-3df4baa587e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715662122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2715662122
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.4112450356
Short name T753
Test name
Test status
Simulation time 70039350247 ps
CPU time 52.43 seconds
Started Aug 14 05:01:03 PM PDT 24
Finished Aug 14 05:01:56 PM PDT 24
Peak memory 200924 kb
Host smart-d69d6d75-1e15-488b-9158-94b067e2f74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112450356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.4112450356
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.621350372
Short name T513
Test name
Test status
Simulation time 35333819026 ps
CPU time 35.83 seconds
Started Aug 14 05:01:04 PM PDT 24
Finished Aug 14 05:01:40 PM PDT 24
Peak memory 200988 kb
Host smart-218f63cc-fec7-4e68-bbe0-bd930e3a901b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621350372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.621350372
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_intr.3355620272
Short name T4
Test name
Test status
Simulation time 17712480799 ps
CPU time 23.45 seconds
Started Aug 14 05:01:03 PM PDT 24
Finished Aug 14 05:01:27 PM PDT 24
Peak memory 197988 kb
Host smart-d04390e7-8bb0-4ebf-b8fe-363c37bf21c8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355620272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3355620272
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.3938789282
Short name T527
Test name
Test status
Simulation time 158023134227 ps
CPU time 1077.53 seconds
Started Aug 14 05:01:05 PM PDT 24
Finished Aug 14 05:19:03 PM PDT 24
Peak memory 200952 kb
Host smart-18a613bf-e791-4b97-a508-be1030b1b302
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3938789282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3938789282
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.353572
Short name T813
Test name
Test status
Simulation time 5577940291 ps
CPU time 2.94 seconds
Started Aug 14 05:01:08 PM PDT 24
Finished Aug 14 05:01:11 PM PDT 24
Peak memory 199636 kb
Host smart-059bf60e-608e-4ef7-a36e-8093641eea9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.353572
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.2901989138
Short name T395
Test name
Test status
Simulation time 101410521869 ps
CPU time 89.33 seconds
Started Aug 14 05:01:01 PM PDT 24
Finished Aug 14 05:02:30 PM PDT 24
Peak memory 199572 kb
Host smart-3fde5748-c0b5-4031-9f4d-c4fa2f06dfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901989138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2901989138
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.59745634
Short name T488
Test name
Test status
Simulation time 14165040250 ps
CPU time 57.27 seconds
Started Aug 14 05:01:02 PM PDT 24
Finished Aug 14 05:01:59 PM PDT 24
Peak memory 200960 kb
Host smart-4bdbf42f-63fc-44e6-aa13-66f3b066e581
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=59745634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.59745634
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2181839966
Short name T363
Test name
Test status
Simulation time 5487687416 ps
CPU time 22.79 seconds
Started Aug 14 05:01:03 PM PDT 24
Finished Aug 14 05:01:26 PM PDT 24
Peak memory 199688 kb
Host smart-99fb5c2d-00ab-4752-8fd5-ff8196151f83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2181839966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2181839966
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1426511538
Short name T167
Test name
Test status
Simulation time 157212497458 ps
CPU time 66.94 seconds
Started Aug 14 05:01:03 PM PDT 24
Finished Aug 14 05:02:10 PM PDT 24
Peak memory 200872 kb
Host smart-0197368b-b5e5-4241-8fad-4ad2d6d1f599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426511538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1426511538
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.3104156009
Short name T868
Test name
Test status
Simulation time 1658036715 ps
CPU time 3.31 seconds
Started Aug 14 05:01:03 PM PDT 24
Finished Aug 14 05:01:06 PM PDT 24
Peak memory 196416 kb
Host smart-f6677d31-0b23-4b46-93c9-bc126a05654b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104156009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3104156009
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1809386303
Short name T1128
Test name
Test status
Simulation time 6207978254 ps
CPU time 18.28 seconds
Started Aug 14 05:01:02 PM PDT 24
Finished Aug 14 05:01:21 PM PDT 24
Peak memory 200652 kb
Host smart-6fbff645-f1cf-4562-a9b2-60f13f2fe2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809386303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1809386303
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.1966402020
Short name T791
Test name
Test status
Simulation time 815863538 ps
CPU time 3.97 seconds
Started Aug 14 05:01:02 PM PDT 24
Finished Aug 14 05:01:06 PM PDT 24
Peak memory 209288 kb
Host smart-4b40d369-f5d8-4da5-9755-88ff58f0b763
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966402020 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1966402020
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1281058474
Short name T778
Test name
Test status
Simulation time 1256182487 ps
CPU time 3.59 seconds
Started Aug 14 05:01:04 PM PDT 24
Finished Aug 14 05:01:08 PM PDT 24
Peak memory 199868 kb
Host smart-c0715a86-b757-4e2c-adfc-b363387b39b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281058474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1281058474
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.2647766881
Short name T493
Test name
Test status
Simulation time 87522910119 ps
CPU time 72.66 seconds
Started Aug 14 05:01:01 PM PDT 24
Finished Aug 14 05:02:14 PM PDT 24
Peak memory 200964 kb
Host smart-0ecf7e81-72d2-4d03-9453-a8bbdcd8980e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647766881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2647766881
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1631699767
Short name T153
Test name
Test status
Simulation time 65471528131 ps
CPU time 13.35 seconds
Started Aug 14 05:04:25 PM PDT 24
Finished Aug 14 05:04:38 PM PDT 24
Peak memory 200724 kb
Host smart-5aa50c6f-ff9a-48b3-9a92-fedeec3d3915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631699767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1631699767
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.907644758
Short name T208
Test name
Test status
Simulation time 204621856044 ps
CPU time 28.4 seconds
Started Aug 14 05:04:22 PM PDT 24
Finished Aug 14 05:04:51 PM PDT 24
Peak memory 200868 kb
Host smart-35128601-ceed-4d40-b4e2-2d8bf5dd4004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907644758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.907644758
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1199172713
Short name T198
Test name
Test status
Simulation time 108131570688 ps
CPU time 250.02 seconds
Started Aug 14 05:04:23 PM PDT 24
Finished Aug 14 05:08:33 PM PDT 24
Peak memory 200964 kb
Host smart-e442a587-1f2b-47d2-9e87-23338183e8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199172713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1199172713
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.4264909495
Short name T1163
Test name
Test status
Simulation time 159459877367 ps
CPU time 401.84 seconds
Started Aug 14 05:04:19 PM PDT 24
Finished Aug 14 05:11:01 PM PDT 24
Peak memory 200880 kb
Host smart-9f26a59b-2d47-420b-916c-8fc518314897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264909495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.4264909495
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.4167987196
Short name T1019
Test name
Test status
Simulation time 127637764515 ps
CPU time 22.65 seconds
Started Aug 14 05:04:22 PM PDT 24
Finished Aug 14 05:04:45 PM PDT 24
Peak memory 200936 kb
Host smart-e067bd67-659c-4de3-a5f8-bab74107d23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167987196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.4167987196
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2211529948
Short name T183
Test name
Test status
Simulation time 22471510858 ps
CPU time 19.35 seconds
Started Aug 14 05:04:22 PM PDT 24
Finished Aug 14 05:04:42 PM PDT 24
Peak memory 200872 kb
Host smart-241f6291-7682-4644-b524-3bee9715e9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211529948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2211529948
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.447521215
Short name T904
Test name
Test status
Simulation time 97163269970 ps
CPU time 41.75 seconds
Started Aug 14 05:04:23 PM PDT 24
Finished Aug 14 05:05:04 PM PDT 24
Peak memory 200952 kb
Host smart-2f4c6d46-37b6-496c-89e2-5d858a4d34a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447521215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.447521215
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3093562856
Short name T192
Test name
Test status
Simulation time 229356962915 ps
CPU time 81.76 seconds
Started Aug 14 05:04:21 PM PDT 24
Finished Aug 14 05:05:43 PM PDT 24
Peak memory 200904 kb
Host smart-0fac18fc-7d62-4bc1-aea7-63efb4ab7b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093562856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3093562856
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.3176036218
Short name T443
Test name
Test status
Simulation time 33859363 ps
CPU time 0.6 seconds
Started Aug 14 04:58:57 PM PDT 24
Finished Aug 14 04:58:58 PM PDT 24
Peak memory 196260 kb
Host smart-12341c3e-4f10-456e-bdf1-9cc3b22819c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176036218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3176036218
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2172068620
Short name T89
Test name
Test status
Simulation time 50388405128 ps
CPU time 16.46 seconds
Started Aug 14 04:58:59 PM PDT 24
Finished Aug 14 04:59:15 PM PDT 24
Peak memory 200896 kb
Host smart-ec29efba-646a-4578-a31b-90cd4e394450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172068620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2172068620
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.1628250717
Short name T335
Test name
Test status
Simulation time 138045497707 ps
CPU time 42.12 seconds
Started Aug 14 04:58:59 PM PDT 24
Finished Aug 14 04:59:41 PM PDT 24
Peak memory 200860 kb
Host smart-5517ec3a-ccd5-444b-8608-a78d46250180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628250717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1628250717
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.545934945
Short name T780
Test name
Test status
Simulation time 99278259039 ps
CPU time 15.14 seconds
Started Aug 14 04:58:57 PM PDT 24
Finished Aug 14 04:59:13 PM PDT 24
Peak memory 200888 kb
Host smart-60fbacfb-5df0-46c9-9df9-eb7372f308b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545934945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.545934945
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.3532121997
Short name T98
Test name
Test status
Simulation time 224246818050 ps
CPU time 311.17 seconds
Started Aug 14 04:58:58 PM PDT 24
Finished Aug 14 05:04:09 PM PDT 24
Peak memory 200880 kb
Host smart-e9791a50-0cb6-4642-b443-528030474c4e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532121997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3532121997
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.31112201
Short name T878
Test name
Test status
Simulation time 225067443278 ps
CPU time 388.11 seconds
Started Aug 14 04:58:57 PM PDT 24
Finished Aug 14 05:05:26 PM PDT 24
Peak memory 200916 kb
Host smart-517abbd1-25af-43e6-a7e1-a2415439aab1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=31112201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.31112201
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2050167589
Short name T453
Test name
Test status
Simulation time 10681991609 ps
CPU time 18.6 seconds
Started Aug 14 04:58:59 PM PDT 24
Finished Aug 14 04:59:18 PM PDT 24
Peak memory 200816 kb
Host smart-03af4bb1-0445-4a56-826a-733ac503a57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050167589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2050167589
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.42933552
Short name T972
Test name
Test status
Simulation time 167899155038 ps
CPU time 22.81 seconds
Started Aug 14 04:58:58 PM PDT 24
Finished Aug 14 04:59:21 PM PDT 24
Peak memory 201164 kb
Host smart-414053d5-8710-4dc1-bce9-400f0f33f60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42933552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.42933552
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.3812242598
Short name T792
Test name
Test status
Simulation time 20465787966 ps
CPU time 609.87 seconds
Started Aug 14 04:59:02 PM PDT 24
Finished Aug 14 05:09:12 PM PDT 24
Peak memory 200856 kb
Host smart-3a2cb362-3657-4269-8c19-709b42d1521f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3812242598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3812242598
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3900635688
Short name T13
Test name
Test status
Simulation time 6246300835 ps
CPU time 54.02 seconds
Started Aug 14 04:58:57 PM PDT 24
Finished Aug 14 04:59:51 PM PDT 24
Peak memory 200012 kb
Host smart-66ca1fb5-66c7-437c-8432-5631b6734c32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3900635688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3900635688
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3575908338
Short name T125
Test name
Test status
Simulation time 34081881803 ps
CPU time 52.55 seconds
Started Aug 14 04:58:59 PM PDT 24
Finished Aug 14 04:59:51 PM PDT 24
Peak memory 201008 kb
Host smart-62eac92d-3e3e-4ebd-9ed9-d5efed74cd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575908338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3575908338
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.3019290455
Short name T806
Test name
Test status
Simulation time 68222761925 ps
CPU time 19.3 seconds
Started Aug 14 04:58:57 PM PDT 24
Finished Aug 14 04:59:17 PM PDT 24
Peak memory 197112 kb
Host smart-fab997ed-4678-4a90-8391-0976338fbca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019290455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3019290455
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3513410424
Short name T26
Test name
Test status
Simulation time 58699168 ps
CPU time 0.85 seconds
Started Aug 14 04:58:56 PM PDT 24
Finished Aug 14 04:58:58 PM PDT 24
Peak memory 219152 kb
Host smart-4918f6de-b335-40ad-ae39-873e4d17fc2e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513410424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3513410424
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.1391827965
Short name T418
Test name
Test status
Simulation time 87551575 ps
CPU time 0.94 seconds
Started Aug 14 04:58:55 PM PDT 24
Finished Aug 14 04:58:57 PM PDT 24
Peak memory 199108 kb
Host smart-b5329e37-f871-489e-85c7-9a8a98ee2f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391827965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1391827965
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.4261822658
Short name T1122
Test name
Test status
Simulation time 260801216687 ps
CPU time 298.03 seconds
Started Aug 14 04:58:57 PM PDT 24
Finished Aug 14 05:03:55 PM PDT 24
Peak memory 209324 kb
Host smart-647dea39-a744-4de2-ad91-57b1deae140c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261822658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.4261822658
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.3887794750
Short name T837
Test name
Test status
Simulation time 6888215967 ps
CPU time 43.84 seconds
Started Aug 14 04:58:56 PM PDT 24
Finished Aug 14 04:59:41 PM PDT 24
Peak memory 217476 kb
Host smart-15f9751d-637a-4a9f-a405-4a5956773508
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887794750 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.3887794750
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.200538034
Short name T1133
Test name
Test status
Simulation time 2724021729 ps
CPU time 1.39 seconds
Started Aug 14 04:58:58 PM PDT 24
Finished Aug 14 04:59:00 PM PDT 24
Peak memory 199808 kb
Host smart-745405ae-127a-44d9-b3ec-4320682110cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200538034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.200538034
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.299094605
Short name T467
Test name
Test status
Simulation time 42800735540 ps
CPU time 21.64 seconds
Started Aug 14 04:58:54 PM PDT 24
Finished Aug 14 04:59:16 PM PDT 24
Peak memory 200884 kb
Host smart-4d48de49-3aa1-4b8f-a6d1-9e35f2dd06bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299094605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.299094605
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.811893660
Short name T1120
Test name
Test status
Simulation time 13323728 ps
CPU time 0.56 seconds
Started Aug 14 05:01:13 PM PDT 24
Finished Aug 14 05:01:13 PM PDT 24
Peak memory 196420 kb
Host smart-62964a8e-439c-43c5-8c7f-df725fe800a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811893660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.811893660
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3414745716
Short name T123
Test name
Test status
Simulation time 108237439796 ps
CPU time 153.4 seconds
Started Aug 14 05:01:03 PM PDT 24
Finished Aug 14 05:03:37 PM PDT 24
Peak memory 200884 kb
Host smart-4ecfacf9-594f-4d9e-bd79-928ee1cc869b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414745716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3414745716
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.2180051825
Short name T591
Test name
Test status
Simulation time 29959825535 ps
CPU time 12.18 seconds
Started Aug 14 05:01:07 PM PDT 24
Finished Aug 14 05:01:19 PM PDT 24
Peak memory 200748 kb
Host smart-9da61d71-d6d3-485b-a9f6-3d894dd06575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180051825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2180051825
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_intr.3941625422
Short name T589
Test name
Test status
Simulation time 61083231088 ps
CPU time 13.47 seconds
Started Aug 14 05:01:06 PM PDT 24
Finished Aug 14 05:01:20 PM PDT 24
Peak memory 200856 kb
Host smart-617c3036-1212-4480-b35a-372a791bbb11
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941625422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3941625422
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2756065267
Short name T384
Test name
Test status
Simulation time 71536776085 ps
CPU time 138.03 seconds
Started Aug 14 05:01:14 PM PDT 24
Finished Aug 14 05:03:32 PM PDT 24
Peak memory 200976 kb
Host smart-91335125-1235-4395-a136-fad678c75baa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2756065267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2756065267
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.2520984333
Short name T381
Test name
Test status
Simulation time 5083475404 ps
CPU time 2.56 seconds
Started Aug 14 05:01:12 PM PDT 24
Finished Aug 14 05:01:15 PM PDT 24
Peak memory 199252 kb
Host smart-1f20c58c-2eb4-48bc-8265-7b88e2486cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520984333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2520984333
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.3518734214
Short name T634
Test name
Test status
Simulation time 197142506900 ps
CPU time 121.83 seconds
Started Aug 14 05:01:03 PM PDT 24
Finished Aug 14 05:03:05 PM PDT 24
Peak memory 209352 kb
Host smart-876bd0b5-54ec-4787-b84f-869da6d11a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518734214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3518734214
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2158865006
Short name T1044
Test name
Test status
Simulation time 18093019920 ps
CPU time 961.01 seconds
Started Aug 14 05:01:12 PM PDT 24
Finished Aug 14 05:17:13 PM PDT 24
Peak memory 200972 kb
Host smart-867cecf1-457c-4164-91ec-8f4484b65608
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2158865006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2158865006
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.448322376
Short name T430
Test name
Test status
Simulation time 4647100578 ps
CPU time 19.27 seconds
Started Aug 14 05:01:03 PM PDT 24
Finished Aug 14 05:01:22 PM PDT 24
Peak memory 199552 kb
Host smart-4336979a-784d-41ad-ae0f-74904866b1d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448322376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.448322376
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.585392229
Short name T481
Test name
Test status
Simulation time 143750984102 ps
CPU time 208.45 seconds
Started Aug 14 05:01:03 PM PDT 24
Finished Aug 14 05:04:32 PM PDT 24
Peak memory 200892 kb
Host smart-e6266aa8-0d0e-4be0-be16-0cc813074066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585392229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.585392229
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.3545859253
Short name T741
Test name
Test status
Simulation time 37449572679 ps
CPU time 15.05 seconds
Started Aug 14 05:01:07 PM PDT 24
Finished Aug 14 05:01:22 PM PDT 24
Peak memory 196988 kb
Host smart-810dd795-5947-4973-99f3-2428a14abd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545859253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3545859253
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.999830006
Short name T1114
Test name
Test status
Simulation time 5361043571 ps
CPU time 8.81 seconds
Started Aug 14 05:01:01 PM PDT 24
Finished Aug 14 05:01:10 PM PDT 24
Peak memory 200500 kb
Host smart-2eae9eb3-3fe8-4d8b-8da2-7c5bbc5e57cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999830006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.999830006
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.902918316
Short name T522
Test name
Test status
Simulation time 3727916327 ps
CPU time 50.21 seconds
Started Aug 14 05:01:12 PM PDT 24
Finished Aug 14 05:02:02 PM PDT 24
Peak memory 217592 kb
Host smart-8c045ef0-ec28-4a15-92c4-783976cb7fa5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902918316 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.902918316
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1075613432
Short name T382
Test name
Test status
Simulation time 865355280 ps
CPU time 2.91 seconds
Started Aug 14 05:01:12 PM PDT 24
Finished Aug 14 05:01:15 PM PDT 24
Peak memory 199336 kb
Host smart-23c246fe-281d-441d-8231-e5361b86153a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075613432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1075613432
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2154966025
Short name T898
Test name
Test status
Simulation time 35001871710 ps
CPU time 38.22 seconds
Started Aug 14 05:01:04 PM PDT 24
Finished Aug 14 05:01:42 PM PDT 24
Peak memory 200916 kb
Host smart-0c95fb2f-f3b4-4c54-b989-b5529b1b79de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154966025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2154966025
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3481210841
Short name T1115
Test name
Test status
Simulation time 36665525 ps
CPU time 0.54 seconds
Started Aug 14 05:01:22 PM PDT 24
Finished Aug 14 05:01:22 PM PDT 24
Peak memory 196256 kb
Host smart-1b070cd6-3fd2-4f0b-bafe-607f2e1b4efd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481210841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3481210841
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1640525781
Short name T982
Test name
Test status
Simulation time 101381922186 ps
CPU time 67.76 seconds
Started Aug 14 05:01:14 PM PDT 24
Finished Aug 14 05:02:22 PM PDT 24
Peak memory 200768 kb
Host smart-2c7fe1a7-2bf0-4a75-a84b-a25005321030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640525781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1640525781
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3421713206
Short name T1132
Test name
Test status
Simulation time 45614004277 ps
CPU time 116.65 seconds
Started Aug 14 05:01:14 PM PDT 24
Finished Aug 14 05:03:11 PM PDT 24
Peak memory 200896 kb
Host smart-b5bf2e6c-65ba-41e6-82ee-e4a54c51f1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421713206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3421713206
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3823567041
Short name T820
Test name
Test status
Simulation time 44279464051 ps
CPU time 36.58 seconds
Started Aug 14 05:01:15 PM PDT 24
Finished Aug 14 05:01:51 PM PDT 24
Peak memory 200996 kb
Host smart-e31b3b64-8b65-42d1-8c10-90eac4b5455c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823567041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3823567041
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2087185791
Short name T299
Test name
Test status
Simulation time 238490779450 ps
CPU time 469.99 seconds
Started Aug 14 05:01:13 PM PDT 24
Finished Aug 14 05:09:03 PM PDT 24
Peak memory 200836 kb
Host smart-be96b590-24f1-49a5-a637-3db102487cbe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087185791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2087185791
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.279301124
Short name T1017
Test name
Test status
Simulation time 107881195330 ps
CPU time 657.3 seconds
Started Aug 14 05:01:20 PM PDT 24
Finished Aug 14 05:12:18 PM PDT 24
Peak memory 200872 kb
Host smart-5466a001-489c-4d50-a5b1-34a926686dda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=279301124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.279301124
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.63419453
Short name T1098
Test name
Test status
Simulation time 12982047389 ps
CPU time 26.57 seconds
Started Aug 14 05:01:24 PM PDT 24
Finished Aug 14 05:01:51 PM PDT 24
Peak memory 200640 kb
Host smart-d13d8b3c-5a59-4d08-93bb-c3d3189f758b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63419453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.63419453
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.562282992
Short name T311
Test name
Test status
Simulation time 95194156536 ps
CPU time 30.39 seconds
Started Aug 14 05:01:13 PM PDT 24
Finished Aug 14 05:01:43 PM PDT 24
Peak memory 200688 kb
Host smart-70932cb0-17fc-4b20-aa08-69cb61b434f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562282992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.562282992
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.988200269
Short name T578
Test name
Test status
Simulation time 17469876064 ps
CPU time 124.4 seconds
Started Aug 14 05:01:22 PM PDT 24
Finished Aug 14 05:03:27 PM PDT 24
Peak memory 200980 kb
Host smart-5f7fc8cf-e84a-4bbb-8be3-13773b099d5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=988200269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.988200269
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1929817724
Short name T666
Test name
Test status
Simulation time 5970846003 ps
CPU time 10.15 seconds
Started Aug 14 05:01:13 PM PDT 24
Finished Aug 14 05:01:23 PM PDT 24
Peak memory 200076 kb
Host smart-79a26948-2c9d-4945-97de-b6b058777a90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1929817724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1929817724
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.2731984722
Short name T324
Test name
Test status
Simulation time 173746344054 ps
CPU time 36.21 seconds
Started Aug 14 05:01:13 PM PDT 24
Finished Aug 14 05:01:50 PM PDT 24
Peak memory 200772 kb
Host smart-2e2952ae-ee36-4296-acb0-2f0b06699f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731984722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.2731984722
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2038794286
Short name T689
Test name
Test status
Simulation time 1966684029 ps
CPU time 3.39 seconds
Started Aug 14 05:01:12 PM PDT 24
Finished Aug 14 05:01:16 PM PDT 24
Peak memory 196448 kb
Host smart-29a2df4c-38a2-40bd-813d-9559c7e9f004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038794286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2038794286
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2021155660
Short name T575
Test name
Test status
Simulation time 676531127 ps
CPU time 1.43 seconds
Started Aug 14 05:01:14 PM PDT 24
Finished Aug 14 05:01:16 PM PDT 24
Peak memory 199364 kb
Host smart-52d28eea-c47f-4065-bbb8-b6ef90d6a38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021155660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2021155660
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.1139774978
Short name T613
Test name
Test status
Simulation time 4139174032 ps
CPU time 45.23 seconds
Started Aug 14 05:01:23 PM PDT 24
Finished Aug 14 05:02:09 PM PDT 24
Peak memory 209184 kb
Host smart-e4209461-867d-481f-845b-2a738d1ae7c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139774978 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1139774978
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1825509485
Short name T1062
Test name
Test status
Simulation time 10198662487 ps
CPU time 1.83 seconds
Started Aug 14 05:01:20 PM PDT 24
Finished Aug 14 05:01:22 PM PDT 24
Peak memory 200332 kb
Host smart-e7cf37a4-a6f6-41fb-8981-40325cfcd401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825509485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1825509485
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.2585774633
Short name T771
Test name
Test status
Simulation time 49744082850 ps
CPU time 38.63 seconds
Started Aug 14 05:01:13 PM PDT 24
Finished Aug 14 05:01:51 PM PDT 24
Peak memory 200900 kb
Host smart-bf438ac3-b8cf-48bd-828f-14b2dcbb4bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585774633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2585774633
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2961521665
Short name T598
Test name
Test status
Simulation time 30916568 ps
CPU time 0.55 seconds
Started Aug 14 05:01:22 PM PDT 24
Finished Aug 14 05:01:23 PM PDT 24
Peak memory 196272 kb
Host smart-0005bdfd-8763-4eef-ba30-084d82ef28ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961521665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2961521665
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1144244753
Short name T91
Test name
Test status
Simulation time 13452026481 ps
CPU time 7.34 seconds
Started Aug 14 05:01:22 PM PDT 24
Finished Aug 14 05:01:30 PM PDT 24
Peak memory 200944 kb
Host smart-b9410889-212d-4e2c-a9a5-2d7411cb97f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144244753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1144244753
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.1345807101
Short name T650
Test name
Test status
Simulation time 50333496069 ps
CPU time 82.58 seconds
Started Aug 14 05:01:23 PM PDT 24
Finished Aug 14 05:02:46 PM PDT 24
Peak memory 200956 kb
Host smart-6693f966-3231-4b5f-abd4-0111b0462c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345807101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1345807101
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3107930626
Short name T993
Test name
Test status
Simulation time 40239562549 ps
CPU time 14.89 seconds
Started Aug 14 05:01:23 PM PDT 24
Finished Aug 14 05:01:38 PM PDT 24
Peak memory 200944 kb
Host smart-8e9db4e3-153a-4949-bced-b5f4b10e8ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107930626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3107930626
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1444186018
Short name T622
Test name
Test status
Simulation time 211771062870 ps
CPU time 340.11 seconds
Started Aug 14 05:01:23 PM PDT 24
Finished Aug 14 05:07:03 PM PDT 24
Peak memory 200252 kb
Host smart-df7f72ea-dd57-4591-aab0-de427c69e540
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444186018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1444186018
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_loopback.3156309507
Short name T924
Test name
Test status
Simulation time 5797080724 ps
CPU time 6.76 seconds
Started Aug 14 05:01:21 PM PDT 24
Finished Aug 14 05:01:28 PM PDT 24
Peak memory 200808 kb
Host smart-85755a2c-a0b9-406d-b688-c84213c094a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156309507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3156309507
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1449310304
Short name T1016
Test name
Test status
Simulation time 61878848216 ps
CPU time 15.86 seconds
Started Aug 14 05:01:24 PM PDT 24
Finished Aug 14 05:01:40 PM PDT 24
Peak memory 201144 kb
Host smart-d323df50-2c89-43a7-abbf-0af970bcd7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449310304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1449310304
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.737282734
Short name T480
Test name
Test status
Simulation time 27127431105 ps
CPU time 101.25 seconds
Started Aug 14 05:01:26 PM PDT 24
Finished Aug 14 05:03:07 PM PDT 24
Peak memory 200880 kb
Host smart-9abddeca-2be7-486e-8de9-425fabd628a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=737282734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.737282734
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.580594770
Short name T1159
Test name
Test status
Simulation time 6072467850 ps
CPU time 28.94 seconds
Started Aug 14 05:01:23 PM PDT 24
Finished Aug 14 05:01:52 PM PDT 24
Peak memory 199116 kb
Host smart-a50f4667-ce59-4ece-b675-cc025217d978
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=580594770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.580594770
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3295950840
Short name T165
Test name
Test status
Simulation time 25565341848 ps
CPU time 19.68 seconds
Started Aug 14 05:01:22 PM PDT 24
Finished Aug 14 05:01:42 PM PDT 24
Peak memory 200856 kb
Host smart-42a008bc-57a6-4ea8-89a5-72385e8855ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295950840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3295950840
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.610727155
Short name T307
Test name
Test status
Simulation time 2902235419 ps
CPU time 5.08 seconds
Started Aug 14 05:01:23 PM PDT 24
Finished Aug 14 05:01:28 PM PDT 24
Peak memory 196764 kb
Host smart-4c0fb8fe-e70f-4b58-9d10-23e24e26c124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610727155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.610727155
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.1732620381
Short name T406
Test name
Test status
Simulation time 103442821 ps
CPU time 1.07 seconds
Started Aug 14 05:01:24 PM PDT 24
Finished Aug 14 05:01:25 PM PDT 24
Peak memory 199380 kb
Host smart-cf614624-833f-4699-b479-df0c38ce08a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732620381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1732620381
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.318351041
Short name T230
Test name
Test status
Simulation time 13132642426 ps
CPU time 32.32 seconds
Started Aug 14 05:01:26 PM PDT 24
Finished Aug 14 05:01:58 PM PDT 24
Peak memory 200852 kb
Host smart-65ed7f92-b0c8-435e-9420-6f90155d9591
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318351041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.318351041
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3210970851
Short name T1060
Test name
Test status
Simulation time 17318320786 ps
CPU time 90.34 seconds
Started Aug 14 05:01:23 PM PDT 24
Finished Aug 14 05:02:54 PM PDT 24
Peak memory 217612 kb
Host smart-c248dbf6-fd84-45ca-b1a3-b4cc7785547a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210970851 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3210970851
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.157164177
Short name T754
Test name
Test status
Simulation time 928032623 ps
CPU time 2.11 seconds
Started Aug 14 05:01:25 PM PDT 24
Finished Aug 14 05:01:27 PM PDT 24
Peak memory 199252 kb
Host smart-5edb3fdb-7aee-4faa-bc7b-a90b5b783a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157164177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.157164177
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2287277460
Short name T1118
Test name
Test status
Simulation time 15717900454 ps
CPU time 25.46 seconds
Started Aug 14 05:01:23 PM PDT 24
Finished Aug 14 05:01:49 PM PDT 24
Peak memory 199684 kb
Host smart-d781a28a-886a-4e05-8c54-5dd1954d2dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287277460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2287277460
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.3388500694
Short name T471
Test name
Test status
Simulation time 55108560 ps
CPU time 0.56 seconds
Started Aug 14 05:01:32 PM PDT 24
Finished Aug 14 05:01:32 PM PDT 24
Peak memory 195932 kb
Host smart-8f548013-dbd6-4df2-acb9-119be4c85a88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388500694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3388500694
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1748378678
Short name T377
Test name
Test status
Simulation time 19767254325 ps
CPU time 34.71 seconds
Started Aug 14 05:01:22 PM PDT 24
Finished Aug 14 05:01:56 PM PDT 24
Peak memory 200960 kb
Host smart-f30decd1-4fde-4611-9377-275301361bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748378678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1748378678
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.2355149790
Short name T417
Test name
Test status
Simulation time 34910795088 ps
CPU time 28.56 seconds
Started Aug 14 05:01:22 PM PDT 24
Finished Aug 14 05:01:50 PM PDT 24
Peak memory 200740 kb
Host smart-8150d064-f50c-424d-8b26-bacd71d5877e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355149790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2355149790
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3438995133
Short name T673
Test name
Test status
Simulation time 129527174758 ps
CPU time 12.33 seconds
Started Aug 14 05:01:23 PM PDT 24
Finished Aug 14 05:01:35 PM PDT 24
Peak memory 200844 kb
Host smart-7403c92b-53d5-4e48-904f-66362574092c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438995133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3438995133
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.92707693
Short name T749
Test name
Test status
Simulation time 38078706477 ps
CPU time 69.43 seconds
Started Aug 14 05:01:21 PM PDT 24
Finished Aug 14 05:02:30 PM PDT 24
Peak memory 200940 kb
Host smart-b60effe7-efc6-4a99-94d3-ce07e5db59ea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92707693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.92707693
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1524373586
Short name T564
Test name
Test status
Simulation time 141898582329 ps
CPU time 155.59 seconds
Started Aug 14 05:01:32 PM PDT 24
Finished Aug 14 05:04:07 PM PDT 24
Peak memory 200968 kb
Host smart-4464edb9-8370-4f06-8dec-79e064000ae7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1524373586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1524373586
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.1423519724
Short name T341
Test name
Test status
Simulation time 7814115452 ps
CPU time 5.77 seconds
Started Aug 14 05:01:33 PM PDT 24
Finished Aug 14 05:01:38 PM PDT 24
Peak memory 199500 kb
Host smart-e45a6a92-23ba-464a-bf9a-598b0e3054da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423519724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1423519724
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.3307997913
Short name T930
Test name
Test status
Simulation time 121338063714 ps
CPU time 101.91 seconds
Started Aug 14 05:01:25 PM PDT 24
Finished Aug 14 05:03:07 PM PDT 24
Peak memory 200916 kb
Host smart-c01fe021-b9a3-4bab-96d6-fc245c970cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307997913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.3307997913
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.1581987179
Short name T269
Test name
Test status
Simulation time 6896619568 ps
CPU time 422.5 seconds
Started Aug 14 05:01:31 PM PDT 24
Finished Aug 14 05:08:34 PM PDT 24
Peak memory 200928 kb
Host smart-cca0970f-95a0-4129-b669-42d9a5c365c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1581987179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1581987179
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2960289252
Short name T875
Test name
Test status
Simulation time 5822313317 ps
CPU time 10.81 seconds
Started Aug 14 05:01:23 PM PDT 24
Finished Aug 14 05:01:34 PM PDT 24
Peak memory 199820 kb
Host smart-445d05d2-3a1f-4baf-aead-bd04fd54822c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2960289252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2960289252
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2748115288
Short name T1123
Test name
Test status
Simulation time 169533455378 ps
CPU time 373.09 seconds
Started Aug 14 05:01:32 PM PDT 24
Finished Aug 14 05:07:45 PM PDT 24
Peak memory 200876 kb
Host smart-ab051e36-344e-4fee-a860-79c332b7c05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748115288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2748115288
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.2048325049
Short name T694
Test name
Test status
Simulation time 32776825451 ps
CPU time 6.87 seconds
Started Aug 14 05:01:25 PM PDT 24
Finished Aug 14 05:01:32 PM PDT 24
Peak memory 196884 kb
Host smart-e2a9feef-603e-43de-a438-f6bcad0d3ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048325049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2048325049
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3385907882
Short name T829
Test name
Test status
Simulation time 5451028498 ps
CPU time 15.53 seconds
Started Aug 14 05:01:24 PM PDT 24
Finished Aug 14 05:01:40 PM PDT 24
Peak memory 200740 kb
Host smart-2666d918-348a-40be-b5d5-65b0c8ee6acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385907882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3385907882
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3669558324
Short name T479
Test name
Test status
Simulation time 67972521623 ps
CPU time 41.7 seconds
Started Aug 14 05:01:31 PM PDT 24
Finished Aug 14 05:02:13 PM PDT 24
Peak memory 200984 kb
Host smart-ccc5d186-c3ab-4a30-bdd4-a0b4b24204ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669558324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3669558324
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.1155185125
Short name T624
Test name
Test status
Simulation time 23978868308 ps
CPU time 20.87 seconds
Started Aug 14 05:01:32 PM PDT 24
Finished Aug 14 05:01:53 PM PDT 24
Peak memory 209492 kb
Host smart-b72c4215-f1ea-4dba-9f81-ba1c55d33eee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155185125 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1155185125
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.275759936
Short name T626
Test name
Test status
Simulation time 504260144 ps
CPU time 1.49 seconds
Started Aug 14 05:01:33 PM PDT 24
Finished Aug 14 05:01:35 PM PDT 24
Peak memory 200644 kb
Host smart-2e890567-8602-4f64-9768-04bb05202138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275759936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.275759936
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1916583947
Short name T1096
Test name
Test status
Simulation time 32629165076 ps
CPU time 15.11 seconds
Started Aug 14 05:01:24 PM PDT 24
Finished Aug 14 05:01:40 PM PDT 24
Peak memory 200912 kb
Host smart-df83bcc8-c9b9-42d1-886d-f1486b63692b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916583947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1916583947
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2292234207
Short name T1102
Test name
Test status
Simulation time 13480697 ps
CPU time 0.56 seconds
Started Aug 14 05:01:31 PM PDT 24
Finished Aug 14 05:01:31 PM PDT 24
Peak memory 195264 kb
Host smart-9efc43f5-3822-4a3f-b819-db81860c29c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292234207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2292234207
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.4169113489
Short name T42
Test name
Test status
Simulation time 78448835273 ps
CPU time 30.81 seconds
Started Aug 14 05:01:33 PM PDT 24
Finished Aug 14 05:02:04 PM PDT 24
Peak memory 200788 kb
Host smart-a641d90f-614d-440a-9a89-a09fbd29257e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169113489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.4169113489
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3319139303
Short name T918
Test name
Test status
Simulation time 28876266092 ps
CPU time 49.66 seconds
Started Aug 14 05:01:38 PM PDT 24
Finished Aug 14 05:02:27 PM PDT 24
Peak memory 200852 kb
Host smart-537f5c47-f65b-477f-bf01-2957e29ebb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319139303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3319139303
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.3977791649
Short name T574
Test name
Test status
Simulation time 38029163754 ps
CPU time 17.81 seconds
Started Aug 14 05:01:32 PM PDT 24
Finished Aug 14 05:01:50 PM PDT 24
Peak memory 200892 kb
Host smart-0848bf3a-5871-4a13-b9ec-a1a6c52e8249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977791649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3977791649
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.2987448686
Short name T362
Test name
Test status
Simulation time 12181148808 ps
CPU time 2.56 seconds
Started Aug 14 05:01:38 PM PDT 24
Finished Aug 14 05:01:40 PM PDT 24
Peak memory 197028 kb
Host smart-37aef1f3-99c4-4f4d-9832-7e8ab22167d8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987448686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.2987448686
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.620926778
Short name T280
Test name
Test status
Simulation time 105393279854 ps
CPU time 964.71 seconds
Started Aug 14 05:01:31 PM PDT 24
Finished Aug 14 05:17:36 PM PDT 24
Peak memory 200908 kb
Host smart-3019b23f-5d20-4083-b334-5903c2902c59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=620926778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.620926778
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2790576889
Short name T358
Test name
Test status
Simulation time 3502555230 ps
CPU time 2.34 seconds
Started Aug 14 05:01:34 PM PDT 24
Finished Aug 14 05:01:36 PM PDT 24
Peak memory 200740 kb
Host smart-b89a0c70-414e-4f99-aaef-7dad19db0f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790576889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2790576889
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.839691190
Short name T831
Test name
Test status
Simulation time 34778265551 ps
CPU time 55.49 seconds
Started Aug 14 05:01:35 PM PDT 24
Finished Aug 14 05:02:31 PM PDT 24
Peak memory 201056 kb
Host smart-94977e2f-8b45-4623-9a9e-3e5bda3e4bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839691190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.839691190
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.2630344187
Short name T999
Test name
Test status
Simulation time 23307739353 ps
CPU time 233.46 seconds
Started Aug 14 05:01:34 PM PDT 24
Finished Aug 14 05:05:27 PM PDT 24
Peak memory 200984 kb
Host smart-c619a64f-c886-4d66-b0dd-36ca90dd2b09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2630344187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.2630344187
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.3712061893
Short name T412
Test name
Test status
Simulation time 2763410278 ps
CPU time 9.94 seconds
Started Aug 14 05:01:30 PM PDT 24
Finished Aug 14 05:01:40 PM PDT 24
Peak memory 199248 kb
Host smart-daa60bd4-00ae-4430-b198-c58045b4cf20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3712061893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3712061893
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.917716496
Short name T144
Test name
Test status
Simulation time 77330427514 ps
CPU time 152.5 seconds
Started Aug 14 05:01:34 PM PDT 24
Finished Aug 14 05:04:07 PM PDT 24
Peak memory 200808 kb
Host smart-17663744-5919-4fec-b4cf-b116a5c7e67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917716496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.917716496
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.813996218
Short name T1156
Test name
Test status
Simulation time 1825522458 ps
CPU time 2.05 seconds
Started Aug 14 05:01:32 PM PDT 24
Finished Aug 14 05:01:34 PM PDT 24
Peak memory 196524 kb
Host smart-a7ad43bb-2dd7-4739-8875-50151857f43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813996218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.813996218
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3471513606
Short name T558
Test name
Test status
Simulation time 466351143 ps
CPU time 1.27 seconds
Started Aug 14 05:01:32 PM PDT 24
Finished Aug 14 05:01:34 PM PDT 24
Peak memory 200404 kb
Host smart-7e24b69d-372f-47c5-9128-12184b13ac86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471513606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3471513606
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.137756957
Short name T391
Test name
Test status
Simulation time 9674852185 ps
CPU time 27.74 seconds
Started Aug 14 05:01:37 PM PDT 24
Finished Aug 14 05:02:05 PM PDT 24
Peak memory 209232 kb
Host smart-5bf2c6db-8794-40cb-afb8-8972bbe98b74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137756957 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.137756957
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.76272446
Short name T727
Test name
Test status
Simulation time 997272365 ps
CPU time 3.68 seconds
Started Aug 14 05:01:30 PM PDT 24
Finished Aug 14 05:01:34 PM PDT 24
Peak memory 200596 kb
Host smart-56a382aa-0191-4db9-a4e9-eee5a4db09f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76272446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.76272446
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.490460571
Short name T331
Test name
Test status
Simulation time 72475299791 ps
CPU time 77.64 seconds
Started Aug 14 05:01:30 PM PDT 24
Finished Aug 14 05:02:48 PM PDT 24
Peak memory 200880 kb
Host smart-8a836136-33bf-495a-ac0c-0c40f13ee39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490460571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.490460571
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.1302535154
Short name T506
Test name
Test status
Simulation time 13230665 ps
CPU time 0.55 seconds
Started Aug 14 05:01:43 PM PDT 24
Finished Aug 14 05:01:44 PM PDT 24
Peak memory 196556 kb
Host smart-467c3f21-bb01-4ed2-b140-e0c1f764da04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302535154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1302535154
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3691609618
Short name T1025
Test name
Test status
Simulation time 118947198577 ps
CPU time 183.62 seconds
Started Aug 14 05:01:31 PM PDT 24
Finished Aug 14 05:04:35 PM PDT 24
Peak memory 200936 kb
Host smart-a771dfe0-077e-49e5-87ea-e6de215a9d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691609618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3691609618
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.3227834580
Short name T424
Test name
Test status
Simulation time 12184696269 ps
CPU time 18.28 seconds
Started Aug 14 05:01:33 PM PDT 24
Finished Aug 14 05:01:51 PM PDT 24
Peak memory 200840 kb
Host smart-47e22e56-193c-45c7-9996-bde0e867c04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227834580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3227834580
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.95905232
Short name T735
Test name
Test status
Simulation time 46636869282 ps
CPU time 36.42 seconds
Started Aug 14 05:01:34 PM PDT 24
Finished Aug 14 05:02:10 PM PDT 24
Peak memory 200860 kb
Host smart-2d49d10d-ce0f-4250-ab7b-1c9833a55b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95905232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.95905232
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.570489202
Short name T336
Test name
Test status
Simulation time 47436531194 ps
CPU time 69.16 seconds
Started Aug 14 05:01:34 PM PDT 24
Finished Aug 14 05:02:43 PM PDT 24
Peak memory 200044 kb
Host smart-9580e9e6-89d8-4103-b325-0e76238118c2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570489202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.570489202
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.1450848783
Short name T995
Test name
Test status
Simulation time 75195406907 ps
CPU time 494.71 seconds
Started Aug 14 05:01:45 PM PDT 24
Finished Aug 14 05:10:00 PM PDT 24
Peak memory 200792 kb
Host smart-a748629d-135d-4e6d-af21-d4d51f38d89e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1450848783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.1450848783
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3732151231
Short name T1036
Test name
Test status
Simulation time 2095228193 ps
CPU time 1.29 seconds
Started Aug 14 05:01:41 PM PDT 24
Finished Aug 14 05:01:42 PM PDT 24
Peak memory 198344 kb
Host smart-251b7aa4-16dc-4d4e-a215-8ce4df67b12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732151231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3732151231
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.1667883033
Short name T651
Test name
Test status
Simulation time 70856406115 ps
CPU time 19.47 seconds
Started Aug 14 05:01:32 PM PDT 24
Finished Aug 14 05:01:51 PM PDT 24
Peak memory 200852 kb
Host smart-c13dcf9b-6d52-4b31-b10c-f26ac9622266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667883033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1667883033
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.1457694522
Short name T293
Test name
Test status
Simulation time 14221844005 ps
CPU time 217.41 seconds
Started Aug 14 05:01:45 PM PDT 24
Finished Aug 14 05:05:22 PM PDT 24
Peak memory 200780 kb
Host smart-ce530044-68bb-43cd-af71-8311d95120be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1457694522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1457694522
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1444541318
Short name T612
Test name
Test status
Simulation time 4299761840 ps
CPU time 27.82 seconds
Started Aug 14 05:01:32 PM PDT 24
Finished Aug 14 05:02:00 PM PDT 24
Peak memory 198684 kb
Host smart-d61b9800-0d13-4181-9e25-bc038df1b031
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1444541318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1444541318
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1379394998
Short name T142
Test name
Test status
Simulation time 47351650862 ps
CPU time 19 seconds
Started Aug 14 05:01:42 PM PDT 24
Finished Aug 14 05:02:01 PM PDT 24
Peak memory 200872 kb
Host smart-81400d9c-6124-4863-947a-65b473e04d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379394998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1379394998
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3927830231
Short name T572
Test name
Test status
Simulation time 32944421753 ps
CPU time 51.49 seconds
Started Aug 14 05:01:43 PM PDT 24
Finished Aug 14 05:02:34 PM PDT 24
Peak memory 197248 kb
Host smart-02fa17c3-135d-4f1c-83f9-ca05fdf9b06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927830231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3927830231
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2544144331
Short name T733
Test name
Test status
Simulation time 290790835 ps
CPU time 1.34 seconds
Started Aug 14 05:01:33 PM PDT 24
Finished Aug 14 05:01:34 PM PDT 24
Peak memory 199004 kb
Host smart-990af949-ab78-4d73-be7b-6f60975042ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544144331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2544144331
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.2048478736
Short name T1108
Test name
Test status
Simulation time 109005393288 ps
CPU time 191.9 seconds
Started Aug 14 05:01:41 PM PDT 24
Finished Aug 14 05:04:53 PM PDT 24
Peak memory 209308 kb
Host smart-b40751b9-1f03-4ce4-809a-8701bd045eb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048478736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2048478736
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2383419274
Short name T487
Test name
Test status
Simulation time 6736934590 ps
CPU time 16.81 seconds
Started Aug 14 05:01:40 PM PDT 24
Finished Aug 14 05:01:56 PM PDT 24
Peak memory 200720 kb
Host smart-e598df62-b32a-475a-ad74-8ff4117e1b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383419274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2383419274
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1375765935
Short name T1182
Test name
Test status
Simulation time 12807206431 ps
CPU time 10.22 seconds
Started Aug 14 05:01:33 PM PDT 24
Finished Aug 14 05:01:43 PM PDT 24
Peak memory 200704 kb
Host smart-31ac6f27-4a4f-4286-9556-90dd1cfa0126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375765935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1375765935
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3953947017
Short name T870
Test name
Test status
Simulation time 44337743 ps
CPU time 0.54 seconds
Started Aug 14 05:01:42 PM PDT 24
Finished Aug 14 05:01:43 PM PDT 24
Peak memory 196256 kb
Host smart-7b78ea04-b151-4544-b2cf-f0c55ea2912c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953947017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3953947017
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.1427039099
Short name T883
Test name
Test status
Simulation time 18642204326 ps
CPU time 31.82 seconds
Started Aug 14 05:01:41 PM PDT 24
Finished Aug 14 05:02:13 PM PDT 24
Peak memory 200948 kb
Host smart-8d03bb32-1716-4ccd-88dd-0713441c4b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427039099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1427039099
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3903787662
Short name T672
Test name
Test status
Simulation time 249879069027 ps
CPU time 306.57 seconds
Started Aug 14 05:01:41 PM PDT 24
Finished Aug 14 05:06:48 PM PDT 24
Peak memory 200964 kb
Host smart-80d385f7-a016-4bb6-b35e-d4ba94d690cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903787662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3903787662
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.1202833563
Short name T625
Test name
Test status
Simulation time 32553796871 ps
CPU time 24.38 seconds
Started Aug 14 05:01:41 PM PDT 24
Finished Aug 14 05:02:06 PM PDT 24
Peak memory 200820 kb
Host smart-59b67b4f-e699-43c8-81fc-d6b8fbb75995
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202833563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1202833563
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.2401723765
Short name T757
Test name
Test status
Simulation time 100782708943 ps
CPU time 146.13 seconds
Started Aug 14 05:01:41 PM PDT 24
Finished Aug 14 05:04:07 PM PDT 24
Peak memory 201000 kb
Host smart-bbb51393-dc10-4e3f-b76f-46638345b05a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2401723765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2401723765
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3054405193
Short name T446
Test name
Test status
Simulation time 8582742834 ps
CPU time 10.73 seconds
Started Aug 14 05:01:41 PM PDT 24
Finished Aug 14 05:01:52 PM PDT 24
Peak memory 198036 kb
Host smart-7e18a19d-cf9a-4b27-a878-b4960d0e34c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054405193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3054405193
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3320535445
Short name T1018
Test name
Test status
Simulation time 91564201602 ps
CPU time 47 seconds
Started Aug 14 05:01:42 PM PDT 24
Finished Aug 14 05:02:29 PM PDT 24
Peak memory 209280 kb
Host smart-4f11bfb9-e437-4896-bd07-5e988994e664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320535445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3320535445
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3329106277
Short name T37
Test name
Test status
Simulation time 8327095616 ps
CPU time 476.83 seconds
Started Aug 14 05:01:40 PM PDT 24
Finished Aug 14 05:09:37 PM PDT 24
Peak memory 200804 kb
Host smart-8292e8fc-f102-4ef3-94ce-96d0719ac06d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3329106277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3329106277
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3103966710
Short name T365
Test name
Test status
Simulation time 4849153559 ps
CPU time 40.2 seconds
Started Aug 14 05:01:42 PM PDT 24
Finished Aug 14 05:02:22 PM PDT 24
Peak memory 197516 kb
Host smart-056f6087-e8e6-46c0-a400-ae7565676aa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3103966710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3103966710
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.333631820
Short name T90
Test name
Test status
Simulation time 214942945799 ps
CPU time 159.97 seconds
Started Aug 14 05:01:41 PM PDT 24
Finished Aug 14 05:04:21 PM PDT 24
Peak memory 200848 kb
Host smart-d24dfb35-3670-4a4f-978a-397d66027ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333631820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.333631820
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3845943179
Short name T556
Test name
Test status
Simulation time 709222808 ps
CPU time 0.96 seconds
Started Aug 14 05:01:42 PM PDT 24
Finished Aug 14 05:01:43 PM PDT 24
Peak memory 194784 kb
Host smart-8797c2d9-05fe-43d7-93d4-6ad80894eb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845943179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3845943179
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3530009343
Short name T801
Test name
Test status
Simulation time 107267999 ps
CPU time 0.99 seconds
Started Aug 14 05:01:41 PM PDT 24
Finished Aug 14 05:01:43 PM PDT 24
Peak memory 197896 kb
Host smart-d9e9e461-bf83-4586-9d93-3e14820bad96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530009343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3530009343
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.2380647843
Short name T902
Test name
Test status
Simulation time 130267393480 ps
CPU time 186.34 seconds
Started Aug 14 05:01:42 PM PDT 24
Finished Aug 14 05:04:48 PM PDT 24
Peak memory 200900 kb
Host smart-299aae65-5a36-4717-9c29-838ccd2e0c83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380647843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2380647843
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3294586965
Short name T396
Test name
Test status
Simulation time 9298377721 ps
CPU time 45.37 seconds
Started Aug 14 05:01:41 PM PDT 24
Finished Aug 14 05:02:27 PM PDT 24
Peak memory 216724 kb
Host smart-51685331-6fdc-45cd-bec4-30adc40bf48c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294586965 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3294586965
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3328934701
Short name T859
Test name
Test status
Simulation time 1026229095 ps
CPU time 1.97 seconds
Started Aug 14 05:01:42 PM PDT 24
Finished Aug 14 05:01:44 PM PDT 24
Peak memory 199444 kb
Host smart-d4a16388-9874-4869-9aa4-baee6bfa531a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328934701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3328934701
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1110426949
Short name T760
Test name
Test status
Simulation time 1054584085 ps
CPU time 0.84 seconds
Started Aug 14 05:01:40 PM PDT 24
Finished Aug 14 05:01:41 PM PDT 24
Peak memory 198472 kb
Host smart-891b43cc-b09d-4d58-81d3-702e5d1419c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110426949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1110426949
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.665329995
Short name T23
Test name
Test status
Simulation time 21331910 ps
CPU time 0.54 seconds
Started Aug 14 05:01:50 PM PDT 24
Finished Aug 14 05:01:51 PM PDT 24
Peak memory 196276 kb
Host smart-ea719088-5806-4a7e-b127-9ea239c89141
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665329995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.665329995
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3216655302
Short name T469
Test name
Test status
Simulation time 47093462699 ps
CPU time 35.42 seconds
Started Aug 14 05:01:41 PM PDT 24
Finished Aug 14 05:02:17 PM PDT 24
Peak memory 200888 kb
Host smart-9147f3b6-c553-4fe6-a374-e4bb9d3ed188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216655302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3216655302
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3472625412
Short name T648
Test name
Test status
Simulation time 37536211962 ps
CPU time 18.51 seconds
Started Aug 14 05:01:50 PM PDT 24
Finished Aug 14 05:02:08 PM PDT 24
Peak memory 200936 kb
Host smart-8e5e345c-e8ca-4673-9eb6-a2600267a965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472625412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3472625412
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3901197829
Short name T526
Test name
Test status
Simulation time 123606193136 ps
CPU time 133.24 seconds
Started Aug 14 05:01:49 PM PDT 24
Finished Aug 14 05:04:02 PM PDT 24
Peak memory 200968 kb
Host smart-9b5afdd4-05ff-4f58-966a-e83b6e28c310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901197829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3901197829
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1212253878
Short name T333
Test name
Test status
Simulation time 94492868879 ps
CPU time 119.38 seconds
Started Aug 14 05:01:53 PM PDT 24
Finished Aug 14 05:03:53 PM PDT 24
Peak memory 198588 kb
Host smart-4a0e73dc-5c1b-462b-903a-d62a6b0696d6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212253878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1212253878
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2698121643
Short name T411
Test name
Test status
Simulation time 200826490596 ps
CPU time 205.65 seconds
Started Aug 14 05:01:50 PM PDT 24
Finished Aug 14 05:05:16 PM PDT 24
Peak memory 200816 kb
Host smart-cd6d60fa-2046-46ee-8645-f19925429110
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2698121643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2698121643
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.1650131781
Short name T1021
Test name
Test status
Simulation time 8654814968 ps
CPU time 17.9 seconds
Started Aug 14 05:01:49 PM PDT 24
Finished Aug 14 05:02:07 PM PDT 24
Peak memory 199692 kb
Host smart-72962633-27e5-4640-8719-ca77235dffd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650131781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1650131781
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.4210812780
Short name T701
Test name
Test status
Simulation time 142201256342 ps
CPU time 159.11 seconds
Started Aug 14 05:01:49 PM PDT 24
Finished Aug 14 05:04:28 PM PDT 24
Peak memory 209312 kb
Host smart-d7030222-b4af-47a1-beb8-99c3fc0f136a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210812780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.4210812780
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.2030585887
Short name T1178
Test name
Test status
Simulation time 20047494571 ps
CPU time 1161.19 seconds
Started Aug 14 05:01:50 PM PDT 24
Finished Aug 14 05:21:11 PM PDT 24
Peak memory 200936 kb
Host smart-45316f97-419c-4714-8e37-fc2799ec2d52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2030585887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2030585887
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.57056923
Short name T967
Test name
Test status
Simulation time 2339485398 ps
CPU time 8.25 seconds
Started Aug 14 05:01:51 PM PDT 24
Finished Aug 14 05:01:59 PM PDT 24
Peak memory 199104 kb
Host smart-31561a58-06d2-4c28-a29b-ff1422c61db0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57056923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.57056923
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3554323349
Short name T860
Test name
Test status
Simulation time 39830859232 ps
CPU time 62.26 seconds
Started Aug 14 05:01:50 PM PDT 24
Finished Aug 14 05:02:53 PM PDT 24
Peak memory 200976 kb
Host smart-dd911801-75b2-4dc4-a218-0caa1e6168e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554323349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3554323349
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1338189267
Short name T867
Test name
Test status
Simulation time 34547960928 ps
CPU time 13.36 seconds
Started Aug 14 05:02:04 PM PDT 24
Finished Aug 14 05:02:18 PM PDT 24
Peak memory 197376 kb
Host smart-2929096b-cba7-449d-a5f1-150283cba080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338189267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1338189267
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.2912841474
Short name T476
Test name
Test status
Simulation time 928192201 ps
CPU time 1.38 seconds
Started Aug 14 05:01:40 PM PDT 24
Finished Aug 14 05:01:41 PM PDT 24
Peak memory 199836 kb
Host smart-c80e035e-2b8b-4399-8acb-da086d1fe10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912841474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2912841474
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.3138412505
Short name T920
Test name
Test status
Simulation time 544559923123 ps
CPU time 126.82 seconds
Started Aug 14 05:01:51 PM PDT 24
Finished Aug 14 05:03:58 PM PDT 24
Peak memory 201016 kb
Host smart-0ad63978-dd9e-497a-94bb-929c9a42a402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138412505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3138412505
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2910233533
Short name T908
Test name
Test status
Simulation time 6860455919 ps
CPU time 40.63 seconds
Started Aug 14 05:01:50 PM PDT 24
Finished Aug 14 05:02:30 PM PDT 24
Peak memory 216316 kb
Host smart-aa4fb305-99e4-466b-b4fc-4504b3cd3b2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910233533 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2910233533
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3852613912
Short name T318
Test name
Test status
Simulation time 2053188474 ps
CPU time 2.24 seconds
Started Aug 14 05:01:49 PM PDT 24
Finished Aug 14 05:01:51 PM PDT 24
Peak memory 199328 kb
Host smart-b760587f-b9d6-4733-9fc2-228325148b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852613912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3852613912
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.3280270863
Short name T1028
Test name
Test status
Simulation time 38676508505 ps
CPU time 16.14 seconds
Started Aug 14 05:01:41 PM PDT 24
Finished Aug 14 05:01:58 PM PDT 24
Peak memory 200832 kb
Host smart-31c49890-4d1d-4b2d-bc7e-61b4826c9352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280270863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3280270863
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3058149780
Short name T615
Test name
Test status
Simulation time 12434528 ps
CPU time 0.6 seconds
Started Aug 14 05:01:51 PM PDT 24
Finished Aug 14 05:01:51 PM PDT 24
Peak memory 195456 kb
Host smart-d699f195-1f97-4b3c-94d6-3a2a6fa77eae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058149780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3058149780
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.2205660868
Short name T674
Test name
Test status
Simulation time 111248912624 ps
CPU time 74.23 seconds
Started Aug 14 05:01:50 PM PDT 24
Finished Aug 14 05:03:04 PM PDT 24
Peak memory 200956 kb
Host smart-d2195cf9-d738-4371-b2a3-a30430d6e140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205660868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2205660868
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3503926376
Short name T563
Test name
Test status
Simulation time 164715399368 ps
CPU time 50.08 seconds
Started Aug 14 05:01:51 PM PDT 24
Finished Aug 14 05:02:41 PM PDT 24
Peak memory 200772 kb
Host smart-3779f1c8-ab61-4f69-a385-ce33b9e273bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503926376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3503926376
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2271428710
Short name T397
Test name
Test status
Simulation time 26335675252 ps
CPU time 52.53 seconds
Started Aug 14 05:01:50 PM PDT 24
Finished Aug 14 05:02:43 PM PDT 24
Peak memory 200884 kb
Host smart-e9f517b6-df37-443f-9784-7f8f3e9a6a52
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271428710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2271428710
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1751994116
Short name T536
Test name
Test status
Simulation time 181467448896 ps
CPU time 193.54 seconds
Started Aug 14 05:01:52 PM PDT 24
Finished Aug 14 05:05:06 PM PDT 24
Peak memory 200980 kb
Host smart-1a8c9865-21b7-445c-a2fa-e46930f5be0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1751994116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1751994116
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.3200694844
Short name T647
Test name
Test status
Simulation time 12503648151 ps
CPU time 23.64 seconds
Started Aug 14 05:01:52 PM PDT 24
Finished Aug 14 05:02:16 PM PDT 24
Peak memory 200904 kb
Host smart-bdd2b53c-964f-430e-bc09-cdb19d58fe8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200694844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3200694844
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.2011938570
Short name T874
Test name
Test status
Simulation time 84625932092 ps
CPU time 31.12 seconds
Started Aug 14 05:01:49 PM PDT 24
Finished Aug 14 05:02:20 PM PDT 24
Peak memory 200984 kb
Host smart-3bcbb02c-a655-426c-8e89-c8c9e7b78493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011938570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.2011938570
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.3343605021
Short name T511
Test name
Test status
Simulation time 21992441479 ps
CPU time 691.91 seconds
Started Aug 14 05:01:50 PM PDT 24
Finished Aug 14 05:13:23 PM PDT 24
Peak memory 200796 kb
Host smart-0eb0335f-2864-4416-894a-24d8c14516f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3343605021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3343605021
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.4094694668
Short name T623
Test name
Test status
Simulation time 7022247207 ps
CPU time 14.2 seconds
Started Aug 14 05:01:49 PM PDT 24
Finished Aug 14 05:02:03 PM PDT 24
Peak memory 200508 kb
Host smart-ca66b55e-dba7-414b-a55c-97bf1cdec217
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4094694668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.4094694668
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.28924615
Short name T530
Test name
Test status
Simulation time 106985241184 ps
CPU time 42.8 seconds
Started Aug 14 05:01:51 PM PDT 24
Finished Aug 14 05:02:34 PM PDT 24
Peak memory 200784 kb
Host smart-c3c53fcc-8f91-45af-bf36-b124fb4cbfe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28924615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.28924615
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2383086015
Short name T277
Test name
Test status
Simulation time 4154671886 ps
CPU time 6.71 seconds
Started Aug 14 05:01:51 PM PDT 24
Finished Aug 14 05:01:58 PM PDT 24
Peak memory 197116 kb
Host smart-15d10ef8-242e-4e89-8d43-9905325d6166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383086015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2383086015
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2710326602
Short name T1160
Test name
Test status
Simulation time 5381696007 ps
CPU time 20.29 seconds
Started Aug 14 05:01:50 PM PDT 24
Finished Aug 14 05:02:10 PM PDT 24
Peak memory 200392 kb
Host smart-a3a6275b-c882-468b-87e4-5eb8dcec45e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710326602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2710326602
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1133847755
Short name T597
Test name
Test status
Simulation time 7017008813 ps
CPU time 10.33 seconds
Started Aug 14 05:01:50 PM PDT 24
Finished Aug 14 05:02:00 PM PDT 24
Peak memory 200384 kb
Host smart-1a534ecc-e5f6-4454-99e5-94420e69fe24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133847755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1133847755
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.1933283845
Short name T9
Test name
Test status
Simulation time 24571634097 ps
CPU time 38.47 seconds
Started Aug 14 05:01:49 PM PDT 24
Finished Aug 14 05:02:28 PM PDT 24
Peak memory 200820 kb
Host smart-d98b9ab2-4485-4734-8377-4c2c1ac057b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933283845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1933283845
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.823855849
Short name T921
Test name
Test status
Simulation time 35044697 ps
CPU time 0.59 seconds
Started Aug 14 05:02:02 PM PDT 24
Finished Aug 14 05:02:03 PM PDT 24
Peak memory 196596 kb
Host smart-a35f728a-737a-4c0b-bd2f-8e3b628a2372
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823855849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.823855849
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2333946246
Short name T110
Test name
Test status
Simulation time 84970712665 ps
CPU time 156.56 seconds
Started Aug 14 05:01:50 PM PDT 24
Finished Aug 14 05:04:27 PM PDT 24
Peak memory 200792 kb
Host smart-b2dc127f-e211-47b4-b3ca-27a61ecc2724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333946246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2333946246
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.720321362
Short name T1167
Test name
Test status
Simulation time 27977409484 ps
CPU time 25.62 seconds
Started Aug 14 05:01:52 PM PDT 24
Finished Aug 14 05:02:18 PM PDT 24
Peak memory 200852 kb
Host smart-bcfce7ad-f08a-431f-aa05-68a10109b779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720321362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.720321362
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_intr.3751272547
Short name T1164
Test name
Test status
Simulation time 7324411484 ps
CPU time 4.69 seconds
Started Aug 14 05:01:58 PM PDT 24
Finished Aug 14 05:02:03 PM PDT 24
Peak memory 200988 kb
Host smart-66a51165-09e2-43ae-bdf6-e94f856137bd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751272547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3751272547
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1463636831
Short name T1124
Test name
Test status
Simulation time 92444104373 ps
CPU time 217.02 seconds
Started Aug 14 05:02:00 PM PDT 24
Finished Aug 14 05:05:37 PM PDT 24
Peak memory 200904 kb
Host smart-9680ad0a-dceb-4ac7-b95e-912b4e291378
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1463636831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1463636831
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.3727118390
Short name T686
Test name
Test status
Simulation time 2580109676 ps
CPU time 2.05 seconds
Started Aug 14 05:01:58 PM PDT 24
Finished Aug 14 05:02:00 PM PDT 24
Peak memory 198812 kb
Host smart-e1ba4b06-9f97-4690-96b9-0897248a4505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727118390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.3727118390
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.2879591052
Short name T272
Test name
Test status
Simulation time 91002456976 ps
CPU time 131.04 seconds
Started Aug 14 05:01:59 PM PDT 24
Finished Aug 14 05:04:11 PM PDT 24
Peak memory 209228 kb
Host smart-f6514f29-f43d-4d05-b9fe-1bb819b7903e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879591052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2879591052
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1289374090
Short name T901
Test name
Test status
Simulation time 16439837160 ps
CPU time 445.96 seconds
Started Aug 14 05:01:59 PM PDT 24
Finished Aug 14 05:09:25 PM PDT 24
Peak memory 200944 kb
Host smart-7bdbbf17-da50-48fa-9b18-80404fbc7600
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1289374090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1289374090
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.2228257512
Short name T562
Test name
Test status
Simulation time 3196712509 ps
CPU time 7.01 seconds
Started Aug 14 05:01:59 PM PDT 24
Finished Aug 14 05:02:06 PM PDT 24
Peak memory 199240 kb
Host smart-d32bb9c1-7cae-40e9-a820-11ce743cf5cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2228257512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2228257512
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2238978952
Short name T129
Test name
Test status
Simulation time 109897817267 ps
CPU time 46.94 seconds
Started Aug 14 05:01:59 PM PDT 24
Finished Aug 14 05:02:47 PM PDT 24
Peak memory 200904 kb
Host smart-50836287-25c4-4ee1-960e-cebe366a0550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238978952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2238978952
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.3896960183
Short name T426
Test name
Test status
Simulation time 593929915 ps
CPU time 1.56 seconds
Started Aug 14 05:02:00 PM PDT 24
Finished Aug 14 05:02:02 PM PDT 24
Peak memory 196480 kb
Host smart-21c37680-fe25-48bd-832c-76cb50af197d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896960183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3896960183
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.772206220
Short name T794
Test name
Test status
Simulation time 307121168 ps
CPU time 1.48 seconds
Started Aug 14 05:01:50 PM PDT 24
Finished Aug 14 05:01:52 PM PDT 24
Peak memory 200088 kb
Host smart-092243fc-0504-4d45-b3de-2fb52aa50978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772206220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.772206220
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2011875630
Short name T1020
Test name
Test status
Simulation time 263038655696 ps
CPU time 336.5 seconds
Started Aug 14 05:02:01 PM PDT 24
Finished Aug 14 05:07:37 PM PDT 24
Peak memory 200888 kb
Host smart-def16c36-e1a3-4912-b661-16f3a20dba04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011875630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2011875630
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.2867894789
Short name T1058
Test name
Test status
Simulation time 8051882795 ps
CPU time 141.71 seconds
Started Aug 14 05:01:58 PM PDT 24
Finished Aug 14 05:04:20 PM PDT 24
Peak memory 209232 kb
Host smart-d154f65b-d2ac-42ce-8cf6-0427f666dbb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867894789 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.2867894789
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.645070374
Short name T393
Test name
Test status
Simulation time 307925463 ps
CPU time 1.06 seconds
Started Aug 14 05:02:00 PM PDT 24
Finished Aug 14 05:02:01 PM PDT 24
Peak memory 199368 kb
Host smart-bcc99bc9-f2ad-47e5-a555-f89f535d14ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645070374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.645070374
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.513864654
Short name T300
Test name
Test status
Simulation time 116374106084 ps
CPU time 47.27 seconds
Started Aug 14 05:01:49 PM PDT 24
Finished Aug 14 05:02:37 PM PDT 24
Peak memory 200968 kb
Host smart-90d997b0-e85f-48e6-8b50-f8e11c08eb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513864654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.513864654
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.2167482156
Short name T519
Test name
Test status
Simulation time 14307187 ps
CPU time 0.58 seconds
Started Aug 14 04:59:09 PM PDT 24
Finished Aug 14 04:59:10 PM PDT 24
Peak memory 196276 kb
Host smart-d0d26b95-d3aa-42d2-8a10-09da57c19fc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167482156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2167482156
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.977324468
Short name T555
Test name
Test status
Simulation time 80456566267 ps
CPU time 67.47 seconds
Started Aug 14 04:58:59 PM PDT 24
Finished Aug 14 05:00:06 PM PDT 24
Peak memory 200944 kb
Host smart-52eb1a71-2f87-43d3-8458-37a9298fd53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977324468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.977324468
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3679838732
Short name T1042
Test name
Test status
Simulation time 23105059925 ps
CPU time 37.22 seconds
Started Aug 14 04:59:09 PM PDT 24
Finished Aug 14 04:59:46 PM PDT 24
Peak memory 200884 kb
Host smart-396398ee-9485-4a5e-b4c3-8cabeee107bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679838732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3679838732
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.501439038
Short name T782
Test name
Test status
Simulation time 91936142796 ps
CPU time 75.59 seconds
Started Aug 14 04:59:07 PM PDT 24
Finished Aug 14 05:00:23 PM PDT 24
Peak memory 200952 kb
Host smart-55667268-f0ce-446c-b7f0-70decc0cb2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501439038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.501439038
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.3227500759
Short name T18
Test name
Test status
Simulation time 47561979968 ps
CPU time 22.95 seconds
Started Aug 14 04:59:08 PM PDT 24
Finished Aug 14 04:59:32 PM PDT 24
Peak memory 200784 kb
Host smart-427ba3f9-57bf-46a3-a748-431be8c225be
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227500759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3227500759
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.577002173
Short name T250
Test name
Test status
Simulation time 58928225644 ps
CPU time 206.55 seconds
Started Aug 14 04:59:08 PM PDT 24
Finished Aug 14 05:02:34 PM PDT 24
Peak memory 200972 kb
Host smart-713da4b5-6195-49a1-9957-970c3832633a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=577002173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.577002173
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2548938275
Short name T19
Test name
Test status
Simulation time 5638430577 ps
CPU time 5.7 seconds
Started Aug 14 04:59:08 PM PDT 24
Finished Aug 14 04:59:14 PM PDT 24
Peak memory 200544 kb
Host smart-de0d2b75-fa06-44a8-b5f7-413aebc2a919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548938275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2548938275
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.2989813061
Short name T355
Test name
Test status
Simulation time 23822865857 ps
CPU time 6.64 seconds
Started Aug 14 04:59:13 PM PDT 24
Finished Aug 14 04:59:20 PM PDT 24
Peak memory 197384 kb
Host smart-14ca4ce9-6265-47e9-ac04-7627120965a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989813061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2989813061
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.2679965975
Short name T1077
Test name
Test status
Simulation time 21261250334 ps
CPU time 175.92 seconds
Started Aug 14 04:59:08 PM PDT 24
Finished Aug 14 05:02:04 PM PDT 24
Peak memory 200960 kb
Host smart-baf43589-51e1-4ca4-b7cd-204788418359
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2679965975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2679965975
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2529486966
Short name T936
Test name
Test status
Simulation time 4511158193 ps
CPU time 37.77 seconds
Started Aug 14 04:59:07 PM PDT 24
Finished Aug 14 04:59:45 PM PDT 24
Peak memory 200308 kb
Host smart-ec92f8f7-e668-40e4-8d0f-278282e77436
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2529486966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2529486966
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.4077433129
Short name T710
Test name
Test status
Simulation time 32972639670 ps
CPU time 26.75 seconds
Started Aug 14 04:59:09 PM PDT 24
Finished Aug 14 04:59:36 PM PDT 24
Peak memory 200932 kb
Host smart-444d8846-e416-4dc8-8fa2-dd9aee63f39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077433129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.4077433129
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.3336629564
Short name T378
Test name
Test status
Simulation time 2812579219 ps
CPU time 5.35 seconds
Started Aug 14 04:59:08 PM PDT 24
Finished Aug 14 04:59:13 PM PDT 24
Peak memory 196680 kb
Host smart-8184fcc5-20d9-4b41-b66c-7540cf1cb671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336629564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3336629564
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.208622657
Short name T28
Test name
Test status
Simulation time 70754443 ps
CPU time 0.76 seconds
Started Aug 14 04:59:09 PM PDT 24
Finished Aug 14 04:59:10 PM PDT 24
Peak memory 218992 kb
Host smart-af58c2a7-3afa-4458-8d4b-9cd50d0786c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208622657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.208622657
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.3026657092
Short name T608
Test name
Test status
Simulation time 290534811 ps
CPU time 1.17 seconds
Started Aug 14 04:58:56 PM PDT 24
Finished Aug 14 04:58:58 PM PDT 24
Peak memory 199360 kb
Host smart-381dce91-2b23-40a5-a6a2-29817cf1dedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026657092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3026657092
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2508966225
Short name T1177
Test name
Test status
Simulation time 302119688901 ps
CPU time 703.03 seconds
Started Aug 14 04:59:07 PM PDT 24
Finished Aug 14 05:10:51 PM PDT 24
Peak memory 200900 kb
Host smart-9c7b201e-532b-400b-88cf-cb596716937e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508966225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2508966225
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.2859546795
Short name T523
Test name
Test status
Simulation time 17895556883 ps
CPU time 119.03 seconds
Started Aug 14 04:59:08 PM PDT 24
Finished Aug 14 05:01:07 PM PDT 24
Peak memory 216632 kb
Host smart-e4d2d046-3adb-4a28-9cfc-b3ddbb3f5753
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859546795 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2859546795
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.589952908
Short name T321
Test name
Test status
Simulation time 7284385192 ps
CPU time 10.64 seconds
Started Aug 14 04:59:09 PM PDT 24
Finished Aug 14 04:59:20 PM PDT 24
Peak memory 200900 kb
Host smart-40837f54-4358-4f44-8774-3e5f16149cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589952908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.589952908
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.752294724
Short name T1146
Test name
Test status
Simulation time 44174125569 ps
CPU time 11.73 seconds
Started Aug 14 04:58:56 PM PDT 24
Finished Aug 14 04:59:08 PM PDT 24
Peak memory 198072 kb
Host smart-bc5a499a-b9b8-4f9f-b76a-7d331561ea39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752294724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.752294724
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2018161631
Short name T955
Test name
Test status
Simulation time 56912105 ps
CPU time 0.57 seconds
Started Aug 14 05:02:09 PM PDT 24
Finished Aug 14 05:02:09 PM PDT 24
Peak memory 196276 kb
Host smart-0573c5bf-8cf7-45ca-b601-3ce34c44c362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018161631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2018161631
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.962572688
Short name T1046
Test name
Test status
Simulation time 135328284593 ps
CPU time 96.85 seconds
Started Aug 14 05:01:59 PM PDT 24
Finished Aug 14 05:03:36 PM PDT 24
Peak memory 200880 kb
Host smart-90695786-2ef4-4e1e-85fe-a4af53abbd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962572688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.962572688
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.4106427319
Short name T681
Test name
Test status
Simulation time 182004423095 ps
CPU time 32.57 seconds
Started Aug 14 05:01:59 PM PDT 24
Finished Aug 14 05:02:32 PM PDT 24
Peak memory 199720 kb
Host smart-c954b395-9086-44ca-9051-ad4394457b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106427319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.4106427319
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.2410147437
Short name T3
Test name
Test status
Simulation time 101948436191 ps
CPU time 27.59 seconds
Started Aug 14 05:01:58 PM PDT 24
Finished Aug 14 05:02:26 PM PDT 24
Peak memory 200984 kb
Host smart-51166357-f1ba-40ef-896b-70c9a4c457d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410147437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2410147437
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.2499162511
Short name T96
Test name
Test status
Simulation time 53310803170 ps
CPU time 85.85 seconds
Started Aug 14 05:01:59 PM PDT 24
Finished Aug 14 05:03:25 PM PDT 24
Peak memory 200100 kb
Host smart-d118025a-8528-45fe-99e8-b99bb170feab
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499162511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2499162511
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3778197513
Short name T953
Test name
Test status
Simulation time 115154015911 ps
CPU time 292.32 seconds
Started Aug 14 05:02:07 PM PDT 24
Finished Aug 14 05:07:00 PM PDT 24
Peak memory 200956 kb
Host smart-f4331136-1fef-41e3-b921-a9abc457ccaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3778197513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3778197513
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.852870048
Short name T552
Test name
Test status
Simulation time 6117690790 ps
CPU time 10.89 seconds
Started Aug 14 05:02:02 PM PDT 24
Finished Aug 14 05:02:13 PM PDT 24
Peak memory 200112 kb
Host smart-3e3a945f-b85d-40e8-a611-9587d8c834af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852870048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.852870048
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.2879651046
Short name T322
Test name
Test status
Simulation time 131339214831 ps
CPU time 59.67 seconds
Started Aug 14 05:02:01 PM PDT 24
Finished Aug 14 05:03:01 PM PDT 24
Peak memory 201156 kb
Host smart-6afee309-e634-49c6-9f0b-f10ff47faabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879651046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2879651046
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.2868900948
Short name T732
Test name
Test status
Simulation time 6678075382 ps
CPU time 15.45 seconds
Started Aug 14 05:01:59 PM PDT 24
Finished Aug 14 05:02:15 PM PDT 24
Peak memory 199780 kb
Host smart-e62ba545-5bbf-4997-a16a-890d1fad4e78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2868900948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2868900948
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.560588646
Short name T665
Test name
Test status
Simulation time 6535110554 ps
CPU time 11.26 seconds
Started Aug 14 05:02:00 PM PDT 24
Finished Aug 14 05:02:12 PM PDT 24
Peak memory 200564 kb
Host smart-9038a624-a240-4ca9-b22c-3214ca0f899a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560588646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.560588646
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.364976949
Short name T520
Test name
Test status
Simulation time 3231660777 ps
CPU time 1.58 seconds
Started Aug 14 05:02:02 PM PDT 24
Finished Aug 14 05:02:04 PM PDT 24
Peak memory 196876 kb
Host smart-874fe960-ae4f-447d-88db-fd2f24f2bf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364976949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.364976949
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.1931107112
Short name T764
Test name
Test status
Simulation time 953704035 ps
CPU time 1.84 seconds
Started Aug 14 05:01:58 PM PDT 24
Finished Aug 14 05:01:59 PM PDT 24
Peak memory 199684 kb
Host smart-473e4936-93f2-4685-8f32-cd60bb8cd123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931107112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1931107112
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.2068459819
Short name T350
Test name
Test status
Simulation time 641202049730 ps
CPU time 76.52 seconds
Started Aug 14 05:02:08 PM PDT 24
Finished Aug 14 05:03:25 PM PDT 24
Peak memory 216760 kb
Host smart-7769a773-c750-4c47-a142-0e129375bd19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068459819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2068459819
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.1689342936
Short name T2
Test name
Test status
Simulation time 13382705088 ps
CPU time 7.54 seconds
Started Aug 14 05:02:00 PM PDT 24
Finished Aug 14 05:02:08 PM PDT 24
Peak memory 200800 kb
Host smart-7fc4b44f-6958-4e05-8c38-a3e7757486ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689342936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1689342936
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.2509201889
Short name T312
Test name
Test status
Simulation time 75078374394 ps
CPU time 58.74 seconds
Started Aug 14 05:02:01 PM PDT 24
Finished Aug 14 05:03:00 PM PDT 24
Peak memory 200896 kb
Host smart-de9fc853-0b9b-4748-83d7-9570fffa42ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509201889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2509201889
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1056184762
Short name T1130
Test name
Test status
Simulation time 23994114 ps
CPU time 0.57 seconds
Started Aug 14 05:02:08 PM PDT 24
Finished Aug 14 05:02:09 PM PDT 24
Peak memory 195144 kb
Host smart-b9b178e8-f8ab-4a11-8054-3d196149d40a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056184762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1056184762
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1545221863
Short name T756
Test name
Test status
Simulation time 57732973256 ps
CPU time 90.27 seconds
Started Aug 14 05:02:12 PM PDT 24
Finished Aug 14 05:03:42 PM PDT 24
Peak memory 200884 kb
Host smart-e92bf867-808f-4fb8-a17e-e0b94f96064a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545221863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1545221863
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2527162665
Short name T1185
Test name
Test status
Simulation time 184170665926 ps
CPU time 69.59 seconds
Started Aug 14 05:02:08 PM PDT 24
Finished Aug 14 05:03:18 PM PDT 24
Peak memory 200900 kb
Host smart-291807d6-a03b-4927-b331-c53a01b01f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527162665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2527162665
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_intr.3823447625
Short name T779
Test name
Test status
Simulation time 25126240821 ps
CPU time 30.89 seconds
Started Aug 14 05:02:10 PM PDT 24
Finished Aug 14 05:02:41 PM PDT 24
Peak memory 198692 kb
Host smart-a616e555-4d21-4691-ae90-8c136644afdf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823447625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3823447625
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3388278411
Short name T1152
Test name
Test status
Simulation time 65365201629 ps
CPU time 76.64 seconds
Started Aug 14 05:02:08 PM PDT 24
Finished Aug 14 05:03:25 PM PDT 24
Peak memory 200940 kb
Host smart-2eb1ae02-13e4-48c4-ae10-b8dca5d44cca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3388278411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3388278411
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3616104810
Short name T1000
Test name
Test status
Simulation time 2796031800 ps
CPU time 1.44 seconds
Started Aug 14 05:02:10 PM PDT 24
Finished Aug 14 05:02:12 PM PDT 24
Peak memory 199528 kb
Host smart-4b2b641b-2ff9-42f3-9e1d-70345e4efa00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616104810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3616104810
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.3986610096
Short name T468
Test name
Test status
Simulation time 74717590540 ps
CPU time 130.47 seconds
Started Aug 14 05:02:07 PM PDT 24
Finished Aug 14 05:04:18 PM PDT 24
Peak memory 209080 kb
Host smart-3cd98d86-7b4e-4315-9ea7-4f76e403cfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986610096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3986610096
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.2209831530
Short name T257
Test name
Test status
Simulation time 10421611448 ps
CPU time 563.8 seconds
Started Aug 14 05:02:09 PM PDT 24
Finished Aug 14 05:11:33 PM PDT 24
Peak memory 200500 kb
Host smart-0ac25bdf-d741-4516-b8c3-2106cb9a836e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2209831530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2209831530
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.2975563782
Short name T662
Test name
Test status
Simulation time 1408592536 ps
CPU time 0.93 seconds
Started Aug 14 05:02:07 PM PDT 24
Finished Aug 14 05:02:08 PM PDT 24
Peak memory 196444 kb
Host smart-9692e5c0-d63f-4c04-b3ad-2384f73f8e70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2975563782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2975563782
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2402881693
Short name T114
Test name
Test status
Simulation time 24046729171 ps
CPU time 38.23 seconds
Started Aug 14 05:02:07 PM PDT 24
Finished Aug 14 05:02:45 PM PDT 24
Peak memory 200888 kb
Host smart-64e1c4f8-f87f-4451-9af0-f46130475508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402881693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2402881693
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.800413940
Short name T542
Test name
Test status
Simulation time 1344407122 ps
CPU time 1.34 seconds
Started Aug 14 05:02:06 PM PDT 24
Finished Aug 14 05:02:07 PM PDT 24
Peak memory 196440 kb
Host smart-77fb8e65-a2d0-40e7-b614-0bf1cec80116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800413940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.800413940
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2883470570
Short name T320
Test name
Test status
Simulation time 5725747710 ps
CPU time 7.66 seconds
Started Aug 14 05:02:05 PM PDT 24
Finished Aug 14 05:02:13 PM PDT 24
Peak memory 200736 kb
Host smart-6ad6b8d9-1602-4913-b383-934e4789a62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883470570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2883470570
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.273190661
Short name T379
Test name
Test status
Simulation time 1853406400 ps
CPU time 24.09 seconds
Started Aug 14 05:02:08 PM PDT 24
Finished Aug 14 05:02:32 PM PDT 24
Peak memory 200920 kb
Host smart-de152fed-9734-4972-b9eb-8441bf443aa7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273190661 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.273190661
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2679706654
Short name T1072
Test name
Test status
Simulation time 2215580107 ps
CPU time 2.56 seconds
Started Aug 14 05:02:09 PM PDT 24
Finished Aug 14 05:02:12 PM PDT 24
Peak memory 200212 kb
Host smart-d66c04a3-7606-4a8c-84e9-bac94e4dcc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679706654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2679706654
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2547482767
Short name T440
Test name
Test status
Simulation time 75604071700 ps
CPU time 36.42 seconds
Started Aug 14 05:02:08 PM PDT 24
Finished Aug 14 05:02:45 PM PDT 24
Peak memory 200880 kb
Host smart-ba4ce518-ff1e-48cc-9047-bd23b13ba47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547482767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2547482767
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.439843004
Short name T374
Test name
Test status
Simulation time 18362014 ps
CPU time 0.56 seconds
Started Aug 14 05:02:10 PM PDT 24
Finished Aug 14 05:02:11 PM PDT 24
Peak memory 195596 kb
Host smart-477a7a1f-6f4e-466d-b914-0b93411e5912
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439843004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.439843004
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.3902788708
Short name T138
Test name
Test status
Simulation time 226789311812 ps
CPU time 49.82 seconds
Started Aug 14 05:02:08 PM PDT 24
Finished Aug 14 05:02:58 PM PDT 24
Peak memory 200888 kb
Host smart-ecae32e3-fc83-4451-9dff-4bffc39640bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902788708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3902788708
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3830699099
Short name T887
Test name
Test status
Simulation time 102442230561 ps
CPU time 41.54 seconds
Started Aug 14 05:02:08 PM PDT 24
Finished Aug 14 05:02:50 PM PDT 24
Peak memory 200788 kb
Host smart-b73d42d6-b569-48da-91e1-c7e6abd1cde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830699099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3830699099
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3476190272
Short name T1008
Test name
Test status
Simulation time 16987404591 ps
CPU time 24.57 seconds
Started Aug 14 05:02:11 PM PDT 24
Finished Aug 14 05:02:35 PM PDT 24
Peak memory 200904 kb
Host smart-aa7d773d-df4b-4847-b45e-49462fa0032a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476190272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3476190272
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2227677033
Short name T383
Test name
Test status
Simulation time 82084396325 ps
CPU time 48.46 seconds
Started Aug 14 05:02:10 PM PDT 24
Finished Aug 14 05:02:59 PM PDT 24
Peak memory 200844 kb
Host smart-d29b076e-0ece-4232-aec8-418db921de99
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227677033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2227677033
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2767075664
Short name T659
Test name
Test status
Simulation time 92534696697 ps
CPU time 183.98 seconds
Started Aug 14 05:02:07 PM PDT 24
Finished Aug 14 05:05:12 PM PDT 24
Peak memory 200840 kb
Host smart-6528264b-6f96-4080-bf0b-df6806d0eba1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2767075664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2767075664
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1979917606
Short name T1116
Test name
Test status
Simulation time 7287343905 ps
CPU time 8.44 seconds
Started Aug 14 05:02:07 PM PDT 24
Finished Aug 14 05:02:16 PM PDT 24
Peak memory 200768 kb
Host smart-207ea5a9-2700-45da-b541-3e41314fa5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979917606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1979917606
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3221970415
Short name T569
Test name
Test status
Simulation time 3064979230 ps
CPU time 4.92 seconds
Started Aug 14 05:02:07 PM PDT 24
Finished Aug 14 05:02:12 PM PDT 24
Peak memory 200944 kb
Host smart-0052295b-4cc0-4c96-ad41-0ae5b1c04d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221970415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3221970415
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.4227253917
Short name T491
Test name
Test status
Simulation time 14660204324 ps
CPU time 106.26 seconds
Started Aug 14 05:02:11 PM PDT 24
Finished Aug 14 05:03:57 PM PDT 24
Peak memory 200952 kb
Host smart-7468dd27-3232-45f0-85a2-f8242461b7c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4227253917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.4227253917
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.1592030185
Short name T394
Test name
Test status
Simulation time 2354860146 ps
CPU time 3.05 seconds
Started Aug 14 05:02:09 PM PDT 24
Finished Aug 14 05:02:12 PM PDT 24
Peak memory 199088 kb
Host smart-48184b8d-fe50-4883-afa6-1493b3e9d82d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1592030185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.1592030185
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.2903729829
Short name T935
Test name
Test status
Simulation time 59948134936 ps
CPU time 88.85 seconds
Started Aug 14 05:02:12 PM PDT 24
Finished Aug 14 05:03:42 PM PDT 24
Peak memory 200792 kb
Host smart-5cb6dd9e-1098-440c-8bb4-78d1eb9b75bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903729829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2903729829
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.2303732969
Short name T408
Test name
Test status
Simulation time 1901015014 ps
CPU time 2.24 seconds
Started Aug 14 05:02:07 PM PDT 24
Finished Aug 14 05:02:09 PM PDT 24
Peak memory 196512 kb
Host smart-486743d7-ac7d-4eeb-a1c3-2c8bb39e5226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303732969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.2303732969
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.814307527
Short name T583
Test name
Test status
Simulation time 674389291 ps
CPU time 3.99 seconds
Started Aug 14 05:02:12 PM PDT 24
Finished Aug 14 05:02:16 PM PDT 24
Peak memory 200192 kb
Host smart-679221fd-00d6-46cb-896e-5ca8f070eba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814307527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.814307527
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.2485619769
Short name T723
Test name
Test status
Simulation time 176086606963 ps
CPU time 56.45 seconds
Started Aug 14 05:02:07 PM PDT 24
Finished Aug 14 05:03:04 PM PDT 24
Peak memory 200980 kb
Host smart-98a94512-d4df-4a4c-bb92-f281f3f5d215
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485619769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2485619769
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2806062013
Short name T823
Test name
Test status
Simulation time 5981600724 ps
CPU time 36.54 seconds
Started Aug 14 05:02:07 PM PDT 24
Finished Aug 14 05:02:43 PM PDT 24
Peak memory 216476 kb
Host smart-7723fc8d-66a2-4b33-ac09-3dea79417871
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806062013 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2806062013
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.4148613199
Short name T774
Test name
Test status
Simulation time 13887410114 ps
CPU time 18.1 seconds
Started Aug 14 05:02:08 PM PDT 24
Finished Aug 14 05:02:26 PM PDT 24
Peak memory 200880 kb
Host smart-63578272-2ecb-4e91-b1c9-836819242b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148613199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.4148613199
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.1893070217
Short name T273
Test name
Test status
Simulation time 193647164843 ps
CPU time 171.26 seconds
Started Aug 14 05:02:07 PM PDT 24
Finished Aug 14 05:04:59 PM PDT 24
Peak memory 200896 kb
Host smart-4ace5443-1034-496b-8ce4-69ce9ec18af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893070217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1893070217
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2312288374
Short name T532
Test name
Test status
Simulation time 12766037 ps
CPU time 0.57 seconds
Started Aug 14 05:02:19 PM PDT 24
Finished Aug 14 05:02:20 PM PDT 24
Peak memory 196200 kb
Host smart-0d40fd7e-8a91-43e1-a8ce-f8dbafe46b53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312288374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2312288374
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.2264006332
Short name T845
Test name
Test status
Simulation time 241385120103 ps
CPU time 235.52 seconds
Started Aug 14 05:02:18 PM PDT 24
Finished Aug 14 05:06:14 PM PDT 24
Peak memory 200864 kb
Host smart-f00137e1-6aa9-41a2-b5c8-57bc62eeab31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264006332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2264006332
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1785578414
Short name T113
Test name
Test status
Simulation time 89659238738 ps
CPU time 133.86 seconds
Started Aug 14 05:02:17 PM PDT 24
Finished Aug 14 05:04:30 PM PDT 24
Peak memory 200888 kb
Host smart-9374939e-b9d8-425c-8ef3-5b37562a1c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785578414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1785578414
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.715743785
Short name T1057
Test name
Test status
Simulation time 45400592338 ps
CPU time 24.19 seconds
Started Aug 14 05:02:18 PM PDT 24
Finished Aug 14 05:02:42 PM PDT 24
Peak memory 200880 kb
Host smart-c77c88c3-b211-4c16-a1b7-011b408a2d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715743785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.715743785
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.4137694701
Short name T865
Test name
Test status
Simulation time 44309970295 ps
CPU time 20.52 seconds
Started Aug 14 05:02:17 PM PDT 24
Finished Aug 14 05:02:38 PM PDT 24
Peak memory 200904 kb
Host smart-676d3f70-f66f-43ab-b6ef-7d4ba794624c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137694701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.4137694701
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.991667834
Short name T715
Test name
Test status
Simulation time 113128465375 ps
CPU time 176.3 seconds
Started Aug 14 05:02:19 PM PDT 24
Finished Aug 14 05:05:16 PM PDT 24
Peak memory 200976 kb
Host smart-702aa478-c1d5-4bd6-857d-f7c0279c6769
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=991667834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.991667834
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3873773798
Short name T1149
Test name
Test status
Simulation time 7620723560 ps
CPU time 7.36 seconds
Started Aug 14 05:02:18 PM PDT 24
Finished Aug 14 05:02:26 PM PDT 24
Peak memory 200752 kb
Host smart-730c7d8c-b8c9-47f1-997b-9091841a6378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873773798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3873773798
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.2161403109
Short name T518
Test name
Test status
Simulation time 15479136956 ps
CPU time 7.43 seconds
Started Aug 14 05:02:18 PM PDT 24
Finished Aug 14 05:02:26 PM PDT 24
Peak memory 196916 kb
Host smart-d0fc70c7-0c81-441d-9f4b-7d64af38732a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161403109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2161403109
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1897706888
Short name T728
Test name
Test status
Simulation time 20128545861 ps
CPU time 287.71 seconds
Started Aug 14 05:02:16 PM PDT 24
Finished Aug 14 05:07:04 PM PDT 24
Peak memory 200816 kb
Host smart-2006be00-40f0-490e-90a5-5091a812fe30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1897706888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1897706888
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.1339096062
Short name T387
Test name
Test status
Simulation time 2722008645 ps
CPU time 6.67 seconds
Started Aug 14 05:02:18 PM PDT 24
Finished Aug 14 05:02:24 PM PDT 24
Peak memory 199164 kb
Host smart-158718a3-e236-4df2-a81f-ec795c5bbf3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1339096062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1339096062
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.726276790
Short name T157
Test name
Test status
Simulation time 67440443708 ps
CPU time 29.38 seconds
Started Aug 14 05:02:17 PM PDT 24
Finished Aug 14 05:02:47 PM PDT 24
Peak memory 200824 kb
Host smart-4d5d0e6d-b2df-4db1-a11e-392c9641b1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726276790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.726276790
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.1182239058
Short name T436
Test name
Test status
Simulation time 4221094519 ps
CPU time 1.75 seconds
Started Aug 14 05:02:16 PM PDT 24
Finished Aug 14 05:02:17 PM PDT 24
Peak memory 197148 kb
Host smart-65b0e95d-36a1-4992-a222-563b6ec3a2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182239058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1182239058
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.436710713
Short name T677
Test name
Test status
Simulation time 301791468 ps
CPU time 1.16 seconds
Started Aug 14 05:02:17 PM PDT 24
Finished Aug 14 05:02:18 PM PDT 24
Peak memory 199068 kb
Host smart-58e4cd08-60c6-4355-844c-5df4c12ab7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436710713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.436710713
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.3632849263
Short name T1153
Test name
Test status
Simulation time 1511806274 ps
CPU time 27.16 seconds
Started Aug 14 05:02:19 PM PDT 24
Finished Aug 14 05:02:46 PM PDT 24
Peak memory 209360 kb
Host smart-9b6231e5-dc61-4274-9d6b-27b01b1452db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632849263 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.3632849263
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.409459379
Short name T256
Test name
Test status
Simulation time 1854532289 ps
CPU time 1.72 seconds
Started Aug 14 05:02:17 PM PDT 24
Finished Aug 14 05:02:19 PM PDT 24
Peak memory 199300 kb
Host smart-16d78d76-1076-4eae-8a06-6c9ac5b5890b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409459379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.409459379
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.4005416719
Short name T327
Test name
Test status
Simulation time 19810006745 ps
CPU time 8.22 seconds
Started Aug 14 05:02:17 PM PDT 24
Finished Aug 14 05:02:25 PM PDT 24
Peak memory 200664 kb
Host smart-416d60f1-db2a-4115-89fe-f8ef10935567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005416719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.4005416719
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.3398134504
Short name T403
Test name
Test status
Simulation time 14002504 ps
CPU time 0.58 seconds
Started Aug 14 05:02:25 PM PDT 24
Finished Aug 14 05:02:26 PM PDT 24
Peak memory 195248 kb
Host smart-4469f458-45ec-4c21-97c0-84c75dfdd5b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398134504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3398134504
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3393879742
Short name T270
Test name
Test status
Simulation time 149330350287 ps
CPU time 79.73 seconds
Started Aug 14 05:02:19 PM PDT 24
Finished Aug 14 05:03:39 PM PDT 24
Peak memory 200980 kb
Host smart-ad4519fd-4b4b-4983-bab9-2561bd6c009b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393879742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3393879742
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.538369085
Short name T212
Test name
Test status
Simulation time 7752594202 ps
CPU time 14.54 seconds
Started Aug 14 05:02:17 PM PDT 24
Finished Aug 14 05:02:32 PM PDT 24
Peak memory 200616 kb
Host smart-869cac7e-cdf8-4416-8af2-06f4e8e4ed10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538369085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.538369085
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.452408858
Short name T1023
Test name
Test status
Simulation time 34346221476 ps
CPU time 50.24 seconds
Started Aug 14 05:02:17 PM PDT 24
Finished Aug 14 05:03:07 PM PDT 24
Peak memory 199428 kb
Host smart-faaa288f-db64-40a6-a8a5-33fa6d888f1c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452408858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.452408858
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.3296803274
Short name T643
Test name
Test status
Simulation time 103508834932 ps
CPU time 308.02 seconds
Started Aug 14 05:02:26 PM PDT 24
Finished Aug 14 05:07:34 PM PDT 24
Peak memory 200852 kb
Host smart-eaca31d2-346b-48b4-9281-86f5be2dd612
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3296803274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3296803274
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.2728486704
Short name T433
Test name
Test status
Simulation time 5302053298 ps
CPU time 10.74 seconds
Started Aug 14 05:02:25 PM PDT 24
Finished Aug 14 05:02:36 PM PDT 24
Peak memory 199224 kb
Host smart-270acef4-7ad5-40a3-ab7d-448f8b05afb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728486704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2728486704
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.1892312045
Short name T894
Test name
Test status
Simulation time 107617807522 ps
CPU time 175.83 seconds
Started Aug 14 05:02:19 PM PDT 24
Finished Aug 14 05:05:15 PM PDT 24
Peak memory 201168 kb
Host smart-8e7a8063-e4e7-49b7-b570-2e9974971685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892312045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1892312045
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.767684911
Short name T1137
Test name
Test status
Simulation time 20593884170 ps
CPU time 1020.82 seconds
Started Aug 14 05:02:26 PM PDT 24
Finished Aug 14 05:19:27 PM PDT 24
Peak memory 200916 kb
Host smart-ba33ff83-7344-4d04-a354-97afedd70f0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=767684911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.767684911
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2280594300
Short name T1168
Test name
Test status
Simulation time 6970997750 ps
CPU time 14.32 seconds
Started Aug 14 05:02:20 PM PDT 24
Finished Aug 14 05:02:34 PM PDT 24
Peak memory 199612 kb
Host smart-6b3dde65-8d53-4625-bf95-41c535a9a1f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2280594300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2280594300
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1651708269
Short name T1032
Test name
Test status
Simulation time 61453071062 ps
CPU time 25.28 seconds
Started Aug 14 05:02:16 PM PDT 24
Finished Aug 14 05:02:42 PM PDT 24
Peak memory 200980 kb
Host smart-3543e42c-b10d-4b4e-9087-5f01e675c99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651708269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1651708269
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.3168223880
Short name T437
Test name
Test status
Simulation time 747940850 ps
CPU time 0.98 seconds
Started Aug 14 05:02:20 PM PDT 24
Finished Aug 14 05:02:21 PM PDT 24
Peak memory 196376 kb
Host smart-9da14b0d-b120-4b81-acbf-fda6e5ddfaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168223880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3168223880
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1772117856
Short name T610
Test name
Test status
Simulation time 646238546 ps
CPU time 1.57 seconds
Started Aug 14 05:02:17 PM PDT 24
Finished Aug 14 05:02:19 PM PDT 24
Peak memory 199704 kb
Host smart-e44d4cd1-73f2-463f-94bc-9bbc0debf814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772117856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1772117856
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.3285766998
Short name T1034
Test name
Test status
Simulation time 120971955763 ps
CPU time 821.22 seconds
Started Aug 14 05:02:26 PM PDT 24
Finished Aug 14 05:16:07 PM PDT 24
Peak memory 200972 kb
Host smart-82f1532e-40e1-4a9d-8063-b2c820095f71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285766998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3285766998
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.52155204
Short name T973
Test name
Test status
Simulation time 3662932103 ps
CPU time 32.56 seconds
Started Aug 14 05:02:24 PM PDT 24
Finished Aug 14 05:02:57 PM PDT 24
Peak memory 210388 kb
Host smart-b0fc7f65-6747-47be-8817-31324f6deff5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52155204 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.52155204
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.253841862
Short name T364
Test name
Test status
Simulation time 635778837 ps
CPU time 1.42 seconds
Started Aug 14 05:02:27 PM PDT 24
Finished Aug 14 05:02:28 PM PDT 24
Peak memory 199556 kb
Host smart-a298d478-5ec7-4961-830d-e3638073e267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253841862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.253841862
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3352020115
Short name T997
Test name
Test status
Simulation time 115024551645 ps
CPU time 222.17 seconds
Started Aug 14 05:02:17 PM PDT 24
Finished Aug 14 05:05:59 PM PDT 24
Peak memory 200880 kb
Host smart-06310a99-1ec4-4442-9d0a-1563864d7d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352020115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3352020115
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.4091433562
Short name T645
Test name
Test status
Simulation time 32868168 ps
CPU time 0.58 seconds
Started Aug 14 05:02:25 PM PDT 24
Finished Aug 14 05:02:26 PM PDT 24
Peak memory 196456 kb
Host smart-d15480af-bf2d-4678-9909-5aa949440bc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091433562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.4091433562
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.868695037
Short name T635
Test name
Test status
Simulation time 17619351763 ps
CPU time 6.64 seconds
Started Aug 14 05:02:26 PM PDT 24
Finished Aug 14 05:02:33 PM PDT 24
Peak memory 200760 kb
Host smart-0de152c3-a09b-4823-ab15-b5d411fb3da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868695037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.868695037
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.156288778
Short name T478
Test name
Test status
Simulation time 36982286831 ps
CPU time 56.97 seconds
Started Aug 14 05:02:24 PM PDT 24
Finished Aug 14 05:03:21 PM PDT 24
Peak memory 200628 kb
Host smart-6054ba8f-872b-4836-9e6c-0a4bcc0705a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156288778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.156288778
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2098507875
Short name T691
Test name
Test status
Simulation time 94170692692 ps
CPU time 79.88 seconds
Started Aug 14 05:02:34 PM PDT 24
Finished Aug 14 05:03:54 PM PDT 24
Peak memory 200952 kb
Host smart-5473e3c5-b2ac-44d1-9cb3-539d08f17200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098507875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2098507875
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.868067459
Short name T906
Test name
Test status
Simulation time 25347329542 ps
CPU time 47.84 seconds
Started Aug 14 05:02:26 PM PDT 24
Finished Aug 14 05:03:14 PM PDT 24
Peak memory 200964 kb
Host smart-7d0c9bd5-f076-43e9-a7a8-e1f6d8cc131e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868067459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.868067459
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.2016533087
Short name T251
Test name
Test status
Simulation time 91089290421 ps
CPU time 670.48 seconds
Started Aug 14 05:02:24 PM PDT 24
Finished Aug 14 05:13:35 PM PDT 24
Peak memory 200912 kb
Host smart-ddbd0799-4b87-4a70-b223-21b509580504
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2016533087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2016533087
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.4206519570
Short name T509
Test name
Test status
Simulation time 11161865830 ps
CPU time 4.73 seconds
Started Aug 14 05:02:29 PM PDT 24
Finished Aug 14 05:02:34 PM PDT 24
Peak memory 200560 kb
Host smart-46059bb5-2648-424d-9d2f-613739eabd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206519570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.4206519570
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.423546147
Short name T264
Test name
Test status
Simulation time 40345384700 ps
CPU time 77.53 seconds
Started Aug 14 05:02:27 PM PDT 24
Finished Aug 14 05:03:44 PM PDT 24
Peak memory 201112 kb
Host smart-e159e7d1-55b4-4ef4-bb6e-fb4a57098195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423546147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.423546147
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.917171894
Short name T714
Test name
Test status
Simulation time 5454719326 ps
CPU time 9.81 seconds
Started Aug 14 05:02:26 PM PDT 24
Finished Aug 14 05:02:36 PM PDT 24
Peak memory 199828 kb
Host smart-f16acb61-36e0-4302-bfe2-7abccb7636ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=917171894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.917171894
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.830278518
Short name T1003
Test name
Test status
Simulation time 68379019839 ps
CPU time 65.14 seconds
Started Aug 14 05:02:26 PM PDT 24
Finished Aug 14 05:03:32 PM PDT 24
Peak memory 200952 kb
Host smart-96ec3e09-cdbe-435e-8ba3-f633c871a3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830278518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.830278518
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3125612275
Short name T968
Test name
Test status
Simulation time 52539364129 ps
CPU time 38.18 seconds
Started Aug 14 05:02:26 PM PDT 24
Finished Aug 14 05:03:04 PM PDT 24
Peak memory 197420 kb
Host smart-2a5feba4-8783-4203-8f04-d0b043053959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125612275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3125612275
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.665667397
Short name T621
Test name
Test status
Simulation time 928698041 ps
CPU time 5.82 seconds
Started Aug 14 05:02:25 PM PDT 24
Finished Aug 14 05:02:30 PM PDT 24
Peak memory 200420 kb
Host smart-4b11dc5a-9053-4728-b10a-4ec90763f15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665667397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.665667397
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.896674405
Short name T833
Test name
Test status
Simulation time 293888109801 ps
CPU time 278.03 seconds
Started Aug 14 05:02:29 PM PDT 24
Finished Aug 14 05:07:07 PM PDT 24
Peak memory 200904 kb
Host smart-913dd534-6acf-43b5-9c80-4c22d19fd963
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896674405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.896674405
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1601960701
Short name T99
Test name
Test status
Simulation time 2898561576 ps
CPU time 34.61 seconds
Started Aug 14 05:02:26 PM PDT 24
Finished Aug 14 05:03:01 PM PDT 24
Peak memory 216600 kb
Host smart-fc043aae-a1e0-48d5-8d6b-4ca9b5f7b9a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601960701 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1601960701
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2978040600
Short name T540
Test name
Test status
Simulation time 2461854936 ps
CPU time 2.13 seconds
Started Aug 14 05:02:29 PM PDT 24
Finished Aug 14 05:02:31 PM PDT 24
Peak memory 200768 kb
Host smart-0a0dac62-9c26-46cf-bb02-ce5eed124ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978040600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2978040600
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1331881352
Short name T1024
Test name
Test status
Simulation time 154113538281 ps
CPU time 14.72 seconds
Started Aug 14 05:02:25 PM PDT 24
Finished Aug 14 05:02:39 PM PDT 24
Peak memory 200880 kb
Host smart-9472db70-348d-449f-9115-e1e488e7a4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331881352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1331881352
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2067688750
Short name T74
Test name
Test status
Simulation time 19077198 ps
CPU time 0.59 seconds
Started Aug 14 05:02:33 PM PDT 24
Finished Aug 14 05:02:34 PM PDT 24
Peak memory 196556 kb
Host smart-7f46e06d-5ddd-4b0a-8938-1fd4a26916fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067688750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2067688750
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.757223914
Short name T892
Test name
Test status
Simulation time 106518115210 ps
CPU time 159.34 seconds
Started Aug 14 05:02:25 PM PDT 24
Finished Aug 14 05:05:05 PM PDT 24
Peak memory 200900 kb
Host smart-4dc26f95-4dcb-4127-91bd-b26e84210d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757223914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.757223914
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3008395536
Short name T1162
Test name
Test status
Simulation time 174713869603 ps
CPU time 120.34 seconds
Started Aug 14 05:02:26 PM PDT 24
Finished Aug 14 05:04:26 PM PDT 24
Peak memory 200816 kb
Host smart-a5ba251f-0c4d-4d15-b6ca-f94681a83dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008395536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3008395536
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.1287513337
Short name T5
Test name
Test status
Simulation time 72720661030 ps
CPU time 57.11 seconds
Started Aug 14 05:02:24 PM PDT 24
Finished Aug 14 05:03:22 PM PDT 24
Peak memory 200864 kb
Host smart-6c7bd5e5-6238-4bb6-bdd9-817fc35c1f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287513337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1287513337
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.245657134
Short name T630
Test name
Test status
Simulation time 3138439380 ps
CPU time 5.29 seconds
Started Aug 14 05:02:26 PM PDT 24
Finished Aug 14 05:02:32 PM PDT 24
Peak memory 197732 kb
Host smart-98027d17-dceb-47d2-84db-2456cd0f2da1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245657134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.245657134
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.729799102
Short name T881
Test name
Test status
Simulation time 145397252883 ps
CPU time 578.01 seconds
Started Aug 14 05:02:34 PM PDT 24
Finished Aug 14 05:12:12 PM PDT 24
Peak memory 200956 kb
Host smart-796978f0-daf6-42e2-b8da-ae86ad42da7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=729799102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.729799102
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.3251387633
Short name T504
Test name
Test status
Simulation time 5785869581 ps
CPU time 11.51 seconds
Started Aug 14 05:02:34 PM PDT 24
Finished Aug 14 05:02:46 PM PDT 24
Peak memory 199856 kb
Host smart-4f385dc9-0f86-45ad-8554-4ed7077cb8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251387633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3251387633
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.4176324347
Short name T334
Test name
Test status
Simulation time 45019578192 ps
CPU time 17.24 seconds
Started Aug 14 05:02:25 PM PDT 24
Finished Aug 14 05:02:42 PM PDT 24
Peak memory 198604 kb
Host smart-9c33716f-aaa2-4a26-9bbd-51c8a8a22176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176324347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.4176324347
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.363370933
Short name T1092
Test name
Test status
Simulation time 18119454733 ps
CPU time 265.16 seconds
Started Aug 14 05:02:34 PM PDT 24
Finished Aug 14 05:07:00 PM PDT 24
Peak memory 200936 kb
Host smart-2fbc3370-18bd-4823-8443-c2c2605be893
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=363370933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.363370933
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.532483958
Short name T579
Test name
Test status
Simulation time 5788783569 ps
CPU time 14.16 seconds
Started Aug 14 05:02:25 PM PDT 24
Finished Aug 14 05:02:39 PM PDT 24
Peak memory 198652 kb
Host smart-a8cbc1cb-c44a-4752-acaa-be513b978f1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=532483958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.532483958
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1603017979
Short name T543
Test name
Test status
Simulation time 46453226811 ps
CPU time 69.69 seconds
Started Aug 14 05:02:34 PM PDT 24
Finished Aug 14 05:03:44 PM PDT 24
Peak memory 200900 kb
Host smart-5fe92809-b8d1-4f74-a01c-657177ecc6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603017979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1603017979
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1829031027
Short name T447
Test name
Test status
Simulation time 3123582744 ps
CPU time 5.18 seconds
Started Aug 14 05:02:24 PM PDT 24
Finished Aug 14 05:02:29 PM PDT 24
Peak memory 196880 kb
Host smart-e7f13f74-f80a-47cc-9602-378dd823fdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829031027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1829031027
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.37867240
Short name T1068
Test name
Test status
Simulation time 5678955197 ps
CPU time 14.17 seconds
Started Aug 14 05:02:26 PM PDT 24
Finished Aug 14 05:02:40 PM PDT 24
Peak memory 200096 kb
Host smart-d9227ec9-e6b1-461c-b6ee-b0490ca553ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37867240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.37867240
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.3375538488
Short name T1061
Test name
Test status
Simulation time 267020151967 ps
CPU time 721.7 seconds
Started Aug 14 05:02:39 PM PDT 24
Finished Aug 14 05:14:41 PM PDT 24
Peak memory 200892 kb
Host smart-0f8c8c32-57b2-4055-b456-207dd4b3d1b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375538488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3375538488
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2297012839
Short name T985
Test name
Test status
Simulation time 1697114284 ps
CPU time 11.21 seconds
Started Aug 14 05:02:34 PM PDT 24
Finished Aug 14 05:02:45 PM PDT 24
Peak memory 216664 kb
Host smart-8cea0a97-048b-45a3-a11e-aa1dfa17e6b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297012839 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2297012839
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3357080785
Short name T944
Test name
Test status
Simulation time 924971769 ps
CPU time 2.67 seconds
Started Aug 14 05:02:41 PM PDT 24
Finished Aug 14 05:02:44 PM PDT 24
Peak memory 199436 kb
Host smart-37fea580-1b4b-4e84-a6f9-331076fc625a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357080785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3357080785
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.2718866282
Short name T895
Test name
Test status
Simulation time 8792405451 ps
CPU time 4.67 seconds
Started Aug 14 05:02:28 PM PDT 24
Finished Aug 14 05:02:32 PM PDT 24
Peak memory 200976 kb
Host smart-432e34d9-e742-4127-923d-6f7cdda2cb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718866282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2718866282
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3809639448
Short name T482
Test name
Test status
Simulation time 19588513 ps
CPU time 0.59 seconds
Started Aug 14 05:02:35 PM PDT 24
Finished Aug 14 05:02:35 PM PDT 24
Peak memory 196316 kb
Host smart-4f09ab2f-258e-4f10-8f76-b929217f357a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809639448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3809639448
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.959945267
Short name T957
Test name
Test status
Simulation time 239183412969 ps
CPU time 123.11 seconds
Started Aug 14 05:02:36 PM PDT 24
Finished Aug 14 05:04:39 PM PDT 24
Peak memory 200880 kb
Host smart-de6524bf-4ea3-43dc-99fa-011b137732ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959945267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.959945267
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3342085469
Short name T147
Test name
Test status
Simulation time 61009131317 ps
CPU time 30.2 seconds
Started Aug 14 05:02:34 PM PDT 24
Finished Aug 14 05:03:04 PM PDT 24
Peak memory 200760 kb
Host smart-2cd070c8-031c-4692-9326-402e0cbe3664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342085469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3342085469
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3632141011
Short name T93
Test name
Test status
Simulation time 169378066700 ps
CPU time 111.62 seconds
Started Aug 14 05:02:41 PM PDT 24
Finished Aug 14 05:04:33 PM PDT 24
Peak memory 200900 kb
Host smart-b1a32e04-c844-40f0-bf5e-7dda8991d4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632141011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3632141011
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2032131893
Short name T1059
Test name
Test status
Simulation time 157055296321 ps
CPU time 82.47 seconds
Started Aug 14 05:02:36 PM PDT 24
Finished Aug 14 05:03:58 PM PDT 24
Peak memory 200848 kb
Host smart-4c34b3e9-45da-4cf9-ba42-52aeb2b568d3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032131893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2032131893
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.224605749
Short name T942
Test name
Test status
Simulation time 89787387059 ps
CPU time 202.56 seconds
Started Aug 14 05:02:34 PM PDT 24
Finished Aug 14 05:05:57 PM PDT 24
Peak memory 200896 kb
Host smart-54442767-df63-436b-83aa-277cfaa5eba5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=224605749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.224605749
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2961498053
Short name T1009
Test name
Test status
Simulation time 10922028482 ps
CPU time 6.94 seconds
Started Aug 14 05:02:42 PM PDT 24
Finished Aug 14 05:02:49 PM PDT 24
Peak memory 200848 kb
Host smart-0349854f-6cc9-47ee-a274-1056f8d8bd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961498053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2961498053
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.735643681
Short name T961
Test name
Test status
Simulation time 61608393011 ps
CPU time 348.6 seconds
Started Aug 14 05:02:36 PM PDT 24
Finished Aug 14 05:08:25 PM PDT 24
Peak memory 201148 kb
Host smart-33c0d286-5af1-4fb8-a59e-4cc1b15cc6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735643681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.735643681
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.4129762764
Short name T990
Test name
Test status
Simulation time 9526065875 ps
CPU time 235.55 seconds
Started Aug 14 05:02:33 PM PDT 24
Finished Aug 14 05:06:29 PM PDT 24
Peak memory 200824 kb
Host smart-e9c99142-b12b-4190-9532-ad8a9e7da8ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4129762764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.4129762764
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1944748914
Short name T498
Test name
Test status
Simulation time 2739803236 ps
CPU time 16.04 seconds
Started Aug 14 05:02:33 PM PDT 24
Finished Aug 14 05:02:49 PM PDT 24
Peak memory 199040 kb
Host smart-84ed540b-80f7-48cf-9ad6-67c6fcfef9f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1944748914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1944748914
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3406317945
Short name T767
Test name
Test status
Simulation time 24861916641 ps
CPU time 36.03 seconds
Started Aug 14 05:02:34 PM PDT 24
Finished Aug 14 05:03:11 PM PDT 24
Peak memory 200972 kb
Host smart-00dbd83a-30f5-41a7-8ea6-46223cf922fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406317945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3406317945
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.2740930921
Short name T614
Test name
Test status
Simulation time 77863595700 ps
CPU time 121.86 seconds
Started Aug 14 05:02:33 PM PDT 24
Finished Aug 14 05:04:35 PM PDT 24
Peak memory 196956 kb
Host smart-4ec8ca60-8e20-4f4d-ab91-384b2de9e3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740930921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2740930921
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.1714006575
Short name T992
Test name
Test status
Simulation time 504173813 ps
CPU time 2.09 seconds
Started Aug 14 05:02:36 PM PDT 24
Finished Aug 14 05:02:38 PM PDT 24
Peak memory 200072 kb
Host smart-63f48935-c48c-45a3-ad4b-a232ada8f021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714006575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1714006575
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1525834284
Short name T1166
Test name
Test status
Simulation time 7106507018 ps
CPU time 27.42 seconds
Started Aug 14 05:02:34 PM PDT 24
Finished Aug 14 05:03:02 PM PDT 24
Peak memory 216704 kb
Host smart-ae76b3a7-7f2e-451e-947f-576eae56cd87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525834284 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1525834284
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1693629027
Short name T276
Test name
Test status
Simulation time 6635410155 ps
CPU time 19.06 seconds
Started Aug 14 05:02:34 PM PDT 24
Finished Aug 14 05:02:53 PM PDT 24
Peak memory 200728 kb
Host smart-68bfa2c1-67c3-4913-baeb-e53eb4dd3a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693629027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1693629027
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2155766771
Short name T692
Test name
Test status
Simulation time 32850242543 ps
CPU time 26.01 seconds
Started Aug 14 05:02:35 PM PDT 24
Finished Aug 14 05:03:01 PM PDT 24
Peak memory 200892 kb
Host smart-c38e9c73-d4d8-448d-9159-d3529206ad77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155766771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2155766771
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2500972250
Short name T445
Test name
Test status
Simulation time 12356745 ps
CPU time 0.55 seconds
Started Aug 14 05:02:47 PM PDT 24
Finished Aug 14 05:02:48 PM PDT 24
Peak memory 196252 kb
Host smart-de7bf83a-2bde-46bf-86c5-b022270e4ef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500972250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2500972250
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.3908726678
Short name T105
Test name
Test status
Simulation time 92387855716 ps
CPU time 29.01 seconds
Started Aug 14 05:02:48 PM PDT 24
Finished Aug 14 05:03:17 PM PDT 24
Peak memory 200884 kb
Host smart-87755aa3-d6f2-43a1-85d2-eb3f136ef0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908726678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3908726678
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.4235573407
Short name T1073
Test name
Test status
Simulation time 28189021324 ps
CPU time 27.51 seconds
Started Aug 14 05:02:47 PM PDT 24
Finished Aug 14 05:03:15 PM PDT 24
Peak memory 200956 kb
Host smart-9dc10cac-082c-4af8-91a6-57ab8063e854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235573407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.4235573407
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.2518663307
Short name T141
Test name
Test status
Simulation time 42712305637 ps
CPU time 44.18 seconds
Started Aug 14 05:02:50 PM PDT 24
Finished Aug 14 05:03:34 PM PDT 24
Peak memory 200996 kb
Host smart-c23004b9-6504-4277-a26a-6e3af2e54905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518663307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2518663307
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.4098811122
Short name T841
Test name
Test status
Simulation time 36884398349 ps
CPU time 55.3 seconds
Started Aug 14 05:02:50 PM PDT 24
Finished Aug 14 05:03:46 PM PDT 24
Peak memory 200412 kb
Host smart-78193b13-30ac-485f-b9a3-42a5db1a7e62
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098811122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.4098811122
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.798146574
Short name T787
Test name
Test status
Simulation time 74313795230 ps
CPU time 208.56 seconds
Started Aug 14 05:02:48 PM PDT 24
Finished Aug 14 05:06:16 PM PDT 24
Peak memory 200880 kb
Host smart-4a459a1c-abfc-4185-93c7-9468c84e4497
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=798146574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.798146574
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.4188230622
Short name T682
Test name
Test status
Simulation time 4032254538 ps
CPU time 4.27 seconds
Started Aug 14 05:02:51 PM PDT 24
Finished Aug 14 05:02:55 PM PDT 24
Peak memory 200268 kb
Host smart-385f194a-21ba-4f96-bbc0-f4bbc9a5d1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188230622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.4188230622
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2924817822
Short name T1151
Test name
Test status
Simulation time 7439486806 ps
CPU time 11.76 seconds
Started Aug 14 05:02:46 PM PDT 24
Finished Aug 14 05:02:58 PM PDT 24
Peak memory 199580 kb
Host smart-adc9da08-3796-4921-ba97-a12fd75cacc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924817822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2924817822
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.2711189639
Short name T268
Test name
Test status
Simulation time 7794893213 ps
CPU time 419.43 seconds
Started Aug 14 05:02:47 PM PDT 24
Finished Aug 14 05:09:47 PM PDT 24
Peak memory 200900 kb
Host smart-9a3671f8-0087-4ddd-86f3-4795b6574484
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2711189639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2711189639
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.3270767330
Short name T373
Test name
Test status
Simulation time 7322071684 ps
CPU time 16.35 seconds
Started Aug 14 05:02:50 PM PDT 24
Finished Aug 14 05:03:07 PM PDT 24
Peak memory 200060 kb
Host smart-73565a34-f504-4c72-a637-b07f99263b21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3270767330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3270767330
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1023632058
Short name T134
Test name
Test status
Simulation time 21736931468 ps
CPU time 23.74 seconds
Started Aug 14 05:02:47 PM PDT 24
Finished Aug 14 05:03:11 PM PDT 24
Peak memory 200840 kb
Host smart-6dd7910a-096d-4be6-8ab0-a39198bd36a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023632058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1023632058
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.2579422436
Short name T834
Test name
Test status
Simulation time 3389547352 ps
CPU time 0.92 seconds
Started Aug 14 05:02:49 PM PDT 24
Finished Aug 14 05:02:50 PM PDT 24
Peak memory 197000 kb
Host smart-48980860-5ed2-408f-b9ed-48dc5fa8a309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579422436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2579422436
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3621851731
Short name T951
Test name
Test status
Simulation time 901787479 ps
CPU time 2.42 seconds
Started Aug 14 05:02:35 PM PDT 24
Finished Aug 14 05:02:37 PM PDT 24
Peak memory 200560 kb
Host smart-a4d1fcfe-54ab-48e7-b473-abe5bd3fa34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621851731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3621851731
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.1847901778
Short name T41
Test name
Test status
Simulation time 123270676139 ps
CPU time 1020.31 seconds
Started Aug 14 05:02:49 PM PDT 24
Finished Aug 14 05:19:50 PM PDT 24
Peak memory 200908 kb
Host smart-bd33d126-0017-4067-9b1d-3408ecf01851
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847901778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1847901778
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.3779591111
Short name T87
Test name
Test status
Simulation time 16180933090 ps
CPU time 38.8 seconds
Started Aug 14 05:02:47 PM PDT 24
Finished Aug 14 05:03:26 PM PDT 24
Peak memory 216644 kb
Host smart-f63fa8dc-147b-423f-a671-d5df2aa97a71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779591111 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.3779591111
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.2271992285
Short name T392
Test name
Test status
Simulation time 1882766735 ps
CPU time 2.6 seconds
Started Aug 14 05:02:50 PM PDT 24
Finished Aug 14 05:02:53 PM PDT 24
Peak memory 200936 kb
Host smart-3d398446-6fbd-476e-8a2b-1d7c8489a0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271992285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2271992285
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1755393713
Short name T1117
Test name
Test status
Simulation time 37181748506 ps
CPU time 15.58 seconds
Started Aug 14 05:02:46 PM PDT 24
Finished Aug 14 05:03:02 PM PDT 24
Peak memory 200884 kb
Host smart-551f140f-4ec5-4045-a687-7b45845849e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755393713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1755393713
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.667928806
Short name T636
Test name
Test status
Simulation time 47015598 ps
CPU time 0.56 seconds
Started Aug 14 05:02:46 PM PDT 24
Finished Aug 14 05:02:46 PM PDT 24
Peak memory 196260 kb
Host smart-7c3e9543-2bb7-4cc8-af17-049539999e7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667928806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.667928806
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.2305062619
Short name T289
Test name
Test status
Simulation time 98020853690 ps
CPU time 197.24 seconds
Started Aug 14 05:02:48 PM PDT 24
Finished Aug 14 05:06:05 PM PDT 24
Peak memory 200912 kb
Host smart-0b7788ef-c319-4be1-8b21-c7896aefaad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305062619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2305062619
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.1419218494
Short name T899
Test name
Test status
Simulation time 242195583980 ps
CPU time 93.94 seconds
Started Aug 14 05:02:48 PM PDT 24
Finished Aug 14 05:04:22 PM PDT 24
Peak memory 200876 kb
Host smart-2aeb6cfb-1177-46ff-ba51-6e04e5c94578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419218494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1419218494
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3752573543
Short name T885
Test name
Test status
Simulation time 31681708261 ps
CPU time 42.09 seconds
Started Aug 14 05:02:46 PM PDT 24
Finished Aug 14 05:03:28 PM PDT 24
Peak memory 200888 kb
Host smart-f5cbcdc9-784d-47fd-9dba-8424e9c63212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752573543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3752573543
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.1942664494
Short name T528
Test name
Test status
Simulation time 59265261524 ps
CPU time 96.44 seconds
Started Aug 14 05:02:47 PM PDT 24
Finished Aug 14 05:04:24 PM PDT 24
Peak memory 200960 kb
Host smart-59b942dc-33c5-4c13-89b0-64cca684ecda
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942664494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1942664494
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3244232490
Short name T495
Test name
Test status
Simulation time 147748521620 ps
CPU time 1287.17 seconds
Started Aug 14 05:02:47 PM PDT 24
Finished Aug 14 05:24:15 PM PDT 24
Peak memory 200904 kb
Host smart-29810cbc-dc09-4740-8626-c85243152079
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3244232490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3244232490
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.3757780156
Short name T596
Test name
Test status
Simulation time 5346217907 ps
CPU time 5.38 seconds
Started Aug 14 05:02:48 PM PDT 24
Finished Aug 14 05:02:53 PM PDT 24
Peak memory 199372 kb
Host smart-3a1bf73c-0967-49d4-9883-b3ffa8548b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757780156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3757780156
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.1074170995
Short name T855
Test name
Test status
Simulation time 39411522907 ps
CPU time 60.98 seconds
Started Aug 14 05:02:48 PM PDT 24
Finished Aug 14 05:03:49 PM PDT 24
Peak memory 199572 kb
Host smart-67ff88b4-ba10-404d-b7d9-f9ea106f6850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074170995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1074170995
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.783035398
Short name T601
Test name
Test status
Simulation time 11019472596 ps
CPU time 638.03 seconds
Started Aug 14 05:02:46 PM PDT 24
Finished Aug 14 05:13:25 PM PDT 24
Peak memory 200900 kb
Host smart-17b473ed-211a-4d3a-b576-9cc69e70fcd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=783035398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.783035398
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.2830853190
Short name T366
Test name
Test status
Simulation time 4771731611 ps
CPU time 7.23 seconds
Started Aug 14 05:02:47 PM PDT 24
Finished Aug 14 05:02:54 PM PDT 24
Peak memory 199960 kb
Host smart-62dd8c1f-37d9-4810-831a-3cb7535e74ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2830853190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.2830853190
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.938177859
Short name T796
Test name
Test status
Simulation time 59665632444 ps
CPU time 31.08 seconds
Started Aug 14 05:02:49 PM PDT 24
Finished Aug 14 05:03:20 PM PDT 24
Peak memory 200948 kb
Host smart-911c2a66-d609-4a32-ac81-db5bc813b4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938177859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.938177859
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1025713422
Short name T965
Test name
Test status
Simulation time 2554655470 ps
CPU time 3.71 seconds
Started Aug 14 05:02:47 PM PDT 24
Finished Aug 14 05:02:51 PM PDT 24
Peak memory 197444 kb
Host smart-0c1463c7-282a-4a87-a506-e871828c7a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025713422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1025713422
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.612861021
Short name T407
Test name
Test status
Simulation time 447443672 ps
CPU time 1.91 seconds
Started Aug 14 05:02:47 PM PDT 24
Finished Aug 14 05:02:49 PM PDT 24
Peak memory 200896 kb
Host smart-4a10cfcd-a22d-481e-bbb9-28119e9979da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612861021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.612861021
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.451382065
Short name T92
Test name
Test status
Simulation time 46157827738 ps
CPU time 92.27 seconds
Started Aug 14 05:02:47 PM PDT 24
Finished Aug 14 05:04:20 PM PDT 24
Peak memory 200896 kb
Host smart-0ad33028-4ee5-4285-bfa5-9b35245d2c5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451382065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.451382065
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.55403255
Short name T866
Test name
Test status
Simulation time 2661309229 ps
CPU time 22.23 seconds
Started Aug 14 05:02:49 PM PDT 24
Finished Aug 14 05:03:11 PM PDT 24
Peak memory 201036 kb
Host smart-dfae8af7-7c2f-4c83-b85f-c907b7d6e5b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55403255 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.55403255
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.4275250786
Short name T291
Test name
Test status
Simulation time 1286525242 ps
CPU time 3.13 seconds
Started Aug 14 05:02:50 PM PDT 24
Finished Aug 14 05:02:53 PM PDT 24
Peak memory 200876 kb
Host smart-4536418e-7d1e-4e3d-8a55-c93458bf51ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275250786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.4275250786
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.3845897827
Short name T1083
Test name
Test status
Simulation time 47106201180 ps
CPU time 22.36 seconds
Started Aug 14 05:02:48 PM PDT 24
Finished Aug 14 05:03:10 PM PDT 24
Peak memory 200864 kb
Host smart-81731342-0313-46ee-888c-a3b085d08ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845897827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3845897827
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.578336988
Short name T402
Test name
Test status
Simulation time 42772383 ps
CPU time 0.57 seconds
Started Aug 14 04:59:07 PM PDT 24
Finished Aug 14 04:59:08 PM PDT 24
Peak memory 196564 kb
Host smart-871067a8-a0c5-4078-afcf-1591d1ef116a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578336988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.578336988
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.270978593
Short name T1029
Test name
Test status
Simulation time 133868755223 ps
CPU time 32.45 seconds
Started Aug 14 04:59:08 PM PDT 24
Finished Aug 14 04:59:41 PM PDT 24
Peak memory 200860 kb
Host smart-a5e1eb0d-8cc8-46d7-bee8-f83620ef5f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270978593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.270978593
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.2734985809
Short name T560
Test name
Test status
Simulation time 10340490119 ps
CPU time 5.5 seconds
Started Aug 14 04:59:12 PM PDT 24
Finished Aug 14 04:59:18 PM PDT 24
Peak memory 199228 kb
Host smart-6235193d-97e4-4d13-88da-08cddc06eb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734985809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2734985809
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.1100115136
Short name T216
Test name
Test status
Simulation time 46047095903 ps
CPU time 37.34 seconds
Started Aug 14 04:59:08 PM PDT 24
Finished Aug 14 04:59:46 PM PDT 24
Peak memory 200584 kb
Host smart-318ce3c3-ed4d-4a37-89da-f4ee47f37ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100115136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1100115136
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.3224530287
Short name T1135
Test name
Test status
Simulation time 8646108933 ps
CPU time 5.8 seconds
Started Aug 14 04:59:07 PM PDT 24
Finished Aug 14 04:59:13 PM PDT 24
Peak memory 199912 kb
Host smart-54138087-a1f0-4cca-a630-937928a5e59a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224530287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3224530287
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.3868862666
Short name T1090
Test name
Test status
Simulation time 298273342176 ps
CPU time 137.48 seconds
Started Aug 14 04:59:07 PM PDT 24
Finished Aug 14 05:01:25 PM PDT 24
Peak memory 200848 kb
Host smart-54d628b5-7864-4f3d-abe3-6b9c389582c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3868862666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3868862666
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.4268394289
Short name T21
Test name
Test status
Simulation time 12621124483 ps
CPU time 5.42 seconds
Started Aug 14 04:59:08 PM PDT 24
Finished Aug 14 04:59:14 PM PDT 24
Peak memory 200820 kb
Host smart-69ae1dd3-d218-4ee6-a815-7fae66049b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268394289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.4268394289
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3408513292
Short name T234
Test name
Test status
Simulation time 49056041404 ps
CPU time 78.57 seconds
Started Aug 14 04:59:07 PM PDT 24
Finished Aug 14 05:00:26 PM PDT 24
Peak memory 209132 kb
Host smart-ba16d720-d575-4e8b-bd48-b8855a490020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408513292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3408513292
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.3816155790
Short name T550
Test name
Test status
Simulation time 4090924703 ps
CPU time 166.18 seconds
Started Aug 14 04:59:14 PM PDT 24
Finished Aug 14 05:02:00 PM PDT 24
Peak memory 200956 kb
Host smart-ddc078b2-e18f-48e5-b5b2-73e9206a1bc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3816155790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3816155790
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1713134555
Short name T400
Test name
Test status
Simulation time 3924270462 ps
CPU time 6.75 seconds
Started Aug 14 04:59:08 PM PDT 24
Finished Aug 14 04:59:15 PM PDT 24
Peak memory 199036 kb
Host smart-c7976d9e-c5a6-477a-8fab-eab24441119f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1713134555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1713134555
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1318478477
Short name T766
Test name
Test status
Simulation time 5089079242 ps
CPU time 7.43 seconds
Started Aug 14 04:59:09 PM PDT 24
Finished Aug 14 04:59:16 PM PDT 24
Peak memory 197184 kb
Host smart-8dbbba23-af88-49b7-8e04-79e8b656009a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318478477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1318478477
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.480966765
Short name T734
Test name
Test status
Simulation time 929196990 ps
CPU time 3.84 seconds
Started Aug 14 04:59:07 PM PDT 24
Finished Aug 14 04:59:11 PM PDT 24
Peak memory 200328 kb
Host smart-ec05cd0a-d72e-4f5b-98df-5cd4ad9537f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480966765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.480966765
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.1976182830
Short name T1070
Test name
Test status
Simulation time 174895465846 ps
CPU time 991.29 seconds
Started Aug 14 04:59:08 PM PDT 24
Finished Aug 14 05:15:40 PM PDT 24
Peak memory 200972 kb
Host smart-d8d22564-8e2b-423c-8be4-f37bd6ee0497
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976182830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1976182830
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.1336825212
Short name T84
Test name
Test status
Simulation time 2747144251 ps
CPU time 13.85 seconds
Started Aug 14 04:59:14 PM PDT 24
Finished Aug 14 04:59:28 PM PDT 24
Peak memory 200972 kb
Host smart-b6102f2a-2668-43d6-9cfe-14b44406369f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336825212 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1336825212
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.687964013
Short name T1050
Test name
Test status
Simulation time 2529230316 ps
CPU time 2.48 seconds
Started Aug 14 04:59:10 PM PDT 24
Finished Aug 14 04:59:13 PM PDT 24
Peak memory 199824 kb
Host smart-256e62cb-e9e7-4460-8f63-7eb222492acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687964013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.687964013
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.192798442
Short name T1048
Test name
Test status
Simulation time 13345327252 ps
CPU time 5.65 seconds
Started Aug 14 04:59:07 PM PDT 24
Finished Aug 14 04:59:13 PM PDT 24
Peak memory 200652 kb
Host smart-771e455e-d707-46a6-acae-328a8426ca0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192798442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.192798442
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2172075207
Short name T8
Test name
Test status
Simulation time 253324201997 ps
CPU time 51.53 seconds
Started Aug 14 05:02:58 PM PDT 24
Finished Aug 14 05:03:50 PM PDT 24
Peak memory 200868 kb
Host smart-a65a760b-7e5e-4864-a1ec-d4971b9a9227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172075207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2172075207
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3399775413
Short name T34
Test name
Test status
Simulation time 4294633988 ps
CPU time 44.46 seconds
Started Aug 14 05:03:03 PM PDT 24
Finished Aug 14 05:03:48 PM PDT 24
Peak memory 217424 kb
Host smart-77d12e96-8982-47b7-a38b-ba4813d46aa7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399775413 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3399775413
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.4208381537
Short name T410
Test name
Test status
Simulation time 9026231732 ps
CPU time 32.35 seconds
Started Aug 14 05:02:57 PM PDT 24
Finished Aug 14 05:03:29 PM PDT 24
Peak memory 209120 kb
Host smart-1e45382a-83fa-4a6f-8040-b7f00a924b43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208381537 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.4208381537
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.920449009
Short name T193
Test name
Test status
Simulation time 55032070269 ps
CPU time 7.97 seconds
Started Aug 14 05:03:01 PM PDT 24
Finished Aug 14 05:03:09 PM PDT 24
Peak memory 200892 kb
Host smart-4f0fdc02-a786-42bd-9b19-aa34d1aa7006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920449009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.920449009
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.3016523363
Short name T17
Test name
Test status
Simulation time 1365210438 ps
CPU time 19.56 seconds
Started Aug 14 05:02:57 PM PDT 24
Finished Aug 14 05:03:16 PM PDT 24
Peak memory 209284 kb
Host smart-b92461d0-fa4a-4b3b-aac1-1be6699c7b08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016523363 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.3016523363
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1195966835
Short name T605
Test name
Test status
Simulation time 559706607 ps
CPU time 7.97 seconds
Started Aug 14 05:02:57 PM PDT 24
Finished Aug 14 05:03:05 PM PDT 24
Peak memory 200944 kb
Host smart-76580d65-880a-4fd6-87e9-26d074a5ccd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195966835 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1195966835
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1343879957
Short name T718
Test name
Test status
Simulation time 168021857908 ps
CPU time 19.03 seconds
Started Aug 14 05:03:05 PM PDT 24
Finished Aug 14 05:03:24 PM PDT 24
Peak memory 200908 kb
Host smart-3cd70903-56c2-4fab-ba5f-c2f9efecd368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343879957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1343879957
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1066141896
Short name T1001
Test name
Test status
Simulation time 8153587204 ps
CPU time 29.86 seconds
Started Aug 14 05:02:56 PM PDT 24
Finished Aug 14 05:03:26 PM PDT 24
Peak memory 217040 kb
Host smart-0d3ac994-259c-4e4f-8817-38d507e9213e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066141896 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1066141896
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.642368532
Short name T343
Test name
Test status
Simulation time 15387381951 ps
CPU time 12.72 seconds
Started Aug 14 05:02:56 PM PDT 24
Finished Aug 14 05:03:09 PM PDT 24
Peak memory 200736 kb
Host smart-1b7d26c0-162d-4b92-b4be-d5ecad77eb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642368532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.642368532
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3704778551
Short name T549
Test name
Test status
Simulation time 17445206476 ps
CPU time 25.37 seconds
Started Aug 14 05:02:57 PM PDT 24
Finished Aug 14 05:03:22 PM PDT 24
Peak memory 217396 kb
Host smart-51b59bdf-f657-4b6d-bddc-28517244722e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704778551 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3704778551
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1061792570
Short name T696
Test name
Test status
Simulation time 95980653353 ps
CPU time 29.43 seconds
Started Aug 14 05:02:57 PM PDT 24
Finished Aug 14 05:03:27 PM PDT 24
Peak memory 200740 kb
Host smart-a89f867b-c243-4d8c-b56f-0e54d0f36b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061792570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1061792570
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.2674853984
Short name T842
Test name
Test status
Simulation time 5564328087 ps
CPU time 30.04 seconds
Started Aug 14 05:02:58 PM PDT 24
Finished Aug 14 05:03:28 PM PDT 24
Peak memory 209480 kb
Host smart-964770a0-3ebc-4e60-a1dd-9df6dc38f1e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674853984 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.2674853984
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.62826924
Short name T566
Test name
Test status
Simulation time 34340516083 ps
CPU time 62.08 seconds
Started Aug 14 05:02:58 PM PDT 24
Finished Aug 14 05:04:00 PM PDT 24
Peak memory 200848 kb
Host smart-604bf3f0-9d0a-412f-a55e-11c080055099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62826924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.62826924
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.977014736
Short name T77
Test name
Test status
Simulation time 3583481649 ps
CPU time 42.81 seconds
Started Aug 14 05:02:57 PM PDT 24
Finished Aug 14 05:03:40 PM PDT 24
Peak memory 216948 kb
Host smart-8f716c08-0354-4724-abde-3e764642cfa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977014736 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.977014736
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.721228698
Short name T804
Test name
Test status
Simulation time 23202270319 ps
CPU time 36.82 seconds
Started Aug 14 05:02:58 PM PDT 24
Finished Aug 14 05:03:35 PM PDT 24
Peak memory 200936 kb
Host smart-d95b4ff0-4ed6-4ec9-a6e6-a67a27a69f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721228698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.721228698
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.1858188655
Short name T946
Test name
Test status
Simulation time 64104547201 ps
CPU time 81.73 seconds
Started Aug 14 05:02:59 PM PDT 24
Finished Aug 14 05:04:21 PM PDT 24
Peak memory 215048 kb
Host smart-9af946f5-e7c8-4897-becc-05cdc1cf4d05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858188655 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.1858188655
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3572258298
Short name T925
Test name
Test status
Simulation time 1630101234 ps
CPU time 11.41 seconds
Started Aug 14 05:02:58 PM PDT 24
Finished Aug 14 05:03:10 PM PDT 24
Peak memory 200860 kb
Host smart-3956a0fd-7b8c-41e4-bdba-0e5280f7be6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572258298 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3572258298
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3323137389
Short name T617
Test name
Test status
Simulation time 12943424 ps
CPU time 0.53 seconds
Started Aug 14 04:59:20 PM PDT 24
Finished Aug 14 04:59:20 PM PDT 24
Peak memory 195736 kb
Host smart-bfa0740b-65c0-42cf-8bf9-f83e3b117793
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323137389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3323137389
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.2959348760
Short name T966
Test name
Test status
Simulation time 138528100620 ps
CPU time 58.6 seconds
Started Aug 14 04:59:20 PM PDT 24
Finished Aug 14 05:00:18 PM PDT 24
Peak memory 200972 kb
Host smart-7c858f92-77a9-4554-a670-b14cf68d74ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959348760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2959348760
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1145635636
Short name T641
Test name
Test status
Simulation time 10796284625 ps
CPU time 29.61 seconds
Started Aug 14 04:59:17 PM PDT 24
Finished Aug 14 04:59:46 PM PDT 24
Peak memory 200900 kb
Host smart-41e33c25-ff3b-4394-8e24-3d7a77c4ec11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145635636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1145635636
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.3767591322
Short name T35
Test name
Test status
Simulation time 158198938203 ps
CPU time 76.47 seconds
Started Aug 14 04:59:22 PM PDT 24
Finished Aug 14 05:00:38 PM PDT 24
Peak memory 200828 kb
Host smart-18b71c76-041f-4e10-89b1-8ecde16a76a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767591322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3767591322
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.4180179262
Short name T1014
Test name
Test status
Simulation time 31552190040 ps
CPU time 54.48 seconds
Started Aug 14 04:59:17 PM PDT 24
Finished Aug 14 05:00:12 PM PDT 24
Peak memory 200888 kb
Host smart-082eb084-de7a-4846-bb2b-55608b382f4c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180179262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.4180179262
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.2520523828
Short name T561
Test name
Test status
Simulation time 83951345421 ps
CPU time 370.52 seconds
Started Aug 14 04:59:18 PM PDT 24
Finished Aug 14 05:05:28 PM PDT 24
Peak memory 200980 kb
Host smart-32cc32ae-6640-4390-9ae3-7c7301f98b8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2520523828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2520523828
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1474954933
Short name T884
Test name
Test status
Simulation time 6654162482 ps
CPU time 3.89 seconds
Started Aug 14 04:59:23 PM PDT 24
Finished Aug 14 04:59:27 PM PDT 24
Peak memory 199100 kb
Host smart-f57c69df-1774-4375-934c-d92980bdfae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474954933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1474954933
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1514861703
Short name T296
Test name
Test status
Simulation time 11383209871 ps
CPU time 19.1 seconds
Started Aug 14 04:59:22 PM PDT 24
Finished Aug 14 04:59:41 PM PDT 24
Peak memory 201068 kb
Host smart-dc037bbc-acc8-4f8b-8b15-7583a54a69ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514861703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1514861703
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.3594090903
Short name T600
Test name
Test status
Simulation time 11305984855 ps
CPU time 136.36 seconds
Started Aug 14 04:59:17 PM PDT 24
Finished Aug 14 05:01:33 PM PDT 24
Peak memory 200920 kb
Host smart-61a1eba2-f895-4e69-8531-a51e2e424b54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3594090903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3594090903
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3709865355
Short name T745
Test name
Test status
Simulation time 6384773526 ps
CPU time 4.12 seconds
Started Aug 14 04:59:16 PM PDT 24
Finished Aug 14 04:59:21 PM PDT 24
Peak memory 199256 kb
Host smart-61d4994d-492f-49a7-9fd8-72556161d19e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3709865355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3709865355
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.64194875
Short name T713
Test name
Test status
Simulation time 131168547487 ps
CPU time 426.44 seconds
Started Aug 14 04:59:18 PM PDT 24
Finished Aug 14 05:06:25 PM PDT 24
Peak memory 200896 kb
Host smart-215589cb-5a03-48c2-926a-e5f6837e4f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64194875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.64194875
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2947010111
Short name T974
Test name
Test status
Simulation time 2068360418 ps
CPU time 3.53 seconds
Started Aug 14 04:59:17 PM PDT 24
Finished Aug 14 04:59:20 PM PDT 24
Peak memory 196616 kb
Host smart-01d920a2-72fd-4a40-a806-65f5828088fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947010111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2947010111
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.546744975
Short name T599
Test name
Test status
Simulation time 5793796131 ps
CPU time 11.58 seconds
Started Aug 14 04:59:17 PM PDT 24
Finished Aug 14 04:59:28 PM PDT 24
Peak memory 201108 kb
Host smart-92d5f729-a0cb-44c2-a6b2-bcf19cbeb4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546744975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.546744975
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.1410863777
Short name T145
Test name
Test status
Simulation time 143377640755 ps
CPU time 59.2 seconds
Started Aug 14 04:59:19 PM PDT 24
Finished Aug 14 05:00:18 PM PDT 24
Peak memory 200984 kb
Host smart-9570cb53-4012-48c2-bb23-4ac165049de3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410863777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1410863777
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3143329532
Short name T663
Test name
Test status
Simulation time 2691256725 ps
CPU time 28.07 seconds
Started Aug 14 04:59:17 PM PDT 24
Finished Aug 14 04:59:45 PM PDT 24
Peak memory 209356 kb
Host smart-d6366a3a-4858-4548-9948-04279e75b427
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143329532 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3143329532
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.3251731216
Short name T329
Test name
Test status
Simulation time 9379730446 ps
CPU time 1.98 seconds
Started Aug 14 04:59:17 PM PDT 24
Finished Aug 14 04:59:19 PM PDT 24
Peak memory 200448 kb
Host smart-0d53bd4d-f250-4938-b582-69c9f809fbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251731216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3251731216
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.3199388909
Short name T786
Test name
Test status
Simulation time 43719246699 ps
CPU time 24.57 seconds
Started Aug 14 04:59:17 PM PDT 24
Finished Aug 14 04:59:42 PM PDT 24
Peak memory 200864 kb
Host smart-9d305342-b435-4221-a22b-ddaafeb89726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199388909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3199388909
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.678082820
Short name T595
Test name
Test status
Simulation time 33645253363 ps
CPU time 52.53 seconds
Started Aug 14 05:02:59 PM PDT 24
Finished Aug 14 05:03:51 PM PDT 24
Peak memory 200972 kb
Host smart-48268a9e-22fc-4872-88a3-cd2b956edcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678082820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.678082820
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.1774707889
Short name T850
Test name
Test status
Simulation time 15550658111 ps
CPU time 91.01 seconds
Started Aug 14 05:03:02 PM PDT 24
Finished Aug 14 05:04:33 PM PDT 24
Peak memory 210892 kb
Host smart-70ebfecc-b20a-4ee0-b5cb-0d19c32495ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774707889 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.1774707889
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3457222826
Short name T873
Test name
Test status
Simulation time 34067169753 ps
CPU time 59.66 seconds
Started Aug 14 05:03:05 PM PDT 24
Finished Aug 14 05:04:05 PM PDT 24
Peak memory 200904 kb
Host smart-33518373-189f-4fbe-86fd-5c2e1be6fce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457222826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3457222826
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1243430861
Short name T31
Test name
Test status
Simulation time 513034398 ps
CPU time 7.56 seconds
Started Aug 14 05:02:59 PM PDT 24
Finished Aug 14 05:03:07 PM PDT 24
Peak memory 200804 kb
Host smart-faa9c422-a617-4274-a46f-0489fa2ce0a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243430861 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1243430861
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.2197453703
Short name T116
Test name
Test status
Simulation time 107541198735 ps
CPU time 48.23 seconds
Started Aug 14 05:02:56 PM PDT 24
Finished Aug 14 05:03:44 PM PDT 24
Peak memory 200916 kb
Host smart-f5303af7-4120-40ec-8829-85ad90aabd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197453703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2197453703
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.2803732173
Short name T510
Test name
Test status
Simulation time 1134911751 ps
CPU time 15.34 seconds
Started Aug 14 05:02:57 PM PDT 24
Finished Aug 14 05:03:13 PM PDT 24
Peak memory 209368 kb
Host smart-a66e041e-58d2-474e-8f24-c5327ad024a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803732173 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2803732173
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.346470926
Short name T489
Test name
Test status
Simulation time 18064602311 ps
CPU time 36.15 seconds
Started Aug 14 05:02:56 PM PDT 24
Finished Aug 14 05:03:32 PM PDT 24
Peak memory 200968 kb
Host smart-8e14f876-ff39-4332-bc41-5b5a5186c68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346470926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.346470926
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.2007739562
Short name T880
Test name
Test status
Simulation time 24280334106 ps
CPU time 55.65 seconds
Started Aug 14 05:02:57 PM PDT 24
Finished Aug 14 05:03:53 PM PDT 24
Peak memory 209112 kb
Host smart-394008c9-1dc3-4eca-9513-3165e83d0054
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007739562 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.2007739562
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2514530097
Short name T1138
Test name
Test status
Simulation time 19002816496 ps
CPU time 15.97 seconds
Started Aug 14 05:03:01 PM PDT 24
Finished Aug 14 05:03:17 PM PDT 24
Peak memory 200904 kb
Host smart-1226bb99-9656-4000-8937-87ecc7a9b668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514530097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2514530097
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.52730376
Short name T888
Test name
Test status
Simulation time 15429731775 ps
CPU time 111.08 seconds
Started Aug 14 05:03:03 PM PDT 24
Finished Aug 14 05:04:54 PM PDT 24
Peak memory 216708 kb
Host smart-f0b62487-7029-4823-a531-2a17315d7071
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52730376 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.52730376
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.1294311477
Short name T182
Test name
Test status
Simulation time 71266674156 ps
CPU time 66.16 seconds
Started Aug 14 05:02:56 PM PDT 24
Finished Aug 14 05:04:02 PM PDT 24
Peak memory 200860 kb
Host smart-0980c8c8-03a5-4140-82e7-4e914c989395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294311477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1294311477
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.3665918335
Short name T533
Test name
Test status
Simulation time 6973993640 ps
CPU time 29.94 seconds
Started Aug 14 05:02:56 PM PDT 24
Finished Aug 14 05:03:26 PM PDT 24
Peak memory 209324 kb
Host smart-1879c1e9-7e3e-43f8-9b30-e56d418851bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665918335 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.3665918335
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1130168394
Short name T900
Test name
Test status
Simulation time 24517263264 ps
CPU time 11.52 seconds
Started Aug 14 05:03:05 PM PDT 24
Finished Aug 14 05:03:17 PM PDT 24
Peak memory 200952 kb
Host smart-74ef01b4-e06e-4d6d-9204-417e4f7d7f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130168394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1130168394
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.4093852170
Short name T593
Test name
Test status
Simulation time 4577218605 ps
CPU time 52.8 seconds
Started Aug 14 05:03:04 PM PDT 24
Finished Aug 14 05:03:57 PM PDT 24
Peak memory 209204 kb
Host smart-fb56bec1-9ffc-422c-810c-564fae9ce330
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093852170 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.4093852170
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1044987793
Short name T817
Test name
Test status
Simulation time 107437932604 ps
CPU time 40.97 seconds
Started Aug 14 05:02:58 PM PDT 24
Finished Aug 14 05:03:39 PM PDT 24
Peak memory 200772 kb
Host smart-2b8aacb2-e658-4f8f-be06-f5da9499a515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044987793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1044987793
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.2033953832
Short name T777
Test name
Test status
Simulation time 3608009396 ps
CPU time 51.08 seconds
Started Aug 14 05:02:58 PM PDT 24
Finished Aug 14 05:03:49 PM PDT 24
Peak memory 209684 kb
Host smart-d0e2097a-c2f1-4923-aace-faf1298c9d78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033953832 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.2033953832
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.713036336
Short name T1154
Test name
Test status
Simulation time 12260879761 ps
CPU time 19.67 seconds
Started Aug 14 05:03:02 PM PDT 24
Finished Aug 14 05:03:22 PM PDT 24
Peak memory 200920 kb
Host smart-1f47bf76-e3ee-45db-9ef8-b8689ff5caeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713036336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.713036336
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.4024709288
Short name T664
Test name
Test status
Simulation time 2059569771 ps
CPU time 15.4 seconds
Started Aug 14 05:02:56 PM PDT 24
Finished Aug 14 05:03:12 PM PDT 24
Peak memory 200920 kb
Host smart-fc9c762c-6442-489a-b207-02339a10fb65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024709288 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.4024709288
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.1063910313
Short name T1095
Test name
Test status
Simulation time 89711088931 ps
CPU time 70.48 seconds
Started Aug 14 05:02:57 PM PDT 24
Finished Aug 14 05:04:07 PM PDT 24
Peak memory 200872 kb
Host smart-1eb5afd1-b314-4c2f-8dab-8c6403f209b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063910313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1063910313
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.4035623256
Short name T828
Test name
Test status
Simulation time 2464256966 ps
CPU time 21.69 seconds
Started Aug 14 05:02:57 PM PDT 24
Finished Aug 14 05:03:19 PM PDT 24
Peak memory 217248 kb
Host smart-55738b35-3a8c-41db-868c-e1570d1e9d42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035623256 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.4035623256
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1897193136
Short name T840
Test name
Test status
Simulation time 25007215 ps
CPU time 0.62 seconds
Started Aug 14 04:59:17 PM PDT 24
Finished Aug 14 04:59:18 PM PDT 24
Peak memory 196196 kb
Host smart-18b8b3fb-90ed-46a5-8241-c68ea5502407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897193136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1897193136
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3033532680
Short name T255
Test name
Test status
Simulation time 107604729371 ps
CPU time 43.65 seconds
Started Aug 14 04:59:17 PM PDT 24
Finished Aug 14 05:00:01 PM PDT 24
Peak memory 200856 kb
Host smart-e9631ce6-0c17-479f-adb3-1d802ceb22fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033532680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3033532680
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3520215500
Short name T149
Test name
Test status
Simulation time 64216012405 ps
CPU time 99.64 seconds
Started Aug 14 04:59:17 PM PDT 24
Finished Aug 14 05:00:57 PM PDT 24
Peak memory 200804 kb
Host smart-d90469e4-ba29-456b-84ae-ce2b269689f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520215500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3520215500
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.3815261601
Short name T1184
Test name
Test status
Simulation time 68350179851 ps
CPU time 37.58 seconds
Started Aug 14 04:59:17 PM PDT 24
Finished Aug 14 04:59:55 PM PDT 24
Peak memory 200964 kb
Host smart-b60c4895-1f98-461d-9c12-f5ca0ffe6095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815261601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.3815261601
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.3139594940
Short name T95
Test name
Test status
Simulation time 12644434055 ps
CPU time 3.58 seconds
Started Aug 14 04:59:19 PM PDT 24
Finished Aug 14 04:59:22 PM PDT 24
Peak memory 200596 kb
Host smart-90de03cc-9488-42f9-869a-d5f4010b1528
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139594940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3139594940
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.1386055976
Short name T409
Test name
Test status
Simulation time 29418320185 ps
CPU time 233.2 seconds
Started Aug 14 04:59:18 PM PDT 24
Finished Aug 14 05:03:11 PM PDT 24
Peak memory 200968 kb
Host smart-b9ec4c57-4f66-4fb7-9516-797ab77b3247
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1386055976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1386055976
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1816403957
Short name T514
Test name
Test status
Simulation time 6067533769 ps
CPU time 6.07 seconds
Started Aug 14 04:59:19 PM PDT 24
Finished Aug 14 04:59:25 PM PDT 24
Peak memory 199748 kb
Host smart-bb213b2c-0bc4-4a87-9cce-ed0083dba60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816403957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1816403957
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.3966677024
Short name T544
Test name
Test status
Simulation time 338746178774 ps
CPU time 30.75 seconds
Started Aug 14 04:59:21 PM PDT 24
Finished Aug 14 04:59:52 PM PDT 24
Peak memory 209292 kb
Host smart-393c8a38-c73c-40a1-9201-32e0871adb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966677024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.3966677024
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.1260085333
Short name T1101
Test name
Test status
Simulation time 18831287322 ps
CPU time 228.9 seconds
Started Aug 14 04:59:16 PM PDT 24
Finished Aug 14 05:03:05 PM PDT 24
Peak memory 200932 kb
Host smart-c808dc6d-1a67-4594-bc22-887edd77985d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1260085333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1260085333
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1557753384
Short name T1081
Test name
Test status
Simulation time 6633627749 ps
CPU time 56.66 seconds
Started Aug 14 04:59:16 PM PDT 24
Finished Aug 14 05:00:13 PM PDT 24
Peak memory 199544 kb
Host smart-5216758d-4d0a-4d6b-924e-71c9c05067c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1557753384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1557753384
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.3473554659
Short name T534
Test name
Test status
Simulation time 67175215569 ps
CPU time 27.52 seconds
Started Aug 14 04:59:22 PM PDT 24
Finished Aug 14 04:59:50 PM PDT 24
Peak memory 200868 kb
Host smart-e53daeac-3c2a-48ae-a313-6f330baeb1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473554659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3473554659
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.738317532
Short name T281
Test name
Test status
Simulation time 4974509208 ps
CPU time 7.69 seconds
Started Aug 14 04:59:18 PM PDT 24
Finished Aug 14 04:59:25 PM PDT 24
Peak memory 197452 kb
Host smart-e3d15e04-cd4f-4bf4-97c4-eca9627acbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738317532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.738317532
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.520090992
Short name T1173
Test name
Test status
Simulation time 492068913 ps
CPU time 1.04 seconds
Started Aug 14 04:59:20 PM PDT 24
Finished Aug 14 04:59:21 PM PDT 24
Peak memory 199268 kb
Host smart-3c299658-cdb1-4614-8a58-c2910e94f2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520090992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.520090992
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.83832165
Short name T473
Test name
Test status
Simulation time 154891810370 ps
CPU time 263.61 seconds
Started Aug 14 04:59:23 PM PDT 24
Finished Aug 14 05:03:47 PM PDT 24
Peak memory 209308 kb
Host smart-351070be-57b4-49fa-81cb-a933018aa263
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83832165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.83832165
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3017334838
Short name T1067
Test name
Test status
Simulation time 19309161249 ps
CPU time 79.03 seconds
Started Aug 14 04:59:18 PM PDT 24
Finished Aug 14 05:00:37 PM PDT 24
Peak memory 211508 kb
Host smart-2718d185-a341-41eb-ac9b-1324322952bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017334838 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3017334838
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.1600082029
Short name T725
Test name
Test status
Simulation time 363810788 ps
CPU time 1.28 seconds
Started Aug 14 04:59:16 PM PDT 24
Finished Aug 14 04:59:17 PM PDT 24
Peak memory 198656 kb
Host smart-ea594049-b914-4f67-802b-76084cd9c385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600082029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1600082029
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.913015503
Short name T847
Test name
Test status
Simulation time 94920925231 ps
CPU time 155.31 seconds
Started Aug 14 04:59:17 PM PDT 24
Finished Aug 14 05:01:52 PM PDT 24
Peak memory 200876 kb
Host smart-94aacd96-9e63-4a8a-881d-66831cd27e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913015503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.913015503
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.4082777380
Short name T910
Test name
Test status
Simulation time 20733320757 ps
CPU time 31.58 seconds
Started Aug 14 05:03:03 PM PDT 24
Finished Aug 14 05:03:35 PM PDT 24
Peak memory 200936 kb
Host smart-2a1040ef-f3fa-4a97-89e8-ea4d66c1e321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082777380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.4082777380
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.4087836971
Short name T88
Test name
Test status
Simulation time 17323797083 ps
CPU time 22.81 seconds
Started Aug 14 05:03:02 PM PDT 24
Finished Aug 14 05:03:25 PM PDT 24
Peak memory 209260 kb
Host smart-b5bfef9f-e869-4807-85c9-76f22ec02f46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087836971 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.4087836971
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.476429386
Short name T500
Test name
Test status
Simulation time 187994809308 ps
CPU time 79.81 seconds
Started Aug 14 05:02:57 PM PDT 24
Finished Aug 14 05:04:17 PM PDT 24
Peak memory 200972 kb
Host smart-335d5ed5-fd6b-461e-805a-4067873e921a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476429386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.476429386
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.1731450831
Short name T340
Test name
Test status
Simulation time 1048960508 ps
CPU time 15.01 seconds
Started Aug 14 05:02:56 PM PDT 24
Finished Aug 14 05:03:11 PM PDT 24
Peak memory 200888 kb
Host smart-9e0e3e7b-2438-416c-ae2b-7f203e2f374c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731450831 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.1731450831
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.212669193
Short name T587
Test name
Test status
Simulation time 40528585696 ps
CPU time 20.12 seconds
Started Aug 14 05:03:02 PM PDT 24
Finished Aug 14 05:03:23 PM PDT 24
Peak memory 200984 kb
Host smart-73596c49-5a35-4ccf-ba7d-e5eb7538ac8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212669193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.212669193
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.499304510
Short name T988
Test name
Test status
Simulation time 15984368115 ps
CPU time 56.82 seconds
Started Aug 14 05:02:56 PM PDT 24
Finished Aug 14 05:03:53 PM PDT 24
Peak memory 210524 kb
Host smart-2024b42f-274b-400d-8980-8ed1ea3c2926
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499304510 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.499304510
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.500861610
Short name T209
Test name
Test status
Simulation time 49249756856 ps
CPU time 47.69 seconds
Started Aug 14 05:03:06 PM PDT 24
Finished Aug 14 05:03:54 PM PDT 24
Peak memory 200844 kb
Host smart-693d30fd-345e-40e9-8b4e-f99bb94bb4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500861610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.500861610
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.1428100781
Short name T797
Test name
Test status
Simulation time 13863059903 ps
CPU time 38.86 seconds
Started Aug 14 05:03:07 PM PDT 24
Finished Aug 14 05:03:46 PM PDT 24
Peak memory 209352 kb
Host smart-c0df598f-58e0-4d1e-ae5b-bfc8f06edaad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428100781 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.1428100781
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3046985559
Short name T1086
Test name
Test status
Simulation time 86271329417 ps
CPU time 20.18 seconds
Started Aug 14 05:03:07 PM PDT 24
Finished Aug 14 05:03:27 PM PDT 24
Peak memory 200984 kb
Host smart-ab240d7c-09be-4c2c-bd34-edaf05092f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046985559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3046985559
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.4105386170
Short name T632
Test name
Test status
Simulation time 19394101522 ps
CPU time 29.78 seconds
Started Aug 14 05:03:05 PM PDT 24
Finished Aug 14 05:03:35 PM PDT 24
Peak memory 200952 kb
Host smart-77c30cdb-da40-4acf-a8e5-0729b6ccec29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105386170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.4105386170
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1978572343
Short name T33
Test name
Test status
Simulation time 1082295580 ps
CPU time 15.5 seconds
Started Aug 14 05:03:05 PM PDT 24
Finished Aug 14 05:03:21 PM PDT 24
Peak memory 200988 kb
Host smart-baf24d11-862c-4d93-a68e-9ecaf2096ddf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978572343 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1978572343
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.690836260
Short name T244
Test name
Test status
Simulation time 75660760465 ps
CPU time 22.37 seconds
Started Aug 14 05:03:06 PM PDT 24
Finished Aug 14 05:03:28 PM PDT 24
Peak memory 200908 kb
Host smart-8f8e5d9a-a542-4f8a-a92c-fe5628bdeac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690836260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.690836260
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.2596288044
Short name T744
Test name
Test status
Simulation time 12970207071 ps
CPU time 54.72 seconds
Started Aug 14 05:03:07 PM PDT 24
Finished Aug 14 05:04:02 PM PDT 24
Peak memory 210680 kb
Host smart-6c1ec5e8-b583-49fb-a613-ff24dc1f1269
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596288044 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2596288044
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.3293257250
Short name T1030
Test name
Test status
Simulation time 23314851597 ps
CPU time 34.54 seconds
Started Aug 14 05:03:08 PM PDT 24
Finished Aug 14 05:03:43 PM PDT 24
Peak memory 199276 kb
Host smart-38401652-9e89-4117-8ab5-c9d2932d3c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293257250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3293257250
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.894205596
Short name T941
Test name
Test status
Simulation time 9936104969 ps
CPU time 33.21 seconds
Started Aug 14 05:03:07 PM PDT 24
Finished Aug 14 05:03:40 PM PDT 24
Peak memory 200932 kb
Host smart-c447e93c-dcb8-4175-9129-11b920c7badd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894205596 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.894205596
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.2779185688
Short name T1063
Test name
Test status
Simulation time 8060571986 ps
CPU time 17.19 seconds
Started Aug 14 05:03:06 PM PDT 24
Finished Aug 14 05:03:23 PM PDT 24
Peak memory 200864 kb
Host smart-537761ac-bd8b-4685-aadf-627c94d73c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779185688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2779185688
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.4238990488
Short name T30
Test name
Test status
Simulation time 5418638419 ps
CPU time 8.61 seconds
Started Aug 14 05:03:08 PM PDT 24
Finished Aug 14 05:03:17 PM PDT 24
Peak memory 209416 kb
Host smart-23e42970-0734-4866-846d-32727f75818b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238990488 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.4238990488
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2456554173
Short name T181
Test name
Test status
Simulation time 65814838525 ps
CPU time 137.56 seconds
Started Aug 14 05:03:05 PM PDT 24
Finished Aug 14 05:05:23 PM PDT 24
Peak memory 200860 kb
Host smart-393536b1-8bf0-4c7a-aac8-3db610f65b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456554173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2456554173
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1859314415
Short name T657
Test name
Test status
Simulation time 22188295 ps
CPU time 0.57 seconds
Started Aug 14 04:59:28 PM PDT 24
Finished Aug 14 04:59:28 PM PDT 24
Peak memory 196280 kb
Host smart-01300cca-eda8-4340-b7fa-4fb6ec7b315e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859314415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1859314415
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.1500930546
Short name T475
Test name
Test status
Simulation time 30366868486 ps
CPU time 19.37 seconds
Started Aug 14 04:59:20 PM PDT 24
Finished Aug 14 04:59:40 PM PDT 24
Peak memory 200924 kb
Host smart-7eefdd07-a89d-44a6-a289-defe4eb9d53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500930546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1500930546
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2491007935
Short name T567
Test name
Test status
Simulation time 84555189007 ps
CPU time 73.87 seconds
Started Aug 14 04:59:28 PM PDT 24
Finished Aug 14 05:00:42 PM PDT 24
Peak memory 200980 kb
Host smart-f2479346-a5c2-4f09-a3b9-f17e37a2dae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491007935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2491007935
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.4146878626
Short name T704
Test name
Test status
Simulation time 47017275080 ps
CPU time 17.25 seconds
Started Aug 14 04:59:26 PM PDT 24
Finished Aug 14 04:59:43 PM PDT 24
Peak memory 200868 kb
Host smart-f55c3d74-a222-4d33-b2e0-672befdac901
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146878626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.4146878626
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.2807572920
Short name T404
Test name
Test status
Simulation time 86665841210 ps
CPU time 400.05 seconds
Started Aug 14 04:59:26 PM PDT 24
Finished Aug 14 05:06:06 PM PDT 24
Peak memory 200852 kb
Host smart-87b29811-64cb-498e-8cc4-8f6dff6229e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2807572920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2807572920
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.53745623
Short name T981
Test name
Test status
Simulation time 5113248690 ps
CPU time 2.37 seconds
Started Aug 14 04:59:30 PM PDT 24
Finished Aug 14 04:59:33 PM PDT 24
Peak memory 199652 kb
Host smart-832d7ae1-6fcd-43de-beb3-89ed6248953a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53745623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.53745623
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.4124472877
Short name T7
Test name
Test status
Simulation time 298084053948 ps
CPU time 58.41 seconds
Started Aug 14 04:59:29 PM PDT 24
Finished Aug 14 05:00:28 PM PDT 24
Peak memory 209336 kb
Host smart-fb8e66cc-0d79-4a15-9f64-8a766c22f194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124472877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.4124472877
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.4283496981
Short name T248
Test name
Test status
Simulation time 31821372732 ps
CPU time 1753.72 seconds
Started Aug 14 04:59:26 PM PDT 24
Finished Aug 14 05:28:40 PM PDT 24
Peak memory 200968 kb
Host smart-9d3f6d51-f464-455d-a4c6-13bd162eecf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4283496981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.4283496981
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2112998192
Short name T800
Test name
Test status
Simulation time 3205607524 ps
CPU time 1.72 seconds
Started Aug 14 04:59:30 PM PDT 24
Finished Aug 14 04:59:32 PM PDT 24
Peak memory 199280 kb
Host smart-c32e288e-1d78-4c66-a12c-ce0b60dc0e7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2112998192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2112998192
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.4003534843
Short name T325
Test name
Test status
Simulation time 58422708999 ps
CPU time 90.38 seconds
Started Aug 14 04:59:28 PM PDT 24
Finished Aug 14 05:00:58 PM PDT 24
Peak memory 200820 kb
Host smart-d3666e99-117a-4a4f-8e07-d032ad87abf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003534843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.4003534843
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.430900667
Short name T594
Test name
Test status
Simulation time 4465364927 ps
CPU time 2.41 seconds
Started Aug 14 04:59:29 PM PDT 24
Finished Aug 14 04:59:32 PM PDT 24
Peak memory 197172 kb
Host smart-5f71cd06-e5c7-44b8-a50f-e0957a59d2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430900667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.430900667
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.2291361763
Short name T668
Test name
Test status
Simulation time 509925895 ps
CPU time 1.46 seconds
Started Aug 14 04:59:17 PM PDT 24
Finished Aug 14 04:59:19 PM PDT 24
Peak memory 199428 kb
Host smart-9a4cdac9-9077-4d8f-9d0b-6e8ca3cb2558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291361763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2291361763
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.1803890486
Short name T789
Test name
Test status
Simulation time 491163642609 ps
CPU time 254.77 seconds
Started Aug 14 04:59:29 PM PDT 24
Finished Aug 14 05:03:44 PM PDT 24
Peak memory 200968 kb
Host smart-137d5154-1407-4f42-84c4-b4ad2e9a14d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803890486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1803890486
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.3694368017
Short name T793
Test name
Test status
Simulation time 20958703716 ps
CPU time 67.16 seconds
Started Aug 14 04:59:28 PM PDT 24
Finished Aug 14 05:00:36 PM PDT 24
Peak memory 217416 kb
Host smart-4bc5e77d-5850-4079-a65c-3ede7abe485f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694368017 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.3694368017
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.1526294255
Short name T776
Test name
Test status
Simulation time 6721208228 ps
CPU time 19.15 seconds
Started Aug 14 04:59:29 PM PDT 24
Finished Aug 14 04:59:48 PM PDT 24
Peak memory 200848 kb
Host smart-9098b8ec-2f2e-42fd-ade9-c37e5fa78cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526294255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1526294255
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.1280737753
Short name T602
Test name
Test status
Simulation time 124577329014 ps
CPU time 63.6 seconds
Started Aug 14 04:59:19 PM PDT 24
Finished Aug 14 05:00:23 PM PDT 24
Peak memory 200900 kb
Host smart-d7c9dce5-5b65-4280-9e8f-ee3eed2148f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280737753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1280737753
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.3819437506
Short name T1104
Test name
Test status
Simulation time 19171222245 ps
CPU time 28.41 seconds
Started Aug 14 05:03:07 PM PDT 24
Finished Aug 14 05:03:35 PM PDT 24
Peak memory 200936 kb
Host smart-699715ff-b84f-4cda-af57-f31c5928e4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819437506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3819437506
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.691279039
Short name T592
Test name
Test status
Simulation time 2359132018 ps
CPU time 30.18 seconds
Started Aug 14 05:03:07 PM PDT 24
Finished Aug 14 05:03:37 PM PDT 24
Peak memory 217316 kb
Host smart-bf4c0e31-033c-4a8b-87db-adebb6d5872a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691279039 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.691279039
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.1199606100
Short name T769
Test name
Test status
Simulation time 1651849161 ps
CPU time 15.21 seconds
Started Aug 14 05:03:09 PM PDT 24
Finished Aug 14 05:03:24 PM PDT 24
Peak memory 209352 kb
Host smart-7c3efd2f-0e78-481c-aa0e-55b6b9259e34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199606100 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1199606100
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3802442718
Short name T427
Test name
Test status
Simulation time 73733581985 ps
CPU time 105.76 seconds
Started Aug 14 05:03:06 PM PDT 24
Finished Aug 14 05:04:52 PM PDT 24
Peak memory 200836 kb
Host smart-4b6490ca-0666-4178-8dc7-53be05a36ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802442718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3802442718
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.1173441618
Short name T785
Test name
Test status
Simulation time 1837052444 ps
CPU time 16.45 seconds
Started Aug 14 05:03:04 PM PDT 24
Finished Aug 14 05:03:21 PM PDT 24
Peak memory 200836 kb
Host smart-3b6b838b-032e-423f-954c-fecc59c175eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173441618 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.1173441618
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3420868842
Short name T585
Test name
Test status
Simulation time 18460435025 ps
CPU time 32.88 seconds
Started Aug 14 05:03:06 PM PDT 24
Finished Aug 14 05:03:39 PM PDT 24
Peak memory 200996 kb
Host smart-e4d86cdc-d4ad-41b7-9267-a71d5a34b018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420868842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3420868842
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.966332595
Short name T729
Test name
Test status
Simulation time 2501901069 ps
CPU time 20.5 seconds
Started Aug 14 05:03:05 PM PDT 24
Finished Aug 14 05:03:26 PM PDT 24
Peak memory 216492 kb
Host smart-e429c627-cd57-4a3e-a451-ffb0c7c6a77c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966332595 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.966332595
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1384198339
Short name T405
Test name
Test status
Simulation time 25847343341 ps
CPU time 12.1 seconds
Started Aug 14 05:03:07 PM PDT 24
Finished Aug 14 05:03:19 PM PDT 24
Peak memory 200908 kb
Host smart-5adabe7a-1b32-4f61-b260-a64cd94198d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384198339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1384198339
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.4173424929
Short name T670
Test name
Test status
Simulation time 951270276 ps
CPU time 37.11 seconds
Started Aug 14 05:03:06 PM PDT 24
Finished Aug 14 05:03:43 PM PDT 24
Peak memory 200964 kb
Host smart-c0f6b7df-cd70-4543-89e5-fac99b74ca2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173424929 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.4173424929
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.4080430952
Short name T166
Test name
Test status
Simulation time 50589369235 ps
CPU time 119.27 seconds
Started Aug 14 05:03:05 PM PDT 24
Finished Aug 14 05:05:04 PM PDT 24
Peak memory 200968 kb
Host smart-4e48eb06-43a3-451d-be7b-870416c59ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080430952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.4080430952
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.935171118
Short name T82
Test name
Test status
Simulation time 3875082771 ps
CPU time 44.35 seconds
Started Aug 14 05:03:07 PM PDT 24
Finished Aug 14 05:03:51 PM PDT 24
Peak memory 217316 kb
Host smart-ab1b8627-b95f-43d3-a8b7-a50903aad2f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935171118 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.935171118
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2989582679
Short name T237
Test name
Test status
Simulation time 30736000749 ps
CPU time 29.37 seconds
Started Aug 14 05:03:07 PM PDT 24
Finished Aug 14 05:03:37 PM PDT 24
Peak memory 200972 kb
Host smart-9e0aa2e3-e60d-4744-aee8-4f3044ddb5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989582679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2989582679
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3319053052
Short name T338
Test name
Test status
Simulation time 4419219481 ps
CPU time 102.28 seconds
Started Aug 14 05:03:07 PM PDT 24
Finished Aug 14 05:04:49 PM PDT 24
Peak memory 217340 kb
Host smart-203ad5f5-8148-42d8-8e01-047e2b1b075f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319053052 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3319053052
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1772752116
Short name T675
Test name
Test status
Simulation time 15351935039 ps
CPU time 14.93 seconds
Started Aug 14 05:03:08 PM PDT 24
Finished Aug 14 05:03:23 PM PDT 24
Peak memory 199252 kb
Host smart-419d5f8f-b573-427f-bab1-8842f6be03fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772752116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1772752116
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.3416031299
Short name T337
Test name
Test status
Simulation time 43853401791 ps
CPU time 60.94 seconds
Started Aug 14 05:03:07 PM PDT 24
Finished Aug 14 05:04:08 PM PDT 24
Peak memory 217524 kb
Host smart-7c8db046-057e-4e36-b523-96d425e24202
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416031299 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.3416031299
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2975979280
Short name T685
Test name
Test status
Simulation time 22072766729 ps
CPU time 54.99 seconds
Started Aug 14 05:03:07 PM PDT 24
Finished Aug 14 05:04:02 PM PDT 24
Peak memory 200920 kb
Host smart-c0e46f84-bd66-49ac-959f-2ee6da110620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975979280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2975979280
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.772976991
Short name T773
Test name
Test status
Simulation time 8500019884 ps
CPU time 74.83 seconds
Started Aug 14 05:03:08 PM PDT 24
Finished Aug 14 05:04:23 PM PDT 24
Peak memory 215244 kb
Host smart-4ac70911-23a7-4d99-932b-d27da12fa1a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772976991 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.772976991
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3870909219
Short name T271
Test name
Test status
Simulation time 100460345425 ps
CPU time 147.82 seconds
Started Aug 14 05:03:08 PM PDT 24
Finished Aug 14 05:05:36 PM PDT 24
Peak memory 200996 kb
Host smart-0322c440-06cf-4933-82ba-3a369605733e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870909219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3870909219
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.3101838443
Short name T1078
Test name
Test status
Simulation time 2204536910 ps
CPU time 30.22 seconds
Started Aug 14 05:03:16 PM PDT 24
Finished Aug 14 05:03:46 PM PDT 24
Peak memory 200992 kb
Host smart-804c4302-30b7-4ec4-a94e-c4e8dcf89b4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101838443 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.3101838443
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.3260042603
Short name T524
Test name
Test status
Simulation time 11158872 ps
CPU time 0.56 seconds
Started Aug 14 04:59:28 PM PDT 24
Finished Aug 14 04:59:29 PM PDT 24
Peak memory 195744 kb
Host smart-585717ba-fa56-450a-8d79-026695e785ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260042603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3260042603
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.2761693721
Short name T499
Test name
Test status
Simulation time 49911354972 ps
CPU time 77.29 seconds
Started Aug 14 04:59:28 PM PDT 24
Finished Aug 14 05:00:45 PM PDT 24
Peak memory 200972 kb
Host smart-d2d07788-5369-40f7-9b24-af9096a0caf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761693721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2761693721
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.3689703401
Short name T863
Test name
Test status
Simulation time 21967609657 ps
CPU time 12.05 seconds
Started Aug 14 04:59:26 PM PDT 24
Finished Aug 14 04:59:38 PM PDT 24
Peak memory 200892 kb
Host smart-6a96b987-e22c-4e1a-bda2-b9b0cc053fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689703401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3689703401
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.3448969057
Short name T352
Test name
Test status
Simulation time 14115677873 ps
CPU time 24.82 seconds
Started Aug 14 04:59:28 PM PDT 24
Finished Aug 14 04:59:53 PM PDT 24
Peak memory 200852 kb
Host smart-13f1be4d-7678-47ec-ab76-32abf51d1551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448969057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3448969057
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.4101660026
Short name T1100
Test name
Test status
Simulation time 41285052534 ps
CPU time 34.43 seconds
Started Aug 14 04:59:29 PM PDT 24
Finished Aug 14 05:00:04 PM PDT 24
Peak memory 200808 kb
Host smart-ceb98504-4576-4009-b98b-908891bcbcb5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101660026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.4101660026
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1638918082
Short name T807
Test name
Test status
Simulation time 118839878036 ps
CPU time 306.56 seconds
Started Aug 14 04:59:26 PM PDT 24
Finished Aug 14 05:04:32 PM PDT 24
Peak memory 200812 kb
Host smart-c76bdc7a-2ba7-4229-b446-6afa4ae7822c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1638918082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1638918082
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.2774288589
Short name T1064
Test name
Test status
Simulation time 8618834214 ps
CPU time 8.48 seconds
Started Aug 14 04:59:26 PM PDT 24
Finished Aug 14 04:59:34 PM PDT 24
Peak memory 199244 kb
Host smart-c2c2c459-7f73-40cc-bec7-705bda23f8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774288589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2774288589
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.2238792726
Short name T470
Test name
Test status
Simulation time 47952222660 ps
CPU time 64.5 seconds
Started Aug 14 04:59:28 PM PDT 24
Finished Aug 14 05:00:32 PM PDT 24
Peak memory 201104 kb
Host smart-cf0455ab-88dd-4234-8452-6bf9ec39b78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238792726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2238792726
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.3436100808
Short name T547
Test name
Test status
Simulation time 11712114414 ps
CPU time 290.5 seconds
Started Aug 14 04:59:27 PM PDT 24
Finished Aug 14 05:04:18 PM PDT 24
Peak memory 200896 kb
Host smart-8573de3a-59e0-4b60-afc4-70127c1a57be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3436100808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3436100808
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.3591634215
Short name T886
Test name
Test status
Simulation time 2860643364 ps
CPU time 6.04 seconds
Started Aug 14 04:59:27 PM PDT 24
Finished Aug 14 04:59:33 PM PDT 24
Peak memory 198900 kb
Host smart-ecf14409-2956-4b88-85f7-0c741bc8d27d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3591634215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.3591634215
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2378283975
Short name T577
Test name
Test status
Simulation time 131225455129 ps
CPU time 172.84 seconds
Started Aug 14 04:59:27 PM PDT 24
Finished Aug 14 05:02:20 PM PDT 24
Peak memory 200852 kb
Host smart-8fd01867-557b-4ec9-bad9-8531a898fa70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378283975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2378283975
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.4193900112
Short name T285
Test name
Test status
Simulation time 2141290446 ps
CPU time 1.79 seconds
Started Aug 14 04:59:30 PM PDT 24
Finished Aug 14 04:59:32 PM PDT 24
Peak memory 196316 kb
Host smart-c6cd73ec-a071-4e47-8a17-1a5028119762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193900112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.4193900112
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1152136135
Short name T1103
Test name
Test status
Simulation time 714105114 ps
CPU time 3.16 seconds
Started Aug 14 04:59:25 PM PDT 24
Finished Aug 14 04:59:29 PM PDT 24
Peak memory 199332 kb
Host smart-1b374f40-1c29-4e37-8d4c-0be496b13332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152136135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1152136135
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.1934965015
Short name T761
Test name
Test status
Simulation time 132584256516 ps
CPU time 1041.57 seconds
Started Aug 14 04:59:28 PM PDT 24
Finished Aug 14 05:16:50 PM PDT 24
Peak memory 200972 kb
Host smart-274ffc88-1fff-4606-926e-bf850d89907d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934965015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1934965015
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3375664016
Short name T827
Test name
Test status
Simulation time 2009895347 ps
CPU time 31.74 seconds
Started Aug 14 04:59:27 PM PDT 24
Finished Aug 14 04:59:59 PM PDT 24
Peak memory 216648 kb
Host smart-8ce2ae64-f34a-4cc0-a0e7-46b6e326e0b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375664016 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3375664016
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1891860839
Short name T316
Test name
Test status
Simulation time 893378050 ps
CPU time 2.71 seconds
Started Aug 14 04:59:27 PM PDT 24
Finished Aug 14 04:59:30 PM PDT 24
Peak memory 199296 kb
Host smart-6e26d4d9-2856-4723-a5f4-1ce4a2e2067d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891860839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1891860839
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.1317254218
Short name T236
Test name
Test status
Simulation time 53209566767 ps
CPU time 18.15 seconds
Started Aug 14 04:59:27 PM PDT 24
Finished Aug 14 04:59:45 PM PDT 24
Peak memory 200956 kb
Host smart-488a9cc2-520b-4b73-8e1d-000b91172a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317254218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1317254218
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.1578998504
Short name T450
Test name
Test status
Simulation time 100324132427 ps
CPU time 45.77 seconds
Started Aug 14 05:03:18 PM PDT 24
Finished Aug 14 05:04:04 PM PDT 24
Peak memory 200876 kb
Host smart-724b4416-5280-49ef-91c1-8cb2a8057e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578998504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1578998504
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.29779905
Short name T736
Test name
Test status
Simulation time 1237110089 ps
CPU time 19.06 seconds
Started Aug 14 05:03:21 PM PDT 24
Finished Aug 14 05:03:40 PM PDT 24
Peak memory 217520 kb
Host smart-10cf3090-cb67-4d8f-a137-14b229c52b28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29779905 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.29779905
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2101148333
Short name T1109
Test name
Test status
Simulation time 59533458623 ps
CPU time 23.65 seconds
Started Aug 14 05:03:16 PM PDT 24
Finished Aug 14 05:03:39 PM PDT 24
Peak memory 200972 kb
Host smart-f12c2aa7-9192-4ca6-8f04-b59d083e7fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101148333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2101148333
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2212784065
Short name T821
Test name
Test status
Simulation time 21974358840 ps
CPU time 117.72 seconds
Started Aug 14 05:03:16 PM PDT 24
Finished Aug 14 05:05:14 PM PDT 24
Peak memory 217512 kb
Host smart-b20474a7-d24c-46ad-9f8b-676d7926a35f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212784065 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2212784065
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.1039734168
Short name T994
Test name
Test status
Simulation time 3322903365 ps
CPU time 13.7 seconds
Started Aug 14 05:03:19 PM PDT 24
Finished Aug 14 05:03:33 PM PDT 24
Peak memory 216768 kb
Host smart-ab8a23bb-5fa4-4634-a5af-bfe7b7f0d5f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039734168 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.1039734168
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3424643120
Short name T267
Test name
Test status
Simulation time 164267948129 ps
CPU time 262.42 seconds
Started Aug 14 05:03:15 PM PDT 24
Finished Aug 14 05:07:38 PM PDT 24
Peak memory 200548 kb
Host smart-25c0df2e-dea8-4933-9aa4-c7ee0873ff30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424643120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3424643120
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.4148222201
Short name T304
Test name
Test status
Simulation time 9928239524 ps
CPU time 28.3 seconds
Started Aug 14 05:03:16 PM PDT 24
Finished Aug 14 05:03:45 PM PDT 24
Peak memory 209412 kb
Host smart-eb3742aa-0638-428d-a14b-7757389fa395
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148222201 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.4148222201
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3185663887
Short name T176
Test name
Test status
Simulation time 38805090382 ps
CPU time 12.53 seconds
Started Aug 14 05:03:20 PM PDT 24
Finished Aug 14 05:03:33 PM PDT 24
Peak memory 200980 kb
Host smart-25a87e53-d7e1-433e-bef1-9a35686ce486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185663887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3185663887
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.2984640718
Short name T86
Test name
Test status
Simulation time 8747502203 ps
CPU time 13.36 seconds
Started Aug 14 05:03:20 PM PDT 24
Finished Aug 14 05:03:34 PM PDT 24
Peak memory 209440 kb
Host smart-47e988aa-b6f6-4533-9177-9247a052a2ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984640718 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.2984640718
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3690523053
Short name T119
Test name
Test status
Simulation time 31844374486 ps
CPU time 27.07 seconds
Started Aug 14 05:03:15 PM PDT 24
Finished Aug 14 05:03:42 PM PDT 24
Peak memory 200880 kb
Host smart-55134224-6ed6-491b-b6c3-9d43ea0b369d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690523053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3690523053
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.1211556932
Short name T849
Test name
Test status
Simulation time 10664013527 ps
CPU time 31.72 seconds
Started Aug 14 05:03:15 PM PDT 24
Finished Aug 14 05:03:47 PM PDT 24
Peak memory 210628 kb
Host smart-b962966d-5384-444a-986a-577c0f933f9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211556932 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.1211556932
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3314674851
Short name T220
Test name
Test status
Simulation time 30012746152 ps
CPU time 55.76 seconds
Started Aug 14 05:03:18 PM PDT 24
Finished Aug 14 05:04:14 PM PDT 24
Peak memory 200900 kb
Host smart-3c24da7a-11cb-4200-b191-cfaeed16ac4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314674851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3314674851
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.76024451
Short name T170
Test name
Test status
Simulation time 14868918677 ps
CPU time 17.65 seconds
Started Aug 14 05:03:16 PM PDT 24
Finished Aug 14 05:03:33 PM PDT 24
Peak memory 209312 kb
Host smart-9d54c6d6-1cc7-4ea6-a8a5-1f9b871a4896
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76024451 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.76024451
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.3737609974
Short name T814
Test name
Test status
Simulation time 111540940537 ps
CPU time 78.93 seconds
Started Aug 14 05:03:16 PM PDT 24
Finished Aug 14 05:04:35 PM PDT 24
Peak memory 200916 kb
Host smart-13193b27-55af-48f6-b81d-e5f99ff48017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737609974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3737609974
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1269758649
Short name T1119
Test name
Test status
Simulation time 4419489828 ps
CPU time 25.85 seconds
Started Aug 14 05:03:17 PM PDT 24
Finished Aug 14 05:03:43 PM PDT 24
Peak memory 217320 kb
Host smart-29f44655-c55b-47ec-96b1-1ebe671a106e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269758649 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1269758649
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.3250286076
Short name T303
Test name
Test status
Simulation time 40208030953 ps
CPU time 13.21 seconds
Started Aug 14 05:03:18 PM PDT 24
Finished Aug 14 05:03:32 PM PDT 24
Peak memory 200916 kb
Host smart-7ec26a81-e788-49ea-8e5e-a1c4283d9550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250286076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3250286076
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.575881210
Short name T1097
Test name
Test status
Simulation time 18198570397 ps
CPU time 48.02 seconds
Started Aug 14 05:03:19 PM PDT 24
Finished Aug 14 05:04:07 PM PDT 24
Peak memory 217640 kb
Host smart-5be01675-419c-4c0e-af44-942a0207bd16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575881210 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.575881210
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.2864390181
Short name T1076
Test name
Test status
Simulation time 23700436455 ps
CPU time 34.84 seconds
Started Aug 14 05:03:15 PM PDT 24
Finished Aug 14 05:03:50 PM PDT 24
Peak memory 200860 kb
Host smart-d392c2ba-8a19-412e-8316-c19611a86f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864390181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2864390181
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.3323004122
Short name T798
Test name
Test status
Simulation time 3290271668 ps
CPU time 41.64 seconds
Started Aug 14 05:03:16 PM PDT 24
Finished Aug 14 05:03:57 PM PDT 24
Peak memory 201040 kb
Host smart-ccb2c4a5-4d4f-4096-8fb4-8d9e0a205b9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323004122 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3323004122
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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