Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	82984	1			T1	1		T2	2		T3	17
all_values[1]	82984	1			T1	1		T2	2		T3	17
all_values[2]	82984	1			T1	1		T2	2		T3	17
all_values[3]	82984	1			T1	1		T2	2		T3	17
all_values[4]	82984	1			T1	1		T2	2		T3	17
all_values[5]	82984	1			T1	1		T2	2		T3	17
all_values[6]	82984	1			T1	1		T2	2		T3	17
all_values[7]	82984	1			T1	1		T2	2		T3	17
all_values[8]	82984	1			T1	1		T2	2		T3	17

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

379882

1

T1

7

T2

14

T3

73

auto[1]

366974

1

T1

2

T2

4

T3

80

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

674944

1

T1

7

T2

13

T3

142

auto[1]

71912

1

T1

2

T2

5

T3

11

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	25240	1			T3	3		T6	7		T9	551
all_values[0]	auto[0]	auto[1]	17406	1			T1	1		T2	2		T4	2
all_values[0]	auto[1]	auto[0]	22312	1			T3	11		T5	3		T6	1
all_values[0]	auto[1]	auto[1]	18026	1			T3	3		T9	163		T11	115
all_values[1]	auto[0]	auto[0]	41003	1			T1	1		T2	2		T3	17
all_values[1]	auto[0]	auto[1]	1292	1			T13	14		T14	2		T74	3
all_values[1]	auto[1]	auto[0]	39437	1			T7	12		T9	1011		T11	21
all_values[1]	auto[1]	auto[1]	1252	1			T15	6		T43	2		T46	2
all_values[2]	auto[0]	auto[0]	38079	1			T1	1		T2	1		T4	1
all_values[2]	auto[0]	auto[1]	2236	1			T2	1		T4	1		T5	2
all_values[2]	auto[1]	auto[0]	40476	1			T3	12		T7	5		T8	1
all_values[2]	auto[1]	auto[1]	2193	1			T3	5		T7	1		T9	7
all_values[3]	auto[0]	auto[0]	42079	1			T2	2		T3	8		T4	2
all_values[3]	auto[0]	auto[1]	263	1			T5	1		T74	2		T134	1
all_values[3]	auto[1]	auto[0]	40340	1			T1	1		T3	9		T5	11
all_values[3]	auto[1]	auto[1]	302	1			T13	1		T14	4		T15	1
all_values[4]	auto[0]	auto[0]	40981	1			T1	1		T2	2		T3	4
all_values[4]	auto[0]	auto[1]	377	1			T13	5		T16	1		T244	6
all_values[4]	auto[1]	auto[0]	41278	1			T3	13		T5	2		T6	7
all_values[4]	auto[1]	auto[1]	348	1			T15	13		T21	11		T39	2
all_values[5]	auto[0]	auto[0]	41843	1			T3	10		T4	2		T5	16
all_values[5]	auto[0]	auto[1]	171	1			T16	3		T18	2		T35	3
all_values[5]	auto[1]	auto[0]	40810	1			T1	1		T2	2		T3	7
all_values[5]	auto[1]	auto[1]	160	1			T18	2		T121	1		T245	1
all_values[6]	auto[0]	auto[0]	42420	1			T1	1		T2	2		T3	14
all_values[6]	auto[0]	auto[1]	153	1			T16	2		T18	3		T35	1
all_values[6]	auto[1]	auto[0]	40255	1			T3	3		T5	2		T6	8
all_values[6]	auto[1]	auto[1]	156	1			T16	2		T121	1		T96	2
all_values[7]	auto[0]	auto[0]	42521	1			T1	1		T2	2		T3	4
all_values[7]	auto[0]	auto[1]	266	1			T18	1		T135	3		T35	2
all_values[7]	auto[1]	auto[0]	39892	1			T3	13		T5	13		T6	7
all_values[7]	auto[1]	auto[1]	305	1			T24	1		T35	1		T246	2
all_values[8]	auto[0]	auto[0]	30285	1			T3	13		T5	3		T6	1
all_values[8]	auto[0]	auto[1]	13267	1			T1	1		T4	2		T6	2
all_values[8]	auto[1]	auto[0]	25693	1			T3	1		T6	7		T7	3
all_values[8]	auto[1]	auto[1]	13739	1			T2	2		T3	3		T5	13