Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2586

1

T1

1

T2

1

T3

1

auto[UartRx]

2586

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4464	1			T1	2		T2	2		T3	2
values[1]	49	1			T16	1		T26	1		T18	2
values[2]	57	1			T16	1		T34	1		T35	2
values[3]	54	1			T16	3		T18	2		T35	1
values[4]	68	1			T26	1		T18	1		T34	1
values[5]	66	1			T36	1		T96	1		T97	2
values[6]	62	1			T26	1		T126	2		T323	2
values[7]	61	1			T25	1		T16	1		T26	1
values[8]	77	1			T18	1		T35	2		T96	1
values[9]	67	1			T16	1		T34	1		T126	2
values[10]	95	1			T25	1		T16	4		T35	2

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2332	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	12	1			T284	1		T324	1		T325	1
auto[UartTx]	values[2]	20	1			T34	1		T35	1		T326	2
auto[UartTx]	values[3]	21	1			T16	2		T18	1		T35	1
auto[UartTx]	values[4]	23	1			T18	1		T35	1		T38	1
auto[UartTx]	values[5]	29	1			T36	1		T327	1		T323	1
auto[UartTx]	values[6]	23	1			T126	1		T323	1		T100	1
auto[UartTx]	values[7]	26	1			T16	1		T26	1		T18	1
auto[UartTx]	values[8]	23	1			T245	1		T126	1		T323	1
auto[UartTx]	values[9]	28	1			T34	1		T126	1		T95	1
auto[UartTx]	values[10]	29	1			T16	2		T39	1		T327	1
auto[UartRx]	values[0]	2132	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	37	1			T16	1		T26	1		T18	2
auto[UartRx]	values[2]	37	1			T16	1		T35	1		T36	1
auto[UartRx]	values[3]	33	1			T16	1		T18	1		T245	1
auto[UartRx]	values[4]	45	1			T26	1		T34	1		T35	1
auto[UartRx]	values[5]	37	1			T96	1		T97	2		T323	1
auto[UartRx]	values[6]	39	1			T26	1		T126	1		T323	1
auto[UartRx]	values[7]	35	1			T25	1		T121	1		T97	1
auto[UartRx]	values[8]	54	1			T18	1		T35	2		T96	1
auto[UartRx]	values[9]	39	1			T16	1		T126	1		T327	2
auto[UartRx]	values[10]	66	1			T25	1		T16	2		T35	2