Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1885	1			T1	10		T5	1		T8	11
auto[BaudRate115200]	1530	1			T4	2		T5	2		T6	1
auto[BaudRate230400]	1539	1			T5	2		T6	2		T9	4
auto[BaudRate128Kbps]	1595	1			T6	3		T7	4		T9	3
auto[BaudRate256Kbps]	1750	1			T2	2		T3	3		T5	2
auto[BaudRate1Mbps]	1500	1			T2	2		T3	1		T6	2
auto[BaudRate1p5Mbps]	1147	1			T2	4		T3	1		T7	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1236	1			T3	5		T8	11		T10	2
freqs[25]	1197	1			T1	10		T33	11		T131	6
freqs[48]	309	1			T142	10		T116	7		T328	2
freqs[50]	459	1			T9	9		T25	5		T288	2
freqs[100]	1302	1			T7	10		T11	9		T15	3

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	199	1			T8	11		T10	1		T156	1
auto[BaudRate9600]	freqs[25]	203	1			T1	10		T33	1		T131	3
auto[BaudRate9600]	freqs[48]	54	1			T142	1		T251	1		T252	2
auto[BaudRate9600]	freqs[50]	87	1			T25	1		T47	2		T329	9
auto[BaudRate9600]	freqs[100]	168	1			T11	3		T46	1		T186	1
auto[BaudRate115200]	freqs[24]	187	1			T10	1		T156	1		T18	2
auto[BaudRate115200]	freqs[25]	159	1			T131	1		T184	3		T267	2
auto[BaudRate115200]	freqs[48]	27	1			T142	1		T116	1		T251	1
auto[BaudRate115200]	freqs[50]	35	1			T25	1		T35	1		T270	1
auto[BaudRate115200]	freqs[100]	194	1			T7	2		T11	1		T15	1
auto[BaudRate230400]	freqs[24]	172	1			T156	2		T18	6		T247	4
auto[BaudRate230400]	freqs[25]	180	1			T33	5		T131	1		T137	2
auto[BaudRate230400]	freqs[48]	41	1			T142	1		T328	1		T246	2
auto[BaudRate230400]	freqs[50]	67	1			T9	4		T47	3		T330	6
auto[BaudRate230400]	freqs[100]	175	1			T11	1		T15	2		T46	3
auto[BaudRate128Kbps]	freqs[24]	186	1			T22	3		T18	4		T331	6
auto[BaudRate128Kbps]	freqs[25]	183	1			T137	1		T184	1		T267	2
auto[BaudRate128Kbps]	freqs[48]	34	1			T116	2		T251	2		T246	2
auto[BaudRate128Kbps]	freqs[50]	68	1			T9	3		T25	1		T47	3
auto[BaudRate128Kbps]	freqs[100]	172	1			T7	4		T11	2		T45	1
auto[BaudRate256Kbps]	freqs[24]	158	1			T3	3		T44	3		T156	1
auto[BaudRate256Kbps]	freqs[25]	176	1			T33	4		T131	1		T137	1
auto[BaudRate256Kbps]	freqs[48]	50	1			T142	4		T116	3		T251	1
auto[BaudRate256Kbps]	freqs[50]	66	1			T25	1		T330	3		T35	2
auto[BaudRate256Kbps]	freqs[100]	194	1			T7	2		T45	1		T46	8
auto[BaudRate1Mbps]	freqs[24]	209	1			T3	1		T44	4		T22	6
auto[BaudRate1Mbps]	freqs[25]	190	1			T184	1		T267	4		T185	1
auto[BaudRate1Mbps]	freqs[48]	47	1			T142	3		T116	1		T251	2
auto[BaudRate1Mbps]	freqs[50]	67	1			T9	1		T288	1		T47	1
auto[BaudRate1Mbps]	freqs[100]	211	1			T7	1		T11	1		T138	2
auto[BaudRate1p5Mbps]	freqs[25]	106	1			T33	1		T137	1		T267	2
auto[BaudRate1p5Mbps]	freqs[48]	56	1			T328	1		T251	2		T37	1
auto[BaudRate1p5Mbps]	freqs[50]	69	1			T9	1		T25	1		T288	1
auto[BaudRate1p5Mbps]	freqs[100]	188	1			T7	1		T11	1		T46	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded