Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.91	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	12	118	90.77

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	12	118	90.77	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	24746225	1			T1	1		T2	22		T3	31379
all_levels[1]	180296	1			T2	2		T3	2050		T7	1
all_levels[2]	2086	1			T2	2		T3	13		T11	2
all_levels[3]	922	1			T11	1		T33	2		T13	2
all_levels[4]	612	1			T2	1		T6	1		T11	2
all_levels[5]	475	1			T6	1		T33	1		T13	2
all_levels[6]	365	1			T11	5		T33	1		T129	1
all_levels[7]	277	1			T6	1		T11	1		T13	1
all_levels[8]	240	1			T2	1		T11	1		T14	1
all_levels[9]	191	1			T6	2		T33	1		T43	2
all_levels[10]	191	1			T2	1		T14	3		T43	1
all_levels[11]	175	1			T2	1		T14	1		T130	1
all_levels[12]	126	1			T2	2		T6	1		T11	1
all_levels[13]	136	1			T2	2		T49	1		T50	1
all_levels[14]	106	1			T33	1		T14	1		T130	1
all_levels[15]	105	1			T11	1		T13	1		T131	1
all_levels[16]	95	1			T131	1		T50	1		T110	2
all_levels[17]	85	1			T129	1		T40	1		T14	1
all_levels[18]	86	1			T33	1		T132	1		T133	2
all_levels[19]	64	1			T134	2		T48	1		T105	1
all_levels[20]	62	1			T5	2		T129	1		T134	2
all_levels[21]	64	1			T107	1		T116	1		T135	1
all_levels[22]	57	1			T6	1		T110	2		T136	1
all_levels[23]	46	1			T6	1		T135	1		T113	1
all_levels[24]	48	1			T14	1		T110	1		T116	2
all_levels[25]	42	1			T13	1		T132	1		T137	1
all_levels[26]	41	1			T14	2		T138	1		T110	1
all_levels[27]	37	1			T139	1		T140	1		T141	1
all_levels[28]	37	1			T74	1		T132	1		T50	2
all_levels[29]	36	1			T142	1		T135	1		T143	1
all_levels[30]	32	1			T11	1		T116	1		T24	1
all_levels[31]	23	1			T50	1		T142	2		T144	1
all_levels[32]	33	1			T13	1		T102	1		T107	1
all_levels[33]	38	1			T13	1		T105	3		T145	1
all_levels[34]	15	1			T13	1		T134	1		T146	1
all_levels[35]	27	1			T107	1		T147	1		T139	1
all_levels[36]	17	1			T114	2		T148	1		T149	1
all_levels[37]	16	1			T14	2		T132	1		T150	1
all_levels[38]	11	1			T134	1		T50	1		T148	1
all_levels[39]	13	1			T13	1		T151	1		T93	1
all_levels[40]	15	1			T150	1		T145	1		T152	1
all_levels[41]	8	1			T48	1		T153	1		T154	1
all_levels[42]	16	1			T47	1		T48	1		T107	1
all_levels[43]	15	1			T112	1		T150	1		T155	1
all_levels[44]	13	1			T156	1		T116	2		T135	1
all_levels[45]	12	1			T157	1		T152	1		T158	1
all_levels[46]	22	1			T159	1		T150	1		T160	1
all_levels[47]	11	1			T116	2		T161	1		T162	2
all_levels[48]	14	1			T110	1		T159	2		T163	1
all_levels[49]	11	1			T143	1		T152	2		T164	4
all_levels[50]	5	1			T50	3		T116	1		T165	1
all_levels[51]	8	1			T146	1		T166	1		T167	1
all_levels[52]	7	1			T132	1		T168	3		T149	1
all_levels[53]	8	1			T132	1		T110	1		T105	1
all_levels[54]	7	1			T140	1		T141	1		T169	1
all_levels[55]	6	1			T170	1		T171	1		T172	1
all_levels[56]	12	1			T24	1		T173	1		T153	2
all_levels[57]	9	1			T174	1		T87	2		T175	1
all_levels[58]	12	1			T116	1		T146	1		T176	1
all_levels[59]	10	1			T74	3		T177	1		T178	1
all_levels[60]	7	1			T116	1		T163	1		T179	1
all_levels[61]	5	1			T105	1		T141	1		T180	1
all_levels[62]	10	1			T50	1		T146	1		T181	1
all_levels[63]	2	1			T182	1		T183	1		-	-
all_levels[64]	100	1			T49	2		T110	1		T156	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24930077

1

T2

34

T3

33442

T5

22

auto[1]

3821

1

T1

1

T5

7

T6

9

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	12	118	90.77	12

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[30]]	[auto[1]]	0	1	1
[all_levels[39] , all_levels[40] , all_levels[41]]	[auto[1]]	--	--	3
[all_levels[43]]	[auto[1]]	0	1	1
[all_levels[51]]	[auto[1]]	0	1	1
[all_levels[53] , all_levels[54] , all_levels[55]]	[auto[1]]	--	--	3
[all_levels[58]]	[auto[1]]	0	1	1
[all_levels[60]]	[auto[1]]	0	1	1
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	24742867	1			T2	22		T3	31379		T5	21
all_levels[0]	auto[1]	3358	1			T1	1		T5	6		T6	9
all_levels[1]	auto[0]	180214	1			T2	2		T3	2050		T7	1
all_levels[1]	auto[1]	82	1			T138	3		T184	1		T142	1
all_levels[2]	auto[0]	2059	1			T2	2		T3	13		T11	2
all_levels[2]	auto[1]	27	1			T184	1		T185	2		T102	2
all_levels[3]	auto[0]	901	1			T11	1		T33	2		T13	2
all_levels[3]	auto[1]	21	1			T47	2		T186	1		T113	1
all_levels[4]	auto[0]	593	1			T2	1		T6	1		T11	2
all_levels[4]	auto[1]	19	1			T187	1		T188	1		T180	1
all_levels[5]	auto[0]	465	1			T6	1		T33	1		T13	2
all_levels[5]	auto[1]	10	1			T47	1		T156	1		T189	2
all_levels[6]	auto[0]	351	1			T11	5		T33	1		T129	1
all_levels[6]	auto[1]	14	1			T134	1		T185	2		T190	1
all_levels[7]	auto[0]	265	1			T6	1		T11	1		T13	1
all_levels[7]	auto[1]	12	1			T113	2		T191	1		T192	2
all_levels[8]	auto[0]	232	1			T2	1		T11	1		T14	1
all_levels[8]	auto[1]	8	1			T138	1		T102	2		T193	1
all_levels[9]	auto[0]	187	1			T6	2		T33	1		T43	2
all_levels[9]	auto[1]	4	1			T194	1		T195	3		-	-
all_levels[10]	auto[0]	165	1			T2	1		T14	1		T43	1
all_levels[10]	auto[1]	26	1			T14	2		T134	2		T196	1
all_levels[11]	auto[0]	162	1			T2	1		T14	1		T130	1
all_levels[11]	auto[1]	13	1			T47	2		T111	1		T174	1
all_levels[12]	auto[0]	115	1			T2	2		T6	1		T11	1
all_levels[12]	auto[1]	11	1			T197	1		T198	2		T199	3
all_levels[13]	auto[0]	123	1			T2	2		T49	1		T50	1
all_levels[13]	auto[1]	13	1			T105	1		T200	1		T201	1
all_levels[14]	auto[0]	88	1			T33	1		T14	1		T130	1
all_levels[14]	auto[1]	18	1			T184	1		T34	1		T202	3
all_levels[15]	auto[0]	99	1			T11	1		T13	1		T131	1
all_levels[15]	auto[1]	6	1			T203	1		T204	2		T205	2
all_levels[16]	auto[0]	82	1			T131	1		T50	1		T110	2
all_levels[16]	auto[1]	13	1			T113	2		T206	1		T207	2
all_levels[17]	auto[0]	77	1			T129	1		T40	1		T14	1
all_levels[17]	auto[1]	8	1			T107	3		T111	1		T201	2
all_levels[18]	auto[0]	76	1			T33	1		T132	1		T133	1
all_levels[18]	auto[1]	10	1			T133	1		T87	2		T173	4
all_levels[19]	auto[0]	57	1			T134	2		T48	1		T105	1
all_levels[19]	auto[1]	7	1			T208	1		T206	2		T114	2
all_levels[20]	auto[0]	56	1			T5	1		T129	1		T134	1
all_levels[20]	auto[1]	6	1			T5	1		T134	1		T209	1
all_levels[21]	auto[0]	56	1			T107	1		T116	1		T135	1
all_levels[21]	auto[1]	8	1			T159	3		T207	1		T198	2
all_levels[22]	auto[0]	53	1			T6	1		T110	2		T136	1
all_levels[22]	auto[1]	4	1			T210	2		T211	1		T212	1
all_levels[23]	auto[0]	41	1			T6	1		T135	1		T113	1
all_levels[23]	auto[1]	5	1			T213	1		T214	2		T215	1
all_levels[24]	auto[0]	41	1			T14	1		T110	1		T116	1
all_levels[24]	auto[1]	7	1			T116	1		T166	1		T216	3
all_levels[25]	auto[0]	39	1			T13	1		T132	1		T137	1
all_levels[25]	auto[1]	3	1			T194	1		T177	1		T217	1
all_levels[26]	auto[0]	34	1			T14	1		T138	1		T110	1
all_levels[26]	auto[1]	7	1			T14	1		T144	1		T218	1
all_levels[27]	auto[0]	32	1			T139	1		T140	1		T141	1
all_levels[27]	auto[1]	5	1			T175	3		T219	2		-	-
all_levels[28]	auto[0]	35	1			T74	1		T132	1		T50	2
all_levels[28]	auto[1]	2	1			T220	1		T221	1		-	-
all_levels[29]	auto[0]	35	1			T142	1		T135	1		T143	1
all_levels[29]	auto[1]	1	1			T222	1		-	-		-	-
all_levels[30]	auto[0]	32	1			T11	1		T116	1		T24	1
all_levels[31]	auto[0]	21	1			T50	1		T142	1		T144	1
all_levels[31]	auto[1]	2	1			T142	1		T223	1		-	-
all_levels[32]	auto[0]	24	1			T13	1		T102	1		T107	1
all_levels[32]	auto[1]	9	1			T157	1		T224	4		T225	1
all_levels[33]	auto[0]	31	1			T13	1		T105	1		T145	1
all_levels[33]	auto[1]	7	1			T105	2		T87	2		T226	2
all_levels[34]	auto[0]	14	1			T13	1		T134	1		T146	1
all_levels[34]	auto[1]	1	1			T162	1		-	-		-	-
all_levels[35]	auto[0]	23	1			T107	1		T147	1		T139	1
all_levels[35]	auto[1]	4	1			T227	1		T228	1		T229	1
all_levels[36]	auto[0]	12	1			T114	1		T148	1		T149	1
all_levels[36]	auto[1]	5	1			T114	1		T230	3		T231	1
all_levels[37]	auto[0]	14	1			T14	1		T132	1		T150	1
all_levels[37]	auto[1]	2	1			T14	1		T232	1		-	-
all_levels[38]	auto[0]	10	1			T134	1		T50	1		T148	1
all_levels[38]	auto[1]	1	1			T233	1		-	-		-	-
all_levels[39]	auto[0]	13	1			T13	1		T151	1		T93	1
all_levels[40]	auto[0]	15	1			T150	1		T145	1		T152	1
all_levels[41]	auto[0]	8	1			T48	1		T153	1		T154	1
all_levels[42]	auto[0]	14	1			T47	1		T48	1		T107	1
all_levels[42]	auto[1]	2	1			T234	1		T235	1		-	-
all_levels[43]	auto[0]	15	1			T112	1		T150	1		T155	1
all_levels[44]	auto[0]	10	1			T156	1		T116	1		T135	1
all_levels[44]	auto[1]	3	1			T116	1		T200	1		T236	1
all_levels[45]	auto[0]	10	1			T157	1		T152	1		T158	1
all_levels[45]	auto[1]	2	1			T237	2		-	-		-	-
all_levels[46]	auto[0]	15	1			T159	1		T150	1		T160	1
all_levels[46]	auto[1]	7	1			T145	1		T238	4		T239	2
all_levels[47]	auto[0]	9	1			T116	2		T161	1		T162	1
all_levels[47]	auto[1]	2	1			T162	1		T240	1		-	-
all_levels[48]	auto[0]	11	1			T110	1		T159	1		T163	1
all_levels[48]	auto[1]	3	1			T159	1		T224	2		-	-
all_levels[49]	auto[0]	8	1			T143	1		T152	2		T164	1
all_levels[49]	auto[1]	3	1			T164	3		-	-		-	-
all_levels[50]	auto[0]	3	1			T50	1		T116	1		T165	1
all_levels[50]	auto[1]	2	1			T50	2		-	-		-	-
all_levels[51]	auto[0]	8	1			T146	1		T166	1		T167	1
all_levels[52]	auto[0]	5	1			T132	1		T168	1		T149	1
all_levels[52]	auto[1]	2	1			T168	2		-	-		-	-
all_levels[53]	auto[0]	8	1			T132	1		T110	1		T105	1
all_levels[54]	auto[0]	7	1			T140	1		T141	1		T169	1
all_levels[55]	auto[0]	6	1			T170	1		T171	1		T172	1
all_levels[56]	auto[0]	9	1			T24	1		T173	1		T153	1
all_levels[56]	auto[1]	3	1			T153	1		T211	1		T241	1
all_levels[57]	auto[0]	6	1			T174	1		T87	1		T175	1
all_levels[57]	auto[1]	3	1			T87	1		T215	2		-	-
all_levels[58]	auto[0]	12	1			T116	1		T146	1		T176	1
all_levels[59]	auto[0]	8	1			T74	1		T177	1		T178	1
all_levels[59]	auto[1]	2	1			T74	2		-	-		-	-
all_levels[60]	auto[0]	7	1			T116	1		T163	1		T179	1
all_levels[61]	auto[0]	4	1			T105	1		T141	1		T180	1
all_levels[61]	auto[1]	1	1			T214	1		-	-		-	-
all_levels[62]	auto[0]	9	1			T50	1		T146	1		T181	1
all_levels[62]	auto[1]	1	1			T242	1		-	-		-	-
all_levels[63]	auto[0]	2	1			T182	1		T183	1		-	-
all_levels[64]	auto[0]	74	1			T49	2		T110	1		T156	1
all_levels[64]	auto[1]	26	1			T174	2		T243	1		T151	1