Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	82984	1			T1	1		T2	2		T3	17
all_pins[1]	82984	1			T1	1		T2	2		T3	17
all_pins[2]	82984	1			T1	1		T2	2		T3	17
all_pins[3]	82984	1			T1	1		T2	2		T3	17
all_pins[4]	82984	1			T1	1		T2	2		T3	17
all_pins[5]	82984	1			T1	1		T2	2		T3	17
all_pins[6]	82984	1			T1	1		T2	2		T3	17
all_pins[7]	82984	1			T1	1		T2	2		T3	17
all_pins[8]	82984	1			T1	1		T2	2		T3	17

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	709639	1			T1	9		T2	16		T3	142
values[0x1]	37217	1			T2	2		T3	11		T5	13
transitions[0x0=>0x1]	28753	1			T2	1		T3	9		T5	13
transitions[0x1=>0x0]	28562	1			T2	2		T3	8		T5	13

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	64913	1			T1	1		T2	2		T3	14
all_pins[0]	values[0x1]	18071	1			T3	3		T9	163		T11	115
all_pins[0]	transitions[0x0=>0x1]	17626	1			T3	3		T9	163		T11	115
all_pins[0]	transitions[0x1=>0x0]	802	1			T46	2		T49	7		T50	2
all_pins[1]	values[0x0]	81737	1			T1	1		T2	2		T3	17
all_pins[1]	values[0x1]	1247	1			T15	6		T43	2		T46	2
all_pins[1]	transitions[0x0=>0x1]	1171	1			T15	6		T43	2		T46	2
all_pins[1]	transitions[0x1=>0x0]	2158	1			T3	5		T7	1		T9	7
all_pins[2]	values[0x0]	80750	1			T1	1		T2	2		T3	12
all_pins[2]	values[0x1]	2234	1			T3	5		T7	1		T9	7
all_pins[2]	transitions[0x0=>0x1]	2140	1			T3	5		T7	1		T9	7
all_pins[2]	transitions[0x1=>0x0]	208	1			T13	1		T15	1		T49	1
all_pins[3]	values[0x0]	82682	1			T1	1		T2	2		T3	17
all_pins[3]	values[0x1]	302	1			T13	1		T14	4		T15	1
all_pins[3]	transitions[0x0=>0x1]	251	1			T13	1		T14	4		T15	1
all_pins[3]	transitions[0x1=>0x0]	297	1			T15	13		T21	11		T96	3
all_pins[4]	values[0x0]	82636	1			T1	1		T2	2		T3	17
all_pins[4]	values[0x1]	348	1			T15	13		T21	11		T39	2
all_pins[4]	transitions[0x0=>0x1]	284	1			T15	11		T21	9		T39	2
all_pins[4]	transitions[0x1=>0x0]	138	1			T18	2		T244	1		T117	1
all_pins[5]	values[0x0]	82782	1			T1	1		T2	2		T3	17
all_pins[5]	values[0x1]	202	1			T15	2		T18	2		T21	2
all_pins[5]	transitions[0x0=>0x1]	163	1			T15	2		T18	2		T21	2
all_pins[5]	transitions[0x1=>0x0]	676	1			T6	1		T13	2		T14	2
all_pins[6]	values[0x0]	82269	1			T1	1		T2	2		T3	17
all_pins[6]	values[0x1]	715	1			T6	1		T13	2		T14	2
all_pins[6]	transitions[0x0=>0x1]	658	1			T6	1		T13	2		T14	2
all_pins[6]	transitions[0x1=>0x0]	248	1			T24	1		T35	1		T246	2
all_pins[7]	values[0x0]	82679	1			T1	1		T2	2		T3	17
all_pins[7]	values[0x1]	305	1			T24	1		T35	1		T246	2
all_pins[7]	transitions[0x0=>0x1]	148	1			T246	2		T96	3		T115	1
all_pins[7]	transitions[0x1=>0x0]	13636	1			T2	2		T3	3		T5	13
all_pins[8]	values[0x0]	69191	1			T1	1		T3	14		T4	2
all_pins[8]	values[0x1]	13793	1			T2	2		T3	3		T5	13
all_pins[8]	transitions[0x0=>0x1]	6312	1			T2	1		T3	1		T5	13
all_pins[8]	transitions[0x1=>0x0]	10399	1			T9	14		T11	23		T33	1