Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6894521	1			T1	1		T2	17		T3	224
all_levels[1]	873478	1			T2	2		T3	8		T5	2
all_levels[2]	464326	1			T2	4		T3	9		T5	3
all_levels[3]	182014	1			T3	11		T5	5		T9	3784
all_levels[4]	209175	1			T3	9		T6	3		T7	3
all_levels[5]	183004	1			T3	9		T9	3787		T11	14
all_levels[6]	159579	1			T3	9		T9	3770		T11	12
all_levels[7]	338498	1			T3	7		T9	3793		T11	23
all_levels[8]	143911	1			T3	4		T9	3782		T11	3
all_levels[9]	246199	1			T3	4		T9	3783		T11	13
all_levels[10]	180031	1			T3	5		T7	5		T9	3765
all_levels[11]	239402	1			T3	11		T9	3765		T11	7
all_levels[12]	271307	1			T3	14		T6	1		T9	3773
all_levels[13]	133525	1			T3	7		T6	3		T9	3779
all_levels[14]	613712	1			T3	8		T9	3785		T11	7
all_levels[15]	216198	1			T3	11		T6	5		T9	3787
all_levels[16]	141644	1			T3	5		T9	3786		T12	139
all_levels[17]	124188	1			T2	1		T3	7		T7	2
all_levels[18]	125576	1			T2	2		T3	7		T9	3706
all_levels[19]	124318	1			T3	7		T6	2		T9	3198
all_levels[20]	122289	1			T3	9		T7	1		T9	3174
all_levels[21]	173250	1			T2	2		T3	12		T9	3048
all_levels[22]	236991	1			T3	8		T9	2137		T11	1
all_levels[23]	195804	1			T3	8		T9	3004		T11	1
all_levels[24]	141509	1			T3	9		T9	3003		T12	136
all_levels[25]	197732	1			T3	8		T9	3020		T11	2
all_levels[26]	273785	1			T3	6		T7	2		T9	3024
all_levels[27]	116430	1			T3	7		T9	3023		T11	5
all_levels[28]	178247	1			T3	11		T7	6		T9	3027
all_levels[29]	250281	1			T3	6		T9	3017		T11	1
all_levels[30]	222568	1			T3	9		T9	3029		T11	13
all_levels[31]	483045	1			T3	249		T9	5481		T11	1
all_levels[32]	10477130	1			T2	6		T3	32724		T5	19

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24930077

1

T2

34

T3

33442

T5

22

auto[1]

3590

1

T1

1

T5

7

T6

9

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6892555	1			T2	17		T3	224		T6	8
all_levels[0]	auto[1]	1966	1			T1	1		T6	5		T7	1
all_levels[1]	auto[0]	873209	1			T2	2		T3	8		T5	1
all_levels[1]	auto[1]	269	1			T5	1		T7	1		T14	1
all_levels[2]	auto[0]	464270	1			T2	4		T3	9		T5	2
all_levels[2]	auto[1]	56	1			T5	1		T138	1		T134	3
all_levels[3]	auto[0]	181884	1			T3	11		T5	2		T9	3784
all_levels[3]	auto[1]	130	1			T5	3		T138	2		T334	1
all_levels[4]	auto[0]	209142	1			T3	9		T6	3		T7	1
all_levels[4]	auto[1]	33	1			T7	2		T134	1		T159	3
all_levels[5]	auto[0]	182987	1			T3	9		T9	3787		T11	14
all_levels[5]	auto[1]	17	1			T156	1		T136	1		T273	1
all_levels[6]	auto[0]	159560	1			T3	9		T9	3770		T11	12
all_levels[6]	auto[1]	19	1			T262	1		T335	1		T151	1
all_levels[7]	auto[0]	338412	1			T3	7		T9	3793		T11	23
all_levels[7]	auto[1]	86	1			T13	11		T14	2		T109	2
all_levels[8]	auto[0]	143883	1			T3	4		T9	3782		T11	3
all_levels[8]	auto[1]	28	1			T133	1		T142	1		T334	2
all_levels[9]	auto[0]	246174	1			T3	4		T9	3783		T11	13
all_levels[9]	auto[1]	25	1			T267	1		T113	3		T200	4
all_levels[10]	auto[0]	180011	1			T3	5		T7	3		T9	3765
all_levels[10]	auto[1]	20	1			T7	2		T47	1		T156	1
all_levels[11]	auto[0]	239373	1			T3	11		T9	3765		T11	7
all_levels[11]	auto[1]	29	1			T130	1		T134	1		T107	1
all_levels[12]	auto[0]	271282	1			T3	14		T6	1		T9	3772
all_levels[12]	auto[1]	25	1			T9	1		T137	1		T197	1
all_levels[13]	auto[0]	133492	1			T3	7		T6	3		T9	3779
all_levels[13]	auto[1]	33	1			T261	1		T306	1		T336	1
all_levels[14]	auto[0]	613689	1			T3	8		T9	3785		T11	7
all_levels[14]	auto[1]	23	1			T142	1		T314	1		T337	1
all_levels[15]	auto[0]	216122	1			T3	11		T6	2		T9	3787
all_levels[15]	auto[1]	76	1			T6	3		T13	28		T15	7
all_levels[16]	auto[0]	141626	1			T3	5		T9	3786		T12	139
all_levels[16]	auto[1]	18	1			T47	1		T34	1		T338	2
all_levels[17]	auto[0]	124172	1			T2	1		T3	7		T7	1
all_levels[17]	auto[1]	16	1			T7	1		T334	1		T339	1
all_levels[18]	auto[0]	125561	1			T2	2		T3	7		T9	3706
all_levels[18]	auto[1]	15	1			T290	1		T200	1		T340	2
all_levels[19]	auto[0]	124297	1			T3	7		T6	1		T9	3198
all_levels[19]	auto[1]	21	1			T6	1		T48	2		T50	1
all_levels[20]	auto[0]	122262	1			T3	9		T7	1		T9	3174
all_levels[20]	auto[1]	27	1			T138	1		T308	5		T190	2
all_levels[21]	auto[0]	173216	1			T2	2		T3	12		T9	3048
all_levels[21]	auto[1]	34	1			T111	2		T292	1		T272	1
all_levels[22]	auto[0]	236977	1			T3	8		T9	2137		T11	1
all_levels[22]	auto[1]	14	1			T210	1		T227	2		T341	1
all_levels[23]	auto[0]	195789	1			T3	8		T9	3004		T11	1
all_levels[23]	auto[1]	15	1			T102	1		T150	1		T313	1
all_levels[24]	auto[0]	141493	1			T3	9		T9	3003		T12	136
all_levels[24]	auto[1]	16	1			T40	4		T133	3		T186	1
all_levels[25]	auto[0]	197714	1			T3	8		T9	3020		T11	2
all_levels[25]	auto[1]	18	1			T102	1		T144	2		T113	1
all_levels[26]	auto[0]	273767	1			T3	6		T7	2		T9	3024
all_levels[26]	auto[1]	18	1			T130	1		T109	1		T190	1
all_levels[27]	auto[0]	116414	1			T3	7		T9	3023		T11	5
all_levels[27]	auto[1]	16	1			T134	1		T279	1		T197	1
all_levels[28]	auto[0]	178223	1			T3	11		T7	5		T9	3027
all_levels[28]	auto[1]	24	1			T7	1		T144	1		T159	1
all_levels[29]	auto[0]	250266	1			T3	6		T9	3017		T11	1
all_levels[29]	auto[1]	15	1			T185	1		T102	2		T308	1
all_levels[30]	auto[0]	222550	1			T3	9		T9	3029		T11	13
all_levels[30]	auto[1]	18	1			T188	1		T342	2		T343	1
all_levels[31]	auto[0]	483033	1			T3	249		T9	5481		T11	1
all_levels[31]	auto[1]	12	1			T184	1		T208	1		T344	1
all_levels[32]	auto[0]	10476672	1			T2	6		T3	32724		T5	17
all_levels[32]	auto[1]	458	1			T5	2		T7	1		T13	2