Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	682	1			T16	4		T18	7		T35	4
all_values[1]	682	1			T16	4		T18	7		T35	4
all_values[2]	682	1			T16	4		T18	7		T35	4
all_values[3]	682	1			T16	4		T18	7		T35	4
all_values[4]	682	1			T16	4		T18	7		T35	4
all_values[5]	682	1			T16	4		T18	7		T35	4
all_values[6]	682	1			T16	4		T18	7		T35	4
all_values[7]	682	1			T16	4		T18	7		T35	4
all_values[8]	682	1			T16	4		T18	7		T35	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3290

1

T16

22

T18

32

T35

24

auto[1]

2848

1

T16

14

T18

31

T35

12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1978

1

T16

15

T18

25

T35

10

auto[1]

4160

1

T16

21

T18

38

T35

26

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3640

1

T16

26

T18

38

T35

24

auto[1]

2498

1

T16

10

T18

25

T35

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	208	1			T16	2		T18	2		T35	1
all_values[0]	auto[0]	auto[1]	auto[1]	216	1			T16	1		T18	1		T35	2
all_values[0]	auto[1]	auto[0]	auto[1]	133	1			T18	2		T39	1		T121	2
all_values[0]	auto[1]	auto[1]	auto[1]	125	1			T16	1		T18	2		T35	1
all_values[1]	auto[0]	auto[0]	auto[0]	216	1			T16	2		T18	1		T35	1
all_values[1]	auto[0]	auto[1]	auto[0]	196	1			T16	2		T18	2		T35	2
all_values[1]	auto[1]	auto[0]	auto[1]	143	1			T18	2		T35	1		T39	1
all_values[1]	auto[1]	auto[1]	auto[1]	127	1			T18	2		T121	1		T96	1
all_values[2]	auto[0]	auto[0]	auto[0]	156	1			T16	1		T18	3		T35	1
all_values[2]	auto[0]	auto[0]	auto[1]	60	1			T16	1		T35	1		T121	1
all_values[2]	auto[0]	auto[1]	auto[0]	139	1			T18	3		T39	1		T96	1
all_values[2]	auto[0]	auto[1]	auto[1]	59	1			T39	1		T121	2		T122	1
all_values[2]	auto[1]	auto[0]	auto[1]	143	1			T16	1		T35	1		T39	1
all_values[2]	auto[1]	auto[1]	auto[1]	125	1			T16	1		T18	1		T35	1
all_values[3]	auto[0]	auto[0]	auto[0]	144	1			T16	1		T18	1		T121	1
all_values[3]	auto[0]	auto[0]	auto[1]	78	1			T16	1		T35	3		T122	1
all_values[3]	auto[0]	auto[1]	auto[0]	106	1			T16	1		T121	1		T96	1
all_values[3]	auto[0]	auto[1]	auto[1]	67	1			T18	2		T39	1		T121	1
all_values[3]	auto[1]	auto[0]	auto[1]	157	1			T16	1		T18	3		T35	1
all_values[3]	auto[1]	auto[1]	auto[1]	130	1			T18	1		T39	3		T121	3
all_values[4]	auto[0]	auto[0]	auto[0]	143	1			T18	1		T35	3		T121	1
all_values[4]	auto[0]	auto[0]	auto[1]	82	1			T121	1		T96	1		T122	1
all_values[4]	auto[0]	auto[1]	auto[0]	100	1			T16	3		T18	5		T39	1
all_values[4]	auto[0]	auto[1]	auto[1]	70	1			T39	1		T121	2		T96	2
all_values[4]	auto[1]	auto[0]	auto[1]	159	1			T16	1		T18	1		T35	1
all_values[4]	auto[1]	auto[1]	auto[1]	128	1			T39	2		T121	2		T96	2
all_values[5]	auto[0]	auto[0]	auto[0]	133	1			T16	1		T18	1		T39	1
all_values[5]	auto[0]	auto[0]	auto[1]	74	1			T16	1		T18	1		T35	2
all_values[5]	auto[0]	auto[1]	auto[0]	111	1			T18	1		T39	2		T121	1
all_values[5]	auto[0]	auto[1]	auto[1]	61	1			T123	1		T124	1		T125	1
all_values[5]	auto[1]	auto[0]	auto[1]	170	1			T16	2		T18	2		T35	1
all_values[5]	auto[1]	auto[1]	auto[1]	133	1			T18	2		T35	1		T121	1
all_values[6]	auto[0]	auto[0]	auto[0]	155	1			T18	1		T35	2		T121	2
all_values[6]	auto[0]	auto[0]	auto[1]	61	1			T16	1		T18	1		T35	1
all_values[6]	auto[0]	auto[1]	auto[0]	127	1			T18	1		T39	2		T121	1
all_values[6]	auto[0]	auto[1]	auto[1]	75	1			T16	1		T96	1		T126	1
all_values[6]	auto[1]	auto[0]	auto[1]	144	1			T16	1		T18	4		T35	1
all_values[6]	auto[1]	auto[1]	auto[1]	120	1			T16	1		T121	1		T96	1
all_values[7]	auto[0]	auto[0]	auto[0]	144	1			T16	2		T18	3		T39	2
all_values[7]	auto[0]	auto[0]	auto[1]	71	1			T35	1		T121	2		T122	2
all_values[7]	auto[0]	auto[1]	auto[0]	108	1			T16	2		T18	2		T35	1
all_values[7]	auto[0]	auto[1]	auto[1]	71	1			T18	1		T35	1		T39	1
all_values[7]	auto[1]	auto[0]	auto[1]	148	1			T18	1		T121	2		T96	2
all_values[7]	auto[1]	auto[1]	auto[1]	140	1			T35	1		T39	1		T96	2
all_values[8]	auto[0]	auto[0]	auto[1]	220	1			T16	2		T18	2		T39	1
all_values[8]	auto[0]	auto[1]	auto[1]	189	1			T16	1		T18	3		T35	2
all_values[8]	auto[1]	auto[0]	auto[1]	148	1			T16	1		T35	2		T121	1
all_values[8]	auto[1]	auto[1]	auto[1]	125	1			T18	2		T39	1		T121	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal