Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.10 99.10 97.65 100.00 98.38 100.00 99.50


Total test records in report: 1316
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
T79 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2869258615 Aug 15 06:00:34 PM PDT 24 Aug 15 06:00:35 PM PDT 24 247166063 ps
T1262 /workspace/coverage/cover_reg_top/45.uart_intr_test.3523554791 Aug 15 06:01:04 PM PDT 24 Aug 15 06:01:04 PM PDT 24 14499568 ps
T1263 /workspace/coverage/cover_reg_top/0.uart_intr_test.2941327251 Aug 15 06:00:01 PM PDT 24 Aug 15 06:00:02 PM PDT 24 11738190 ps
T56 /workspace/coverage/cover_reg_top/0.uart_csr_rw.3837220564 Aug 15 05:59:58 PM PDT 24 Aug 15 05:59:59 PM PDT 24 66842621 ps
T1264 /workspace/coverage/cover_reg_top/12.uart_intr_test.2337890310 Aug 15 06:00:50 PM PDT 24 Aug 15 06:00:50 PM PDT 24 74997764 ps
T1265 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3806246247 Aug 15 06:00:57 PM PDT 24 Aug 15 06:00:58 PM PDT 24 290939471 ps
T1266 /workspace/coverage/cover_reg_top/18.uart_tl_errors.140019165 Aug 15 06:01:01 PM PDT 24 Aug 15 06:01:03 PM PDT 24 289781599 ps
T1267 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2315681899 Aug 15 06:00:14 PM PDT 24 Aug 15 06:00:15 PM PDT 24 35474564 ps
T1268 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.4243045627 Aug 15 06:00:05 PM PDT 24 Aug 15 06:00:08 PM PDT 24 360192989 ps
T1269 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.4159135787 Aug 15 06:00:06 PM PDT 24 Aug 15 06:00:08 PM PDT 24 47560542 ps
T1270 /workspace/coverage/cover_reg_top/11.uart_intr_test.3767077495 Aug 15 06:00:41 PM PDT 24 Aug 15 06:00:42 PM PDT 24 17823392 ps
T1271 /workspace/coverage/cover_reg_top/41.uart_intr_test.3578464510 Aug 15 06:01:05 PM PDT 24 Aug 15 06:01:06 PM PDT 24 12427668 ps
T1272 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.397127219 Aug 15 06:00:27 PM PDT 24 Aug 15 06:00:27 PM PDT 24 25038535 ps
T57 /workspace/coverage/cover_reg_top/14.uart_csr_rw.3888121303 Aug 15 06:00:49 PM PDT 24 Aug 15 06:00:49 PM PDT 24 23547047 ps
T1273 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1530237050 Aug 15 06:00:24 PM PDT 24 Aug 15 06:00:26 PM PDT 24 119131670 ps
T1274 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1774425228 Aug 15 06:00:41 PM PDT 24 Aug 15 06:00:42 PM PDT 24 225890081 ps
T1275 /workspace/coverage/cover_reg_top/27.uart_intr_test.587131092 Aug 15 06:01:07 PM PDT 24 Aug 15 06:01:08 PM PDT 24 11778038 ps
T1276 /workspace/coverage/cover_reg_top/14.uart_intr_test.1192908411 Aug 15 06:00:47 PM PDT 24 Aug 15 06:00:48 PM PDT 24 16475724 ps
T1277 /workspace/coverage/cover_reg_top/43.uart_intr_test.2092339991 Aug 15 06:01:04 PM PDT 24 Aug 15 06:01:04 PM PDT 24 43535977 ps
T1278 /workspace/coverage/cover_reg_top/14.uart_tl_errors.1922934500 Aug 15 06:00:49 PM PDT 24 Aug 15 06:00:51 PM PDT 24 99959443 ps
T1279 /workspace/coverage/cover_reg_top/5.uart_intr_test.4175611827 Aug 15 06:00:27 PM PDT 24 Aug 15 06:00:27 PM PDT 24 12334763 ps
T1280 /workspace/coverage/cover_reg_top/16.uart_tl_errors.561712917 Aug 15 06:00:48 PM PDT 24 Aug 15 06:00:50 PM PDT 24 43993989 ps
T1281 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2530824252 Aug 15 06:00:47 PM PDT 24 Aug 15 06:00:48 PM PDT 24 104149851 ps
T1282 /workspace/coverage/cover_reg_top/25.uart_intr_test.3063669472 Aug 15 06:01:09 PM PDT 24 Aug 15 06:01:10 PM PDT 24 11528631 ps
T1283 /workspace/coverage/cover_reg_top/19.uart_intr_test.2078840058 Aug 15 06:00:57 PM PDT 24 Aug 15 06:00:57 PM PDT 24 45443039 ps
T1284 /workspace/coverage/cover_reg_top/15.uart_csr_rw.271433504 Aug 15 06:00:48 PM PDT 24 Aug 15 06:00:49 PM PDT 24 26623562 ps
T1285 /workspace/coverage/cover_reg_top/46.uart_intr_test.3580228355 Aug 15 06:01:09 PM PDT 24 Aug 15 06:01:10 PM PDT 24 13450102 ps
T1286 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.65080895 Aug 15 06:00:24 PM PDT 24 Aug 15 06:00:25 PM PDT 24 19180902 ps
T1287 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3305954638 Aug 15 06:00:32 PM PDT 24 Aug 15 06:00:33 PM PDT 24 54556285 ps
T62 /workspace/coverage/cover_reg_top/7.uart_csr_rw.1956084715 Aug 15 06:00:33 PM PDT 24 Aug 15 06:00:34 PM PDT 24 46867701 ps
T58 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.595194755 Aug 15 06:00:01 PM PDT 24 Aug 15 06:00:01 PM PDT 24 16719955 ps
T1288 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3590588323 Aug 15 06:00:36 PM PDT 24 Aug 15 06:00:37 PM PDT 24 47394223 ps
T1289 /workspace/coverage/cover_reg_top/39.uart_intr_test.2071232116 Aug 15 06:01:04 PM PDT 24 Aug 15 06:01:04 PM PDT 24 27469587 ps
T1290 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1105069473 Aug 15 06:00:04 PM PDT 24 Aug 15 06:00:08 PM PDT 24 26221742 ps
T1291 /workspace/coverage/cover_reg_top/40.uart_intr_test.1921659586 Aug 15 06:01:06 PM PDT 24 Aug 15 06:01:07 PM PDT 24 19662581 ps
T1292 /workspace/coverage/cover_reg_top/12.uart_csr_rw.3227330262 Aug 15 06:00:52 PM PDT 24 Aug 15 06:00:53 PM PDT 24 12212389 ps
T59 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2440664579 Aug 15 06:00:06 PM PDT 24 Aug 15 06:00:08 PM PDT 24 20258524 ps
T1293 /workspace/coverage/cover_reg_top/30.uart_intr_test.2865908007 Aug 15 06:01:04 PM PDT 24 Aug 15 06:01:05 PM PDT 24 23491288 ps
T60 /workspace/coverage/cover_reg_top/18.uart_csr_rw.4097906732 Aug 15 06:00:58 PM PDT 24 Aug 15 06:00:59 PM PDT 24 14642594 ps
T65 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3803706683 Aug 15 06:00:11 PM PDT 24 Aug 15 06:00:12 PM PDT 24 33217954 ps
T1294 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1646590827 Aug 15 06:00:58 PM PDT 24 Aug 15 06:00:59 PM PDT 24 263384479 ps
T1295 /workspace/coverage/cover_reg_top/3.uart_tl_errors.3341680701 Aug 15 06:00:23 PM PDT 24 Aug 15 06:00:25 PM PDT 24 26090355 ps
T1296 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3481208256 Aug 15 06:01:02 PM PDT 24 Aug 15 06:01:03 PM PDT 24 25249491 ps
T1297 /workspace/coverage/cover_reg_top/35.uart_intr_test.3481945694 Aug 15 06:01:04 PM PDT 24 Aug 15 06:01:05 PM PDT 24 28060539 ps
T1298 /workspace/coverage/cover_reg_top/13.uart_intr_test.3004677503 Aug 15 06:00:47 PM PDT 24 Aug 15 06:00:48 PM PDT 24 50131347 ps
T1299 /workspace/coverage/cover_reg_top/15.uart_intr_test.2019252832 Aug 15 06:00:51 PM PDT 24 Aug 15 06:00:52 PM PDT 24 177998110 ps
T1300 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2894788840 Aug 15 06:00:05 PM PDT 24 Aug 15 06:00:08 PM PDT 24 106746415 ps
T1301 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2777043408 Aug 15 06:00:11 PM PDT 24 Aug 15 06:00:12 PM PDT 24 48186861 ps
T1302 /workspace/coverage/cover_reg_top/21.uart_intr_test.3382679848 Aug 15 06:01:05 PM PDT 24 Aug 15 06:01:05 PM PDT 24 32579078 ps
T1303 /workspace/coverage/cover_reg_top/42.uart_intr_test.1542887064 Aug 15 06:01:13 PM PDT 24 Aug 15 06:01:14 PM PDT 24 14843589 ps
T1304 /workspace/coverage/cover_reg_top/20.uart_intr_test.2860449439 Aug 15 06:00:59 PM PDT 24 Aug 15 06:01:00 PM PDT 24 59419477 ps
T1305 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1973392020 Aug 15 06:00:49 PM PDT 24 Aug 15 06:00:50 PM PDT 24 138183450 ps
T1306 /workspace/coverage/cover_reg_top/17.uart_csr_rw.1335862526 Aug 15 06:00:48 PM PDT 24 Aug 15 06:00:49 PM PDT 24 17936297 ps
T1307 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3751154726 Aug 15 06:00:05 PM PDT 24 Aug 15 06:00:08 PM PDT 24 16307012 ps
T1308 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3701784347 Aug 15 06:00:48 PM PDT 24 Aug 15 06:00:49 PM PDT 24 136987094 ps
T63 /workspace/coverage/cover_reg_top/13.uart_csr_rw.770188448 Aug 15 06:00:52 PM PDT 24 Aug 15 06:00:53 PM PDT 24 92295691 ps
T1309 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.611444670 Aug 15 06:00:04 PM PDT 24 Aug 15 06:00:09 PM PDT 24 464932254 ps
T1310 /workspace/coverage/cover_reg_top/8.uart_intr_test.4140759385 Aug 15 06:00:46 PM PDT 24 Aug 15 06:00:47 PM PDT 24 28669174 ps
T1311 /workspace/coverage/cover_reg_top/38.uart_intr_test.3491231421 Aug 15 06:01:05 PM PDT 24 Aug 15 06:01:06 PM PDT 24 22597538 ps
T1312 /workspace/coverage/cover_reg_top/10.uart_csr_rw.2321944137 Aug 15 06:00:42 PM PDT 24 Aug 15 06:00:42 PM PDT 24 29517220 ps
T1313 /workspace/coverage/cover_reg_top/11.uart_csr_rw.4030727107 Aug 15 06:00:48 PM PDT 24 Aug 15 06:00:49 PM PDT 24 24305835 ps
T64 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2088019830 Aug 15 06:00:25 PM PDT 24 Aug 15 06:00:25 PM PDT 24 16282333 ps
T1314 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1555357440 Aug 15 06:00:56 PM PDT 24 Aug 15 06:00:57 PM PDT 24 26454012 ps
T1315 /workspace/coverage/cover_reg_top/15.uart_tl_errors.2732169661 Aug 15 06:00:49 PM PDT 24 Aug 15 06:00:52 PM PDT 24 91867693 ps
T127 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1658584550 Aug 15 06:00:51 PM PDT 24 Aug 15 06:00:53 PM PDT 24 83094118 ps
T1316 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3874936464 Aug 15 06:00:43 PM PDT 24 Aug 15 06:00:44 PM PDT 24 214646298 ps

Test location /workspace/coverage/default/22.uart_perf.71221640
Short name T9
Test name
Test status
Simulation time 25416051959 ps
CPU time 655.94 seconds
Started Aug 15 06:27:09 PM PDT 24
Finished Aug 15 06:38:05 PM PDT 24
Peak memory 200956 kb
Host smart-8be231f5-8b8a-47a6-8fc7-efe498daaf49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=71221640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.71221640
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1735032796
Short name T18
Test name
Test status
Simulation time 9386845224 ps
CPU time 41.22 seconds
Started Aug 15 06:29:57 PM PDT 24
Finished Aug 15 06:30:39 PM PDT 24
Peak memory 216696 kb
Host smart-b6a2254a-8192-4246-9a4b-6c2850fdaa9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735032796 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1735032796
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_stress_all.4244380008
Short name T146
Test name
Test status
Simulation time 272060256175 ps
CPU time 301.45 seconds
Started Aug 15 06:27:33 PM PDT 24
Finished Aug 15 06:32:35 PM PDT 24
Peak memory 201080 kb
Host smart-060817c1-5faf-40b3-919c-aed9bb6426f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244380008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.4244380008
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all.3807769353
Short name T13
Test name
Test status
Simulation time 392467750076 ps
CPU time 158.02 seconds
Started Aug 15 06:28:02 PM PDT 24
Finished Aug 15 06:30:40 PM PDT 24
Peak memory 200952 kb
Host smart-116b4c01-fa08-4615-bcef-05915208e422
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807769353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3807769353
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all.2479292654
Short name T136
Test name
Test status
Simulation time 424864812230 ps
CPU time 805.74 seconds
Started Aug 15 06:28:12 PM PDT 24
Finished Aug 15 06:41:38 PM PDT 24
Peak memory 209276 kb
Host smart-d317ddde-541f-4180-b28d-0c1b99dfe788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479292654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2479292654
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all.1636594567
Short name T24
Test name
Test status
Simulation time 221744702667 ps
CPU time 1175.12 seconds
Started Aug 15 06:28:56 PM PDT 24
Finished Aug 15 06:48:31 PM PDT 24
Peak memory 200908 kb
Host smart-460b9377-5c0e-481d-8603-99ce1424272d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636594567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1636594567
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.826182534
Short name T3
Test name
Test status
Simulation time 86404843865 ps
CPU time 125.7 seconds
Started Aug 15 06:27:51 PM PDT 24
Finished Aug 15 06:29:57 PM PDT 24
Peak memory 200968 kb
Host smart-6eb51686-8573-415e-b4cf-967adab6e5ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=826182534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.826182534
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_stress_all.2736523470
Short name T135
Test name
Test status
Simulation time 139144668384 ps
CPU time 300.2 seconds
Started Aug 15 06:26:56 PM PDT 24
Finished Aug 15 06:31:57 PM PDT 24
Peak memory 199788 kb
Host smart-03e6cfe0-9fef-4bce-8067-dfb96523c4b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736523470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2736523470
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all.40580651
Short name T50
Test name
Test status
Simulation time 118642892937 ps
CPU time 489.65 seconds
Started Aug 15 06:24:46 PM PDT 24
Finished Aug 15 06:32:56 PM PDT 24
Peak memory 200944 kb
Host smart-75fc7256-cf7f-4498-9146-abd38acf1fb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40580651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.40580651
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.1467809597
Short name T44
Test name
Test status
Simulation time 130678284867 ps
CPU time 238.29 seconds
Started Aug 15 06:28:04 PM PDT 24
Finished Aug 15 06:32:03 PM PDT 24
Peak memory 200868 kb
Host smart-54702bd5-4fd4-4dae-966f-ca88ca86caf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1467809597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1467809597
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.22762545
Short name T53
Test name
Test status
Simulation time 43028375 ps
CPU time 0.57 seconds
Started Aug 15 06:00:43 PM PDT 24
Finished Aug 15 06:00:44 PM PDT 24
Peak memory 195564 kb
Host smart-ac7172fe-e454-4ab0-9442-95cb39565813
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22762545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.22762545
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1190564574
Short name T31
Test name
Test status
Simulation time 39392516 ps
CPU time 0.8 seconds
Started Aug 15 06:24:50 PM PDT 24
Finished Aug 15 06:24:51 PM PDT 24
Peak memory 218996 kb
Host smart-241562ae-e9d4-4f7e-b3c4-0cba20b62a23
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190564574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1190564574
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/17.uart_alert_test.16983950
Short name T29
Test name
Test status
Simulation time 25809277 ps
CPU time 0.57 seconds
Started Aug 15 06:26:46 PM PDT 24
Finished Aug 15 06:26:47 PM PDT 24
Peak memory 196548 kb
Host smart-81640fe6-98fc-4ccc-b5a3-8d41c99f5233
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16983950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.16983950
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.4231991850
Short name T139
Test name
Test status
Simulation time 196878607630 ps
CPU time 119.88 seconds
Started Aug 15 06:28:51 PM PDT 24
Finished Aug 15 06:30:51 PM PDT 24
Peak memory 200884 kb
Host smart-81e61512-da9c-4eca-b09e-074dafa2a6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231991850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.4231991850
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.1093357752
Short name T11
Test name
Test status
Simulation time 252302656561 ps
CPU time 482.55 seconds
Started Aug 15 06:25:55 PM PDT 24
Finished Aug 15 06:33:58 PM PDT 24
Peak memory 200892 kb
Host smart-e7b7bb2f-2688-4d84-8f4f-f62c3299d500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093357752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1093357752
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2478482176
Short name T14
Test name
Test status
Simulation time 53821951156 ps
CPU time 20.11 seconds
Started Aug 15 06:30:19 PM PDT 24
Finished Aug 15 06:30:39 PM PDT 24
Peak memory 200976 kb
Host smart-8ed07e63-68e6-4d54-83c6-36b32b737286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478482176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2478482176
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.923846152
Short name T107
Test name
Test status
Simulation time 142630356630 ps
CPU time 314.36 seconds
Started Aug 15 06:29:48 PM PDT 24
Finished Aug 15 06:35:02 PM PDT 24
Peak memory 200944 kb
Host smart-9b1c40d5-28ae-4387-8870-736b03cfb03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923846152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.923846152
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.1803750045
Short name T1
Test name
Test status
Simulation time 4007106731 ps
CPU time 9.18 seconds
Started Aug 15 06:26:47 PM PDT 24
Finished Aug 15 06:26:56 PM PDT 24
Peak memory 199424 kb
Host smart-4123d5fb-01a3-46ea-b633-bc850481dd23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1803750045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1803750045
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2400049780
Short name T80
Test name
Test status
Simulation time 353844340 ps
CPU time 0.95 seconds
Started Aug 15 06:00:05 PM PDT 24
Finished Aug 15 06:00:08 PM PDT 24
Peak memory 199348 kb
Host smart-dacdeae8-b084-42cb-a36d-bd652763a196
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400049780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2400049780
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2505583420
Short name T132
Test name
Test status
Simulation time 152055238630 ps
CPU time 193.46 seconds
Started Aug 15 06:26:18 PM PDT 24
Finished Aug 15 06:29:31 PM PDT 24
Peak memory 200972 kb
Host smart-9f89629f-fbef-4d42-a062-0e5d5203499a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505583420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2505583420
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3222833699
Short name T150
Test name
Test status
Simulation time 88071494882 ps
CPU time 29.19 seconds
Started Aug 15 06:26:39 PM PDT 24
Finished Aug 15 06:27:09 PM PDT 24
Peak memory 200956 kb
Host smart-2d29e98a-8f23-4be6-8ceb-c403f877f4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222833699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3222833699
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_stress_all.2448392225
Short name T306
Test name
Test status
Simulation time 240807486485 ps
CPU time 1020.32 seconds
Started Aug 15 06:25:48 PM PDT 24
Finished Aug 15 06:42:49 PM PDT 24
Peak memory 209364 kb
Host smart-ba152e4e-09cb-4f6c-a2eb-6d4f7f987bb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448392225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2448392225
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all.2632115084
Short name T123
Test name
Test status
Simulation time 142270641533 ps
CPU time 155.66 seconds
Started Aug 15 06:26:26 PM PDT 24
Finished Aug 15 06:29:01 PM PDT 24
Peak memory 200844 kb
Host smart-d3ccca95-6233-41f8-8348-f0322ff99647
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632115084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2632115084
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all.3656658317
Short name T274
Test name
Test status
Simulation time 202203204290 ps
CPU time 390.14 seconds
Started Aug 15 06:28:35 PM PDT 24
Finished Aug 15 06:35:06 PM PDT 24
Peak memory 209252 kb
Host smart-e3f95a36-8750-4c14-bf63-8e602777eba2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656658317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3656658317
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.559705399
Short name T323
Test name
Test status
Simulation time 4825660212 ps
CPU time 34.99 seconds
Started Aug 15 06:29:37 PM PDT 24
Finished Aug 15 06:30:13 PM PDT 24
Peak memory 209208 kb
Host smart-4d4bf2fc-1304-4a86-9950-08ded3838e2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559705399 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.559705399
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.1161487029
Short name T159
Test name
Test status
Simulation time 114081708931 ps
CPU time 169.77 seconds
Started Aug 15 06:30:42 PM PDT 24
Finished Aug 15 06:33:32 PM PDT 24
Peak memory 200904 kb
Host smart-e7fc4b06-6362-4d53-8708-be783d84aa7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161487029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1161487029
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3798886089
Short name T246
Test name
Test status
Simulation time 25698873999 ps
CPU time 18.73 seconds
Started Aug 15 06:28:04 PM PDT 24
Finished Aug 15 06:28:23 PM PDT 24
Peak memory 200828 kb
Host smart-c0c371d9-5344-4b5b-a2e0-15faedb0d258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798886089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3798886089
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_stress_all.2277462625
Short name T297
Test name
Test status
Simulation time 116174399046 ps
CPU time 116.51 seconds
Started Aug 15 06:24:56 PM PDT 24
Finished Aug 15 06:26:53 PM PDT 24
Peak memory 200964 kb
Host smart-8311cd22-a65d-416c-bd2f-e05d90d32179
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277462625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2277462625
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all.3557255386
Short name T171
Test name
Test status
Simulation time 166702013397 ps
CPU time 628.11 seconds
Started Aug 15 06:29:09 PM PDT 24
Finished Aug 15 06:39:37 PM PDT 24
Peak memory 200984 kb
Host smart-026ad7f3-6286-482e-9c6f-7ba84fe7232c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557255386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.3557255386
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3269463745
Short name T189
Test name
Test status
Simulation time 227779763142 ps
CPU time 87.15 seconds
Started Aug 15 06:31:08 PM PDT 24
Finished Aug 15 06:32:35 PM PDT 24
Peak memory 200908 kb
Host smart-2cc10dc6-3cc0-41d1-a20f-a6c1a8838f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269463745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3269463745
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_stress_all.332251943
Short name T285
Test name
Test status
Simulation time 183231505444 ps
CPU time 225.05 seconds
Started Aug 15 06:27:57 PM PDT 24
Finished Aug 15 06:31:42 PM PDT 24
Peak memory 200952 kb
Host smart-f59aa477-0f10-4bad-b3e7-c13b6abf2288
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332251943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.332251943
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all.1970239569
Short name T182
Test name
Test status
Simulation time 547977248178 ps
CPU time 330.58 seconds
Started Aug 15 06:27:02 PM PDT 24
Finished Aug 15 06:32:33 PM PDT 24
Peak memory 200976 kb
Host smart-1a4e2645-637f-448f-8f0c-91ffdab6beff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970239569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1970239569
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2648289585
Short name T47
Test name
Test status
Simulation time 142443157437 ps
CPU time 96.76 seconds
Started Aug 15 06:30:47 PM PDT 24
Finished Aug 15 06:32:24 PM PDT 24
Peak memory 200924 kb
Host smart-74dccea9-2809-4786-96ee-2e112f4b090c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648289585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2648289585
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1848317289
Short name T77
Test name
Test status
Simulation time 429289785 ps
CPU time 1.29 seconds
Started Aug 15 06:00:35 PM PDT 24
Finished Aug 15 06:00:36 PM PDT 24
Peak memory 199548 kb
Host smart-fd697baf-b09a-4d1c-b8e3-b7c030762c69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848317289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1848317289
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.3790442210
Short name T325
Test name
Test status
Simulation time 3093497245 ps
CPU time 40.54 seconds
Started Aug 15 06:26:50 PM PDT 24
Finished Aug 15 06:27:31 PM PDT 24
Peak memory 201208 kb
Host smart-ff798a9b-c6e4-422b-b1d4-1a2ce4e64686
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790442210 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3790442210
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1698583655
Short name T152
Test name
Test status
Simulation time 27623884734 ps
CPU time 41.77 seconds
Started Aug 15 06:30:46 PM PDT 24
Finished Aug 15 06:31:28 PM PDT 24
Peak memory 200932 kb
Host smart-a3583dbe-6065-4f64-9483-105e0ab51282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698583655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1698583655
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.696991938
Short name T184
Test name
Test status
Simulation time 75844272586 ps
CPU time 34.52 seconds
Started Aug 15 06:31:04 PM PDT 24
Finished Aug 15 06:31:38 PM PDT 24
Peak memory 201136 kb
Host smart-fa360112-411e-437e-9039-832696fee10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696991938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.696991938
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.1389402505
Short name T105
Test name
Test status
Simulation time 234327032775 ps
CPU time 30.59 seconds
Started Aug 15 06:29:42 PM PDT 24
Finished Aug 15 06:30:13 PM PDT 24
Peak memory 200948 kb
Host smart-c9e3a800-85e8-48ce-96bb-8bee1c2a73e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389402505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1389402505
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.2639321334
Short name T190
Test name
Test status
Simulation time 30412194831 ps
CPU time 48.14 seconds
Started Aug 15 06:31:03 PM PDT 24
Finished Aug 15 06:31:51 PM PDT 24
Peak memory 200764 kb
Host smart-c13ee2e8-18dc-48aa-83a5-a4fb458fdb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639321334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2639321334
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2960938784
Short name T83
Test name
Test status
Simulation time 193154530 ps
CPU time 0.92 seconds
Started Aug 15 06:00:43 PM PDT 24
Finished Aug 15 06:00:44 PM PDT 24
Peak memory 199200 kb
Host smart-51a2e2ac-b2cd-4f9b-8cbd-ebd2640a8b44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960938784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2960938784
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.43178191
Short name T175
Test name
Test status
Simulation time 20000896853 ps
CPU time 43.75 seconds
Started Aug 15 06:30:41 PM PDT 24
Finished Aug 15 06:31:25 PM PDT 24
Peak memory 200896 kb
Host smart-703e845d-a18c-43dc-acf5-df55df63d2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43178191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.43178191
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3639875622
Short name T270
Test name
Test status
Simulation time 24839815013 ps
CPU time 19.33 seconds
Started Aug 15 06:27:10 PM PDT 24
Finished Aug 15 06:27:29 PM PDT 24
Peak memory 200872 kb
Host smart-26a43bbd-af68-4f96-852f-b90ff372db2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639875622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3639875622
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3131715113
Short name T206
Test name
Test status
Simulation time 48622181821 ps
CPU time 19.77 seconds
Started Aug 15 06:29:59 PM PDT 24
Finished Aug 15 06:30:19 PM PDT 24
Peak memory 200836 kb
Host smart-0dcad36d-5b7a-439c-b497-afbb74611bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131715113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3131715113
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1081000480
Short name T198
Test name
Test status
Simulation time 73181603848 ps
CPU time 122.65 seconds
Started Aug 15 06:30:18 PM PDT 24
Finished Aug 15 06:32:21 PM PDT 24
Peak memory 200880 kb
Host smart-cbde5f0d-f3f0-45c0-bf6b-386756bb4bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081000480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1081000480
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.3910455143
Short name T116
Test name
Test status
Simulation time 62121055757 ps
CPU time 54.14 seconds
Started Aug 15 06:30:18 PM PDT 24
Finished Aug 15 06:31:12 PM PDT 24
Peak memory 200948 kb
Host smart-dd2bcb2e-3638-4765-9b68-5941bb0ae851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910455143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3910455143
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2349951333
Short name T191
Test name
Test status
Simulation time 58855084749 ps
CPU time 331.51 seconds
Started Aug 15 06:30:35 PM PDT 24
Finished Aug 15 06:36:06 PM PDT 24
Peak memory 200936 kb
Host smart-4ae7475e-a140-43e3-9e1e-052fb6f9606e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349951333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2349951333
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.344652744
Short name T214
Test name
Test status
Simulation time 63284331560 ps
CPU time 49.88 seconds
Started Aug 15 06:30:42 PM PDT 24
Finished Aug 15 06:31:32 PM PDT 24
Peak memory 200916 kb
Host smart-ad0408ea-3858-4397-944d-cd397fabaa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344652744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.344652744
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_stress_all.1960189122
Short name T141
Test name
Test status
Simulation time 80658620649 ps
CPU time 1413.79 seconds
Started Aug 15 06:25:09 PM PDT 24
Finished Aug 15 06:48:44 PM PDT 24
Peak memory 200936 kb
Host smart-19380fcc-fba7-4aa2-a87e-ba83f0ed4138
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960189122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1960189122
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3579082913
Short name T1044
Test name
Test status
Simulation time 175409767154 ps
CPU time 71.87 seconds
Started Aug 15 06:28:03 PM PDT 24
Finished Aug 15 06:29:15 PM PDT 24
Peak memory 200936 kb
Host smart-c229dca6-acd2-48ca-9d89-45affd38b7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579082913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3579082913
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.454986607
Short name T153
Test name
Test status
Simulation time 72508292816 ps
CPU time 27.1 seconds
Started Aug 15 06:29:11 PM PDT 24
Finished Aug 15 06:29:38 PM PDT 24
Peak memory 200976 kb
Host smart-e3f326d4-6f5a-4054-bad8-fa59cd5b1428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454986607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.454986607
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.663761165
Short name T251
Test name
Test status
Simulation time 66218077425 ps
CPU time 56.61 seconds
Started Aug 15 06:29:23 PM PDT 24
Finished Aug 15 06:30:20 PM PDT 24
Peak memory 200916 kb
Host smart-d0e533c8-0501-45c0-ab63-5f381fc72af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663761165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.663761165
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2435334440
Short name T133
Test name
Test status
Simulation time 99509946378 ps
CPU time 18.55 seconds
Started Aug 15 06:29:57 PM PDT 24
Finished Aug 15 06:30:16 PM PDT 24
Peak memory 200964 kb
Host smart-53cab080-c62b-4fd4-a6d8-d9d35f0811d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435334440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2435334440
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1418676104
Short name T5
Test name
Test status
Simulation time 191679950307 ps
CPU time 41.79 seconds
Started Aug 15 06:30:13 PM PDT 24
Finished Aug 15 06:30:55 PM PDT 24
Peak memory 200932 kb
Host smart-e120ad0f-a8aa-44b8-9cd1-d57cc7d88f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418676104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1418676104
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.134914762
Short name T34
Test name
Test status
Simulation time 8373355037 ps
CPU time 63.34 seconds
Started Aug 15 06:26:39 PM PDT 24
Finished Aug 15 06:27:43 PM PDT 24
Peak memory 209192 kb
Host smart-c3712f05-89a9-4ae5-829b-9f344c598e29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134914762 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.134914762
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.3034561541
Short name T162
Test name
Test status
Simulation time 81360308587 ps
CPU time 23.23 seconds
Started Aug 15 06:30:28 PM PDT 24
Finished Aug 15 06:30:51 PM PDT 24
Peak memory 200920 kb
Host smart-2cebe1bc-302f-43a3-a62b-2681715afaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034561541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.3034561541
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3822610559
Short name T194
Test name
Test status
Simulation time 11622558891 ps
CPU time 19.61 seconds
Started Aug 15 06:30:28 PM PDT 24
Finished Aug 15 06:30:48 PM PDT 24
Peak memory 200916 kb
Host smart-58bea890-883a-4948-a940-fff6f01cf9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822610559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3822610559
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.2007198293
Short name T222
Test name
Test status
Simulation time 76146928643 ps
CPU time 47.31 seconds
Started Aug 15 06:30:51 PM PDT 24
Finished Aug 15 06:31:39 PM PDT 24
Peak memory 200952 kb
Host smart-840b9f68-f2c1-40c6-a56c-cee47089175b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007198293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2007198293
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.1303872102
Short name T199
Test name
Test status
Simulation time 178223792896 ps
CPU time 70.31 seconds
Started Aug 15 06:27:34 PM PDT 24
Finished Aug 15 06:28:44 PM PDT 24
Peak memory 200924 kb
Host smart-8dc65e27-a84b-491b-b981-3f002eb64c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303872102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1303872102
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3230822367
Short name T215
Test name
Test status
Simulation time 44906015904 ps
CPU time 23 seconds
Started Aug 15 06:31:04 PM PDT 24
Finished Aug 15 06:31:27 PM PDT 24
Peak memory 200900 kb
Host smart-59848d49-20d5-4eae-83c3-fc4fc3a85395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230822367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3230822367
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1196677286
Short name T231
Test name
Test status
Simulation time 161752151008 ps
CPU time 35.7 seconds
Started Aug 15 06:26:02 PM PDT 24
Finished Aug 15 06:26:38 PM PDT 24
Peak memory 200960 kb
Host smart-6335e071-384e-4ce9-8213-f2b5d98037b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196677286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1196677286
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2617997232
Short name T235
Test name
Test status
Simulation time 46939365541 ps
CPU time 22.23 seconds
Started Aug 15 06:30:12 PM PDT 24
Finished Aug 15 06:30:35 PM PDT 24
Peak memory 200964 kb
Host smart-77f1f730-7355-4547-8a98-a2d352841fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617997232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2617997232
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.129137845
Short name T212
Test name
Test status
Simulation time 16727865926 ps
CPU time 32.24 seconds
Started Aug 15 06:30:11 PM PDT 24
Finished Aug 15 06:30:44 PM PDT 24
Peak memory 200904 kb
Host smart-0b0caa32-f872-44de-9b11-29e995e651f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129137845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.129137845
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2654743657
Short name T227
Test name
Test status
Simulation time 22554445584 ps
CPU time 16.77 seconds
Started Aug 15 06:30:10 PM PDT 24
Finished Aug 15 06:30:27 PM PDT 24
Peak memory 200960 kb
Host smart-1e0e0a36-5a17-40c7-bf96-5dfffc509175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654743657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2654743657
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all.1742477991
Short name T1013
Test name
Test status
Simulation time 432754826241 ps
CPU time 382.25 seconds
Started Aug 15 06:26:17 PM PDT 24
Finished Aug 15 06:32:40 PM PDT 24
Peak memory 209332 kb
Host smart-3bc26110-ba01-45d5-b0a3-34fac1b48ef8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742477991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1742477991
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3344091911
Short name T221
Test name
Test status
Simulation time 113239139857 ps
CPU time 50.35 seconds
Started Aug 15 06:30:24 PM PDT 24
Finished Aug 15 06:31:14 PM PDT 24
Peak memory 200952 kb
Host smart-1b2346b5-eb8a-4e11-8a58-92607c6bb53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344091911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3344091911
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.2783055188
Short name T1129
Test name
Test status
Simulation time 45416173480 ps
CPU time 13.06 seconds
Started Aug 15 06:26:31 PM PDT 24
Finished Aug 15 06:26:44 PM PDT 24
Peak memory 200960 kb
Host smart-fbce12fb-91b3-4303-a77c-600cb1600e16
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783055188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2783055188
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.4154846464
Short name T74
Test name
Test status
Simulation time 69521303309 ps
CPU time 15.62 seconds
Started Aug 15 06:30:21 PM PDT 24
Finished Aug 15 06:30:37 PM PDT 24
Peak memory 200024 kb
Host smart-57e56116-e0e0-4247-a10b-8cc9f3539ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154846464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.4154846464
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.4286939860
Short name T237
Test name
Test status
Simulation time 16012237028 ps
CPU time 13.31 seconds
Started Aug 15 06:30:28 PM PDT 24
Finished Aug 15 06:30:41 PM PDT 24
Peak memory 200936 kb
Host smart-991029be-0de3-40ed-b1d9-b0804a5a6d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286939860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.4286939860
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3034302286
Short name T168
Test name
Test status
Simulation time 44760019160 ps
CPU time 21.8 seconds
Started Aug 15 06:30:27 PM PDT 24
Finished Aug 15 06:30:49 PM PDT 24
Peak memory 200944 kb
Host smart-80188f6c-43f3-4e3a-9136-cb0e0d55a690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034302286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3034302286
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3223288005
Short name T164
Test name
Test status
Simulation time 145714893973 ps
CPU time 36.31 seconds
Started Aug 15 06:30:25 PM PDT 24
Finished Aug 15 06:31:01 PM PDT 24
Peak memory 200944 kb
Host smart-fcd59576-f14b-49c7-b6af-58515d974dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223288005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3223288005
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.2703653593
Short name T142
Test name
Test status
Simulation time 56498958448 ps
CPU time 46.1 seconds
Started Aug 15 06:30:33 PM PDT 24
Finished Aug 15 06:31:20 PM PDT 24
Peak memory 200948 kb
Host smart-64c3ab35-7e34-4329-9970-a9ae09f0aa6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703653593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2703653593
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.432688770
Short name T242
Test name
Test status
Simulation time 25285016549 ps
CPU time 13.96 seconds
Started Aug 15 06:27:17 PM PDT 24
Finished Aug 15 06:27:31 PM PDT 24
Peak memory 200964 kb
Host smart-afed5de6-f04d-4720-a258-f29122f3594d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432688770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.432688770
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.2879287929
Short name T238
Test name
Test status
Simulation time 134622467105 ps
CPU time 29.91 seconds
Started Aug 15 06:29:40 PM PDT 24
Finished Aug 15 06:30:10 PM PDT 24
Peak memory 200740 kb
Host smart-8005e58c-4017-498a-8f8d-446b97b7b787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879287929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2879287929
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.1699103801
Short name T233
Test name
Test status
Simulation time 18552891004 ps
CPU time 14.76 seconds
Started Aug 15 06:29:50 PM PDT 24
Finished Aug 15 06:30:05 PM PDT 24
Peak memory 200352 kb
Host smart-7981581e-6dee-4d32-a599-01767f0998b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699103801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1699103801
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1659579763
Short name T1237
Test name
Test status
Simulation time 22437801 ps
CPU time 0.68 seconds
Started Aug 15 06:00:04 PM PDT 24
Finished Aug 15 06:00:08 PM PDT 24
Peak memory 195648 kb
Host smart-ad5f0a08-ebab-4956-b125-0058229f90e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659579763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1659579763
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1476362707
Short name T1255
Test name
Test status
Simulation time 748095367 ps
CPU time 1.53 seconds
Started Aug 15 05:59:58 PM PDT 24
Finished Aug 15 06:00:00 PM PDT 24
Peak memory 198052 kb
Host smart-ff8bf53c-4370-41d3-8603-6973a31d0d86
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476362707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1476362707
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.595194755
Short name T58
Test name
Test status
Simulation time 16719955 ps
CPU time 0.63 seconds
Started Aug 15 06:00:01 PM PDT 24
Finished Aug 15 06:00:01 PM PDT 24
Peak memory 195520 kb
Host smart-2955c5d7-8a3d-42fd-97ce-e84de7d38527
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595194755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.595194755
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1105069473
Short name T1290
Test name
Test status
Simulation time 26221742 ps
CPU time 0.78 seconds
Started Aug 15 06:00:04 PM PDT 24
Finished Aug 15 06:00:08 PM PDT 24
Peak memory 199428 kb
Host smart-0e9245e4-cc23-4ee4-9d83-c92403104ddc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105069473 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1105069473
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3837220564
Short name T56
Test name
Test status
Simulation time 66842621 ps
CPU time 0.6 seconds
Started Aug 15 05:59:58 PM PDT 24
Finished Aug 15 05:59:59 PM PDT 24
Peak memory 195628 kb
Host smart-6c52f366-7c56-48b4-91f0-b4a0ce81b6e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837220564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3837220564
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.2941327251
Short name T1263
Test name
Test status
Simulation time 11738190 ps
CPU time 0.57 seconds
Started Aug 15 06:00:01 PM PDT 24
Finished Aug 15 06:00:02 PM PDT 24
Peak memory 194576 kb
Host smart-1a5654bc-9414-4ff3-af3c-2ffa6c83de51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941327251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.2941327251
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.4159135787
Short name T1269
Test name
Test status
Simulation time 47560542 ps
CPU time 0.71 seconds
Started Aug 15 06:00:06 PM PDT 24
Finished Aug 15 06:00:08 PM PDT 24
Peak memory 197164 kb
Host smart-8e325d4d-5f11-48d7-8296-aca20ecf1c18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159135787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.4159135787
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2403378483
Short name T1192
Test name
Test status
Simulation time 58770360 ps
CPU time 1.36 seconds
Started Aug 15 05:59:58 PM PDT 24
Finished Aug 15 06:00:00 PM PDT 24
Peak memory 200268 kb
Host smart-f6dd6ef9-619e-4ef7-91a3-f37e634fb130
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403378483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2403378483
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2286207160
Short name T1259
Test name
Test status
Simulation time 58938604 ps
CPU time 0.93 seconds
Started Aug 15 05:59:58 PM PDT 24
Finished Aug 15 05:59:59 PM PDT 24
Peak memory 199200 kb
Host smart-a4d9ecda-528f-4dbd-b4b1-c2aa3c98a8ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286207160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2286207160
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2440664579
Short name T59
Test name
Test status
Simulation time 20258524 ps
CPU time 0.65 seconds
Started Aug 15 06:00:06 PM PDT 24
Finished Aug 15 06:00:08 PM PDT 24
Peak memory 195172 kb
Host smart-b56edfa6-c158-4aba-be18-cc5f29020fe1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440664579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2440664579
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.611444670
Short name T1309
Test name
Test status
Simulation time 464932254 ps
CPU time 2.43 seconds
Started Aug 15 06:00:04 PM PDT 24
Finished Aug 15 06:00:09 PM PDT 24
Peak memory 198020 kb
Host smart-4dda355d-f61b-425e-940a-84a7b647d7fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611444670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.611444670
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1545517412
Short name T1195
Test name
Test status
Simulation time 1030903732 ps
CPU time 1.92 seconds
Started Aug 15 06:00:05 PM PDT 24
Finished Aug 15 06:00:09 PM PDT 24
Peak memory 195592 kb
Host smart-dc416732-b51c-4eac-9f98-0c7bcac22122
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545517412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1545517412
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3292208813
Short name T1208
Test name
Test status
Simulation time 67943727 ps
CPU time 0.99 seconds
Started Aug 15 06:00:04 PM PDT 24
Finished Aug 15 06:00:08 PM PDT 24
Peak memory 200008 kb
Host smart-78b0150f-6074-483a-a73c-61a6fcde657b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292208813 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3292208813
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.1427328395
Short name T52
Test name
Test status
Simulation time 35832869 ps
CPU time 0.57 seconds
Started Aug 15 06:00:05 PM PDT 24
Finished Aug 15 06:00:08 PM PDT 24
Peak memory 195492 kb
Host smart-1ab121de-6e3a-4ec5-b714-2c232bf2085b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427328395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1427328395
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3091588638
Short name T1231
Test name
Test status
Simulation time 48072636 ps
CPU time 0.56 seconds
Started Aug 15 06:00:03 PM PDT 24
Finished Aug 15 06:00:08 PM PDT 24
Peak memory 194528 kb
Host smart-46eecc3f-d1a9-491c-a40e-8e26f778d6e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091588638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3091588638
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2894788840
Short name T1300
Test name
Test status
Simulation time 106746415 ps
CPU time 0.63 seconds
Started Aug 15 06:00:05 PM PDT 24
Finished Aug 15 06:00:08 PM PDT 24
Peak memory 194916 kb
Host smart-bcb69bfd-14a6-4e87-9319-8cd7a7ec759f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894788840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2894788840
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.891161802
Short name T1256
Test name
Test status
Simulation time 257704354 ps
CPU time 2.32 seconds
Started Aug 15 06:00:05 PM PDT 24
Finished Aug 15 06:00:09 PM PDT 24
Peak memory 200208 kb
Host smart-b54f4202-b54f-4140-8d28-d47a7d4994e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891161802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.891161802
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.4243045627
Short name T1268
Test name
Test status
Simulation time 360192989 ps
CPU time 1.31 seconds
Started Aug 15 06:00:05 PM PDT 24
Finished Aug 15 06:00:08 PM PDT 24
Peak memory 199628 kb
Host smart-46f46238-b6ec-489f-a51b-f41867a00b5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243045627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.4243045627
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3698301849
Short name T1203
Test name
Test status
Simulation time 53166485 ps
CPU time 0.79 seconds
Started Aug 15 06:00:46 PM PDT 24
Finished Aug 15 06:00:47 PM PDT 24
Peak memory 200004 kb
Host smart-e23adb23-b43c-4aa4-a8b7-7b0c89d95f9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698301849 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3698301849
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2321944137
Short name T1312
Test name
Test status
Simulation time 29517220 ps
CPU time 0.57 seconds
Started Aug 15 06:00:42 PM PDT 24
Finished Aug 15 06:00:42 PM PDT 24
Peak memory 195548 kb
Host smart-025bcc5b-5632-48b7-afb7-3db6b5993f99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321944137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2321944137
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.1728539065
Short name T1213
Test name
Test status
Simulation time 107131915 ps
CPU time 0.54 seconds
Started Aug 15 06:00:40 PM PDT 24
Finished Aug 15 06:00:41 PM PDT 24
Peak memory 194584 kb
Host smart-b830a935-ff8e-40cd-a3a6-35ad61a36f8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728539065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1728539065
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3874936464
Short name T1316
Test name
Test status
Simulation time 214646298 ps
CPU time 0.75 seconds
Started Aug 15 06:00:43 PM PDT 24
Finished Aug 15 06:00:44 PM PDT 24
Peak memory 197092 kb
Host smart-3f3d72e4-0d75-472c-940c-8dd7d0d715da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874936464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.3874936464
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3603919438
Short name T1244
Test name
Test status
Simulation time 24060923 ps
CPU time 1.23 seconds
Started Aug 15 06:00:43 PM PDT 24
Finished Aug 15 06:00:44 PM PDT 24
Peak memory 200136 kb
Host smart-cb6bf4f3-c3c3-4846-8f64-52476cca1073
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603919438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3603919438
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1779331270
Short name T1207
Test name
Test status
Simulation time 27539780 ps
CPU time 1.15 seconds
Started Aug 15 06:00:50 PM PDT 24
Finished Aug 15 06:00:51 PM PDT 24
Peak memory 200228 kb
Host smart-42974068-8f5a-46a8-9fa3-e0d2f7a48372
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779331270 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1779331270
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.4030727107
Short name T1313
Test name
Test status
Simulation time 24305835 ps
CPU time 0.57 seconds
Started Aug 15 06:00:48 PM PDT 24
Finished Aug 15 06:00:49 PM PDT 24
Peak memory 195544 kb
Host smart-bdfdc475-723e-41e2-9fc3-ee2c456d40d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030727107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.4030727107
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.3767077495
Short name T1270
Test name
Test status
Simulation time 17823392 ps
CPU time 0.54 seconds
Started Aug 15 06:00:41 PM PDT 24
Finished Aug 15 06:00:42 PM PDT 24
Peak memory 194568 kb
Host smart-4cfd4037-8171-4027-bec4-04dab854eb91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767077495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3767077495
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.393891819
Short name T67
Test name
Test status
Simulation time 15305243 ps
CPU time 0.65 seconds
Started Aug 15 06:00:51 PM PDT 24
Finished Aug 15 06:00:52 PM PDT 24
Peak memory 196112 kb
Host smart-a896afa8-d9d6-4d5d-933e-3e8459024ffc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393891819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr
_outstanding.393891819
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.4066245409
Short name T1214
Test name
Test status
Simulation time 24719706 ps
CPU time 1.19 seconds
Started Aug 15 06:00:41 PM PDT 24
Finished Aug 15 06:00:43 PM PDT 24
Peak memory 200264 kb
Host smart-50027ce2-2e1a-449f-a87a-1b63e77da9ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066245409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.4066245409
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.195334949
Short name T84
Test name
Test status
Simulation time 144745596 ps
CPU time 0.9 seconds
Started Aug 15 06:00:46 PM PDT 24
Finished Aug 15 06:00:47 PM PDT 24
Peak memory 198888 kb
Host smart-a8e022b8-a3ac-4af6-8e09-91a031687f04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195334949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.195334949
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3701784347
Short name T1308
Test name
Test status
Simulation time 136987094 ps
CPU time 0.64 seconds
Started Aug 15 06:00:48 PM PDT 24
Finished Aug 15 06:00:49 PM PDT 24
Peak memory 197560 kb
Host smart-5232b056-4041-4cfb-bf96-6bbf8720d79a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701784347 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3701784347
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.3227330262
Short name T1292
Test name
Test status
Simulation time 12212389 ps
CPU time 0.61 seconds
Started Aug 15 06:00:52 PM PDT 24
Finished Aug 15 06:00:53 PM PDT 24
Peak memory 195656 kb
Host smart-ee453a91-5aff-4e04-a1b2-d4eff0ff5b6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227330262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3227330262
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2337890310
Short name T1264
Test name
Test status
Simulation time 74997764 ps
CPU time 0.55 seconds
Started Aug 15 06:00:50 PM PDT 24
Finished Aug 15 06:00:50 PM PDT 24
Peak memory 194600 kb
Host smart-bdde4322-b60d-4e03-ad6a-c16c80a728fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337890310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2337890310
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1916579186
Short name T1241
Test name
Test status
Simulation time 16375256 ps
CPU time 0.71 seconds
Started Aug 15 06:00:50 PM PDT 24
Finished Aug 15 06:00:52 PM PDT 24
Peak memory 197724 kb
Host smart-df3be0aa-3eda-4d09-b12d-144e99373b5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916579186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1916579186
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.486517623
Short name T1225
Test name
Test status
Simulation time 200788845 ps
CPU time 1.13 seconds
Started Aug 15 06:00:51 PM PDT 24
Finished Aug 15 06:00:52 PM PDT 24
Peak memory 200236 kb
Host smart-d3907633-897e-4156-8751-390edd594166
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486517623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.486517623
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2313913344
Short name T128
Test name
Test status
Simulation time 83944655 ps
CPU time 1.34 seconds
Started Aug 15 06:00:48 PM PDT 24
Finished Aug 15 06:00:50 PM PDT 24
Peak memory 199596 kb
Host smart-2ba2a45f-fd65-46eb-a3a5-b65de8d91f0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313913344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2313913344
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2107961832
Short name T1240
Test name
Test status
Simulation time 31144407 ps
CPU time 0.78 seconds
Started Aug 15 06:00:50 PM PDT 24
Finished Aug 15 06:00:51 PM PDT 24
Peak memory 199216 kb
Host smart-34a686ff-bb7d-4104-b710-7fbf5446ab3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107961832 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2107961832
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.770188448
Short name T63
Test name
Test status
Simulation time 92295691 ps
CPU time 0.61 seconds
Started Aug 15 06:00:52 PM PDT 24
Finished Aug 15 06:00:53 PM PDT 24
Peak memory 195588 kb
Host smart-9b771d85-9d66-4861-ad03-d1abecfe274a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770188448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.770188448
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3004677503
Short name T1298
Test name
Test status
Simulation time 50131347 ps
CPU time 0.58 seconds
Started Aug 15 06:00:47 PM PDT 24
Finished Aug 15 06:00:48 PM PDT 24
Peak memory 194628 kb
Host smart-16544bab-d98e-43e7-a233-ba22897adfa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004677503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3004677503
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3432313656
Short name T68
Test name
Test status
Simulation time 70115809 ps
CPU time 0.66 seconds
Started Aug 15 06:00:51 PM PDT 24
Finished Aug 15 06:00:52 PM PDT 24
Peak memory 196100 kb
Host smart-7342ebcf-378c-4e00-b1eb-fffd9bef78ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432313656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3432313656
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.2152207989
Short name T1238
Test name
Test status
Simulation time 59163785 ps
CPU time 1.28 seconds
Started Aug 15 06:00:51 PM PDT 24
Finished Aug 15 06:00:53 PM PDT 24
Peak memory 200224 kb
Host smart-4d085894-a6a1-4f3c-a060-0eeec5846f3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152207989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.2152207989
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1255614705
Short name T1260
Test name
Test status
Simulation time 45847763 ps
CPU time 0.94 seconds
Started Aug 15 06:00:51 PM PDT 24
Finished Aug 15 06:00:52 PM PDT 24
Peak memory 199144 kb
Host smart-1861b113-803b-4321-977c-85981e4d3a17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255614705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1255614705
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2496593014
Short name T1224
Test name
Test status
Simulation time 174088645 ps
CPU time 0.66 seconds
Started Aug 15 06:00:49 PM PDT 24
Finished Aug 15 06:00:50 PM PDT 24
Peak memory 197576 kb
Host smart-0dd8215e-42e8-40f0-b263-dcdf998d8039
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496593014 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2496593014
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3888121303
Short name T57
Test name
Test status
Simulation time 23547047 ps
CPU time 0.62 seconds
Started Aug 15 06:00:49 PM PDT 24
Finished Aug 15 06:00:49 PM PDT 24
Peak memory 195772 kb
Host smart-4d84c593-7ecc-46cd-9e37-1f7818e94e7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888121303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3888121303
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.1192908411
Short name T1276
Test name
Test status
Simulation time 16475724 ps
CPU time 0.59 seconds
Started Aug 15 06:00:47 PM PDT 24
Finished Aug 15 06:00:48 PM PDT 24
Peak memory 194552 kb
Host smart-54ba50e1-11ef-4189-b475-72dc0a1f86ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192908411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1192908411
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1025934859
Short name T71
Test name
Test status
Simulation time 25754023 ps
CPU time 0.7 seconds
Started Aug 15 06:00:48 PM PDT 24
Finished Aug 15 06:00:48 PM PDT 24
Peak memory 197128 kb
Host smart-cbabb0a0-18aa-49de-82a0-2835470a134d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025934859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1025934859
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1922934500
Short name T1278
Test name
Test status
Simulation time 99959443 ps
CPU time 1.48 seconds
Started Aug 15 06:00:49 PM PDT 24
Finished Aug 15 06:00:51 PM PDT 24
Peak memory 200252 kb
Host smart-13ec2d74-3a3f-45b9-ae48-278bd8d4f597
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922934500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1922934500
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3746377319
Short name T75
Test name
Test status
Simulation time 93270893 ps
CPU time 0.92 seconds
Started Aug 15 06:00:50 PM PDT 24
Finished Aug 15 06:00:52 PM PDT 24
Peak memory 198980 kb
Host smart-692441ee-9f42-4bad-a62d-c82ba4f2ad6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746377319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3746377319
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1526901693
Short name T1190
Test name
Test status
Simulation time 26232504 ps
CPU time 0.83 seconds
Started Aug 15 06:00:49 PM PDT 24
Finished Aug 15 06:00:50 PM PDT 24
Peak memory 199980 kb
Host smart-a6166182-6508-4403-b4a9-00c2ce255df9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526901693 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1526901693
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.271433504
Short name T1284
Test name
Test status
Simulation time 26623562 ps
CPU time 0.61 seconds
Started Aug 15 06:00:48 PM PDT 24
Finished Aug 15 06:00:49 PM PDT 24
Peak memory 195608 kb
Host smart-1a6d5dbd-3da0-4488-ba18-d8f335b668f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271433504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.271433504
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2019252832
Short name T1299
Test name
Test status
Simulation time 177998110 ps
CPU time 0.56 seconds
Started Aug 15 06:00:51 PM PDT 24
Finished Aug 15 06:00:52 PM PDT 24
Peak memory 194612 kb
Host smart-b075390f-f1ba-476e-ab46-0859fc72c8e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019252832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2019252832
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2708115888
Short name T69
Test name
Test status
Simulation time 175383101 ps
CPU time 0.74 seconds
Started Aug 15 06:00:50 PM PDT 24
Finished Aug 15 06:00:52 PM PDT 24
Peak memory 197352 kb
Host smart-10237f95-a451-40ae-9905-c95a2029ff30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708115888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.2708115888
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2732169661
Short name T1315
Test name
Test status
Simulation time 91867693 ps
CPU time 1.99 seconds
Started Aug 15 06:00:49 PM PDT 24
Finished Aug 15 06:00:52 PM PDT 24
Peak memory 200508 kb
Host smart-9751a062-16f6-4aab-a8ff-fc97b4602272
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732169661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2732169661
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1658584550
Short name T127
Test name
Test status
Simulation time 83094118 ps
CPU time 1.26 seconds
Started Aug 15 06:00:51 PM PDT 24
Finished Aug 15 06:00:53 PM PDT 24
Peak memory 199668 kb
Host smart-c651adb3-5386-4e38-b621-8ce6f30bf8d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658584550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1658584550
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1800583859
Short name T1253
Test name
Test status
Simulation time 37661203 ps
CPU time 0.75 seconds
Started Aug 15 06:00:49 PM PDT 24
Finished Aug 15 06:00:50 PM PDT 24
Peak memory 199052 kb
Host smart-b7600bff-a24d-42b7-bfb1-d30c55784669
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800583859 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1800583859
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1451913443
Short name T1218
Test name
Test status
Simulation time 21417313 ps
CPU time 0.62 seconds
Started Aug 15 06:00:50 PM PDT 24
Finished Aug 15 06:00:50 PM PDT 24
Peak memory 195668 kb
Host smart-511d7c7a-47d4-46f0-881f-50bc87ead16b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451913443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1451913443
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.722426322
Short name T1209
Test name
Test status
Simulation time 31240866 ps
CPU time 0.58 seconds
Started Aug 15 06:00:50 PM PDT 24
Finished Aug 15 06:00:51 PM PDT 24
Peak memory 194540 kb
Host smart-5c10c302-b1bb-4f5f-bdfb-ea3e3ef1c178
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722426322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.722426322
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1973392020
Short name T1305
Test name
Test status
Simulation time 138183450 ps
CPU time 0.66 seconds
Started Aug 15 06:00:49 PM PDT 24
Finished Aug 15 06:00:50 PM PDT 24
Peak memory 195756 kb
Host smart-08a2d554-7ad1-4360-85bc-78557a307942
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973392020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1973392020
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.561712917
Short name T1280
Test name
Test status
Simulation time 43993989 ps
CPU time 2.03 seconds
Started Aug 15 06:00:48 PM PDT 24
Finished Aug 15 06:00:50 PM PDT 24
Peak memory 200236 kb
Host smart-cbd6f32d-4e78-4bfe-8a24-338e327d6b80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561712917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.561712917
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2555841766
Short name T1258
Test name
Test status
Simulation time 86410703 ps
CPU time 1.35 seconds
Started Aug 15 06:00:50 PM PDT 24
Finished Aug 15 06:00:52 PM PDT 24
Peak memory 199528 kb
Host smart-0d44045c-1929-446b-9656-d18e6b22634c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555841766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2555841766
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3481208256
Short name T1296
Test name
Test status
Simulation time 25249491 ps
CPU time 0.77 seconds
Started Aug 15 06:01:02 PM PDT 24
Finished Aug 15 06:01:03 PM PDT 24
Peak memory 199032 kb
Host smart-86593764-4337-4ad3-95bf-2e38d7ea52d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481208256 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3481208256
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.1335862526
Short name T1306
Test name
Test status
Simulation time 17936297 ps
CPU time 0.57 seconds
Started Aug 15 06:00:48 PM PDT 24
Finished Aug 15 06:00:49 PM PDT 24
Peak memory 195484 kb
Host smart-f07b63fb-dcd1-4a3f-a143-fbfe0a8c6af9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335862526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1335862526
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.552647893
Short name T1194
Test name
Test status
Simulation time 133230733 ps
CPU time 0.57 seconds
Started Aug 15 06:00:50 PM PDT 24
Finished Aug 15 06:00:51 PM PDT 24
Peak memory 194628 kb
Host smart-d7a4c73e-7b44-4b0a-8c7b-a19974fbff83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552647893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.552647893
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2933651867
Short name T1257
Test name
Test status
Simulation time 19888376 ps
CPU time 0.67 seconds
Started Aug 15 06:00:57 PM PDT 24
Finished Aug 15 06:00:58 PM PDT 24
Peak memory 195732 kb
Host smart-740196b9-7bd2-4c61-b40d-158686907672
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933651867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2933651867
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.1017948023
Short name T1206
Test name
Test status
Simulation time 139147571 ps
CPU time 2.09 seconds
Started Aug 15 06:00:49 PM PDT 24
Finished Aug 15 06:00:51 PM PDT 24
Peak memory 200260 kb
Host smart-8bbe234f-c1c3-4c9e-8aec-fd5d7bbb31db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017948023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1017948023
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2813980681
Short name T81
Test name
Test status
Simulation time 295424811 ps
CPU time 1.28 seconds
Started Aug 15 06:00:46 PM PDT 24
Finished Aug 15 06:00:48 PM PDT 24
Peak memory 199544 kb
Host smart-58bd058e-940b-49e7-90b9-992c13c3a05b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813980681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2813980681
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.4143501934
Short name T1227
Test name
Test status
Simulation time 50153487 ps
CPU time 0.62 seconds
Started Aug 15 06:00:57 PM PDT 24
Finished Aug 15 06:00:58 PM PDT 24
Peak memory 197384 kb
Host smart-a0164ea4-f94b-4917-8d21-fb06854af8b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143501934 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.4143501934
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.4097906732
Short name T60
Test name
Test status
Simulation time 14642594 ps
CPU time 0.61 seconds
Started Aug 15 06:00:58 PM PDT 24
Finished Aug 15 06:00:59 PM PDT 24
Peak memory 195524 kb
Host smart-8d3e01cc-fc53-4857-9ea2-d1ea9d9a8ff7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097906732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.4097906732
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.1169133569
Short name T1191
Test name
Test status
Simulation time 49086086 ps
CPU time 0.57 seconds
Started Aug 15 06:00:56 PM PDT 24
Finished Aug 15 06:00:57 PM PDT 24
Peak memory 194636 kb
Host smart-2fdd28c2-159d-4c53-ae1a-debaa7df0338
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169133569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1169133569
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1555357440
Short name T1314
Test name
Test status
Simulation time 26454012 ps
CPU time 0.62 seconds
Started Aug 15 06:00:56 PM PDT 24
Finished Aug 15 06:00:57 PM PDT 24
Peak memory 196724 kb
Host smart-9bd374f1-2d96-4a25-80c2-55ec55dcccbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555357440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.1555357440
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.140019165
Short name T1266
Test name
Test status
Simulation time 289781599 ps
CPU time 1.69 seconds
Started Aug 15 06:01:01 PM PDT 24
Finished Aug 15 06:01:03 PM PDT 24
Peak memory 200196 kb
Host smart-cd8cb3e2-97ba-43c1-97d5-b94ce1ad3e24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140019165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.140019165
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1646590827
Short name T1294
Test name
Test status
Simulation time 263384479 ps
CPU time 1.29 seconds
Started Aug 15 06:00:58 PM PDT 24
Finished Aug 15 06:00:59 PM PDT 24
Peak memory 199448 kb
Host smart-0bf31456-1d73-4e4f-b051-317287965a6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646590827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1646590827
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.175885768
Short name T1196
Test name
Test status
Simulation time 43343771 ps
CPU time 1.17 seconds
Started Aug 15 06:00:58 PM PDT 24
Finished Aug 15 06:00:59 PM PDT 24
Peak memory 200248 kb
Host smart-858d963d-488f-4fca-8e2f-9891a27d03ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175885768 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.175885768
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.88551081
Short name T1226
Test name
Test status
Simulation time 42144892 ps
CPU time 0.65 seconds
Started Aug 15 06:00:56 PM PDT 24
Finished Aug 15 06:00:57 PM PDT 24
Peak memory 195640 kb
Host smart-a323767b-657e-4cef-ab4d-60f73d19ddfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88551081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.88551081
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.2078840058
Short name T1283
Test name
Test status
Simulation time 45443039 ps
CPU time 0.56 seconds
Started Aug 15 06:00:57 PM PDT 24
Finished Aug 15 06:00:57 PM PDT 24
Peak memory 194636 kb
Host smart-8541c2cf-1adf-4583-b28f-60206cd44b40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078840058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2078840058
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1566331486
Short name T66
Test name
Test status
Simulation time 90505120 ps
CPU time 0.77 seconds
Started Aug 15 06:01:02 PM PDT 24
Finished Aug 15 06:01:03 PM PDT 24
Peak memory 197308 kb
Host smart-78093294-cc92-4ee2-aa23-4caac20b5b72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566331486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1566331486
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2387623298
Short name T1254
Test name
Test status
Simulation time 108352996 ps
CPU time 2.07 seconds
Started Aug 15 06:01:03 PM PDT 24
Finished Aug 15 06:01:05 PM PDT 24
Peak memory 200192 kb
Host smart-6a65500d-3ad2-4b95-8d1d-0037aa63320f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387623298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2387623298
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3806246247
Short name T1265
Test name
Test status
Simulation time 290939471 ps
CPU time 1.27 seconds
Started Aug 15 06:00:57 PM PDT 24
Finished Aug 15 06:00:58 PM PDT 24
Peak memory 199356 kb
Host smart-f7839609-acb8-4350-8816-4c8288b85256
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806246247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3806246247
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.767937408
Short name T1251
Test name
Test status
Simulation time 21150680 ps
CPU time 0.66 seconds
Started Aug 15 06:00:11 PM PDT 24
Finished Aug 15 06:00:12 PM PDT 24
Peak memory 195136 kb
Host smart-0e0932c3-49f4-4b15-877e-295b6f73934a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767937408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.767937408
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3273133051
Short name T1205
Test name
Test status
Simulation time 363357232 ps
CPU time 1.49 seconds
Started Aug 15 06:00:12 PM PDT 24
Finished Aug 15 06:00:14 PM PDT 24
Peak memory 197808 kb
Host smart-76c050ae-0cfd-4e0a-9a82-35f29785e04d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273133051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3273133051
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3751154726
Short name T1307
Test name
Test status
Simulation time 16307012 ps
CPU time 0.59 seconds
Started Aug 15 06:00:05 PM PDT 24
Finished Aug 15 06:00:08 PM PDT 24
Peak memory 195540 kb
Host smart-eb52d0d6-7013-42bd-8261-afb08b19ea67
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751154726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3751154726
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2777043408
Short name T1301
Test name
Test status
Simulation time 48186861 ps
CPU time 0.88 seconds
Started Aug 15 06:00:11 PM PDT 24
Finished Aug 15 06:00:12 PM PDT 24
Peak memory 199996 kb
Host smart-25d9c3ca-fb5f-471d-b0e8-20506eabfd9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777043408 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2777043408
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.3473797549
Short name T1201
Test name
Test status
Simulation time 13598017 ps
CPU time 0.63 seconds
Started Aug 15 06:00:11 PM PDT 24
Finished Aug 15 06:00:11 PM PDT 24
Peak memory 195572 kb
Host smart-be936c04-016f-46f0-97e0-ddc7f54df455
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473797549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3473797549
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.2251126734
Short name T1249
Test name
Test status
Simulation time 13329578 ps
CPU time 0.54 seconds
Started Aug 15 06:00:05 PM PDT 24
Finished Aug 15 06:00:08 PM PDT 24
Peak memory 194568 kb
Host smart-be9b39df-ca89-49dc-9998-97fe35bb3232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251126734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2251126734
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1600017225
Short name T73
Test name
Test status
Simulation time 13122683 ps
CPU time 0.65 seconds
Started Aug 15 06:00:11 PM PDT 24
Finished Aug 15 06:00:12 PM PDT 24
Peak memory 195804 kb
Host smart-4c4d626c-7ba6-44f3-a7e0-a783b4cfd762
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600017225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.1600017225
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.4062637864
Short name T1215
Test name
Test status
Simulation time 61427726 ps
CPU time 0.89 seconds
Started Aug 15 06:00:05 PM PDT 24
Finished Aug 15 06:00:08 PM PDT 24
Peak memory 200020 kb
Host smart-972e8ed4-fb71-4464-ae05-90f1be66626e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062637864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.4062637864
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2860449439
Short name T1304
Test name
Test status
Simulation time 59419477 ps
CPU time 0.57 seconds
Started Aug 15 06:00:59 PM PDT 24
Finished Aug 15 06:01:00 PM PDT 24
Peak memory 194588 kb
Host smart-8081c3e0-ff15-456e-9728-3da55d3e5587
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860449439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2860449439
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.3382679848
Short name T1302
Test name
Test status
Simulation time 32579078 ps
CPU time 0.57 seconds
Started Aug 15 06:01:05 PM PDT 24
Finished Aug 15 06:01:05 PM PDT 24
Peak memory 194512 kb
Host smart-458d779e-7541-4422-abea-23cf1105ca63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382679848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3382679848
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.3369950992
Short name T1235
Test name
Test status
Simulation time 21208076 ps
CPU time 0.58 seconds
Started Aug 15 06:01:03 PM PDT 24
Finished Aug 15 06:01:04 PM PDT 24
Peak memory 194572 kb
Host smart-1a49798b-ca82-4123-9432-75f24619406c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369950992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.3369950992
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.402140630
Short name T1223
Test name
Test status
Simulation time 44066387 ps
CPU time 0.57 seconds
Started Aug 15 06:01:04 PM PDT 24
Finished Aug 15 06:01:05 PM PDT 24
Peak memory 194604 kb
Host smart-e750efef-1a73-4915-a0c1-1565187c474f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402140630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.402140630
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.619346942
Short name T1233
Test name
Test status
Simulation time 21974304 ps
CPU time 0.57 seconds
Started Aug 15 06:01:06 PM PDT 24
Finished Aug 15 06:01:07 PM PDT 24
Peak memory 194628 kb
Host smart-bec6bee1-480a-46b7-b7ea-5328c31ecdcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619346942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.619346942
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3063669472
Short name T1282
Test name
Test status
Simulation time 11528631 ps
CPU time 0.58 seconds
Started Aug 15 06:01:09 PM PDT 24
Finished Aug 15 06:01:10 PM PDT 24
Peak memory 194612 kb
Host smart-ec8c262f-3613-4525-8a60-6c79049a8fcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063669472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3063669472
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.4017706044
Short name T1188
Test name
Test status
Simulation time 23843074 ps
CPU time 0.57 seconds
Started Aug 15 06:01:05 PM PDT 24
Finished Aug 15 06:01:05 PM PDT 24
Peak memory 194616 kb
Host smart-9a45b5c7-9059-42ee-bc12-f8b51e9999e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017706044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.4017706044
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.587131092
Short name T1275
Test name
Test status
Simulation time 11778038 ps
CPU time 0.55 seconds
Started Aug 15 06:01:07 PM PDT 24
Finished Aug 15 06:01:08 PM PDT 24
Peak memory 194520 kb
Host smart-8d43cbfc-6caf-4cfb-a82b-0a0e132fa098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587131092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.587131092
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3174290859
Short name T1220
Test name
Test status
Simulation time 47466151 ps
CPU time 0.55 seconds
Started Aug 15 06:01:03 PM PDT 24
Finished Aug 15 06:01:04 PM PDT 24
Peak memory 194596 kb
Host smart-cc33ccf1-1569-44cb-bb2b-772b33df4b64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174290859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3174290859
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.1419289281
Short name T1199
Test name
Test status
Simulation time 71100094 ps
CPU time 0.56 seconds
Started Aug 15 06:01:03 PM PDT 24
Finished Aug 15 06:01:03 PM PDT 24
Peak memory 194584 kb
Host smart-c59d6b01-8779-4b7d-b22c-d831f8b9e508
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419289281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1419289281
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1629203548
Short name T1248
Test name
Test status
Simulation time 20115255 ps
CPU time 0.68 seconds
Started Aug 15 06:00:24 PM PDT 24
Finished Aug 15 06:00:25 PM PDT 24
Peak memory 195160 kb
Host smart-858fddcf-93c4-45b7-a8ad-eb1efa6e62cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629203548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1629203548
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.4028672657
Short name T61
Test name
Test status
Simulation time 124853819 ps
CPU time 1.59 seconds
Started Aug 15 06:00:12 PM PDT 24
Finished Aug 15 06:00:14 PM PDT 24
Peak memory 198108 kb
Host smart-ac95c1b6-9d68-448a-aae4-4c6fa4fa3d29
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028672657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.4028672657
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3803706683
Short name T65
Test name
Test status
Simulation time 33217954 ps
CPU time 0.57 seconds
Started Aug 15 06:00:11 PM PDT 24
Finished Aug 15 06:00:12 PM PDT 24
Peak memory 195572 kb
Host smart-ba7e1c01-203d-4f9e-b780-d8a43b6b553d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803706683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3803706683
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.65080895
Short name T1286
Test name
Test status
Simulation time 19180902 ps
CPU time 0.67 seconds
Started Aug 15 06:00:24 PM PDT 24
Finished Aug 15 06:00:25 PM PDT 24
Peak memory 198132 kb
Host smart-4a1e6021-fdbe-4713-98c6-d0cb844354b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65080895 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.65080895
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.21343732
Short name T1200
Test name
Test status
Simulation time 16022463 ps
CPU time 0.6 seconds
Started Aug 15 06:00:12 PM PDT 24
Finished Aug 15 06:00:13 PM PDT 24
Peak memory 195524 kb
Host smart-248a8758-9201-4713-848d-3083e9146216
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21343732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.21343732
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2362901249
Short name T1228
Test name
Test status
Simulation time 16816874 ps
CPU time 0.59 seconds
Started Aug 15 06:00:23 PM PDT 24
Finished Aug 15 06:00:24 PM PDT 24
Peak memory 194620 kb
Host smart-cbce0b71-800b-4d92-8a86-ec6190056016
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362901249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2362901249
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2315681899
Short name T1267
Test name
Test status
Simulation time 35474564 ps
CPU time 0.75 seconds
Started Aug 15 06:00:14 PM PDT 24
Finished Aug 15 06:00:15 PM PDT 24
Peak memory 197304 kb
Host smart-7dc311b3-821f-4e95-abe9-94b64452a1ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315681899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2315681899
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3341680701
Short name T1295
Test name
Test status
Simulation time 26090355 ps
CPU time 1.25 seconds
Started Aug 15 06:00:23 PM PDT 24
Finished Aug 15 06:00:25 PM PDT 24
Peak memory 200272 kb
Host smart-7f83171d-fd45-446c-afa7-3382142d9589
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341680701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3341680701
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.991925827
Short name T78
Test name
Test status
Simulation time 67973752 ps
CPU time 1.33 seconds
Started Aug 15 06:00:13 PM PDT 24
Finished Aug 15 06:00:14 PM PDT 24
Peak memory 199672 kb
Host smart-0f4282c3-1a68-46ba-a451-da2d01b0f738
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991925827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.991925827
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.2865908007
Short name T1293
Test name
Test status
Simulation time 23491288 ps
CPU time 0.57 seconds
Started Aug 15 06:01:04 PM PDT 24
Finished Aug 15 06:01:05 PM PDT 24
Peak memory 194556 kb
Host smart-f4f252a3-a607-401f-8e4b-4e2ffee5e3b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865908007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.2865908007
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.188706660
Short name T1216
Test name
Test status
Simulation time 10348761 ps
CPU time 0.57 seconds
Started Aug 15 06:01:04 PM PDT 24
Finished Aug 15 06:01:05 PM PDT 24
Peak memory 194592 kb
Host smart-d797cc00-b99b-4c1c-9367-fe97e8981544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188706660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.188706660
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.4237895106
Short name T1210
Test name
Test status
Simulation time 39192243 ps
CPU time 0.57 seconds
Started Aug 15 06:01:05 PM PDT 24
Finished Aug 15 06:01:06 PM PDT 24
Peak memory 194640 kb
Host smart-32c2b57b-a0ba-4ede-b6d5-6096927bf474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237895106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.4237895106
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.524861007
Short name T1232
Test name
Test status
Simulation time 13437665 ps
CPU time 0.56 seconds
Started Aug 15 06:01:04 PM PDT 24
Finished Aug 15 06:01:05 PM PDT 24
Peak memory 194616 kb
Host smart-80c57378-c71c-46e5-a6d4-f10455a3c1f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524861007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.524861007
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.20516205
Short name T1197
Test name
Test status
Simulation time 32537745 ps
CPU time 0.6 seconds
Started Aug 15 06:01:03 PM PDT 24
Finished Aug 15 06:01:03 PM PDT 24
Peak memory 194584 kb
Host smart-3a2c5e0b-08c6-41d7-961c-5b5ab8b9089a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20516205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.20516205
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3481945694
Short name T1297
Test name
Test status
Simulation time 28060539 ps
CPU time 0.6 seconds
Started Aug 15 06:01:04 PM PDT 24
Finished Aug 15 06:01:05 PM PDT 24
Peak memory 194592 kb
Host smart-6a09139c-5e9f-44f2-97a4-a8b75dbf648b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481945694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3481945694
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1472093751
Short name T1187
Test name
Test status
Simulation time 14700672 ps
CPU time 0.59 seconds
Started Aug 15 06:01:07 PM PDT 24
Finished Aug 15 06:01:07 PM PDT 24
Peak memory 194632 kb
Host smart-5f17e071-cdbc-4334-9411-9514d47e674d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472093751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1472093751
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1246345056
Short name T1222
Test name
Test status
Simulation time 67984662 ps
CPU time 0.6 seconds
Started Aug 15 06:01:10 PM PDT 24
Finished Aug 15 06:01:11 PM PDT 24
Peak memory 194620 kb
Host smart-f43e907e-f2e3-47e9-a4b2-572cf2b7300f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246345056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1246345056
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3491231421
Short name T1311
Test name
Test status
Simulation time 22597538 ps
CPU time 0.55 seconds
Started Aug 15 06:01:05 PM PDT 24
Finished Aug 15 06:01:06 PM PDT 24
Peak memory 193532 kb
Host smart-b9430e79-84f9-4f9c-8c3a-e9366a5ec31e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491231421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3491231421
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.2071232116
Short name T1289
Test name
Test status
Simulation time 27469587 ps
CPU time 0.58 seconds
Started Aug 15 06:01:04 PM PDT 24
Finished Aug 15 06:01:04 PM PDT 24
Peak memory 194596 kb
Host smart-460d76c7-5aaf-49c6-9945-93437acefa85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071232116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2071232116
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.871594304
Short name T51
Test name
Test status
Simulation time 18358793 ps
CPU time 0.68 seconds
Started Aug 15 06:00:33 PM PDT 24
Finished Aug 15 06:00:33 PM PDT 24
Peak memory 195316 kb
Host smart-85b5f6eb-d152-46db-b7fe-f0745c944286
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871594304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.871594304
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1530237050
Short name T1273
Test name
Test status
Simulation time 119131670 ps
CPU time 1.5 seconds
Started Aug 15 06:00:24 PM PDT 24
Finished Aug 15 06:00:26 PM PDT 24
Peak memory 197900 kb
Host smart-1ce5d412-f7f5-439a-876f-a03974d39859
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530237050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1530237050
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2088019830
Short name T64
Test name
Test status
Simulation time 16282333 ps
CPU time 0.58 seconds
Started Aug 15 06:00:25 PM PDT 24
Finished Aug 15 06:00:25 PM PDT 24
Peak memory 195492 kb
Host smart-6a49e2e6-8212-4729-928c-1b2b270bae97
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088019830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2088019830
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2812979232
Short name T1198
Test name
Test status
Simulation time 30912847 ps
CPU time 0.69 seconds
Started Aug 15 06:00:33 PM PDT 24
Finished Aug 15 06:00:33 PM PDT 24
Peak memory 197788 kb
Host smart-0b2e6c76-734f-4cdf-ac28-609128d56298
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812979232 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2812979232
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1822328817
Short name T54
Test name
Test status
Simulation time 27213402 ps
CPU time 0.6 seconds
Started Aug 15 06:00:23 PM PDT 24
Finished Aug 15 06:00:24 PM PDT 24
Peak memory 195652 kb
Host smart-a98ecb5d-de5e-4aff-aee0-4aab85f07e9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822328817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1822328817
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.300433210
Short name T1243
Test name
Test status
Simulation time 45845794 ps
CPU time 0.57 seconds
Started Aug 15 06:00:24 PM PDT 24
Finished Aug 15 06:00:25 PM PDT 24
Peak memory 194572 kb
Host smart-238d6a75-3a8b-4449-a20c-f75b6aaef0b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300433210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.300433210
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2933886282
Short name T72
Test name
Test status
Simulation time 192963459 ps
CPU time 0.66 seconds
Started Aug 15 06:00:29 PM PDT 24
Finished Aug 15 06:00:30 PM PDT 24
Peak memory 196024 kb
Host smart-e1b91acb-ee30-42fa-8746-411a5988ef99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933886282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2933886282
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3575403459
Short name T1236
Test name
Test status
Simulation time 346905923 ps
CPU time 1.75 seconds
Started Aug 15 06:00:24 PM PDT 24
Finished Aug 15 06:00:26 PM PDT 24
Peak memory 200268 kb
Host smart-d0ab4ffd-6a3a-494a-8e77-2be53dc24ba2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575403459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3575403459
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2415486583
Short name T1252
Test name
Test status
Simulation time 40777053 ps
CPU time 0.89 seconds
Started Aug 15 06:00:24 PM PDT 24
Finished Aug 15 06:00:25 PM PDT 24
Peak memory 198752 kb
Host smart-57cfefff-3322-4140-8a90-5c548248da6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415486583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2415486583
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.1921659586
Short name T1291
Test name
Test status
Simulation time 19662581 ps
CPU time 0.55 seconds
Started Aug 15 06:01:06 PM PDT 24
Finished Aug 15 06:01:07 PM PDT 24
Peak memory 194620 kb
Host smart-1ea34dd3-2898-4624-8f05-627eba752cb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921659586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1921659586
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3578464510
Short name T1271
Test name
Test status
Simulation time 12427668 ps
CPU time 0.57 seconds
Started Aug 15 06:01:05 PM PDT 24
Finished Aug 15 06:01:06 PM PDT 24
Peak memory 194636 kb
Host smart-85cc482c-e622-44b3-9548-2e49f3a2feec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578464510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3578464510
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1542887064
Short name T1303
Test name
Test status
Simulation time 14843589 ps
CPU time 0.57 seconds
Started Aug 15 06:01:13 PM PDT 24
Finished Aug 15 06:01:14 PM PDT 24
Peak memory 194612 kb
Host smart-37843be9-0618-4caa-bdc7-2944f8fa9857
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542887064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1542887064
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2092339991
Short name T1277
Test name
Test status
Simulation time 43535977 ps
CPU time 0.55 seconds
Started Aug 15 06:01:04 PM PDT 24
Finished Aug 15 06:01:04 PM PDT 24
Peak memory 194392 kb
Host smart-3cbcce65-a418-4c8c-b4cf-fa081d93023f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092339991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2092339991
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.421113071
Short name T1246
Test name
Test status
Simulation time 112297728 ps
CPU time 0.56 seconds
Started Aug 15 06:01:06 PM PDT 24
Finished Aug 15 06:01:07 PM PDT 24
Peak memory 194628 kb
Host smart-5f1edf92-9e5b-4368-9f46-85bb16c07448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421113071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.421113071
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3523554791
Short name T1262
Test name
Test status
Simulation time 14499568 ps
CPU time 0.57 seconds
Started Aug 15 06:01:04 PM PDT 24
Finished Aug 15 06:01:04 PM PDT 24
Peak memory 194596 kb
Host smart-155a5ec0-2ae4-46c7-914f-e507ecdc1751
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523554791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3523554791
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3580228355
Short name T1285
Test name
Test status
Simulation time 13450102 ps
CPU time 0.56 seconds
Started Aug 15 06:01:09 PM PDT 24
Finished Aug 15 06:01:10 PM PDT 24
Peak memory 194612 kb
Host smart-d5b7e02f-91e5-4b1b-8b06-d6f3728c0f10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580228355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3580228355
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.2074005324
Short name T1193
Test name
Test status
Simulation time 39992795 ps
CPU time 0.57 seconds
Started Aug 15 06:01:04 PM PDT 24
Finished Aug 15 06:01:05 PM PDT 24
Peak memory 194548 kb
Host smart-0108d529-6a7a-42a6-a30a-d669cf370aa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074005324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2074005324
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.1106773354
Short name T1211
Test name
Test status
Simulation time 23855896 ps
CPU time 0.57 seconds
Started Aug 15 06:01:05 PM PDT 24
Finished Aug 15 06:01:05 PM PDT 24
Peak memory 194544 kb
Host smart-fa32a4fc-dd0f-424d-a9d0-0c7f1c83b3b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106773354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1106773354
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3034433442
Short name T1204
Test name
Test status
Simulation time 13051833 ps
CPU time 0.54 seconds
Started Aug 15 06:01:06 PM PDT 24
Finished Aug 15 06:01:07 PM PDT 24
Peak memory 194548 kb
Host smart-e08b8020-2f65-4850-8125-6e019a69cbab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034433442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3034433442
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.397127219
Short name T1272
Test name
Test status
Simulation time 25038535 ps
CPU time 0.81 seconds
Started Aug 15 06:00:27 PM PDT 24
Finished Aug 15 06:00:27 PM PDT 24
Peak memory 199972 kb
Host smart-a19d2b53-7658-4394-bd1e-d78e121e6efe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397127219 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.397127219
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3680459337
Short name T70
Test name
Test status
Simulation time 11194991 ps
CPU time 0.6 seconds
Started Aug 15 06:00:29 PM PDT 24
Finished Aug 15 06:00:30 PM PDT 24
Peak memory 195556 kb
Host smart-71ba6cad-73ab-4137-9a46-642e70be955d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680459337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3680459337
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.4175611827
Short name T1279
Test name
Test status
Simulation time 12334763 ps
CPU time 0.6 seconds
Started Aug 15 06:00:27 PM PDT 24
Finished Aug 15 06:00:27 PM PDT 24
Peak memory 194592 kb
Host smart-73728098-946d-4f16-9ca1-d946f012ef87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175611827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.4175611827
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.4166932808
Short name T1261
Test name
Test status
Simulation time 42520928 ps
CPU time 0.65 seconds
Started Aug 15 06:00:33 PM PDT 24
Finished Aug 15 06:00:33 PM PDT 24
Peak memory 195912 kb
Host smart-bdc5e223-09bb-40c5-9060-3057ac7c92da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166932808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.4166932808
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.2017565247
Short name T1189
Test name
Test status
Simulation time 86872442 ps
CPU time 1.3 seconds
Started Aug 15 06:00:25 PM PDT 24
Finished Aug 15 06:00:26 PM PDT 24
Peak memory 200268 kb
Host smart-8e24e5ec-eb04-4923-8020-e80238745599
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017565247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2017565247
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1077639540
Short name T1247
Test name
Test status
Simulation time 87023113 ps
CPU time 0.99 seconds
Started Aug 15 06:00:33 PM PDT 24
Finished Aug 15 06:00:34 PM PDT 24
Peak memory 199020 kb
Host smart-36ff31de-c0f0-4398-ba42-141bc15fed81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077639540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1077639540
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3590588323
Short name T1288
Test name
Test status
Simulation time 47394223 ps
CPU time 0.77 seconds
Started Aug 15 06:00:36 PM PDT 24
Finished Aug 15 06:00:37 PM PDT 24
Peak memory 199680 kb
Host smart-5b0d1873-0433-41de-b6aa-0cc6cb77cad6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590588323 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.3590588323
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3451898051
Short name T55
Test name
Test status
Simulation time 24226027 ps
CPU time 0.59 seconds
Started Aug 15 06:00:33 PM PDT 24
Finished Aug 15 06:00:34 PM PDT 24
Peak memory 195604 kb
Host smart-d53aa07c-1af1-4060-a1bc-152dbe0e436c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451898051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3451898051
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.4120607410
Short name T1217
Test name
Test status
Simulation time 44315498 ps
CPU time 0.59 seconds
Started Aug 15 06:00:35 PM PDT 24
Finished Aug 15 06:00:36 PM PDT 24
Peak memory 194840 kb
Host smart-19c9c666-8512-4df9-abcf-d7e3b6405ba2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120607410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.4120607410
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3305954638
Short name T1287
Test name
Test status
Simulation time 54556285 ps
CPU time 0.63 seconds
Started Aug 15 06:00:32 PM PDT 24
Finished Aug 15 06:00:33 PM PDT 24
Peak memory 194812 kb
Host smart-1af3bbe3-3cfb-48b7-9977-fabb83416cbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305954638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.3305954638
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1525993361
Short name T1242
Test name
Test status
Simulation time 121113768 ps
CPU time 1.5 seconds
Started Aug 15 06:00:25 PM PDT 24
Finished Aug 15 06:00:27 PM PDT 24
Peak memory 200276 kb
Host smart-eb006c5a-faea-4d4e-a538-c3a6da52b60c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525993361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1525993361
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2869258615
Short name T79
Test name
Test status
Simulation time 247166063 ps
CPU time 1.25 seconds
Started Aug 15 06:00:34 PM PDT 24
Finished Aug 15 06:00:35 PM PDT 24
Peak memory 199724 kb
Host smart-fabc072a-1f49-41f0-b919-cb57ad85fa47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869258615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2869258615
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1175709053
Short name T1202
Test name
Test status
Simulation time 113292632 ps
CPU time 0.84 seconds
Started Aug 15 06:00:34 PM PDT 24
Finished Aug 15 06:00:35 PM PDT 24
Peak memory 199984 kb
Host smart-76cde2a4-71ee-48ae-9d4e-d3500c8a09ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175709053 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1175709053
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1956084715
Short name T62
Test name
Test status
Simulation time 46867701 ps
CPU time 0.61 seconds
Started Aug 15 06:00:33 PM PDT 24
Finished Aug 15 06:00:34 PM PDT 24
Peak memory 195604 kb
Host smart-887fb823-b76a-4352-8993-cc126879e527
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956084715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1956084715
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1778200670
Short name T1219
Test name
Test status
Simulation time 85559122 ps
CPU time 0.56 seconds
Started Aug 15 06:00:34 PM PDT 24
Finished Aug 15 06:00:34 PM PDT 24
Peak memory 194564 kb
Host smart-6ae2fb6e-7c32-4671-9fb6-9dd627c94c78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778200670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1778200670
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1215533770
Short name T1234
Test name
Test status
Simulation time 54037651 ps
CPU time 0.71 seconds
Started Aug 15 06:00:33 PM PDT 24
Finished Aug 15 06:00:34 PM PDT 24
Peak memory 197268 kb
Host smart-c94605c6-b7cc-43b4-83d3-c5f46248feef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215533770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1215533770
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1342412389
Short name T1229
Test name
Test status
Simulation time 46879370 ps
CPU time 1.29 seconds
Started Aug 15 06:00:35 PM PDT 24
Finished Aug 15 06:00:36 PM PDT 24
Peak memory 200324 kb
Host smart-f02aed28-8690-4513-88b3-9b1ad1c7207c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342412389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1342412389
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2768038146
Short name T1239
Test name
Test status
Simulation time 18828896 ps
CPU time 0.73 seconds
Started Aug 15 06:00:42 PM PDT 24
Finished Aug 15 06:00:42 PM PDT 24
Peak memory 197804 kb
Host smart-bbff4e95-471a-43d2-b63d-ee7d713d0f9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768038146 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2768038146
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.4140759385
Short name T1310
Test name
Test status
Simulation time 28669174 ps
CPU time 0.57 seconds
Started Aug 15 06:00:46 PM PDT 24
Finished Aug 15 06:00:47 PM PDT 24
Peak memory 194632 kb
Host smart-8e3727f9-8a6d-48d6-852a-80f7c1196152
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140759385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.4140759385
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1774425228
Short name T1274
Test name
Test status
Simulation time 225890081 ps
CPU time 0.73 seconds
Started Aug 15 06:00:41 PM PDT 24
Finished Aug 15 06:00:42 PM PDT 24
Peak memory 197160 kb
Host smart-9dd15b1b-b63e-4b69-bc82-91352a48f521
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774425228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1774425228
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3652511897
Short name T1221
Test name
Test status
Simulation time 408955460 ps
CPU time 2.04 seconds
Started Aug 15 06:00:34 PM PDT 24
Finished Aug 15 06:00:37 PM PDT 24
Peak memory 200284 kb
Host smart-9ae5d65b-68c9-49e5-80c5-b80365427a42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652511897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3652511897
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3255908098
Short name T82
Test name
Test status
Simulation time 72917341 ps
CPU time 0.99 seconds
Started Aug 15 06:00:42 PM PDT 24
Finished Aug 15 06:00:43 PM PDT 24
Peak memory 198876 kb
Host smart-fb1de008-dd91-4030-bd5f-72da7f9471c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255908098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3255908098
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2525578299
Short name T1212
Test name
Test status
Simulation time 27065964 ps
CPU time 0.79 seconds
Started Aug 15 06:00:43 PM PDT 24
Finished Aug 15 06:00:44 PM PDT 24
Peak memory 200008 kb
Host smart-214c05d8-46cc-4518-9e9c-cf1e64593c0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525578299 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2525578299
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.375669262
Short name T1230
Test name
Test status
Simulation time 16559907 ps
CPU time 0.6 seconds
Started Aug 15 06:00:42 PM PDT 24
Finished Aug 15 06:00:42 PM PDT 24
Peak memory 195672 kb
Host smart-562ab961-4194-493f-9b30-e617774c9aed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375669262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.375669262
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.3966643199
Short name T1245
Test name
Test status
Simulation time 34629640 ps
CPU time 0.55 seconds
Started Aug 15 06:00:42 PM PDT 24
Finished Aug 15 06:00:42 PM PDT 24
Peak memory 194592 kb
Host smart-edf95a9f-7afa-423a-bae2-16973bc9d4dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966643199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3966643199
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2530824252
Short name T1281
Test name
Test status
Simulation time 104149851 ps
CPU time 0.74 seconds
Started Aug 15 06:00:47 PM PDT 24
Finished Aug 15 06:00:48 PM PDT 24
Peak memory 197804 kb
Host smart-34d623b4-03ff-4d6b-b7db-efee9216ec16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530824252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2530824252
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.2773571555
Short name T1250
Test name
Test status
Simulation time 170002933 ps
CPU time 1.77 seconds
Started Aug 15 06:00:40 PM PDT 24
Finished Aug 15 06:00:42 PM PDT 24
Peak memory 200268 kb
Host smart-73110a5e-c06a-47da-bdf0-4ad55868d965
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773571555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2773571555
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1704349859
Short name T76
Test name
Test status
Simulation time 42136953 ps
CPU time 0.93 seconds
Started Aug 15 06:00:46 PM PDT 24
Finished Aug 15 06:00:48 PM PDT 24
Peak memory 199208 kb
Host smart-8508ac82-cc32-4837-b580-a13d2b6a8ee0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704349859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1704349859
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.4016894601
Short name T615
Test name
Test status
Simulation time 21415664 ps
CPU time 0.56 seconds
Started Aug 15 06:24:49 PM PDT 24
Finished Aug 15 06:24:49 PM PDT 24
Peak memory 196492 kb
Host smart-30c5efe6-de11-4463-81c0-1ee465b8efd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016894601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.4016894601
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.800801427
Short name T725
Test name
Test status
Simulation time 29385938633 ps
CPU time 36.64 seconds
Started Aug 15 06:24:42 PM PDT 24
Finished Aug 15 06:25:19 PM PDT 24
Peak memory 200684 kb
Host smart-8da8b780-e97d-4adc-8b23-15926ef45b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800801427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.800801427
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.4024446821
Short name T383
Test name
Test status
Simulation time 97827376515 ps
CPU time 71.95 seconds
Started Aug 15 06:24:50 PM PDT 24
Finished Aug 15 06:26:02 PM PDT 24
Peak memory 200848 kb
Host smart-6beb6320-20ba-453b-b882-dd50b2615180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024446821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.4024446821
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3756288220
Short name T790
Test name
Test status
Simulation time 102551426563 ps
CPU time 15.71 seconds
Started Aug 15 06:24:49 PM PDT 24
Finished Aug 15 06:25:05 PM PDT 24
Peak memory 200936 kb
Host smart-1dcf9020-5e56-4499-a836-59280fa17795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756288220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3756288220
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.1586992935
Short name T899
Test name
Test status
Simulation time 13041473947 ps
CPU time 17.93 seconds
Started Aug 15 06:24:50 PM PDT 24
Finished Aug 15 06:25:09 PM PDT 24
Peak memory 197968 kb
Host smart-db44fb74-7593-48db-b4da-4e042647638f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586992935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1586992935
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.3163864383
Short name T746
Test name
Test status
Simulation time 131437002761 ps
CPU time 1039.75 seconds
Started Aug 15 06:24:50 PM PDT 24
Finished Aug 15 06:42:10 PM PDT 24
Peak memory 200920 kb
Host smart-b1b1e3ac-a623-4d74-b315-ec1c2ef83414
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3163864383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3163864383
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.805175472
Short name T469
Test name
Test status
Simulation time 10341739745 ps
CPU time 4.98 seconds
Started Aug 15 06:24:49 PM PDT 24
Finished Aug 15 06:24:54 PM PDT 24
Peak memory 200832 kb
Host smart-1bf7f526-347c-4b24-9eba-17fc5b6a1966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805175472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.805175472
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.3792438471
Short name T821
Test name
Test status
Simulation time 109281402672 ps
CPU time 206.38 seconds
Started Aug 15 06:24:48 PM PDT 24
Finished Aug 15 06:28:14 PM PDT 24
Peak memory 200548 kb
Host smart-a9575d9f-d5af-4b24-a3b1-de24443934b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792438471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3792438471
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.3305432586
Short name T483
Test name
Test status
Simulation time 5882096108 ps
CPU time 362.16 seconds
Started Aug 15 06:24:49 PM PDT 24
Finished Aug 15 06:30:51 PM PDT 24
Peak memory 200948 kb
Host smart-a6ae682d-e7c7-4eb8-9f28-971ce7a21a40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3305432586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3305432586
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3781218939
Short name T346
Test name
Test status
Simulation time 3920574741 ps
CPU time 7.25 seconds
Started Aug 15 06:24:49 PM PDT 24
Finished Aug 15 06:24:56 PM PDT 24
Peak memory 199124 kb
Host smart-ec6d6450-af51-42f8-a811-5d258ccc6b8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3781218939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3781218939
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2644809393
Short name T163
Test name
Test status
Simulation time 147222523490 ps
CPU time 17.36 seconds
Started Aug 15 06:24:50 PM PDT 24
Finished Aug 15 06:25:07 PM PDT 24
Peak memory 200712 kb
Host smart-a051c796-81f0-4823-a31f-b4ce8c453f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644809393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2644809393
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.3280924140
Short name T348
Test name
Test status
Simulation time 1497380209 ps
CPU time 1.17 seconds
Started Aug 15 06:24:49 PM PDT 24
Finished Aug 15 06:24:50 PM PDT 24
Peak memory 196644 kb
Host smart-74767316-5224-4a17-9843-2346a98b50cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280924140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3280924140
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.38198229
Short name T927
Test name
Test status
Simulation time 498783794 ps
CPU time 3.85 seconds
Started Aug 15 06:24:43 PM PDT 24
Finished Aug 15 06:24:47 PM PDT 24
Peak memory 199840 kb
Host smart-bb97c4b9-0a8f-4c53-bb77-371238e1e796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38198229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.38198229
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.1284140522
Short name T457
Test name
Test status
Simulation time 10799984441 ps
CPU time 40.15 seconds
Started Aug 15 06:24:49 PM PDT 24
Finished Aug 15 06:25:30 PM PDT 24
Peak memory 209272 kb
Host smart-4e9cd24b-8666-4f06-a62d-58e544313df2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284140522 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.1284140522
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.187357613
Short name T404
Test name
Test status
Simulation time 2344231258 ps
CPU time 1.4 seconds
Started Aug 15 06:24:49 PM PDT 24
Finished Aug 15 06:24:51 PM PDT 24
Peak memory 199376 kb
Host smart-27129e66-768a-444d-9ba0-d4390692a4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187357613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.187357613
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1846993248
Short name T871
Test name
Test status
Simulation time 55272039660 ps
CPU time 100.23 seconds
Started Aug 15 06:24:42 PM PDT 24
Finished Aug 15 06:26:23 PM PDT 24
Peak memory 200916 kb
Host smart-5270c92f-2362-4f46-a3e1-1e6591ca2c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846993248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1846993248
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.2964152659
Short name T890
Test name
Test status
Simulation time 47246381 ps
CPU time 0.54 seconds
Started Aug 15 06:24:54 PM PDT 24
Finished Aug 15 06:24:55 PM PDT 24
Peak memory 196540 kb
Host smart-7feeded7-acd2-460b-9308-03b8a3c7ab99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964152659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2964152659
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.92767959
Short name T904
Test name
Test status
Simulation time 63663512848 ps
CPU time 19 seconds
Started Aug 15 06:24:54 PM PDT 24
Finished Aug 15 06:25:14 PM PDT 24
Peak memory 200876 kb
Host smart-98d03c43-280b-44a7-b5e7-aa57ef90843d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92767959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.92767959
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.569718710
Short name T855
Test name
Test status
Simulation time 22355884951 ps
CPU time 25.92 seconds
Started Aug 15 06:24:55 PM PDT 24
Finished Aug 15 06:25:21 PM PDT 24
Peak memory 200868 kb
Host smart-92c7ac4c-1ff4-44bd-9d2c-0557a5b62a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569718710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.569718710
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3481556939
Short name T40
Test name
Test status
Simulation time 32168747658 ps
CPU time 7.03 seconds
Started Aug 15 06:24:57 PM PDT 24
Finished Aug 15 06:25:04 PM PDT 24
Peak memory 200896 kb
Host smart-454d450c-e297-4957-887a-c77ea9f37f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481556939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3481556939
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.2540651899
Short name T351
Test name
Test status
Simulation time 32970280333 ps
CPU time 49.75 seconds
Started Aug 15 06:24:57 PM PDT 24
Finished Aug 15 06:25:47 PM PDT 24
Peak memory 200920 kb
Host smart-c7e588f5-c74d-4735-905a-c02ec66c009a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540651899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2540651899
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1892025103
Short name T763
Test name
Test status
Simulation time 83430501008 ps
CPU time 577.36 seconds
Started Aug 15 06:24:57 PM PDT 24
Finished Aug 15 06:34:34 PM PDT 24
Peak memory 200900 kb
Host smart-dd3d6639-9203-4aa3-aa54-6e5d10caeabe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1892025103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1892025103
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.4058462823
Short name T872
Test name
Test status
Simulation time 6632724314 ps
CPU time 12.16 seconds
Started Aug 15 06:24:58 PM PDT 24
Finished Aug 15 06:25:10 PM PDT 24
Peak memory 199472 kb
Host smart-711918c4-1931-4228-8628-a68f93328bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058462823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.4058462823
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.2203702343
Short name T983
Test name
Test status
Simulation time 21805655531 ps
CPU time 31.42 seconds
Started Aug 15 06:24:58 PM PDT 24
Finished Aug 15 06:25:30 PM PDT 24
Peak memory 199752 kb
Host smart-8553d5a8-33e4-4181-bc83-714ce10c1648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203702343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2203702343
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.2251602766
Short name T798
Test name
Test status
Simulation time 7344357626 ps
CPU time 370.74 seconds
Started Aug 15 06:24:58 PM PDT 24
Finished Aug 15 06:31:09 PM PDT 24
Peak memory 200904 kb
Host smart-31638e93-384c-4ad0-bfa8-2fe3cd367079
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2251602766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2251602766
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2721749303
Short name T395
Test name
Test status
Simulation time 6948323978 ps
CPU time 6.42 seconds
Started Aug 15 06:24:57 PM PDT 24
Finished Aug 15 06:25:03 PM PDT 24
Peak memory 199752 kb
Host smart-62d9ae71-6a03-45fb-8447-bc0d520abb69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2721749303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2721749303
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.1809913055
Short name T804
Test name
Test status
Simulation time 147908030297 ps
CPU time 294.17 seconds
Started Aug 15 06:24:56 PM PDT 24
Finished Aug 15 06:29:50 PM PDT 24
Peak memory 200940 kb
Host smart-c3558a11-d8f7-470d-ac66-3832327983eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809913055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1809913055
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.925591824
Short name T1075
Test name
Test status
Simulation time 2203901008 ps
CPU time 1.58 seconds
Started Aug 15 06:24:55 PM PDT 24
Finished Aug 15 06:24:57 PM PDT 24
Peak memory 196680 kb
Host smart-98aceb33-6792-477f-9301-72c7f632cced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925591824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.925591824
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.3246894119
Short name T86
Test name
Test status
Simulation time 506604282 ps
CPU time 0.85 seconds
Started Aug 15 06:24:56 PM PDT 24
Finished Aug 15 06:24:56 PM PDT 24
Peak memory 219012 kb
Host smart-b2c94d02-18b0-471e-8054-7640edf93e05
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246894119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3246894119
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.312696206
Short name T263
Test name
Test status
Simulation time 5361109103 ps
CPU time 13.71 seconds
Started Aug 15 06:24:51 PM PDT 24
Finished Aug 15 06:25:04 PM PDT 24
Peak memory 200920 kb
Host smart-1d49bf79-9717-4288-904b-6d57d21f262d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312696206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.312696206
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.3141792924
Short name T975
Test name
Test status
Simulation time 48844377548 ps
CPU time 53.74 seconds
Started Aug 15 06:24:55 PM PDT 24
Finished Aug 15 06:25:49 PM PDT 24
Peak memory 217348 kb
Host smart-b65c287e-84c1-409c-bb4f-14ecf7aeb729
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141792924 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3141792924
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.1790051196
Short name T516
Test name
Test status
Simulation time 6099975913 ps
CPU time 14.08 seconds
Started Aug 15 06:24:56 PM PDT 24
Finished Aug 15 06:25:10 PM PDT 24
Peak memory 200780 kb
Host smart-9e89d5bc-1a7a-4358-ad2c-39c011659eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790051196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1790051196
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.131034130
Short name T673
Test name
Test status
Simulation time 39420828871 ps
CPU time 35.66 seconds
Started Aug 15 06:24:52 PM PDT 24
Finished Aug 15 06:25:28 PM PDT 24
Peak memory 200952 kb
Host smart-c3da679a-01bd-4eae-b045-497a2c82c012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131034130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.131034130
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.1760264043
Short name T428
Test name
Test status
Simulation time 63364650 ps
CPU time 0.53 seconds
Started Aug 15 06:26:06 PM PDT 24
Finished Aug 15 06:26:06 PM PDT 24
Peak memory 195516 kb
Host smart-a59af576-6981-4d93-818f-d6e817e54a53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760264043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1760264043
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.98229399
Short name T667
Test name
Test status
Simulation time 53233938881 ps
CPU time 20.55 seconds
Started Aug 15 06:25:58 PM PDT 24
Finished Aug 15 06:26:19 PM PDT 24
Peak memory 200940 kb
Host smart-bedbaf4f-b65c-4432-b6fe-c5919aac805c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98229399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.98229399
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_intr.553417555
Short name T729
Test name
Test status
Simulation time 97490866079 ps
CPU time 154.79 seconds
Started Aug 15 06:26:00 PM PDT 24
Finished Aug 15 06:28:35 PM PDT 24
Peak memory 200892 kb
Host smart-2c2e9f43-85fb-49e7-8c69-a92ec0e8b4b6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553417555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.553417555
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.779647823
Short name T509
Test name
Test status
Simulation time 213165358471 ps
CPU time 106.71 seconds
Started Aug 15 06:26:08 PM PDT 24
Finished Aug 15 06:27:54 PM PDT 24
Peak memory 200840 kb
Host smart-e9032610-b346-49a9-9d23-694cdb17d9a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=779647823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.779647823
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2641188311
Short name T910
Test name
Test status
Simulation time 3377474916 ps
CPU time 2.37 seconds
Started Aug 15 06:26:03 PM PDT 24
Finished Aug 15 06:26:05 PM PDT 24
Peak memory 197640 kb
Host smart-7a00be50-f5cd-47ee-a446-c3d14c0f3bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641188311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2641188311
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.2648966396
Short name T1011
Test name
Test status
Simulation time 38764759201 ps
CPU time 17.28 seconds
Started Aug 15 06:26:03 PM PDT 24
Finished Aug 15 06:26:20 PM PDT 24
Peak memory 196208 kb
Host smart-cc0649ee-5b60-477b-908a-c4cfe4f7ecfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648966396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2648966396
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.1757548287
Short name T419
Test name
Test status
Simulation time 7505467103 ps
CPU time 129.28 seconds
Started Aug 15 06:26:05 PM PDT 24
Finished Aug 15 06:28:15 PM PDT 24
Peak memory 200900 kb
Host smart-43933074-ef67-426a-ba88-c95ead9874e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1757548287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.1757548287
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2222003910
Short name T542
Test name
Test status
Simulation time 1559478717 ps
CPU time 5.41 seconds
Started Aug 15 06:25:54 PM PDT 24
Finished Aug 15 06:26:00 PM PDT 24
Peak memory 199216 kb
Host smart-8505c5c8-3613-49d2-860f-7d983638db3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2222003910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2222003910
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.848604933
Short name T440
Test name
Test status
Simulation time 85878669027 ps
CPU time 26.63 seconds
Started Aug 15 06:26:03 PM PDT 24
Finished Aug 15 06:26:30 PM PDT 24
Peak memory 200728 kb
Host smart-f9cb809a-ab33-4e5b-934d-4639646c9bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848604933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.848604933
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.146349680
Short name T984
Test name
Test status
Simulation time 39656085526 ps
CPU time 64.97 seconds
Started Aug 15 06:26:03 PM PDT 24
Finished Aug 15 06:27:08 PM PDT 24
Peak memory 197260 kb
Host smart-6c33816a-a630-4879-9b80-e1811b8dc804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146349680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.146349680
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3392334308
Short name T932
Test name
Test status
Simulation time 485166735 ps
CPU time 1.2 seconds
Started Aug 15 06:25:54 PM PDT 24
Finished Aug 15 06:25:55 PM PDT 24
Peak memory 199280 kb
Host smart-623512a7-8265-4035-9d66-c6ac4017384a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392334308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3392334308
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.1879396344
Short name T607
Test name
Test status
Simulation time 376912726984 ps
CPU time 240.96 seconds
Started Aug 15 06:26:02 PM PDT 24
Finished Aug 15 06:30:03 PM PDT 24
Peak memory 209604 kb
Host smart-cc19f289-ad55-41e4-b027-44bc841b9c7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879396344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.1879396344
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1318859588
Short name T125
Test name
Test status
Simulation time 2278707114 ps
CPU time 30.16 seconds
Started Aug 15 06:26:02 PM PDT 24
Finished Aug 15 06:26:32 PM PDT 24
Peak memory 200976 kb
Host smart-f8801991-d041-49a8-b15c-4f2555263d6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318859588 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1318859588
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.2722172814
Short name T1127
Test name
Test status
Simulation time 829466421 ps
CPU time 1.98 seconds
Started Aug 15 06:26:03 PM PDT 24
Finished Aug 15 06:26:05 PM PDT 24
Peak memory 200892 kb
Host smart-32e5a06a-c5e5-4966-b750-39c17a9b3661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722172814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.2722172814
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.1532947642
Short name T43
Test name
Test status
Simulation time 8480199562 ps
CPU time 6.55 seconds
Started Aug 15 06:25:58 PM PDT 24
Finished Aug 15 06:26:05 PM PDT 24
Peak memory 199316 kb
Host smart-61064a9d-cc35-4c9e-9190-cc1fd74774af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532947642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1532947642
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2641345833
Short name T166
Test name
Test status
Simulation time 33721674976 ps
CPU time 58.23 seconds
Started Aug 15 06:30:06 PM PDT 24
Finished Aug 15 06:31:04 PM PDT 24
Peak memory 200916 kb
Host smart-dbeacb2d-09f2-4ff3-bcd7-6d854a91a195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641345833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2641345833
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3511888033
Short name T592
Test name
Test status
Simulation time 62238871152 ps
CPU time 160.39 seconds
Started Aug 15 06:30:10 PM PDT 24
Finished Aug 15 06:32:51 PM PDT 24
Peak memory 200944 kb
Host smart-c2f32e8d-6b26-48b5-864a-d711e7217667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511888033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3511888033
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2265379406
Short name T1045
Test name
Test status
Simulation time 38881587414 ps
CPU time 10.66 seconds
Started Aug 15 06:30:03 PM PDT 24
Finished Aug 15 06:30:14 PM PDT 24
Peak memory 200872 kb
Host smart-74cfebd0-3fd9-46e0-9968-f6fa26f51a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265379406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2265379406
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1526554459
Short name T492
Test name
Test status
Simulation time 39123852666 ps
CPU time 21.64 seconds
Started Aug 15 06:30:04 PM PDT 24
Finished Aug 15 06:30:26 PM PDT 24
Peak memory 200940 kb
Host smart-109650e5-52e1-4b33-8c67-81c70d060042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526554459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1526554459
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3917005342
Short name T268
Test name
Test status
Simulation time 192947638159 ps
CPU time 109.22 seconds
Started Aug 15 06:30:05 PM PDT 24
Finished Aug 15 06:31:54 PM PDT 24
Peak memory 200944 kb
Host smart-d8fe0cc1-f49f-448c-89aa-4142118eb220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917005342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3917005342
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1013634909
Short name T1091
Test name
Test status
Simulation time 37847180949 ps
CPU time 15.72 seconds
Started Aug 15 06:30:05 PM PDT 24
Finished Aug 15 06:30:21 PM PDT 24
Peak memory 201136 kb
Host smart-c81e51e2-4dc9-4043-aa0d-a1049353399b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013634909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1013634909
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1955439610
Short name T1042
Test name
Test status
Simulation time 155054052776 ps
CPU time 31.2 seconds
Started Aug 15 06:30:05 PM PDT 24
Finished Aug 15 06:30:36 PM PDT 24
Peak memory 200976 kb
Host smart-e4218b3b-08ab-44a3-9e80-7b0327e5db53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955439610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1955439610
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3868147918
Short name T180
Test name
Test status
Simulation time 39661481384 ps
CPU time 17.39 seconds
Started Aug 15 06:30:06 PM PDT 24
Finished Aug 15 06:30:23 PM PDT 24
Peak memory 200980 kb
Host smart-2244b1e5-731b-46db-bcce-6050ba8a0177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868147918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3868147918
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2878015340
Short name T844
Test name
Test status
Simulation time 42728532365 ps
CPU time 66.11 seconds
Started Aug 15 06:30:04 PM PDT 24
Finished Aug 15 06:31:11 PM PDT 24
Peak memory 200972 kb
Host smart-e27890cb-c8b1-4a8b-a53a-1b191c327478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878015340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2878015340
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.455356417
Short name T186
Test name
Test status
Simulation time 24018370780 ps
CPU time 39.81 seconds
Started Aug 15 06:30:10 PM PDT 24
Finished Aug 15 06:30:50 PM PDT 24
Peak memory 200968 kb
Host smart-d5890a5c-5c8c-4f6e-9aa9-4a744825ce36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455356417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.455356417
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.1838752101
Short name T652
Test name
Test status
Simulation time 47651721 ps
CPU time 0.56 seconds
Started Aug 15 06:26:10 PM PDT 24
Finished Aug 15 06:26:11 PM PDT 24
Peak memory 196244 kb
Host smart-5ef3cd5c-261e-43d8-9e3e-ea729ba4b33a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838752101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.1838752101
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3564957750
Short name T708
Test name
Test status
Simulation time 207227455082 ps
CPU time 82.4 seconds
Started Aug 15 06:26:02 PM PDT 24
Finished Aug 15 06:27:25 PM PDT 24
Peak memory 200872 kb
Host smart-44a3ef8a-1a6d-4932-95a9-d3121889e092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564957750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3564957750
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.1255817776
Short name T765
Test name
Test status
Simulation time 122296347988 ps
CPU time 191.44 seconds
Started Aug 15 06:26:05 PM PDT 24
Finished Aug 15 06:29:17 PM PDT 24
Peak memory 200684 kb
Host smart-67e0b6ec-6b7f-4ed7-8f8a-e7ab9fab968f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255817776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1255817776
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1314782656
Short name T463
Test name
Test status
Simulation time 17427468396 ps
CPU time 14.76 seconds
Started Aug 15 06:26:05 PM PDT 24
Finished Aug 15 06:26:20 PM PDT 24
Peak memory 200812 kb
Host smart-d695362b-a7f3-49f0-9df0-cda00d0c4814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314782656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1314782656
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.4271867623
Short name T244
Test name
Test status
Simulation time 25585973064 ps
CPU time 21.88 seconds
Started Aug 15 06:26:02 PM PDT 24
Finished Aug 15 06:26:24 PM PDT 24
Peak memory 200968 kb
Host smart-c877a398-796f-4511-b969-36eb97109b6d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271867623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.4271867623
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.523385863
Short name T250
Test name
Test status
Simulation time 199858103760 ps
CPU time 545.45 seconds
Started Aug 15 06:26:09 PM PDT 24
Finished Aug 15 06:35:15 PM PDT 24
Peak memory 200932 kb
Host smart-8881ff7e-0f4e-4a0b-ab61-acf3f4b736b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=523385863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.523385863
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.4178628608
Short name T376
Test name
Test status
Simulation time 9346027787 ps
CPU time 14.98 seconds
Started Aug 15 06:26:04 PM PDT 24
Finished Aug 15 06:26:19 PM PDT 24
Peak memory 199708 kb
Host smart-9e5e9ae6-37cc-4ba7-8969-2a4e80b59450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178628608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.4178628608
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.3047869768
Short name T1018
Test name
Test status
Simulation time 125306111971 ps
CPU time 46.86 seconds
Started Aug 15 06:26:03 PM PDT 24
Finished Aug 15 06:26:50 PM PDT 24
Peak memory 200304 kb
Host smart-b67e60b6-6b20-4fed-ab8a-a519d15b436e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047869768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3047869768
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.2078140400
Short name T969
Test name
Test status
Simulation time 31885733713 ps
CPU time 392.07 seconds
Started Aug 15 06:26:08 PM PDT 24
Finished Aug 15 06:32:40 PM PDT 24
Peak memory 200908 kb
Host smart-a36357f2-c426-46d9-9ad5-86a271cce0d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2078140400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2078140400
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3099962779
Short name T561
Test name
Test status
Simulation time 6002615593 ps
CPU time 8.88 seconds
Started Aug 15 06:26:02 PM PDT 24
Finished Aug 15 06:26:11 PM PDT 24
Peak memory 199204 kb
Host smart-d90e1d23-04c0-4ddd-b822-a473bd4bcadb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3099962779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3099962779
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.4207554442
Short name T671
Test name
Test status
Simulation time 64138440295 ps
CPU time 16.51 seconds
Started Aug 15 06:26:08 PM PDT 24
Finished Aug 15 06:26:25 PM PDT 24
Peak memory 200748 kb
Host smart-313f0b0a-597b-4316-a889-109d83a38e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207554442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.4207554442
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2831873582
Short name T10
Test name
Test status
Simulation time 37747656487 ps
CPU time 15.81 seconds
Started Aug 15 06:26:03 PM PDT 24
Finished Aug 15 06:26:19 PM PDT 24
Peak memory 197424 kb
Host smart-af3065a4-e204-408e-8f49-99dd21c36500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831873582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2831873582
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2208830402
Short name T585
Test name
Test status
Simulation time 127385449 ps
CPU time 0.84 seconds
Started Aug 15 06:26:03 PM PDT 24
Finished Aug 15 06:26:04 PM PDT 24
Peak memory 198780 kb
Host smart-a923b382-bfed-4b4f-992b-62297f4d52ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208830402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2208830402
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.1145235347
Short name T845
Test name
Test status
Simulation time 237044907160 ps
CPU time 1292.29 seconds
Started Aug 15 06:26:09 PM PDT 24
Finished Aug 15 06:47:41 PM PDT 24
Peak memory 200888 kb
Host smart-e8f89dcf-7fe0-45f7-bf1c-53cc826f53fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145235347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1145235347
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.2329233300
Short name T1039
Test name
Test status
Simulation time 3438135963 ps
CPU time 44.8 seconds
Started Aug 15 06:26:13 PM PDT 24
Finished Aug 15 06:26:58 PM PDT 24
Peak memory 217368 kb
Host smart-577e53c5-ba24-449b-92eb-57aaa6a2e0b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329233300 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2329233300
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.345451332
Short name T782
Test name
Test status
Simulation time 1475688439 ps
CPU time 3.14 seconds
Started Aug 15 06:26:04 PM PDT 24
Finished Aug 15 06:26:07 PM PDT 24
Peak memory 200340 kb
Host smart-63e4aa3c-09ec-4760-b253-337b81defa2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345451332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.345451332
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.4111712504
Short name T290
Test name
Test status
Simulation time 27471669264 ps
CPU time 43.52 seconds
Started Aug 15 06:26:02 PM PDT 24
Finished Aug 15 06:26:45 PM PDT 24
Peak memory 200840 kb
Host smart-daa41c41-26d6-4c91-bdd3-8c31bca88cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111712504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.4111712504
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.2311996957
Short name T87
Test name
Test status
Simulation time 60941281653 ps
CPU time 34.84 seconds
Started Aug 15 06:30:06 PM PDT 24
Finished Aug 15 06:30:41 PM PDT 24
Peak memory 200956 kb
Host smart-6f7164d5-d8d7-46ee-8c87-08d168a2861e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311996957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2311996957
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1760124810
Short name T598
Test name
Test status
Simulation time 65151954928 ps
CPU time 82.07 seconds
Started Aug 15 06:30:11 PM PDT 24
Finished Aug 15 06:31:34 PM PDT 24
Peak memory 200904 kb
Host smart-4afb82fd-3ac0-437d-9b62-74e5166329f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760124810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1760124810
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.2896123306
Short name T554
Test name
Test status
Simulation time 144799741902 ps
CPU time 63.2 seconds
Started Aug 15 06:30:04 PM PDT 24
Finished Aug 15 06:31:07 PM PDT 24
Peak memory 200924 kb
Host smart-6dcda2b8-46f9-48f4-a07c-e724a772117d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896123306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2896123306
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1399105387
Short name T471
Test name
Test status
Simulation time 30870832239 ps
CPU time 13.01 seconds
Started Aug 15 06:30:15 PM PDT 24
Finished Aug 15 06:30:28 PM PDT 24
Peak memory 200324 kb
Host smart-ba13c033-8ea3-4eda-a992-6bc7db02758e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399105387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1399105387
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2281216229
Short name T1063
Test name
Test status
Simulation time 33028773098 ps
CPU time 12.36 seconds
Started Aug 15 06:30:11 PM PDT 24
Finished Aug 15 06:30:24 PM PDT 24
Peak memory 200828 kb
Host smart-bd12e7f3-1c8e-4a08-92a8-f2f057e70f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281216229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2281216229
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.727134262
Short name T1136
Test name
Test status
Simulation time 67005436501 ps
CPU time 28.52 seconds
Started Aug 15 06:30:12 PM PDT 24
Finished Aug 15 06:30:40 PM PDT 24
Peak memory 200908 kb
Host smart-9efd5060-4f59-48d8-935c-bc389fe08a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727134262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.727134262
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.871162427
Short name T938
Test name
Test status
Simulation time 8512464807 ps
CPU time 10.66 seconds
Started Aug 15 06:30:12 PM PDT 24
Finished Aug 15 06:30:23 PM PDT 24
Peak memory 200996 kb
Host smart-c4f138f6-1087-4a9a-a608-9aef696c81b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871162427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.871162427
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1103593104
Short name T717
Test name
Test status
Simulation time 63383336557 ps
CPU time 64.08 seconds
Started Aug 15 06:30:10 PM PDT 24
Finished Aug 15 06:31:14 PM PDT 24
Peak memory 200888 kb
Host smart-b8f21470-3051-4cf7-b066-2f603e27c7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103593104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1103593104
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.109852537
Short name T403
Test name
Test status
Simulation time 12742063 ps
CPU time 0.55 seconds
Started Aug 15 06:26:13 PM PDT 24
Finished Aug 15 06:26:13 PM PDT 24
Peak memory 196544 kb
Host smart-1d40a9c4-1d74-4139-90bb-88ec3dfa03be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109852537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.109852537
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2196476201
Short name T485
Test name
Test status
Simulation time 100154791713 ps
CPU time 42.98 seconds
Started Aug 15 06:26:08 PM PDT 24
Finished Aug 15 06:26:51 PM PDT 24
Peak memory 200956 kb
Host smart-f2f808a3-eb65-4b5a-953c-fdfbc60c787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196476201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2196476201
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2270435885
Short name T1141
Test name
Test status
Simulation time 49593596765 ps
CPU time 40.49 seconds
Started Aug 15 06:26:11 PM PDT 24
Finished Aug 15 06:26:51 PM PDT 24
Peak memory 200908 kb
Host smart-8cbd4feb-e413-444c-aeae-20f46114a17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270435885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2270435885
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.1543042515
Short name T167
Test name
Test status
Simulation time 81342230299 ps
CPU time 94.16 seconds
Started Aug 15 06:26:13 PM PDT 24
Finished Aug 15 06:27:47 PM PDT 24
Peak memory 200960 kb
Host smart-cb02f0df-efd3-4773-8947-b290f3c7fbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543042515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1543042515
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.1890214261
Short name T21
Test name
Test status
Simulation time 14140162380 ps
CPU time 20.57 seconds
Started Aug 15 06:26:13 PM PDT 24
Finished Aug 15 06:26:33 PM PDT 24
Peak memory 198288 kb
Host smart-240dc093-b22a-4ba7-9c8c-5f86069ff977
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890214261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1890214261
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.4115224823
Short name T900
Test name
Test status
Simulation time 108615541350 ps
CPU time 166.86 seconds
Started Aug 15 06:26:10 PM PDT 24
Finished Aug 15 06:28:57 PM PDT 24
Peak memory 200876 kb
Host smart-471f8aaa-48e6-4ac6-9c58-ba4c3b00b919
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4115224823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.4115224823
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.2821797974
Short name T369
Test name
Test status
Simulation time 7787987289 ps
CPU time 4.57 seconds
Started Aug 15 06:26:13 PM PDT 24
Finished Aug 15 06:26:18 PM PDT 24
Peak memory 200784 kb
Host smart-98c2b50e-7f9b-4efe-9eab-deb09b65303b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821797974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2821797974
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.1550623320
Short name T801
Test name
Test status
Simulation time 90173876351 ps
CPU time 92.69 seconds
Started Aug 15 06:26:09 PM PDT 24
Finished Aug 15 06:27:42 PM PDT 24
Peak memory 200520 kb
Host smart-c97ba2d5-da44-4a71-b0a7-055a915a5e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550623320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1550623320
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.2235267279
Short name T443
Test name
Test status
Simulation time 14049119491 ps
CPU time 138.44 seconds
Started Aug 15 06:26:07 PM PDT 24
Finished Aug 15 06:28:26 PM PDT 24
Peak memory 200944 kb
Host smart-ca8302b5-fd16-4932-86aa-2b975dbb8330
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2235267279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2235267279
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.3740213429
Short name T1087
Test name
Test status
Simulation time 3724819719 ps
CPU time 8.31 seconds
Started Aug 15 06:26:16 PM PDT 24
Finished Aug 15 06:26:25 PM PDT 24
Peak memory 199972 kb
Host smart-672712cb-039b-4ae9-a7e4-13749844234f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3740213429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3740213429
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.698329164
Short name T496
Test name
Test status
Simulation time 66889463328 ps
CPU time 98.68 seconds
Started Aug 15 06:26:13 PM PDT 24
Finished Aug 15 06:27:52 PM PDT 24
Peak memory 200936 kb
Host smart-9527c092-9d88-4e07-8cb4-5bad72f93a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698329164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.698329164
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.612124521
Short name T528
Test name
Test status
Simulation time 1653697306 ps
CPU time 2.98 seconds
Started Aug 15 06:26:09 PM PDT 24
Finished Aug 15 06:26:12 PM PDT 24
Peak memory 196568 kb
Host smart-250a4111-5c30-4757-9de0-3159711abe1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612124521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.612124521
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2261460433
Short name T833
Test name
Test status
Simulation time 6054489181 ps
CPU time 10.22 seconds
Started Aug 15 06:26:09 PM PDT 24
Finished Aug 15 06:26:20 PM PDT 24
Peak memory 200796 kb
Host smart-20dfce30-c895-4134-a8e7-8dc91e0e1450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261460433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2261460433
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.3411871877
Short name T713
Test name
Test status
Simulation time 39585937663 ps
CPU time 137.17 seconds
Started Aug 15 06:26:10 PM PDT 24
Finished Aug 15 06:28:27 PM PDT 24
Peak memory 201112 kb
Host smart-5e719c07-06c7-442b-af19-b65faf0e4a40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411871877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3411871877
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.31542355
Short name T633
Test name
Test status
Simulation time 980740563 ps
CPU time 12.59 seconds
Started Aug 15 06:26:09 PM PDT 24
Finished Aug 15 06:26:22 PM PDT 24
Peak memory 216652 kb
Host smart-4143a6dd-eb5e-487e-9574-68669cfc5fac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31542355 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.31542355
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.2431734230
Short name T985
Test name
Test status
Simulation time 657263366 ps
CPU time 2 seconds
Started Aug 15 06:26:09 PM PDT 24
Finished Aug 15 06:26:11 PM PDT 24
Peak memory 199352 kb
Host smart-71625a37-180c-4d57-8871-0f9883dcfbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431734230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2431734230
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.3110315699
Short name T820
Test name
Test status
Simulation time 46712558000 ps
CPU time 42.24 seconds
Started Aug 15 06:26:14 PM PDT 24
Finished Aug 15 06:26:56 PM PDT 24
Peak memory 200924 kb
Host smart-a1a08d00-5e2c-4663-9fd3-1544dbcc4f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110315699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3110315699
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.2754812974
Short name T738
Test name
Test status
Simulation time 36193167138 ps
CPU time 17.52 seconds
Started Aug 15 06:30:11 PM PDT 24
Finished Aug 15 06:30:29 PM PDT 24
Peak memory 200944 kb
Host smart-6d0dba24-a1ac-4fff-9a7b-654c1d60bb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754812974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2754812974
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2179571894
Short name T943
Test name
Test status
Simulation time 11901507315 ps
CPU time 42.37 seconds
Started Aug 15 06:30:13 PM PDT 24
Finished Aug 15 06:30:55 PM PDT 24
Peak memory 200912 kb
Host smart-3983968b-783c-43f4-bf2c-f5af3e9b5f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179571894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2179571894
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3501191573
Short name T869
Test name
Test status
Simulation time 162246850972 ps
CPU time 293.99 seconds
Started Aug 15 06:30:11 PM PDT 24
Finished Aug 15 06:35:06 PM PDT 24
Peak memory 200948 kb
Host smart-d6936ae7-394e-48cc-b8b5-9d87259a34bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501191573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3501191573
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3488826428
Short name T687
Test name
Test status
Simulation time 243615509261 ps
CPU time 743.59 seconds
Started Aug 15 06:30:12 PM PDT 24
Finished Aug 15 06:42:36 PM PDT 24
Peak memory 200948 kb
Host smart-96f53f0e-c935-4ec0-99af-b8d3ac264dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488826428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3488826428
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.3473417143
Short name T439
Test name
Test status
Simulation time 54054493064 ps
CPU time 20.71 seconds
Started Aug 15 06:30:11 PM PDT 24
Finished Aug 15 06:30:31 PM PDT 24
Peak memory 200948 kb
Host smart-56c62f3c-8e26-48a8-90c6-c4b7e47131af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473417143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3473417143
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.3755610848
Short name T762
Test name
Test status
Simulation time 71504036609 ps
CPU time 32.44 seconds
Started Aug 15 06:30:12 PM PDT 24
Finished Aug 15 06:30:44 PM PDT 24
Peak memory 200872 kb
Host smart-debeb9f6-9d07-4989-bc6b-efd00ae56556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755610848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3755610848
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.759306772
Short name T1038
Test name
Test status
Simulation time 21432614890 ps
CPU time 9.86 seconds
Started Aug 15 06:30:10 PM PDT 24
Finished Aug 15 06:30:20 PM PDT 24
Peak memory 200960 kb
Host smart-044d06b0-bc1b-4099-b7b4-0edeab926a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759306772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.759306772
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2545728176
Short name T819
Test name
Test status
Simulation time 42223609824 ps
CPU time 88.08 seconds
Started Aug 15 06:30:12 PM PDT 24
Finished Aug 15 06:31:41 PM PDT 24
Peak memory 200968 kb
Host smart-a5e20a34-640a-4045-9e96-4e31e80b6cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545728176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2545728176
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1729067946
Short name T475
Test name
Test status
Simulation time 36178587 ps
CPU time 0.55 seconds
Started Aug 15 06:26:17 PM PDT 24
Finished Aug 15 06:26:17 PM PDT 24
Peak memory 196264 kb
Host smart-bd98829b-7d3b-487d-95d7-e4d08c199a47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729067946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1729067946
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.3584695438
Short name T1025
Test name
Test status
Simulation time 12928965771 ps
CPU time 12.69 seconds
Started Aug 15 06:26:19 PM PDT 24
Finished Aug 15 06:26:31 PM PDT 24
Peak memory 200928 kb
Host smart-e0af91c9-8bd7-4b87-8dd6-f5412a8c8e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584695438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3584695438
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1897960586
Short name T919
Test name
Test status
Simulation time 18015996981 ps
CPU time 29.21 seconds
Started Aug 15 06:26:17 PM PDT 24
Finished Aug 15 06:26:46 PM PDT 24
Peak memory 200892 kb
Host smart-4f4e09d1-81bf-413c-8b2c-1eb8289bd77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897960586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1897960586
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.1162182787
Short name T795
Test name
Test status
Simulation time 117876449177 ps
CPU time 173.37 seconds
Started Aug 15 06:26:18 PM PDT 24
Finished Aug 15 06:29:12 PM PDT 24
Peak memory 200828 kb
Host smart-44c1f1ce-fbab-4db6-96b3-9253ca925f21
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162182787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1162182787
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.2670281954
Short name T994
Test name
Test status
Simulation time 151174239447 ps
CPU time 647.71 seconds
Started Aug 15 06:26:17 PM PDT 24
Finished Aug 15 06:37:05 PM PDT 24
Peak memory 200920 kb
Host smart-6d84e99f-8cea-481f-b487-a9cbb0911069
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2670281954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2670281954
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.2659027024
Short name T438
Test name
Test status
Simulation time 6326683451 ps
CPU time 6.1 seconds
Started Aug 15 06:26:17 PM PDT 24
Finished Aug 15 06:26:23 PM PDT 24
Peak memory 200692 kb
Host smart-3435ea25-588c-48e9-a991-2788b6a46309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659027024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.2659027024
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.2755687876
Short name T911
Test name
Test status
Simulation time 61941383933 ps
CPU time 205.47 seconds
Started Aug 15 06:26:16 PM PDT 24
Finished Aug 15 06:29:42 PM PDT 24
Peak memory 201116 kb
Host smart-6131a9e1-4f4c-4b63-bfcb-1eb7683357dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755687876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2755687876
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.2145748387
Short name T277
Test name
Test status
Simulation time 4578634662 ps
CPU time 187.11 seconds
Started Aug 15 06:26:21 PM PDT 24
Finished Aug 15 06:29:28 PM PDT 24
Peak memory 200940 kb
Host smart-fd10ddc9-3e5b-454c-a1af-9938869f5679
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2145748387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2145748387
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.3102811999
Short name T878
Test name
Test status
Simulation time 3756164995 ps
CPU time 2.02 seconds
Started Aug 15 06:26:20 PM PDT 24
Finished Aug 15 06:26:22 PM PDT 24
Peak memory 199624 kb
Host smart-fc0e7874-1fb4-4d50-af7e-e64db276c4e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3102811999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3102811999
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3193909534
Short name T842
Test name
Test status
Simulation time 52025932888 ps
CPU time 23.81 seconds
Started Aug 15 06:26:17 PM PDT 24
Finished Aug 15 06:26:41 PM PDT 24
Peak memory 200684 kb
Host smart-6398a99e-1025-4ec9-93e3-60f750c06fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193909534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3193909534
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2774852175
Short name T1070
Test name
Test status
Simulation time 41329417410 ps
CPU time 54.67 seconds
Started Aug 15 06:26:17 PM PDT 24
Finished Aug 15 06:27:11 PM PDT 24
Peak memory 196988 kb
Host smart-2d03e017-ae84-492f-b052-813c9d216467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774852175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2774852175
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.139333672
Short name T445
Test name
Test status
Simulation time 1013772491 ps
CPU time 1.27 seconds
Started Aug 15 06:26:12 PM PDT 24
Finished Aug 15 06:26:14 PM PDT 24
Peak memory 199680 kb
Host smart-23d41b75-71c0-4851-b984-e52f8efbbfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139333672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.139333672
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.466828311
Short name T98
Test name
Test status
Simulation time 2520678528 ps
CPU time 13.89 seconds
Started Aug 15 06:26:18 PM PDT 24
Finished Aug 15 06:26:32 PM PDT 24
Peak memory 217284 kb
Host smart-6b88ea0e-c265-46d8-a027-fc962d390f0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466828311 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.466828311
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.761054265
Short name T747
Test name
Test status
Simulation time 1233859945 ps
CPU time 1.36 seconds
Started Aug 15 06:26:20 PM PDT 24
Finished Aug 15 06:26:22 PM PDT 24
Peak memory 199464 kb
Host smart-27504f7b-4e22-4d84-a2db-aed3ac600fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761054265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.761054265
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.4003547783
Short name T1029
Test name
Test status
Simulation time 83231827402 ps
CPU time 138.5 seconds
Started Aug 15 06:26:16 PM PDT 24
Finished Aug 15 06:28:34 PM PDT 24
Peak memory 200936 kb
Host smart-3ac1acd2-c4f3-416d-aac6-56895e0402be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003547783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.4003547783
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.957322966
Short name T236
Test name
Test status
Simulation time 20177950232 ps
CPU time 22.61 seconds
Started Aug 15 06:30:14 PM PDT 24
Finished Aug 15 06:30:36 PM PDT 24
Peak memory 200928 kb
Host smart-fa05cfcc-f7fa-4e43-a71a-76183a9c8633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957322966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.957322966
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2056316146
Short name T589
Test name
Test status
Simulation time 118816400992 ps
CPU time 102.65 seconds
Started Aug 15 06:30:12 PM PDT 24
Finished Aug 15 06:31:55 PM PDT 24
Peak memory 200936 kb
Host smart-08adad00-6237-41e9-b279-b1c0b418cf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056316146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2056316146
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.904024888
Short name T988
Test name
Test status
Simulation time 6834628793 ps
CPU time 12.07 seconds
Started Aug 15 06:30:13 PM PDT 24
Finished Aug 15 06:30:25 PM PDT 24
Peak memory 200900 kb
Host smart-97a2f667-8a18-413d-a9c2-00accc0691eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904024888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.904024888
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2036178173
Short name T241
Test name
Test status
Simulation time 141337827222 ps
CPU time 35.09 seconds
Started Aug 15 06:30:15 PM PDT 24
Finished Aug 15 06:30:50 PM PDT 24
Peak memory 200832 kb
Host smart-9074c043-1893-41a4-aa11-97193dfa0ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036178173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2036178173
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.2123817376
Short name T202
Test name
Test status
Simulation time 7199074276 ps
CPU time 13.8 seconds
Started Aug 15 06:30:20 PM PDT 24
Finished Aug 15 06:30:34 PM PDT 24
Peak memory 200960 kb
Host smart-6d45d479-d4eb-447f-b107-737e7a3092cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123817376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2123817376
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3407960513
Short name T226
Test name
Test status
Simulation time 88114947783 ps
CPU time 43.31 seconds
Started Aug 15 06:30:20 PM PDT 24
Finished Aug 15 06:31:03 PM PDT 24
Peak memory 200968 kb
Host smart-77c25205-12da-422f-a44a-92f6df570c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407960513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3407960513
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3736711106
Short name T1082
Test name
Test status
Simulation time 126200198079 ps
CPU time 50.91 seconds
Started Aug 15 06:30:28 PM PDT 24
Finished Aug 15 06:31:19 PM PDT 24
Peak memory 200908 kb
Host smart-ea8f27ed-0d67-4b24-912a-7538921d8a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736711106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3736711106
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.83521787
Short name T562
Test name
Test status
Simulation time 145215360404 ps
CPU time 27.93 seconds
Started Aug 15 06:30:18 PM PDT 24
Finished Aug 15 06:30:46 PM PDT 24
Peak memory 200840 kb
Host smart-5df16245-21c7-4e22-8471-a7ed86fa97aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83521787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.83521787
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3639477637
Short name T232
Test name
Test status
Simulation time 140807142293 ps
CPU time 55.48 seconds
Started Aug 15 06:30:19 PM PDT 24
Finished Aug 15 06:31:15 PM PDT 24
Peak memory 200920 kb
Host smart-92a7ece3-13af-4c7c-865b-62d24b41724d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639477637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3639477637
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.4119314516
Short name T832
Test name
Test status
Simulation time 108465016983 ps
CPU time 59.42 seconds
Started Aug 15 06:30:30 PM PDT 24
Finished Aug 15 06:31:29 PM PDT 24
Peak memory 200892 kb
Host smart-3b779b80-ab08-402a-bfdf-0d7bd1b4392a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119314516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.4119314516
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.738772338
Short name T964
Test name
Test status
Simulation time 18895580 ps
CPU time 0.55 seconds
Started Aug 15 06:26:25 PM PDT 24
Finished Aug 15 06:26:26 PM PDT 24
Peak memory 196736 kb
Host smart-89a1bab0-1616-45de-96ef-0f7b2fcba73d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738772338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.738772338
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.1592353749
Short name T873
Test name
Test status
Simulation time 45944075096 ps
CPU time 68.15 seconds
Started Aug 15 06:26:25 PM PDT 24
Finished Aug 15 06:27:34 PM PDT 24
Peak memory 200924 kb
Host smart-974f3fc1-1c79-4a21-9d42-ca13a72eaa96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592353749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1592353749
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3573755412
Short name T365
Test name
Test status
Simulation time 118834405395 ps
CPU time 63.54 seconds
Started Aug 15 06:26:26 PM PDT 24
Finished Aug 15 06:27:30 PM PDT 24
Peak memory 200892 kb
Host smart-4f0e62f2-64aa-4a65-bc56-533a0fa9fd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573755412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3573755412
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.2360031290
Short name T947
Test name
Test status
Simulation time 10044747242 ps
CPU time 16.93 seconds
Started Aug 15 06:26:26 PM PDT 24
Finished Aug 15 06:26:44 PM PDT 24
Peak memory 200920 kb
Host smart-3361ab1b-66d4-4fa3-a740-d83431a80335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360031290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2360031290
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.2743306453
Short name T906
Test name
Test status
Simulation time 12860491937 ps
CPU time 10.1 seconds
Started Aug 15 06:26:23 PM PDT 24
Finished Aug 15 06:26:34 PM PDT 24
Peak memory 200188 kb
Host smart-43b9d8ee-5fb6-45ad-8931-2334d376a194
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743306453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2743306453
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.996495307
Short name T425
Test name
Test status
Simulation time 218182050744 ps
CPU time 168.8 seconds
Started Aug 15 06:26:25 PM PDT 24
Finished Aug 15 06:29:14 PM PDT 24
Peak memory 200900 kb
Host smart-239edb8a-e3f5-4b53-9639-7f32d9eb8b5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=996495307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.996495307
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.37871723
Short name T998
Test name
Test status
Simulation time 8168118071 ps
CPU time 9.59 seconds
Started Aug 15 06:26:24 PM PDT 24
Finished Aug 15 06:26:34 PM PDT 24
Peak memory 199352 kb
Host smart-ed490da1-fe47-49cb-9e6f-9f18a2e1adcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37871723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.37871723
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.323423862
Short name T427
Test name
Test status
Simulation time 55294203844 ps
CPU time 94.11 seconds
Started Aug 15 06:26:26 PM PDT 24
Finished Aug 15 06:28:00 PM PDT 24
Peak memory 199976 kb
Host smart-3d3d0c2b-e798-4111-8f2d-4bfac9adbf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323423862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.323423862
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.3161854937
Short name T537
Test name
Test status
Simulation time 46085282671 ps
CPU time 357.14 seconds
Started Aug 15 06:26:27 PM PDT 24
Finished Aug 15 06:32:24 PM PDT 24
Peak memory 200948 kb
Host smart-ad54bf94-4f35-4183-9562-cd60a6f26add
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3161854937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3161854937
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.3165818772
Short name T364
Test name
Test status
Simulation time 6205753660 ps
CPU time 43.97 seconds
Started Aug 15 06:26:26 PM PDT 24
Finished Aug 15 06:27:10 PM PDT 24
Peak memory 199156 kb
Host smart-490e8651-72d4-4d6c-bdc3-768f4554ab2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3165818772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3165818772
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.1041680971
Short name T779
Test name
Test status
Simulation time 41478510311 ps
CPU time 36.2 seconds
Started Aug 15 06:26:25 PM PDT 24
Finished Aug 15 06:27:01 PM PDT 24
Peak memory 200764 kb
Host smart-92466543-788b-475f-b06e-f95b8fc411c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041680971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1041680971
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3731347453
Short name T288
Test name
Test status
Simulation time 458507613 ps
CPU time 0.95 seconds
Started Aug 15 06:26:25 PM PDT 24
Finished Aug 15 06:26:26 PM PDT 24
Peak memory 196576 kb
Host smart-2b5b4c44-308c-4a9c-b8d9-71bcbb20cdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731347453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3731347453
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.201975771
Short name T487
Test name
Test status
Simulation time 567911510 ps
CPU time 2.09 seconds
Started Aug 15 06:26:24 PM PDT 24
Finished Aug 15 06:26:26 PM PDT 24
Peak memory 199316 kb
Host smart-392743b3-7c2b-4c39-9fd2-23375e482d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201975771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.201975771
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3882256534
Short name T245
Test name
Test status
Simulation time 53237015327 ps
CPU time 56.17 seconds
Started Aug 15 06:26:24 PM PDT 24
Finished Aug 15 06:27:20 PM PDT 24
Peak memory 217416 kb
Host smart-0e98a365-fce9-427b-acc0-b4b2534ba94a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882256534 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3882256534
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.3411167739
Short name T748
Test name
Test status
Simulation time 1887409413 ps
CPU time 1.71 seconds
Started Aug 15 06:26:26 PM PDT 24
Finished Aug 15 06:26:28 PM PDT 24
Peak memory 199656 kb
Host smart-96a0800a-84de-4dbe-9226-790f85950bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411167739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3411167739
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1072733649
Short name T862
Test name
Test status
Simulation time 45568242556 ps
CPU time 76.67 seconds
Started Aug 15 06:26:25 PM PDT 24
Finished Aug 15 06:27:42 PM PDT 24
Peak memory 200920 kb
Host smart-cd2bd77c-1dd4-4444-ad31-b09202d49ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072733649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1072733649
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3609679259
Short name T1004
Test name
Test status
Simulation time 60020504337 ps
CPU time 54.32 seconds
Started Aug 15 06:30:30 PM PDT 24
Finished Aug 15 06:31:24 PM PDT 24
Peak memory 200836 kb
Host smart-6737f12f-a867-483f-a928-c2fc24f36779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609679259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3609679259
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2329197575
Short name T530
Test name
Test status
Simulation time 18386191797 ps
CPU time 22.18 seconds
Started Aug 15 06:30:19 PM PDT 24
Finished Aug 15 06:30:41 PM PDT 24
Peak memory 200872 kb
Host smart-af664c38-b9b8-4c45-97e5-e371dad66951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329197575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2329197575
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2329421582
Short name T848
Test name
Test status
Simulation time 28760429568 ps
CPU time 46.97 seconds
Started Aug 15 06:30:19 PM PDT 24
Finished Aug 15 06:31:06 PM PDT 24
Peak memory 200868 kb
Host smart-0099922c-c87f-400e-bde2-fab4ffb13c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329421582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2329421582
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3555593759
Short name T1062
Test name
Test status
Simulation time 106896329724 ps
CPU time 140.55 seconds
Started Aug 15 06:30:21 PM PDT 24
Finished Aug 15 06:32:42 PM PDT 24
Peak memory 200948 kb
Host smart-c562c40d-bdf1-4d91-b0bd-f3c68d818db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555593759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3555593759
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3937480800
Short name T1031
Test name
Test status
Simulation time 67186252210 ps
CPU time 98.93 seconds
Started Aug 15 06:30:28 PM PDT 24
Finished Aug 15 06:32:07 PM PDT 24
Peak memory 200684 kb
Host smart-fa2a6273-bd90-4ebe-8c34-3f2058fc4b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937480800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3937480800
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1524862972
Short name T1171
Test name
Test status
Simulation time 8065746367 ps
CPU time 17.7 seconds
Started Aug 15 06:30:21 PM PDT 24
Finished Aug 15 06:30:38 PM PDT 24
Peak memory 200928 kb
Host smart-3e87a0db-931c-4cd3-b91d-434210908bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524862972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1524862972
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.547232046
Short name T813
Test name
Test status
Simulation time 112099643933 ps
CPU time 78.4 seconds
Started Aug 15 06:30:23 PM PDT 24
Finished Aug 15 06:31:41 PM PDT 24
Peak memory 200776 kb
Host smart-cdf1f326-76d3-4787-b73a-864cd76a0fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547232046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.547232046
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.2623594344
Short name T743
Test name
Test status
Simulation time 20806479 ps
CPU time 0.56 seconds
Started Aug 15 06:26:32 PM PDT 24
Finished Aug 15 06:26:33 PM PDT 24
Peak memory 196232 kb
Host smart-73670e7d-0aa8-42d4-a901-6a6513d8ac08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623594344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2623594344
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2416266211
Short name T106
Test name
Test status
Simulation time 283184137287 ps
CPU time 46.2 seconds
Started Aug 15 06:26:26 PM PDT 24
Finished Aug 15 06:27:13 PM PDT 24
Peak memory 200900 kb
Host smart-18e658c7-f13f-47a4-860c-fad9f01106df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416266211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2416266211
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.4180667728
Short name T91
Test name
Test status
Simulation time 122558472475 ps
CPU time 102.24 seconds
Started Aug 15 06:26:23 PM PDT 24
Finished Aug 15 06:28:06 PM PDT 24
Peak memory 200960 kb
Host smart-464ab6b6-5a21-41d2-9456-a102617049c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180667728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.4180667728
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.1961387516
Short name T750
Test name
Test status
Simulation time 428447050635 ps
CPU time 48.83 seconds
Started Aug 15 06:26:25 PM PDT 24
Finished Aug 15 06:27:14 PM PDT 24
Peak memory 200968 kb
Host smart-d364e70e-f0e1-4df1-b6cf-a54669bd31fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961387516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1961387516
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.347710235
Short name T916
Test name
Test status
Simulation time 111406074110 ps
CPU time 516.12 seconds
Started Aug 15 06:26:32 PM PDT 24
Finished Aug 15 06:35:08 PM PDT 24
Peak memory 200924 kb
Host smart-89bc3175-e48c-4e31-969b-f5312d6aeea2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=347710235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.347710235
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.4112951673
Short name T734
Test name
Test status
Simulation time 3147119217 ps
CPU time 2.17 seconds
Started Aug 15 06:26:32 PM PDT 24
Finished Aug 15 06:26:35 PM PDT 24
Peak memory 197028 kb
Host smart-83dca0ec-a624-4dc1-abd1-c936b8c39c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112951673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.4112951673
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.3071281914
Short name T1167
Test name
Test status
Simulation time 50238527481 ps
CPU time 77.35 seconds
Started Aug 15 06:26:33 PM PDT 24
Finished Aug 15 06:27:51 PM PDT 24
Peak memory 200244 kb
Host smart-581ec206-27e5-4b5c-be12-67c74fd1f733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071281914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3071281914
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2174980980
Short name T266
Test name
Test status
Simulation time 12700368789 ps
CPU time 149.72 seconds
Started Aug 15 06:26:31 PM PDT 24
Finished Aug 15 06:29:01 PM PDT 24
Peak memory 200912 kb
Host smart-2691d97f-bdda-477b-8f37-4fc7bc5cd64d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2174980980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2174980980
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.97456685
Short name T23
Test name
Test status
Simulation time 6023290830 ps
CPU time 21.94 seconds
Started Aug 15 06:26:24 PM PDT 24
Finished Aug 15 06:26:46 PM PDT 24
Peak memory 199592 kb
Host smart-142f152c-c3e8-4cb3-a88e-d957e524e7c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=97456685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.97456685
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.2590168046
Short name T571
Test name
Test status
Simulation time 24756363900 ps
CPU time 23.45 seconds
Started Aug 15 06:26:33 PM PDT 24
Finished Aug 15 06:26:56 PM PDT 24
Peak memory 200888 kb
Host smart-96c8e52a-d48c-4b27-a7da-eb8fdbb82542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590168046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2590168046
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.2133930629
Short name T374
Test name
Test status
Simulation time 33215775793 ps
CPU time 8.04 seconds
Started Aug 15 06:26:35 PM PDT 24
Finished Aug 15 06:26:43 PM PDT 24
Peak memory 197436 kb
Host smart-2fb15a95-f160-49cf-874c-f60f78d8a82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133930629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2133930629
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.4226416654
Short name T1182
Test name
Test status
Simulation time 6030323874 ps
CPU time 22.32 seconds
Started Aug 15 06:26:24 PM PDT 24
Finished Aug 15 06:26:46 PM PDT 24
Peak memory 200904 kb
Host smart-9e9ff7c6-bf01-48bb-8d07-102e243409c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226416654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.4226416654
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.3849612984
Short name T511
Test name
Test status
Simulation time 137344917170 ps
CPU time 785.1 seconds
Started Aug 15 06:26:34 PM PDT 24
Finished Aug 15 06:39:39 PM PDT 24
Peak memory 200916 kb
Host smart-c0d1f92f-f551-43e9-acd3-7c3a9a85fd59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849612984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3849612984
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3404809104
Short name T1026
Test name
Test status
Simulation time 9995910686 ps
CPU time 44.38 seconds
Started Aug 15 06:26:38 PM PDT 24
Finished Aug 15 06:27:22 PM PDT 24
Peak memory 216356 kb
Host smart-d9dae7a3-8b6e-4b9d-9243-516b213f700e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404809104 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3404809104
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1375042664
Short name T677
Test name
Test status
Simulation time 1807769599 ps
CPU time 1.7 seconds
Started Aug 15 06:26:32 PM PDT 24
Finished Aug 15 06:26:34 PM PDT 24
Peak memory 199168 kb
Host smart-6941c7d5-920a-4f61-b9ce-3d715175fa36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375042664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1375042664
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2061520079
Short name T452
Test name
Test status
Simulation time 68987098593 ps
CPU time 24.91 seconds
Started Aug 15 06:26:25 PM PDT 24
Finished Aug 15 06:26:51 PM PDT 24
Peak memory 200988 kb
Host smart-175e76a4-d9aa-4838-851d-438aec66a8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061520079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2061520079
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.1263475568
Short name T850
Test name
Test status
Simulation time 33273537132 ps
CPU time 44.1 seconds
Started Aug 15 06:30:19 PM PDT 24
Finished Aug 15 06:31:03 PM PDT 24
Peak memory 200796 kb
Host smart-4a92d3a4-b037-4cb3-b091-f49c18fb0242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263475568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1263475568
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.215865584
Short name T1152
Test name
Test status
Simulation time 42520116008 ps
CPU time 16.25 seconds
Started Aug 15 06:30:21 PM PDT 24
Finished Aug 15 06:30:37 PM PDT 24
Peak memory 200884 kb
Host smart-58323353-d1e2-4021-9794-0ae6b3098a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215865584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.215865584
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.4231403707
Short name T312
Test name
Test status
Simulation time 33200031038 ps
CPU time 13.79 seconds
Started Aug 15 06:30:19 PM PDT 24
Finished Aug 15 06:30:33 PM PDT 24
Peak memory 200716 kb
Host smart-f739b7de-dc21-42cb-9df8-6ffb2e112ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231403707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.4231403707
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.572103270
Short name T1170
Test name
Test status
Simulation time 62663198602 ps
CPU time 42.04 seconds
Started Aug 15 06:30:18 PM PDT 24
Finished Aug 15 06:31:00 PM PDT 24
Peak memory 200952 kb
Host smart-69e7237a-2c72-49dc-bdd7-d6cceb9fa0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572103270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.572103270
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.3286412851
Short name T6
Test name
Test status
Simulation time 52118164834 ps
CPU time 18.98 seconds
Started Aug 15 06:30:20 PM PDT 24
Finished Aug 15 06:30:39 PM PDT 24
Peak memory 200892 kb
Host smart-97c0b8d9-c3be-4d64-8c58-dcca53f445b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286412851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3286412851
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.886265559
Short name T1028
Test name
Test status
Simulation time 26796198438 ps
CPU time 47.57 seconds
Started Aug 15 06:30:19 PM PDT 24
Finished Aug 15 06:31:07 PM PDT 24
Peak memory 200916 kb
Host smart-2531614e-1820-4a42-b903-6f9690a628da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886265559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.886265559
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3877809881
Short name T523
Test name
Test status
Simulation time 61489040014 ps
CPU time 28.86 seconds
Started Aug 15 06:30:28 PM PDT 24
Finished Aug 15 06:30:57 PM PDT 24
Peak memory 200892 kb
Host smart-87cabfb7-7c17-4725-9998-0050dc20a6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877809881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3877809881
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1084584366
Short name T442
Test name
Test status
Simulation time 20402967377 ps
CPU time 34.35 seconds
Started Aug 15 06:30:22 PM PDT 24
Finished Aug 15 06:30:57 PM PDT 24
Peak memory 200956 kb
Host smart-c8dbb264-f7ed-4c7d-b795-627a79370080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084584366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1084584366
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.39322883
Short name T201
Test name
Test status
Simulation time 407034581054 ps
CPU time 32.66 seconds
Started Aug 15 06:30:23 PM PDT 24
Finished Aug 15 06:30:56 PM PDT 24
Peak memory 200852 kb
Host smart-44517089-8fdc-4ae2-a608-90ae55219955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39322883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.39322883
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2589934881
Short name T818
Test name
Test status
Simulation time 27199096 ps
CPU time 0.52 seconds
Started Aug 15 06:26:38 PM PDT 24
Finished Aug 15 06:26:39 PM PDT 24
Peak memory 195700 kb
Host smart-49fe447f-c580-4fef-924a-e9d764c253aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589934881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2589934881
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.376658709
Short name T539
Test name
Test status
Simulation time 39136156351 ps
CPU time 57.92 seconds
Started Aug 15 06:26:33 PM PDT 24
Finished Aug 15 06:27:31 PM PDT 24
Peak memory 200892 kb
Host smart-ad5035d6-4cf0-4c70-8d69-bb1a558d8eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376658709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.376658709
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2477570137
Short name T1155
Test name
Test status
Simulation time 23716171105 ps
CPU time 42.59 seconds
Started Aug 15 06:26:30 PM PDT 24
Finished Aug 15 06:27:13 PM PDT 24
Peak memory 200916 kb
Host smart-1f3a11ae-4f75-4755-a0d0-3886c6e27c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477570137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2477570137
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.4155333894
Short name T240
Test name
Test status
Simulation time 113875425399 ps
CPU time 156.31 seconds
Started Aug 15 06:26:32 PM PDT 24
Finished Aug 15 06:29:09 PM PDT 24
Peak memory 200692 kb
Host smart-91c10789-1c65-40e8-8232-91d7609ea4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155333894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.4155333894
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.4084830537
Short name T514
Test name
Test status
Simulation time 21236537314 ps
CPU time 6.73 seconds
Started Aug 15 06:26:32 PM PDT 24
Finished Aug 15 06:26:39 PM PDT 24
Peak memory 197980 kb
Host smart-4893b9c2-4e6a-4704-8628-04723c247292
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084830537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.4084830537
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.457459457
Short name T89
Test name
Test status
Simulation time 38319874844 ps
CPU time 237.87 seconds
Started Aug 15 06:26:39 PM PDT 24
Finished Aug 15 06:30:37 PM PDT 24
Peak memory 200960 kb
Host smart-f7ad9508-5466-4305-ae46-02e8a36890a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=457459457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.457459457
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.2550342393
Short name T997
Test name
Test status
Simulation time 1642492688 ps
CPU time 3.77 seconds
Started Aug 15 06:26:32 PM PDT 24
Finished Aug 15 06:26:36 PM PDT 24
Peak memory 199240 kb
Host smart-d5da1e2d-17b3-4dd9-8455-9bc8a3a4e6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550342393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2550342393
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.3820610379
Short name T949
Test name
Test status
Simulation time 94514350516 ps
CPU time 34.3 seconds
Started Aug 15 06:26:38 PM PDT 24
Finished Aug 15 06:27:12 PM PDT 24
Peak memory 201112 kb
Host smart-d5762eba-f7c8-4f87-ace9-8324213ddede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820610379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3820610379
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2549510650
Short name T260
Test name
Test status
Simulation time 24997515022 ps
CPU time 1307.94 seconds
Started Aug 15 06:26:31 PM PDT 24
Finished Aug 15 06:48:19 PM PDT 24
Peak memory 200932 kb
Host smart-3c8586b7-afe1-4afc-a5d9-71b83a5f42fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2549510650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2549510650
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2968342275
Short name T678
Test name
Test status
Simulation time 3910605622 ps
CPU time 31.85 seconds
Started Aug 15 06:26:34 PM PDT 24
Finished Aug 15 06:27:06 PM PDT 24
Peak memory 199052 kb
Host smart-d1f75ebc-94cc-41cf-a82b-c00f835a090e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2968342275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2968342275
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.4290338487
Short name T319
Test name
Test status
Simulation time 66212988621 ps
CPU time 57.47 seconds
Started Aug 15 06:26:33 PM PDT 24
Finished Aug 15 06:27:31 PM PDT 24
Peak memory 200844 kb
Host smart-07084279-b13a-40f0-8dc1-cffece427eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290338487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.4290338487
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.3785642508
Short name T1092
Test name
Test status
Simulation time 690614272 ps
CPU time 1.65 seconds
Started Aug 15 06:26:36 PM PDT 24
Finished Aug 15 06:26:38 PM PDT 24
Peak memory 196604 kb
Host smart-a72f9283-1225-40a9-81e6-b1f7b4ccc60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785642508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3785642508
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.315461657
Short name T1056
Test name
Test status
Simulation time 867564725 ps
CPU time 1.94 seconds
Started Aug 15 06:26:38 PM PDT 24
Finished Aug 15 06:26:40 PM PDT 24
Peak memory 200456 kb
Host smart-411fa4e3-8a3b-4363-a7e9-c73f3ec2b164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315461657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.315461657
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.1708137539
Short name T1081
Test name
Test status
Simulation time 507092820829 ps
CPU time 65.45 seconds
Started Aug 15 06:26:37 PM PDT 24
Finished Aug 15 06:27:43 PM PDT 24
Peak memory 200972 kb
Host smart-96413354-19a7-4665-ae49-686e1c103ded
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708137539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.1708137539
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.3282199412
Short name T996
Test name
Test status
Simulation time 7663194788 ps
CPU time 8.86 seconds
Started Aug 15 06:26:38 PM PDT 24
Finished Aug 15 06:26:47 PM PDT 24
Peak memory 200784 kb
Host smart-c8f49ef8-a9a7-4a9f-87de-e1b5ea778f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282199412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3282199412
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3376059772
Short name T314
Test name
Test status
Simulation time 10377594435 ps
CPU time 8.22 seconds
Started Aug 15 06:26:33 PM PDT 24
Finished Aug 15 06:26:41 PM PDT 24
Peak memory 200656 kb
Host smart-aef53cf9-d23c-438a-a7bc-9cacfec8fb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376059772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3376059772
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.1003827775
Short name T512
Test name
Test status
Simulation time 12406813339 ps
CPU time 22.91 seconds
Started Aug 15 06:30:20 PM PDT 24
Finished Aug 15 06:30:43 PM PDT 24
Peak memory 200884 kb
Host smart-34c0947b-4688-475c-8936-37e3e58665fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003827775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.1003827775
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.416173803
Short name T672
Test name
Test status
Simulation time 225590235756 ps
CPU time 159.88 seconds
Started Aug 15 06:30:20 PM PDT 24
Finished Aug 15 06:33:00 PM PDT 24
Peak memory 200884 kb
Host smart-5eb9990c-41d5-4fc5-84e1-1d392b910ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416173803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.416173803
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.1147901699
Short name T114
Test name
Test status
Simulation time 57158012137 ps
CPU time 26.12 seconds
Started Aug 15 06:30:18 PM PDT 24
Finished Aug 15 06:30:44 PM PDT 24
Peak memory 200852 kb
Host smart-8c6a7fea-5130-410e-81ff-11453f7d3cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147901699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1147901699
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.2050441492
Short name T1098
Test name
Test status
Simulation time 85176562950 ps
CPU time 223.45 seconds
Started Aug 15 06:30:19 PM PDT 24
Finished Aug 15 06:34:03 PM PDT 24
Peak memory 200948 kb
Host smart-83f95e90-5770-4ede-b8f0-d46bd0c01d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050441492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2050441492
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2848218614
Short name T334
Test name
Test status
Simulation time 15160178087 ps
CPU time 24.09 seconds
Started Aug 15 06:30:21 PM PDT 24
Finished Aug 15 06:30:45 PM PDT 24
Peak memory 200940 kb
Host smart-ec6a4be3-a6e0-45f4-bb21-91fa657068af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848218614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2848218614
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1628238806
Short name T1033
Test name
Test status
Simulation time 189800105352 ps
CPU time 52.4 seconds
Started Aug 15 06:30:28 PM PDT 24
Finished Aug 15 06:31:21 PM PDT 24
Peak memory 200840 kb
Host smart-d24a70bf-3cc9-45ae-9fbc-8fd6796b5cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628238806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1628238806
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.500292002
Short name T775
Test name
Test status
Simulation time 135818830426 ps
CPU time 97.98 seconds
Started Aug 15 06:30:27 PM PDT 24
Finished Aug 15 06:32:06 PM PDT 24
Peak memory 200896 kb
Host smart-ada4f1a7-ac7e-4e3d-b3fa-f15435796f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500292002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.500292002
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1572264807
Short name T187
Test name
Test status
Simulation time 103857292913 ps
CPU time 171.12 seconds
Started Aug 15 06:30:28 PM PDT 24
Finished Aug 15 06:33:19 PM PDT 24
Peak memory 200968 kb
Host smart-007b434b-be7d-4d50-a519-81c20e195bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572264807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1572264807
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.3656224942
Short name T49
Test name
Test status
Simulation time 48209208946 ps
CPU time 31.81 seconds
Started Aug 15 06:26:39 PM PDT 24
Finished Aug 15 06:27:11 PM PDT 24
Peak memory 200812 kb
Host smart-4a9ec109-6a47-4549-8da3-4dbcb207003e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656224942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3656224942
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.836128843
Short name T230
Test name
Test status
Simulation time 51884565452 ps
CPU time 39.41 seconds
Started Aug 15 06:26:38 PM PDT 24
Finished Aug 15 06:27:18 PM PDT 24
Peak memory 200912 kb
Host smart-b480de13-94fa-4c7f-8d0a-7afe3b593eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836128843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.836128843
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.80527306
Short name T816
Test name
Test status
Simulation time 29870892245 ps
CPU time 12.56 seconds
Started Aug 15 06:26:39 PM PDT 24
Finished Aug 15 06:26:51 PM PDT 24
Peak memory 200052 kb
Host smart-b59eca87-9710-45cc-8ea4-2086f8ad25b9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80527306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.80527306
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2939112624
Short name T1102
Test name
Test status
Simulation time 86540193266 ps
CPU time 443.9 seconds
Started Aug 15 06:26:48 PM PDT 24
Finished Aug 15 06:34:12 PM PDT 24
Peak memory 200912 kb
Host smart-baa44262-2bd6-4722-b7ff-201cad3435ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2939112624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2939112624
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.1065244754
Short name T377
Test name
Test status
Simulation time 5888873561 ps
CPU time 4.5 seconds
Started Aug 15 06:26:40 PM PDT 24
Finished Aug 15 06:26:45 PM PDT 24
Peak memory 199504 kb
Host smart-5123cb54-0544-40f5-ab10-aaf32bada3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065244754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.1065244754
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.1891031852
Short name T612
Test name
Test status
Simulation time 211783865911 ps
CPU time 61.21 seconds
Started Aug 15 06:26:39 PM PDT 24
Finished Aug 15 06:27:41 PM PDT 24
Peak memory 209280 kb
Host smart-72369f15-b175-40cd-ab01-49b5559cef56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891031852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1891031852
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.2544219808
Short name T522
Test name
Test status
Simulation time 10369780450 ps
CPU time 589.64 seconds
Started Aug 15 06:26:49 PM PDT 24
Finished Aug 15 06:36:38 PM PDT 24
Peak memory 200944 kb
Host smart-0141e98e-7627-4771-b50d-0b728edcbf36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2544219808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2544219808
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.1049919085
Short name T436
Test name
Test status
Simulation time 1595435443 ps
CPU time 2.67 seconds
Started Aug 15 06:26:40 PM PDT 24
Finished Aug 15 06:26:43 PM PDT 24
Peak memory 200160 kb
Host smart-7c3006d8-98c4-4235-b0ca-88b8a2261b10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1049919085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.1049919085
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1326249640
Short name T172
Test name
Test status
Simulation time 208130510443 ps
CPU time 104.71 seconds
Started Aug 15 06:26:40 PM PDT 24
Finished Aug 15 06:28:25 PM PDT 24
Peak memory 200868 kb
Host smart-f5791aca-91ea-45c4-8550-a727184bad5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326249640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1326249640
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.4134369570
Short name T307
Test name
Test status
Simulation time 42943256254 ps
CPU time 15.56 seconds
Started Aug 15 06:26:41 PM PDT 24
Finished Aug 15 06:26:57 PM PDT 24
Peak memory 197020 kb
Host smart-fb0270ec-672b-4952-ad1a-ad36900ee253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134369570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.4134369570
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1038611047
Short name T774
Test name
Test status
Simulation time 456060521 ps
CPU time 2.03 seconds
Started Aug 15 06:26:38 PM PDT 24
Finished Aug 15 06:26:40 PM PDT 24
Peak memory 200716 kb
Host smart-8d1b7dcd-32b4-42ae-8b6e-f90a4a236e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038611047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1038611047
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.1847373028
Short name T792
Test name
Test status
Simulation time 113429239687 ps
CPU time 164.68 seconds
Started Aug 15 06:26:49 PM PDT 24
Finished Aug 15 06:29:34 PM PDT 24
Peak memory 209320 kb
Host smart-d2a51998-2bc6-47a4-b398-a77e9261d494
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847373028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1847373028
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.670571739
Short name T1061
Test name
Test status
Simulation time 19079028210 ps
CPU time 130.89 seconds
Started Aug 15 06:26:48 PM PDT 24
Finished Aug 15 06:28:59 PM PDT 24
Peak memory 217592 kb
Host smart-4b277943-c224-445a-930f-0d0b76652e47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670571739 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.670571739
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.2050247059
Short name T491
Test name
Test status
Simulation time 6722514984 ps
CPU time 28.71 seconds
Started Aug 15 06:26:41 PM PDT 24
Finished Aug 15 06:27:10 PM PDT 24
Peak memory 200488 kb
Host smart-0c941393-0590-479d-a86b-d12f34265db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050247059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2050247059
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2407299973
Short name T33
Test name
Test status
Simulation time 75945128210 ps
CPU time 41.08 seconds
Started Aug 15 06:26:41 PM PDT 24
Finished Aug 15 06:27:22 PM PDT 24
Peak memory 200960 kb
Host smart-322767a1-a611-4671-abb0-9c3ba4b74382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407299973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2407299973
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.311821280
Short name T224
Test name
Test status
Simulation time 120738959474 ps
CPU time 26.02 seconds
Started Aug 15 06:30:26 PM PDT 24
Finished Aug 15 06:30:52 PM PDT 24
Peak memory 200780 kb
Host smart-a201ee7a-12c3-4b22-9534-8b295c68f146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311821280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.311821280
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3026674530
Short name T282
Test name
Test status
Simulation time 198805746453 ps
CPU time 310.82 seconds
Started Aug 15 06:30:24 PM PDT 24
Finished Aug 15 06:35:35 PM PDT 24
Peak memory 200928 kb
Host smart-6ec98054-86f7-4d6d-8ba1-89aeeda9b313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026674530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3026674530
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1237154550
Short name T216
Test name
Test status
Simulation time 107930395175 ps
CPU time 62.88 seconds
Started Aug 15 06:30:31 PM PDT 24
Finished Aug 15 06:31:34 PM PDT 24
Peak memory 200836 kb
Host smart-c42806ab-c1a5-4701-8603-7b73979447e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237154550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1237154550
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3401014235
Short name T339
Test name
Test status
Simulation time 34109890560 ps
CPU time 15.04 seconds
Started Aug 15 06:30:26 PM PDT 24
Finished Aug 15 06:30:41 PM PDT 24
Peak memory 200856 kb
Host smart-2e493946-72c0-422b-8fd8-97c9682d08d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401014235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3401014235
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.1879249442
Short name T208
Test name
Test status
Simulation time 81730612660 ps
CPU time 37.69 seconds
Started Aug 15 06:30:27 PM PDT 24
Finished Aug 15 06:31:05 PM PDT 24
Peak memory 200964 kb
Host smart-1203f8f4-b378-4703-93e8-4cb2634d843c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879249442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1879249442
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.3723517644
Short name T1112
Test name
Test status
Simulation time 116873450285 ps
CPU time 171.16 seconds
Started Aug 15 06:30:31 PM PDT 24
Finished Aug 15 06:33:23 PM PDT 24
Peak memory 200880 kb
Host smart-3964bb4d-3b98-45a5-824a-e043f2ef0a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723517644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3723517644
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1239824893
Short name T826
Test name
Test status
Simulation time 120804015571 ps
CPU time 178.05 seconds
Started Aug 15 06:30:27 PM PDT 24
Finished Aug 15 06:33:25 PM PDT 24
Peak memory 200920 kb
Host smart-0ff558a3-de73-4f85-8ed9-225aecf84817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239824893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1239824893
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1792511870
Short name T780
Test name
Test status
Simulation time 23762519 ps
CPU time 0.56 seconds
Started Aug 15 06:26:47 PM PDT 24
Finished Aug 15 06:26:48 PM PDT 24
Peak memory 196560 kb
Host smart-8fa4c45c-fe9a-462d-b9e1-348a7f28fa47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792511870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1792511870
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.549792836
Short name T433
Test name
Test status
Simulation time 144030745547 ps
CPU time 64.07 seconds
Started Aug 15 06:26:52 PM PDT 24
Finished Aug 15 06:27:57 PM PDT 24
Peak memory 200940 kb
Host smart-882c08e5-d10f-480c-9607-e2f3af8553ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549792836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.549792836
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3106356238
Short name T1100
Test name
Test status
Simulation time 74735006560 ps
CPU time 102.14 seconds
Started Aug 15 06:26:49 PM PDT 24
Finished Aug 15 06:28:32 PM PDT 24
Peak memory 200912 kb
Host smart-fc090aed-75d9-476d-a55d-de45b94550c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106356238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3106356238
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2921068795
Short name T381
Test name
Test status
Simulation time 107764094998 ps
CPU time 27.81 seconds
Started Aug 15 06:26:47 PM PDT 24
Finished Aug 15 06:27:15 PM PDT 24
Peak memory 200756 kb
Host smart-5e67d1a0-a3e4-46ad-a769-c689d11533cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921068795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2921068795
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.545810825
Short name T945
Test name
Test status
Simulation time 14361368772 ps
CPU time 8.45 seconds
Started Aug 15 06:26:48 PM PDT 24
Finished Aug 15 06:26:57 PM PDT 24
Peak memory 198792 kb
Host smart-cdc43b68-f44b-4359-999c-bf5cae4b1c70
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545810825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.545810825
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2888522597
Short name T12
Test name
Test status
Simulation time 97061731775 ps
CPU time 695.8 seconds
Started Aug 15 06:26:48 PM PDT 24
Finished Aug 15 06:38:24 PM PDT 24
Peak memory 200876 kb
Host smart-e8b76bee-f72c-48b2-8578-e2e4480259a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2888522597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2888522597
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2954681684
Short name T331
Test name
Test status
Simulation time 5628209148 ps
CPU time 5.16 seconds
Started Aug 15 06:26:46 PM PDT 24
Finished Aug 15 06:26:51 PM PDT 24
Peak memory 199444 kb
Host smart-45069666-6880-4cd9-ad7a-1803800cb6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954681684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2954681684
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.890191577
Short name T926
Test name
Test status
Simulation time 28849295789 ps
CPU time 13.13 seconds
Started Aug 15 06:26:47 PM PDT 24
Finished Aug 15 06:27:00 PM PDT 24
Peak memory 197664 kb
Host smart-e86e0d67-12a2-4a8e-8bd4-f15258079042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890191577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.890191577
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.52683675
Short name T41
Test name
Test status
Simulation time 12409532530 ps
CPU time 174.13 seconds
Started Aug 15 06:26:49 PM PDT 24
Finished Aug 15 06:29:43 PM PDT 24
Peak memory 200956 kb
Host smart-e5f63da5-cd3d-4140-bae2-444e276bfdb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=52683675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.52683675
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1751843966
Short name T563
Test name
Test status
Simulation time 89649562813 ps
CPU time 69.62 seconds
Started Aug 15 06:26:48 PM PDT 24
Finished Aug 15 06:27:58 PM PDT 24
Peak memory 200908 kb
Host smart-60b2430f-4e12-43fc-b9cf-cf6c3af816e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751843966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1751843966
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1209901659
Short name T310
Test name
Test status
Simulation time 617632241 ps
CPU time 1.09 seconds
Started Aug 15 06:26:47 PM PDT 24
Finished Aug 15 06:26:48 PM PDT 24
Peak memory 196580 kb
Host smart-e6a625aa-baf5-4874-9b7c-a15a454819d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209901659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1209901659
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.3218288253
Short name T583
Test name
Test status
Simulation time 1004082047 ps
CPU time 2.4 seconds
Started Aug 15 06:26:46 PM PDT 24
Finished Aug 15 06:26:49 PM PDT 24
Peak memory 200856 kb
Host smart-9e0733bb-a81d-4f13-a4b9-823da13b40ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218288253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3218288253
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.3207684038
Short name T484
Test name
Test status
Simulation time 214239770771 ps
CPU time 1216.01 seconds
Started Aug 15 06:26:48 PM PDT 24
Finished Aug 15 06:47:04 PM PDT 24
Peak memory 200888 kb
Host smart-a9d3b27c-a1e5-4303-8027-f98d0ec509f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207684038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3207684038
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.2213863235
Short name T501
Test name
Test status
Simulation time 6578942821 ps
CPU time 15.09 seconds
Started Aug 15 06:26:49 PM PDT 24
Finished Aug 15 06:27:05 PM PDT 24
Peak memory 200892 kb
Host smart-8cbc215b-bf87-4758-ac8a-3813eb02e345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213863235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2213863235
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.2361792404
Short name T967
Test name
Test status
Simulation time 45493342564 ps
CPU time 30.85 seconds
Started Aug 15 06:26:47 PM PDT 24
Finished Aug 15 06:27:18 PM PDT 24
Peak memory 200908 kb
Host smart-0d6bb4fc-1ece-4e18-9757-bd8b6d4536b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361792404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2361792404
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.3985774271
Short name T870
Test name
Test status
Simulation time 8400263624 ps
CPU time 15.86 seconds
Started Aug 15 06:30:26 PM PDT 24
Finished Aug 15 06:30:42 PM PDT 24
Peak memory 200840 kb
Host smart-80611a72-c096-4784-8e1e-338dd68fdede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985774271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3985774271
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.4242065582
Short name T660
Test name
Test status
Simulation time 52445279125 ps
CPU time 121.54 seconds
Started Aug 15 06:30:27 PM PDT 24
Finished Aug 15 06:32:29 PM PDT 24
Peak memory 200832 kb
Host smart-0d9c232b-cdbd-4773-889c-5dc43553bfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242065582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.4242065582
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.109176418
Short name T1145
Test name
Test status
Simulation time 46642441267 ps
CPU time 21.17 seconds
Started Aug 15 06:30:28 PM PDT 24
Finished Aug 15 06:30:49 PM PDT 24
Peak memory 200964 kb
Host smart-bcbb0500-eba5-422d-ab7e-85916c3a91a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109176418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.109176418
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2128912699
Short name T837
Test name
Test status
Simulation time 33258607793 ps
CPU time 16.94 seconds
Started Aug 15 06:30:27 PM PDT 24
Finished Aug 15 06:30:44 PM PDT 24
Peak memory 200948 kb
Host smart-e3f1921b-5906-425a-ae81-b4a995088b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128912699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2128912699
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3992359488
Short name T682
Test name
Test status
Simulation time 148629146602 ps
CPU time 94.19 seconds
Started Aug 15 06:30:27 PM PDT 24
Finished Aug 15 06:32:01 PM PDT 24
Peak memory 200964 kb
Host smart-0f1c11d5-909c-46d4-a98a-b6a8c023c363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992359488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3992359488
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3955478209
Short name T1005
Test name
Test status
Simulation time 47765670209 ps
CPU time 20.07 seconds
Started Aug 15 06:30:27 PM PDT 24
Finished Aug 15 06:30:47 PM PDT 24
Peak memory 200872 kb
Host smart-fc9af912-ecff-4633-b7f1-5be8d38c0e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955478209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3955478209
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2559803308
Short name T343
Test name
Test status
Simulation time 195908191800 ps
CPU time 110.61 seconds
Started Aug 15 06:30:26 PM PDT 24
Finished Aug 15 06:32:17 PM PDT 24
Peak memory 200820 kb
Host smart-d4de381c-7ba6-4497-b405-59d09d588f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559803308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2559803308
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.2819327557
Short name T1078
Test name
Test status
Simulation time 63019142006 ps
CPU time 29.34 seconds
Started Aug 15 06:30:26 PM PDT 24
Finished Aug 15 06:30:55 PM PDT 24
Peak memory 200944 kb
Host smart-9626fde6-2635-4aa4-bfc9-bf033237c0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819327557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2819327557
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.577021696
Short name T591
Test name
Test status
Simulation time 93891167536 ps
CPU time 42.57 seconds
Started Aug 15 06:30:35 PM PDT 24
Finished Aug 15 06:31:18 PM PDT 24
Peak memory 200956 kb
Host smart-b943b05d-1af4-4821-afdf-61db13ce2926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577021696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.577021696
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.3624132937
Short name T874
Test name
Test status
Simulation time 50662081 ps
CPU time 0.59 seconds
Started Aug 15 06:26:57 PM PDT 24
Finished Aug 15 06:26:58 PM PDT 24
Peak memory 196232 kb
Host smart-5d20f94a-6e86-4392-ae28-0668eb413abc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624132937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.3624132937
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.231375658
Short name T771
Test name
Test status
Simulation time 55536461238 ps
CPU time 22.07 seconds
Started Aug 15 06:26:48 PM PDT 24
Finished Aug 15 06:27:10 PM PDT 24
Peak memory 200920 kb
Host smart-173ff086-f056-496c-b26a-f3fbfe9b2f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231375658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.231375658
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.3017911247
Short name T256
Test name
Test status
Simulation time 68374835425 ps
CPU time 55.97 seconds
Started Aug 15 06:26:46 PM PDT 24
Finished Aug 15 06:27:42 PM PDT 24
Peak memory 200896 kb
Host smart-84aa8c28-5386-4cfb-bb01-39f576519097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017911247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3017911247
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.640309038
Short name T1115
Test name
Test status
Simulation time 21576527645 ps
CPU time 28.21 seconds
Started Aug 15 06:26:49 PM PDT 24
Finished Aug 15 06:27:17 PM PDT 24
Peak memory 200884 kb
Host smart-639c98b4-e4bf-484a-9bbe-71e42b4ab79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640309038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.640309038
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3177223647
Short name T480
Test name
Test status
Simulation time 212145130164 ps
CPU time 90.82 seconds
Started Aug 15 06:26:48 PM PDT 24
Finished Aug 15 06:28:19 PM PDT 24
Peak memory 198528 kb
Host smart-9a9d158b-fafb-439a-99dd-791bc024994f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177223647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3177223647
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.3783063861
Short name T421
Test name
Test status
Simulation time 47839692464 ps
CPU time 131.44 seconds
Started Aug 15 06:26:55 PM PDT 24
Finished Aug 15 06:29:06 PM PDT 24
Peak memory 200920 kb
Host smart-8de5d8f3-347a-4397-9f8f-c987e25f28d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3783063861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3783063861
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.3735836994
Short name T330
Test name
Test status
Simulation time 5130667255 ps
CPU time 6.71 seconds
Started Aug 15 06:26:55 PM PDT 24
Finished Aug 15 06:27:02 PM PDT 24
Peak memory 200792 kb
Host smart-340491f2-4dae-41ef-aef9-dfd4ea3b670a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735836994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3735836994
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.137008412
Short name T749
Test name
Test status
Simulation time 82236070118 ps
CPU time 32.9 seconds
Started Aug 15 06:26:46 PM PDT 24
Finished Aug 15 06:27:20 PM PDT 24
Peak memory 201132 kb
Host smart-4c5e38e3-332a-4d82-932e-59e47023fa2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137008412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.137008412
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.3585620336
Short name T336
Test name
Test status
Simulation time 4915161176 ps
CPU time 96.76 seconds
Started Aug 15 06:26:55 PM PDT 24
Finished Aug 15 06:28:32 PM PDT 24
Peak memory 200868 kb
Host smart-e55f8fa3-426a-4643-a1c1-72c1d63bd132
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3585620336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3585620336
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.594804140
Short name T1151
Test name
Test status
Simulation time 5156449296 ps
CPU time 10.73 seconds
Started Aug 15 06:26:47 PM PDT 24
Finished Aug 15 06:26:58 PM PDT 24
Peak memory 199144 kb
Host smart-c2de7cbe-9315-4a73-9570-49451b325a12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=594804140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.594804140
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.145542948
Short name T662
Test name
Test status
Simulation time 48113190932 ps
CPU time 27.92 seconds
Started Aug 15 06:26:55 PM PDT 24
Finished Aug 15 06:27:23 PM PDT 24
Peak memory 200944 kb
Host smart-713dc406-8ca0-4a17-8939-4b63adcbe1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145542948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.145542948
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3128116747
Short name T287
Test name
Test status
Simulation time 3465754944 ps
CPU time 6.02 seconds
Started Aug 15 06:26:48 PM PDT 24
Finished Aug 15 06:26:54 PM PDT 24
Peak memory 197008 kb
Host smart-56710300-24a9-462d-aa46-9caec39ad76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128116747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3128116747
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.3974799878
Short name T989
Test name
Test status
Simulation time 5892322032 ps
CPU time 20.16 seconds
Started Aug 15 06:26:47 PM PDT 24
Finished Aug 15 06:27:07 PM PDT 24
Peak memory 200832 kb
Host smart-9bdaf2f7-0f78-41fe-854a-4d9578f9a489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974799878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3974799878
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.57648218
Short name T608
Test name
Test status
Simulation time 2466232651 ps
CPU time 30.7 seconds
Started Aug 15 06:26:57 PM PDT 24
Finished Aug 15 06:27:28 PM PDT 24
Peak memory 217404 kb
Host smart-5c3ddf74-4626-4c6f-afec-b2ea786a164e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57648218 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.57648218
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1617515137
Short name T464
Test name
Test status
Simulation time 6195800349 ps
CPU time 12.29 seconds
Started Aug 15 06:26:58 PM PDT 24
Finished Aug 15 06:27:10 PM PDT 24
Peak memory 200776 kb
Host smart-b8d1e157-c656-43c4-9e1f-f42a277fcd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617515137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1617515137
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.1883163241
Short name T479
Test name
Test status
Simulation time 15922028158 ps
CPU time 6.37 seconds
Started Aug 15 06:26:49 PM PDT 24
Finished Aug 15 06:26:55 PM PDT 24
Peak memory 198252 kb
Host smart-a5b42f5d-689e-4be2-8909-64955c0d77a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883163241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1883163241
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.815978927
Short name T219
Test name
Test status
Simulation time 175675297008 ps
CPU time 65.39 seconds
Started Aug 15 06:30:32 PM PDT 24
Finished Aug 15 06:31:38 PM PDT 24
Peak memory 200968 kb
Host smart-3a2e5a33-0bcb-4df0-8ea6-f08f63372b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815978927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.815978927
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.2156451519
Short name T102
Test name
Test status
Simulation time 10962688064 ps
CPU time 17.3 seconds
Started Aug 15 06:30:33 PM PDT 24
Finished Aug 15 06:30:50 PM PDT 24
Peak memory 200892 kb
Host smart-99a6ed0b-904e-4e27-9349-65891e96de5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156451519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2156451519
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.4097782399
Short name T1003
Test name
Test status
Simulation time 18742836001 ps
CPU time 14.69 seconds
Started Aug 15 06:30:41 PM PDT 24
Finished Aug 15 06:30:56 PM PDT 24
Peak memory 200432 kb
Host smart-0f7b2959-837b-4bbf-b3fb-5d247a196d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097782399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.4097782399
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.2748451699
Short name T7
Test name
Test status
Simulation time 20592908819 ps
CPU time 30 seconds
Started Aug 15 06:30:32 PM PDT 24
Finished Aug 15 06:31:02 PM PDT 24
Peak memory 200936 kb
Host smart-d97dd617-d9a7-4865-bddd-bf41d333b12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748451699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2748451699
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3609478778
Short name T800
Test name
Test status
Simulation time 107436814538 ps
CPU time 21.38 seconds
Started Aug 15 06:30:34 PM PDT 24
Finished Aug 15 06:30:56 PM PDT 24
Peak memory 200892 kb
Host smart-85414e3e-aecc-434f-ad8c-f39d9fe24388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609478778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3609478778
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2023529691
Short name T759
Test name
Test status
Simulation time 96704055423 ps
CPU time 16.65 seconds
Started Aug 15 06:30:35 PM PDT 24
Finished Aug 15 06:30:52 PM PDT 24
Peak memory 200808 kb
Host smart-2f825fd4-9704-47e8-8ee4-48a4ba2b012d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023529691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2023529691
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3300642992
Short name T758
Test name
Test status
Simulation time 138789474454 ps
CPU time 65.13 seconds
Started Aug 15 06:30:34 PM PDT 24
Finished Aug 15 06:31:39 PM PDT 24
Peak memory 200880 kb
Host smart-56c0bb40-262c-4de4-8047-730f0c7cc1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300642992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3300642992
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1718592082
Short name T617
Test name
Test status
Simulation time 189676092466 ps
CPU time 93.73 seconds
Started Aug 15 06:30:35 PM PDT 24
Finished Aug 15 06:32:09 PM PDT 24
Peak memory 200908 kb
Host smart-797c2a87-5b4c-4bb8-963c-55ed8b81417b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718592082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1718592082
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.2099843302
Short name T506
Test name
Test status
Simulation time 65053622173 ps
CPU time 25.82 seconds
Started Aug 15 06:30:38 PM PDT 24
Finished Aug 15 06:31:04 PM PDT 24
Peak memory 200828 kb
Host smart-13e953bc-6ebb-4d7b-a1f2-9ca3411d8200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099843302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2099843302
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1898198664
Short name T634
Test name
Test status
Simulation time 22601129 ps
CPU time 0.55 seconds
Started Aug 15 06:25:04 PM PDT 24
Finished Aug 15 06:25:04 PM PDT 24
Peak memory 195932 kb
Host smart-b09556a1-35a8-413d-bd12-18e110488e20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898198664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1898198664
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1008032406
Short name T714
Test name
Test status
Simulation time 38816809624 ps
CPU time 67.09 seconds
Started Aug 15 06:24:55 PM PDT 24
Finished Aug 15 06:26:02 PM PDT 24
Peak memory 200872 kb
Host smart-839a5016-1dfc-4952-9121-de1d70e670d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008032406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1008032406
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.924494177
Short name T315
Test name
Test status
Simulation time 15035121377 ps
CPU time 51.64 seconds
Started Aug 15 06:24:55 PM PDT 24
Finished Aug 15 06:25:47 PM PDT 24
Peak memory 200836 kb
Host smart-32b0b6a1-c37d-41d8-b304-46359b21db4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924494177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.924494177
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2289574593
Short name T188
Test name
Test status
Simulation time 30964641138 ps
CPU time 47.74 seconds
Started Aug 15 06:25:06 PM PDT 24
Finished Aug 15 06:25:53 PM PDT 24
Peak memory 200752 kb
Host smart-33fcfb44-1a26-4316-b436-d1434e085e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289574593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2289574593
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2728233332
Short name T624
Test name
Test status
Simulation time 221144116287 ps
CPU time 29.79 seconds
Started Aug 15 06:25:06 PM PDT 24
Finished Aug 15 06:25:36 PM PDT 24
Peak memory 198452 kb
Host smart-7a6b771d-00f6-42f8-b58f-7cd614b11db9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728233332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2728233332
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.3599356226
Short name T393
Test name
Test status
Simulation time 58806348863 ps
CPU time 311.66 seconds
Started Aug 15 06:25:03 PM PDT 24
Finished Aug 15 06:30:15 PM PDT 24
Peak memory 200952 kb
Host smart-b177ee47-b613-4fd6-a4df-a65a30654849
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3599356226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3599356226
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1524017450
Short name T631
Test name
Test status
Simulation time 6624787277 ps
CPU time 3.97 seconds
Started Aug 15 06:25:05 PM PDT 24
Finished Aug 15 06:25:09 PM PDT 24
Peak memory 200220 kb
Host smart-ecf29d7b-99c2-4588-915b-2a1fa2fd8918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524017450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1524017450
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.1619080370
Short name T1121
Test name
Test status
Simulation time 76550710322 ps
CPU time 147.81 seconds
Started Aug 15 06:25:03 PM PDT 24
Finished Aug 15 06:27:31 PM PDT 24
Peak memory 209288 kb
Host smart-b71b5f3a-cab4-4e0b-9126-55a728a76886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619080370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1619080370
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.2075653247
Short name T1109
Test name
Test status
Simulation time 18217020706 ps
CPU time 348.46 seconds
Started Aug 15 06:25:03 PM PDT 24
Finished Aug 15 06:30:51 PM PDT 24
Peak memory 199360 kb
Host smart-ef4a1f12-8514-4f97-8b1d-2baf49adf615
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2075653247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2075653247
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.1116917791
Short name T651
Test name
Test status
Simulation time 1598591556 ps
CPU time 2.65 seconds
Started Aug 15 06:25:03 PM PDT 24
Finished Aug 15 06:25:06 PM PDT 24
Peak memory 199020 kb
Host smart-e3228668-7890-47a2-a9e5-1a03bd78d7be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1116917791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1116917791
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3672499403
Short name T1020
Test name
Test status
Simulation time 35477901339 ps
CPU time 68.14 seconds
Started Aug 15 06:25:03 PM PDT 24
Finished Aug 15 06:26:11 PM PDT 24
Peak memory 200920 kb
Host smart-ee757498-cd71-49f5-9350-920024054c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672499403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3672499403
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.875158515
Short name T300
Test name
Test status
Simulation time 37104484222 ps
CPU time 15.15 seconds
Started Aug 15 06:25:03 PM PDT 24
Finished Aug 15 06:25:18 PM PDT 24
Peak memory 197380 kb
Host smart-9df6d199-bfbf-4029-8395-e5d4f08d2c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875158515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.875158515
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2689469412
Short name T32
Test name
Test status
Simulation time 276169513 ps
CPU time 0.83 seconds
Started Aug 15 06:25:06 PM PDT 24
Finished Aug 15 06:25:07 PM PDT 24
Peak memory 218916 kb
Host smart-9be66049-a511-4da1-9624-23b0130368c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689469412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2689469412
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.133146196
Short name T902
Test name
Test status
Simulation time 6284972911 ps
CPU time 30.26 seconds
Started Aug 15 06:24:56 PM PDT 24
Finished Aug 15 06:25:26 PM PDT 24
Peak memory 200908 kb
Host smart-925452a3-dadd-4e5d-b02b-e2cce0f0e908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133146196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.133146196
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.1932136258
Short name T588
Test name
Test status
Simulation time 659560174362 ps
CPU time 566.72 seconds
Started Aug 15 06:25:03 PM PDT 24
Finished Aug 15 06:34:30 PM PDT 24
Peak memory 200900 kb
Host smart-060b132a-25bd-4437-adab-dac8b452b721
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932136258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1932136258
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.650606340
Short name T99
Test name
Test status
Simulation time 2800158289 ps
CPU time 22.08 seconds
Started Aug 15 06:25:06 PM PDT 24
Finished Aug 15 06:25:28 PM PDT 24
Peak memory 217332 kb
Host smart-1ebb7816-7453-4c35-8dd7-5edcdd171019
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650606340 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.650606340
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3153074097
Short name T914
Test name
Test status
Simulation time 987160978 ps
CPU time 1.17 seconds
Started Aug 15 06:25:04 PM PDT 24
Finished Aug 15 06:25:06 PM PDT 24
Peak memory 197676 kb
Host smart-47e04a36-a8b0-48aa-b524-bf23f91bbefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153074097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3153074097
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3318331771
Short name T956
Test name
Test status
Simulation time 32960927000 ps
CPU time 101.95 seconds
Started Aug 15 06:24:55 PM PDT 24
Finished Aug 15 06:26:37 PM PDT 24
Peak memory 200944 kb
Host smart-428a8123-754f-47ef-9eb5-e9541250756a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318331771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3318331771
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.3422646287
Short name T644
Test name
Test status
Simulation time 12848074 ps
CPU time 0.61 seconds
Started Aug 15 06:27:02 PM PDT 24
Finished Aug 15 06:27:02 PM PDT 24
Peak memory 196260 kb
Host smart-5d1b4f12-ea25-4ae2-a1e7-637bb42dfd5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422646287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3422646287
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1496442275
Short name T451
Test name
Test status
Simulation time 17033733638 ps
CPU time 24.82 seconds
Started Aug 15 06:26:57 PM PDT 24
Finished Aug 15 06:27:22 PM PDT 24
Peak memory 200884 kb
Host smart-8512b981-e576-410d-bac5-56766f6ed0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496442275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1496442275
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3189592346
Short name T271
Test name
Test status
Simulation time 151325947807 ps
CPU time 239.41 seconds
Started Aug 15 06:26:57 PM PDT 24
Finished Aug 15 06:30:57 PM PDT 24
Peak memory 200980 kb
Host smart-84e0106c-c131-47cf-80e3-2f9fa1f94c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189592346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3189592346
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.639883830
Short name T1125
Test name
Test status
Simulation time 93587053818 ps
CPU time 42.31 seconds
Started Aug 15 06:26:56 PM PDT 24
Finished Aug 15 06:27:38 PM PDT 24
Peak memory 200960 kb
Host smart-af427fd1-67d4-4126-9271-bccf6a0cb555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639883830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.639883830
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.2695036956
Short name T806
Test name
Test status
Simulation time 34967778830 ps
CPU time 57 seconds
Started Aug 15 06:26:53 PM PDT 24
Finished Aug 15 06:27:50 PM PDT 24
Peak memory 200440 kb
Host smart-2589e4c9-869f-4efa-be0c-1dde42007fa3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695036956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2695036956
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2345070605
Short name T676
Test name
Test status
Simulation time 244538493698 ps
CPU time 217.86 seconds
Started Aug 15 06:26:56 PM PDT 24
Finished Aug 15 06:30:34 PM PDT 24
Peak memory 199336 kb
Host smart-3e234262-eec6-42c4-a3c5-67615cb8e5ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2345070605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2345070605
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2673603849
Short name T968
Test name
Test status
Simulation time 2920741032 ps
CPU time 2.04 seconds
Started Aug 15 06:26:58 PM PDT 24
Finished Aug 15 06:27:00 PM PDT 24
Peak memory 199688 kb
Host smart-db958028-a662-4526-baa0-26ab95876bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673603849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2673603849
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.1606453531
Short name T309
Test name
Test status
Simulation time 44553028708 ps
CPU time 76.1 seconds
Started Aug 15 06:26:54 PM PDT 24
Finished Aug 15 06:28:10 PM PDT 24
Peak memory 201080 kb
Host smart-9e4e9b1f-1cd0-463e-99a2-8dc0fb0fb67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606453531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.1606453531
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.3233128790
Short name T394
Test name
Test status
Simulation time 10880223488 ps
CPU time 144.18 seconds
Started Aug 15 06:26:56 PM PDT 24
Finished Aug 15 06:29:20 PM PDT 24
Peak memory 200924 kb
Host smart-507b988f-fc7e-4bfe-83b5-060cd9c32c9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3233128790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3233128790
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1335395967
Short name T524
Test name
Test status
Simulation time 5257905479 ps
CPU time 43.5 seconds
Started Aug 15 06:26:58 PM PDT 24
Finished Aug 15 06:27:41 PM PDT 24
Peak memory 200348 kb
Host smart-ee792d7d-4e39-4cd9-bad7-c38ef3485be0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1335395967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1335395967
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.2130541930
Short name T929
Test name
Test status
Simulation time 169833998731 ps
CPU time 167.88 seconds
Started Aug 15 06:26:54 PM PDT 24
Finished Aug 15 06:29:42 PM PDT 24
Peak memory 200932 kb
Host smart-a3e37a35-9cf1-4050-bb41-a108d3ecfd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130541930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2130541930
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.274549964
Short name T305
Test name
Test status
Simulation time 4252069745 ps
CPU time 2.39 seconds
Started Aug 15 06:26:57 PM PDT 24
Finished Aug 15 06:26:59 PM PDT 24
Peak memory 197808 kb
Host smart-457a7c08-504a-4a26-9b59-7530557a3872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274549964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.274549964
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.2612882727
Short name T1180
Test name
Test status
Simulation time 468563865 ps
CPU time 1.63 seconds
Started Aug 15 06:26:54 PM PDT 24
Finished Aug 15 06:26:56 PM PDT 24
Peak memory 200184 kb
Host smart-4ec02dbb-d79c-41e6-93f9-4c5a94f9c0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612882727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2612882727
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.495337848
Short name T908
Test name
Test status
Simulation time 5455009152 ps
CPU time 66.25 seconds
Started Aug 15 06:27:13 PM PDT 24
Finished Aug 15 06:28:19 PM PDT 24
Peak memory 217584 kb
Host smart-48f1394d-2674-4baf-a4ec-6bb7a49f3412
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495337848 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.495337848
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.3304313639
Short name T584
Test name
Test status
Simulation time 1512595392 ps
CPU time 1.41 seconds
Started Aug 15 06:26:54 PM PDT 24
Finished Aug 15 06:26:55 PM PDT 24
Peak memory 198888 kb
Host smart-d030a7e4-be22-4d63-8555-72652975e2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304313639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3304313639
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2594139141
Short name T257
Test name
Test status
Simulation time 154855190044 ps
CPU time 88.89 seconds
Started Aug 15 06:26:57 PM PDT 24
Finished Aug 15 06:28:26 PM PDT 24
Peak memory 200864 kb
Host smart-5d4975ff-76e0-4471-8b35-b66d8fe53e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594139141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2594139141
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1205684148
Short name T174
Test name
Test status
Simulation time 73586031688 ps
CPU time 147.63 seconds
Started Aug 15 06:30:38 PM PDT 24
Finished Aug 15 06:33:06 PM PDT 24
Peak memory 200888 kb
Host smart-aad49ce6-54d1-4dde-bd50-65729d1c8ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205684148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1205684148
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.83168632
Short name T547
Test name
Test status
Simulation time 90368082512 ps
CPU time 161.08 seconds
Started Aug 15 06:30:34 PM PDT 24
Finished Aug 15 06:33:15 PM PDT 24
Peak memory 200956 kb
Host smart-c266dc5e-0b81-474a-9814-e28cc47723d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83168632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.83168632
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1423001597
Short name T342
Test name
Test status
Simulation time 7200580374 ps
CPU time 12.06 seconds
Started Aug 15 06:30:34 PM PDT 24
Finished Aug 15 06:30:46 PM PDT 24
Peak memory 200960 kb
Host smart-cbef00cd-8f02-47e1-bd2a-bfb2c634e694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423001597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1423001597
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.4011456065
Short name T173
Test name
Test status
Simulation time 23335559100 ps
CPU time 43.76 seconds
Started Aug 15 06:30:41 PM PDT 24
Finished Aug 15 06:31:25 PM PDT 24
Peak memory 200952 kb
Host smart-52a5e51d-7fc9-44f8-a966-3bc0ccbccc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011456065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.4011456065
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1479939028
Short name T1111
Test name
Test status
Simulation time 13588426676 ps
CPU time 31.69 seconds
Started Aug 15 06:30:43 PM PDT 24
Finished Aug 15 06:31:15 PM PDT 24
Peak memory 200896 kb
Host smart-c4d4fb62-e781-4d58-bae8-5650825f03fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479939028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1479939028
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.637624024
Short name T220
Test name
Test status
Simulation time 25134231499 ps
CPU time 18.91 seconds
Started Aug 15 06:30:42 PM PDT 24
Finished Aug 15 06:31:02 PM PDT 24
Peak memory 200948 kb
Host smart-cf539314-5fef-4562-93ba-b617dcf853dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637624024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.637624024
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.149783259
Short name T650
Test name
Test status
Simulation time 160061518973 ps
CPU time 31.25 seconds
Started Aug 15 06:30:40 PM PDT 24
Finished Aug 15 06:31:11 PM PDT 24
Peak memory 200916 kb
Host smart-e2e6f864-8009-4476-be87-79812d09b230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149783259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.149783259
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.4123397945
Short name T936
Test name
Test status
Simulation time 89494399035 ps
CPU time 117.98 seconds
Started Aug 15 06:30:42 PM PDT 24
Finished Aug 15 06:32:41 PM PDT 24
Peak memory 200956 kb
Host smart-043b4511-7ed1-4a03-b93e-9e2370b39fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123397945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.4123397945
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2577558585
Short name T1016
Test name
Test status
Simulation time 37995523 ps
CPU time 0.57 seconds
Started Aug 15 06:27:01 PM PDT 24
Finished Aug 15 06:27:01 PM PDT 24
Peak memory 196276 kb
Host smart-a2140bb8-d4cf-42a9-959d-aff88b67702e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577558585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2577558585
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.1378090567
Short name T90
Test name
Test status
Simulation time 214360928145 ps
CPU time 48.29 seconds
Started Aug 15 06:27:03 PM PDT 24
Finished Aug 15 06:27:52 PM PDT 24
Peak memory 200884 kb
Host smart-85398eb6-5a73-4fa0-8119-ed170e380125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378090567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.1378090567
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.4247685585
Short name T160
Test name
Test status
Simulation time 204020604104 ps
CPU time 40.52 seconds
Started Aug 15 06:27:13 PM PDT 24
Finished Aug 15 06:27:53 PM PDT 24
Peak memory 200880 kb
Host smart-a7b54210-1a92-4a55-a056-454bdf754a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247685585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.4247685585
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.4083282897
Short name T778
Test name
Test status
Simulation time 95882090386 ps
CPU time 27.55 seconds
Started Aug 15 06:27:04 PM PDT 24
Finished Aug 15 06:27:31 PM PDT 24
Peak memory 200896 kb
Host smart-9d1a1cae-e207-4762-a9a4-cc7f273ab3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083282897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.4083282897
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.2340310662
Short name T823
Test name
Test status
Simulation time 38010602347 ps
CPU time 19.14 seconds
Started Aug 15 06:27:13 PM PDT 24
Finished Aug 15 06:27:32 PM PDT 24
Peak memory 200916 kb
Host smart-16856841-3997-4064-b334-6f67f1ee5e07
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340310662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2340310662
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3594031466
Short name T390
Test name
Test status
Simulation time 114490791162 ps
CPU time 1118.97 seconds
Started Aug 15 06:27:13 PM PDT 24
Finished Aug 15 06:45:52 PM PDT 24
Peak memory 200936 kb
Host smart-a62914ce-4afc-46d4-9887-ce0a9e9cced5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3594031466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3594031466
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.3805972166
Short name T350
Test name
Test status
Simulation time 6440957453 ps
CPU time 10.29 seconds
Started Aug 15 06:27:01 PM PDT 24
Finished Aug 15 06:27:12 PM PDT 24
Peak memory 200748 kb
Host smart-00da3dda-f22c-4f1a-9989-7751f04974fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805972166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3805972166
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3594714414
Short name T761
Test name
Test status
Simulation time 295155905083 ps
CPU time 33.33 seconds
Started Aug 15 06:27:02 PM PDT 24
Finished Aug 15 06:27:35 PM PDT 24
Peak memory 200400 kb
Host smart-9ae03ffa-da20-49ca-8dc5-dd5160c21f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594714414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3594714414
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.3466830702
Short name T434
Test name
Test status
Simulation time 12887458027 ps
CPU time 293.79 seconds
Started Aug 15 06:27:03 PM PDT 24
Finished Aug 15 06:31:57 PM PDT 24
Peak memory 200896 kb
Host smart-301abc21-8295-40b9-9350-44466333bcab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3466830702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3466830702
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.15233954
Short name T767
Test name
Test status
Simulation time 5962896288 ps
CPU time 42.28 seconds
Started Aug 15 06:27:04 PM PDT 24
Finished Aug 15 06:27:47 PM PDT 24
Peak memory 199284 kb
Host smart-55bb3fdb-0a46-4960-a971-3fb0d83fd91f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=15233954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.15233954
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.932846641
Short name T921
Test name
Test status
Simulation time 37845447222 ps
CPU time 61.25 seconds
Started Aug 15 06:27:02 PM PDT 24
Finished Aug 15 06:28:04 PM PDT 24
Peak memory 200908 kb
Host smart-f76b7114-832e-4134-83fd-ae154ed3619d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932846641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.932846641
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.3393562204
Short name T757
Test name
Test status
Simulation time 5588648619 ps
CPU time 4.91 seconds
Started Aug 15 06:27:04 PM PDT 24
Finished Aug 15 06:27:09 PM PDT 24
Peak memory 197240 kb
Host smart-8adb6526-3bb8-4288-bf41-7a63fa8eb67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393562204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3393562204
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.829465741
Short name T108
Test name
Test status
Simulation time 273331621 ps
CPU time 1.46 seconds
Started Aug 15 06:27:01 PM PDT 24
Finished Aug 15 06:27:02 PM PDT 24
Peak memory 199152 kb
Host smart-edfb5796-8b24-4675-a800-7b426ecf7356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829465741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.829465741
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.1620460981
Short name T1090
Test name
Test status
Simulation time 219643186342 ps
CPU time 317.59 seconds
Started Aug 15 06:27:12 PM PDT 24
Finished Aug 15 06:32:30 PM PDT 24
Peak memory 201140 kb
Host smart-35d14497-58e5-4ba2-bbbd-1a7c5ffb736f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620460981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1620460981
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.4054634418
Short name T327
Test name
Test status
Simulation time 5295960893 ps
CPU time 81.44 seconds
Started Aug 15 06:27:03 PM PDT 24
Finished Aug 15 06:28:25 PM PDT 24
Peak memory 217480 kb
Host smart-a5755a85-2991-4789-9837-f31d31287adb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054634418 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.4054634418
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2743874604
Short name T1099
Test name
Test status
Simulation time 2054063269 ps
CPU time 2.02 seconds
Started Aug 15 06:27:12 PM PDT 24
Finished Aug 15 06:27:14 PM PDT 24
Peak memory 200768 kb
Host smart-8235ae55-d14e-462e-8741-ecd2d833aba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743874604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2743874604
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.465369138
Short name T799
Test name
Test status
Simulation time 45542248509 ps
CPU time 95.82 seconds
Started Aug 15 06:27:00 PM PDT 24
Finished Aug 15 06:28:36 PM PDT 24
Peak memory 200916 kb
Host smart-5d8f2d8c-d5f1-45b1-96d6-4c801c2cfa36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465369138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.465369138
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3644482282
Short name T318
Test name
Test status
Simulation time 26379618143 ps
CPU time 43.61 seconds
Started Aug 15 06:30:42 PM PDT 24
Finished Aug 15 06:31:26 PM PDT 24
Peak memory 200848 kb
Host smart-df8d8172-b6df-43a5-8f1a-245b518dc55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644482282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3644482282
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.1865685401
Short name T213
Test name
Test status
Simulation time 155665446920 ps
CPU time 120.93 seconds
Started Aug 15 06:30:42 PM PDT 24
Finished Aug 15 06:32:43 PM PDT 24
Peak memory 200920 kb
Host smart-2c58c6d2-5279-4d8b-b985-18e75f2dc84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865685401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1865685401
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.490137170
Short name T555
Test name
Test status
Simulation time 87908297341 ps
CPU time 73.23 seconds
Started Aug 15 06:30:42 PM PDT 24
Finished Aug 15 06:31:56 PM PDT 24
Peak memory 200944 kb
Host smart-5963a7c6-33a0-4934-bd7b-c0ea727ac9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490137170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.490137170
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.3189623927
Short name T674
Test name
Test status
Simulation time 25580985226 ps
CPU time 8.62 seconds
Started Aug 15 06:30:43 PM PDT 24
Finished Aug 15 06:30:52 PM PDT 24
Peak memory 200884 kb
Host smart-269943f8-4d91-4fe8-bc6e-7b6d73588750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189623927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3189623927
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2837389754
Short name T279
Test name
Test status
Simulation time 53318796724 ps
CPU time 84.08 seconds
Started Aug 15 06:30:41 PM PDT 24
Finished Aug 15 06:32:06 PM PDT 24
Peak memory 200932 kb
Host smart-20a42d83-e80e-43a7-8dfd-492456b552e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837389754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2837389754
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1669061077
Short name T702
Test name
Test status
Simulation time 31756753841 ps
CPU time 44.86 seconds
Started Aug 15 06:30:40 PM PDT 24
Finished Aug 15 06:31:25 PM PDT 24
Peak memory 200964 kb
Host smart-4b5e6447-ffdc-4844-91db-bd8c215681f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669061077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1669061077
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.3307617835
Short name T1122
Test name
Test status
Simulation time 59939329883 ps
CPU time 16.02 seconds
Started Aug 15 06:30:42 PM PDT 24
Finished Aug 15 06:30:58 PM PDT 24
Peak memory 200908 kb
Host smart-8a3a55ed-e6b8-442d-aeff-2ba6cd7e3999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307617835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3307617835
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2869630359
Short name T609
Test name
Test status
Simulation time 57417682944 ps
CPU time 15.7 seconds
Started Aug 15 06:30:40 PM PDT 24
Finished Aug 15 06:30:56 PM PDT 24
Peak memory 200480 kb
Host smart-f7b71193-73f7-4c30-8f3c-e6bd4e0b2c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869630359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2869630359
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.243983241
Short name T706
Test name
Test status
Simulation time 50129823 ps
CPU time 0.53 seconds
Started Aug 15 06:27:10 PM PDT 24
Finished Aug 15 06:27:11 PM PDT 24
Peak memory 195520 kb
Host smart-f846a23e-b707-4329-b9d0-d33c1488b4a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243983241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.243983241
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.875381337
Short name T679
Test name
Test status
Simulation time 59754741872 ps
CPU time 24.15 seconds
Started Aug 15 06:27:02 PM PDT 24
Finished Aug 15 06:27:26 PM PDT 24
Peak memory 200936 kb
Host smart-2704a760-8fb9-4130-a4cb-7eccc37dbb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875381337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.875381337
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3309155874
Short name T286
Test name
Test status
Simulation time 79202199066 ps
CPU time 278.86 seconds
Started Aug 15 06:27:12 PM PDT 24
Finished Aug 15 06:31:51 PM PDT 24
Peak memory 200940 kb
Host smart-ec7d2c5b-ef78-4b36-9991-86033c454784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309155874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3309155874
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.4056339398
Short name T515
Test name
Test status
Simulation time 28216403013 ps
CPU time 45.1 seconds
Started Aug 15 06:27:02 PM PDT 24
Finished Aug 15 06:27:47 PM PDT 24
Peak memory 200760 kb
Host smart-331584f0-b446-4822-8e73-e795a5ec6133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056339398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.4056339398
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.3181014946
Short name T621
Test name
Test status
Simulation time 376032565541 ps
CPU time 194.08 seconds
Started Aug 15 06:27:10 PM PDT 24
Finished Aug 15 06:30:24 PM PDT 24
Peak memory 200712 kb
Host smart-65bbe593-74df-453e-83b9-84ab36a11e3d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181014946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3181014946
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.227283256
Short name T755
Test name
Test status
Simulation time 108837305004 ps
CPU time 308.77 seconds
Started Aug 15 06:27:10 PM PDT 24
Finished Aug 15 06:32:19 PM PDT 24
Peak memory 200968 kb
Host smart-e6c91cfa-dde7-4aac-b6ee-ff094db12a1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=227283256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.227283256
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1292615937
Short name T978
Test name
Test status
Simulation time 6649243497 ps
CPU time 14.74 seconds
Started Aug 15 06:27:08 PM PDT 24
Finished Aug 15 06:27:22 PM PDT 24
Peak memory 200840 kb
Host smart-f3014355-bf99-4513-a517-bfde120b5ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292615937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1292615937
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.3513898398
Short name T267
Test name
Test status
Simulation time 177901022133 ps
CPU time 77.78 seconds
Started Aug 15 06:27:08 PM PDT 24
Finished Aug 15 06:28:26 PM PDT 24
Peak memory 209268 kb
Host smart-e5d74bc7-ff8b-44e6-ab5c-db11e3e664f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513898398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3513898398
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.2203503894
Short name T482
Test name
Test status
Simulation time 5855263061 ps
CPU time 12.22 seconds
Started Aug 15 06:27:09 PM PDT 24
Finished Aug 15 06:27:21 PM PDT 24
Peak memory 199660 kb
Host smart-f4958ee6-3521-4110-b429-bafcdd6353c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2203503894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2203503894
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.3446217095
Short name T831
Test name
Test status
Simulation time 86014065194 ps
CPU time 80.84 seconds
Started Aug 15 06:27:08 PM PDT 24
Finished Aug 15 06:28:29 PM PDT 24
Peak memory 200968 kb
Host smart-3506abdc-8210-4da9-b409-9530049e1bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446217095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.3446217095
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.3829881804
Short name T278
Test name
Test status
Simulation time 5821363858 ps
CPU time 9.45 seconds
Started Aug 15 06:27:09 PM PDT 24
Finished Aug 15 06:27:18 PM PDT 24
Peak memory 197104 kb
Host smart-7f04f375-cf6a-4a87-963a-9559eeefb4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829881804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3829881804
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1695969503
Short name T255
Test name
Test status
Simulation time 321975284 ps
CPU time 1.09 seconds
Started Aug 15 06:27:00 PM PDT 24
Finished Aug 15 06:27:02 PM PDT 24
Peak memory 199612 kb
Host smart-7677f2d8-6ace-491b-9f54-3b621ee8ff58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695969503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1695969503
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.1033401860
Short name T787
Test name
Test status
Simulation time 347651761736 ps
CPU time 323.84 seconds
Started Aug 15 06:27:11 PM PDT 24
Finished Aug 15 06:32:35 PM PDT 24
Peak memory 201080 kb
Host smart-63b64a6c-1ffe-4cdf-b02c-dbeb239faaae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033401860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1033401860
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2771389373
Short name T973
Test name
Test status
Simulation time 6630779452 ps
CPU time 54.62 seconds
Started Aug 15 06:27:10 PM PDT 24
Finished Aug 15 06:28:04 PM PDT 24
Peak memory 209372 kb
Host smart-483fdc0d-e48a-4b49-b81b-03cfb6faf624
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771389373 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2771389373
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.1079896391
Short name T797
Test name
Test status
Simulation time 1761223624 ps
CPU time 1.75 seconds
Started Aug 15 06:27:09 PM PDT 24
Finished Aug 15 06:27:10 PM PDT 24
Peak memory 199888 kb
Host smart-34f4026b-b37c-4c81-8984-06a5eae2e29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079896391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1079896391
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.2857870396
Short name T1159
Test name
Test status
Simulation time 125651758620 ps
CPU time 160.05 seconds
Started Aug 15 06:27:02 PM PDT 24
Finished Aug 15 06:29:43 PM PDT 24
Peak memory 200896 kb
Host smart-fab322ab-85a8-4f7d-bfab-d99e1dd605a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857870396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2857870396
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.990844926
Short name T1048
Test name
Test status
Simulation time 109748035559 ps
CPU time 49.8 seconds
Started Aug 15 06:30:40 PM PDT 24
Finished Aug 15 06:31:30 PM PDT 24
Peak memory 200892 kb
Host smart-4aaea5af-b631-41fe-b1f5-9c440fcb8ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990844926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.990844926
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2824854056
Short name T580
Test name
Test status
Simulation time 196317342588 ps
CPU time 34.2 seconds
Started Aug 15 06:30:40 PM PDT 24
Finished Aug 15 06:31:15 PM PDT 24
Peak memory 200964 kb
Host smart-86a6fb0e-f464-47c2-9e80-8275f2320d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824854056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2824854056
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.2851935761
Short name T551
Test name
Test status
Simulation time 171536881762 ps
CPU time 37.1 seconds
Started Aug 15 06:30:41 PM PDT 24
Finished Aug 15 06:31:18 PM PDT 24
Peak memory 200948 kb
Host smart-578b9e33-efe8-4c2f-8be5-175928b285f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851935761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2851935761
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.898694011
Short name T1113
Test name
Test status
Simulation time 27767536711 ps
CPU time 49.43 seconds
Started Aug 15 06:30:41 PM PDT 24
Finished Aug 15 06:31:31 PM PDT 24
Peak memory 200960 kb
Host smart-1ca42b2c-b004-4d18-b804-46d3e1784b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898694011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.898694011
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.1146316004
Short name T1024
Test name
Test status
Simulation time 136363659306 ps
CPU time 46.73 seconds
Started Aug 15 06:30:50 PM PDT 24
Finished Aug 15 06:31:37 PM PDT 24
Peak memory 200916 kb
Host smart-23d38c71-0b99-4c37-9776-046f334c8913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146316004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1146316004
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.407810101
Short name T1059
Test name
Test status
Simulation time 26486289563 ps
CPU time 44.8 seconds
Started Aug 15 06:30:53 PM PDT 24
Finished Aug 15 06:31:38 PM PDT 24
Peak memory 200956 kb
Host smart-978a531f-8135-4b98-8e69-0cc37f67f708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407810101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.407810101
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1060107293
Short name T448
Test name
Test status
Simulation time 23896975179 ps
CPU time 18.3 seconds
Started Aug 15 06:30:47 PM PDT 24
Finished Aug 15 06:31:06 PM PDT 24
Peak memory 200916 kb
Host smart-71a5b0f9-64c0-4d39-b596-a10c690b8e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060107293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1060107293
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1971419735
Short name T229
Test name
Test status
Simulation time 17292948545 ps
CPU time 13.94 seconds
Started Aug 15 06:30:52 PM PDT 24
Finished Aug 15 06:31:06 PM PDT 24
Peak memory 200956 kb
Host smart-40c5ecf0-78dd-4e76-8fdc-812acc3b9d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971419735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1971419735
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.299944875
Short name T852
Test name
Test status
Simulation time 79335906 ps
CPU time 0.55 seconds
Started Aug 15 06:27:17 PM PDT 24
Finished Aug 15 06:27:18 PM PDT 24
Peak memory 196264 kb
Host smart-51718965-8462-4e5b-a76a-e33c4ed05471
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299944875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.299944875
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.3671047479
Short name T437
Test name
Test status
Simulation time 167032289986 ps
CPU time 82.11 seconds
Started Aug 15 06:27:08 PM PDT 24
Finished Aug 15 06:28:30 PM PDT 24
Peak memory 200972 kb
Host smart-1acdd2e1-df1a-49ba-a468-7ee54cc56d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671047479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3671047479
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3386459604
Short name T129
Test name
Test status
Simulation time 22885740404 ps
CPU time 58.03 seconds
Started Aug 15 06:27:11 PM PDT 24
Finished Aug 15 06:28:09 PM PDT 24
Peak memory 200944 kb
Host smart-d800739b-286c-4502-8d2f-9c258505394f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386459604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3386459604
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.64556317
Short name T461
Test name
Test status
Simulation time 12209317956 ps
CPU time 20.47 seconds
Started Aug 15 06:27:09 PM PDT 24
Finished Aug 15 06:27:29 PM PDT 24
Peak memory 200948 kb
Host smart-d7c8e263-c4f1-484a-a239-1d0c461ac4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64556317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.64556317
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.2937201936
Short name T333
Test name
Test status
Simulation time 33819667327 ps
CPU time 48.96 seconds
Started Aug 15 06:27:09 PM PDT 24
Finished Aug 15 06:27:58 PM PDT 24
Peak memory 200908 kb
Host smart-8e4a4bc5-5446-4155-bef6-259325a44f65
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937201936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2937201936
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.2533632692
Short name T626
Test name
Test status
Simulation time 61146077561 ps
CPU time 580.9 seconds
Started Aug 15 06:27:09 PM PDT 24
Finished Aug 15 06:36:51 PM PDT 24
Peak memory 200944 kb
Host smart-ff12ca63-10d8-439f-89aa-8fc359449d9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2533632692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2533632692
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.458953734
Short name T1169
Test name
Test status
Simulation time 11437361599 ps
CPU time 11.8 seconds
Started Aug 15 06:27:08 PM PDT 24
Finished Aug 15 06:27:19 PM PDT 24
Peak memory 200260 kb
Host smart-7ced06b3-95c6-432c-b44e-af5b2b4b116d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458953734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.458953734
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.2893950126
Short name T1058
Test name
Test status
Simulation time 78349503991 ps
CPU time 201.62 seconds
Started Aug 15 06:27:09 PM PDT 24
Finished Aug 15 06:30:31 PM PDT 24
Peak memory 201160 kb
Host smart-9933c040-c09f-4042-8b03-0ac4ba932c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893950126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2893950126
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.3968974143
Short name T380
Test name
Test status
Simulation time 13506698289 ps
CPU time 208.79 seconds
Started Aug 15 06:27:10 PM PDT 24
Finished Aug 15 06:30:39 PM PDT 24
Peak memory 200876 kb
Host smart-10b33661-cb64-4914-99ab-ae3e8ee12ec4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3968974143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3968974143
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1564926662
Short name T653
Test name
Test status
Simulation time 1376016369 ps
CPU time 2.67 seconds
Started Aug 15 06:27:11 PM PDT 24
Finished Aug 15 06:27:14 PM PDT 24
Peak memory 198864 kb
Host smart-e95b0644-a635-4838-8fd9-9186f115d971
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1564926662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1564926662
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.311790391
Short name T703
Test name
Test status
Simulation time 31763323046 ps
CPU time 52.59 seconds
Started Aug 15 06:27:11 PM PDT 24
Finished Aug 15 06:28:04 PM PDT 24
Peak memory 196756 kb
Host smart-f81ed586-2d30-4d1d-8820-8a811c21d595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311790391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.311790391
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1026041594
Short name T45
Test name
Test status
Simulation time 627741164 ps
CPU time 2.73 seconds
Started Aug 15 06:27:11 PM PDT 24
Finished Aug 15 06:27:14 PM PDT 24
Peak memory 200620 kb
Host smart-b3e26a85-cb40-4f87-9264-bcd7d1fa6144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026041594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1026041594
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.3734358275
Short name T407
Test name
Test status
Simulation time 291544936612 ps
CPU time 1937.14 seconds
Started Aug 15 06:27:17 PM PDT 24
Finished Aug 15 06:59:35 PM PDT 24
Peak memory 200880 kb
Host smart-3247c0d9-3f0d-428f-95ec-eb4d4d7351d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734358275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3734358275
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.1767955119
Short name T1119
Test name
Test status
Simulation time 12403745917 ps
CPU time 74.18 seconds
Started Aug 15 06:27:16 PM PDT 24
Finished Aug 15 06:28:31 PM PDT 24
Peak memory 209192 kb
Host smart-3b099da1-13bb-4dbb-a2bd-5ac16843b1a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767955119 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.1767955119
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.278384706
Short name T1147
Test name
Test status
Simulation time 1835457977 ps
CPU time 2.36 seconds
Started Aug 15 06:27:11 PM PDT 24
Finished Aug 15 06:27:13 PM PDT 24
Peak memory 200032 kb
Host smart-10978ed3-ebcc-49bf-b03c-bcd8cff9b01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278384706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.278384706
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1451481938
Short name T1083
Test name
Test status
Simulation time 158654687867 ps
CPU time 70.21 seconds
Started Aug 15 06:27:09 PM PDT 24
Finished Aug 15 06:28:20 PM PDT 24
Peak memory 200864 kb
Host smart-c6f32e60-9d3a-4b7c-a36a-bc77f161a4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451481938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1451481938
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2573884232
Short name T867
Test name
Test status
Simulation time 70450793296 ps
CPU time 29.93 seconds
Started Aug 15 06:30:48 PM PDT 24
Finished Aug 15 06:31:18 PM PDT 24
Peak memory 200892 kb
Host smart-90a7b241-a73e-4c99-a695-d6ccd270610e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573884232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2573884232
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.469533600
Short name T200
Test name
Test status
Simulation time 24775459714 ps
CPU time 46.91 seconds
Started Aug 15 06:30:48 PM PDT 24
Finished Aug 15 06:31:35 PM PDT 24
Peak memory 200936 kb
Host smart-9cb6db8b-ceb7-4ea2-99e3-29aa6d45c1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469533600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.469533600
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.3630591798
Short name T960
Test name
Test status
Simulation time 84005708704 ps
CPU time 136.57 seconds
Started Aug 15 06:30:48 PM PDT 24
Finished Aug 15 06:33:04 PM PDT 24
Peak memory 200972 kb
Host smart-be98dd24-4123-4d18-800d-e5375143de02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630591798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3630591798
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.123539460
Short name T839
Test name
Test status
Simulation time 29292082098 ps
CPU time 12.88 seconds
Started Aug 15 06:30:49 PM PDT 24
Finished Aug 15 06:31:02 PM PDT 24
Peak memory 200664 kb
Host smart-e5f75d18-0cb1-43a2-94d3-b529632f02e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123539460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.123539460
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3903206460
Short name T48
Test name
Test status
Simulation time 45691705045 ps
CPU time 20.5 seconds
Started Aug 15 06:30:50 PM PDT 24
Finished Aug 15 06:31:11 PM PDT 24
Peak memory 200944 kb
Host smart-666fcbd4-1cc3-487c-bfbe-96a943d16878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903206460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3903206460
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1419050260
Short name T1101
Test name
Test status
Simulation time 124183189133 ps
CPU time 35.37 seconds
Started Aug 15 06:30:53 PM PDT 24
Finished Aug 15 06:31:28 PM PDT 24
Peak memory 200952 kb
Host smart-a2e14ad7-4ea8-4f78-a7ab-6a1baaa18ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419050260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1419050260
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.2379065538
Short name T863
Test name
Test status
Simulation time 239399892375 ps
CPU time 42.69 seconds
Started Aug 15 06:30:51 PM PDT 24
Finished Aug 15 06:31:34 PM PDT 24
Peak memory 200948 kb
Host smart-448163a4-ddcc-4f1e-98be-232b830b22a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379065538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2379065538
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.4278387847
Short name T764
Test name
Test status
Simulation time 165242357732 ps
CPU time 195.11 seconds
Started Aug 15 06:30:48 PM PDT 24
Finished Aug 15 06:34:04 PM PDT 24
Peak memory 200944 kb
Host smart-460c3708-45c4-45f4-a926-cc61c49de1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278387847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.4278387847
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2731593429
Short name T112
Test name
Test status
Simulation time 228677107895 ps
CPU time 90.95 seconds
Started Aug 15 06:30:47 PM PDT 24
Finished Aug 15 06:32:18 PM PDT 24
Peak memory 200884 kb
Host smart-29373d71-f4ba-4402-a980-32ed37d12a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731593429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2731593429
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1514656481
Short name T363
Test name
Test status
Simulation time 91510105 ps
CPU time 0.54 seconds
Started Aug 15 06:27:23 PM PDT 24
Finished Aug 15 06:27:24 PM PDT 24
Peak memory 196208 kb
Host smart-94ceed72-51b8-4ab4-ad2f-a11238cd1679
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514656481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1514656481
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.4188352694
Short name T272
Test name
Test status
Simulation time 62607898577 ps
CPU time 30.86 seconds
Started Aug 15 06:27:17 PM PDT 24
Finished Aug 15 06:27:48 PM PDT 24
Peak memory 200944 kb
Host smart-9b5d53ce-7ee5-453c-ae32-cb214133f230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188352694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.4188352694
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.1542338456
Short name T143
Test name
Test status
Simulation time 53943402527 ps
CPU time 43.12 seconds
Started Aug 15 06:27:16 PM PDT 24
Finished Aug 15 06:27:59 PM PDT 24
Peak memory 200860 kb
Host smart-0d2c2593-2ea4-446d-b655-36f5bd1011de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542338456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1542338456
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_intr.3610665083
Short name T120
Test name
Test status
Simulation time 389903872060 ps
CPU time 158.36 seconds
Started Aug 15 06:27:16 PM PDT 24
Finished Aug 15 06:29:55 PM PDT 24
Peak memory 200552 kb
Host smart-bd9f5720-bded-46f3-b15b-308b9b2ca760
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610665083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3610665083
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.682070931
Short name T352
Test name
Test status
Simulation time 125131995576 ps
CPU time 431.82 seconds
Started Aug 15 06:27:16 PM PDT 24
Finished Aug 15 06:34:28 PM PDT 24
Peak memory 200864 kb
Host smart-03bfbc36-830e-455e-bddc-a6430bed61c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=682070931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.682070931
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3378080310
Short name T358
Test name
Test status
Simulation time 6683982348 ps
CPU time 11.12 seconds
Started Aug 15 06:27:15 PM PDT 24
Finished Aug 15 06:27:27 PM PDT 24
Peak memory 200852 kb
Host smart-312783ce-7eec-402e-ad56-b3d89787788a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378080310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3378080310
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.806271156
Short name T316
Test name
Test status
Simulation time 120783221477 ps
CPU time 268.83 seconds
Started Aug 15 06:27:19 PM PDT 24
Finished Aug 15 06:31:48 PM PDT 24
Peak memory 201028 kb
Host smart-ee375ede-6717-44c1-b7de-8ac5c9adef8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806271156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.806271156
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3415158034
Short name T355
Test name
Test status
Simulation time 26817367970 ps
CPU time 178.89 seconds
Started Aug 15 06:27:17 PM PDT 24
Finished Aug 15 06:30:16 PM PDT 24
Peak memory 200932 kb
Host smart-f334f7c2-5d2c-4f6d-acfa-04b48dce0e27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3415158034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3415158034
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.2623347856
Short name T386
Test name
Test status
Simulation time 3890704521 ps
CPU time 16.78 seconds
Started Aug 15 06:27:18 PM PDT 24
Finished Aug 15 06:27:35 PM PDT 24
Peak memory 200020 kb
Host smart-43560a7d-08fb-45fb-b677-ccd2e6ed9226
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2623347856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2623347856
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2682007116
Short name T1023
Test name
Test status
Simulation time 24200189312 ps
CPU time 39.67 seconds
Started Aug 15 06:27:17 PM PDT 24
Finished Aug 15 06:27:56 PM PDT 24
Peak memory 201000 kb
Host smart-3a1fc5f8-f7e5-4444-931b-e1d34f0563fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682007116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2682007116
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1208790976
Short name T1120
Test name
Test status
Simulation time 4820066898 ps
CPU time 3.32 seconds
Started Aug 15 06:27:19 PM PDT 24
Finished Aug 15 06:27:22 PM PDT 24
Peak memory 197392 kb
Host smart-2dc8e1ff-ca1d-4e7b-8a92-ae15e8818117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208790976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1208790976
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3653798298
Short name T638
Test name
Test status
Simulation time 87042737 ps
CPU time 0.9 seconds
Started Aug 15 06:27:19 PM PDT 24
Finished Aug 15 06:27:20 PM PDT 24
Peak memory 198960 kb
Host smart-d77198b4-f555-46b2-a3ec-92b8e39a9f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653798298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3653798298
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.2982913796
Short name T468
Test name
Test status
Simulation time 135532477958 ps
CPU time 536.2 seconds
Started Aug 15 06:27:23 PM PDT 24
Finished Aug 15 06:36:19 PM PDT 24
Peak memory 200888 kb
Host smart-ba9fa3ff-fb17-4abe-a0da-2ecd17a02604
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982913796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2982913796
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2108971837
Short name T1009
Test name
Test status
Simulation time 3467810808 ps
CPU time 40.15 seconds
Started Aug 15 06:27:23 PM PDT 24
Finished Aug 15 06:28:03 PM PDT 24
Peak memory 216692 kb
Host smart-d688c046-fd33-43d1-9c07-247f0fddffed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108971837 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2108971837
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2251647628
Short name T455
Test name
Test status
Simulation time 631780029 ps
CPU time 2.55 seconds
Started Aug 15 06:27:19 PM PDT 24
Finished Aug 15 06:27:21 PM PDT 24
Peak memory 199628 kb
Host smart-4ee387f3-a6c0-415e-98a5-150064f894ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251647628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2251647628
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.543730296
Short name T707
Test name
Test status
Simulation time 108012384355 ps
CPU time 43.74 seconds
Started Aug 15 06:27:17 PM PDT 24
Finished Aug 15 06:28:01 PM PDT 24
Peak memory 200952 kb
Host smart-ea985aa1-f271-4378-9290-8deba00e2855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543730296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.543730296
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.4014877007
Short name T185
Test name
Test status
Simulation time 77545592047 ps
CPU time 33.11 seconds
Started Aug 15 06:30:47 PM PDT 24
Finished Aug 15 06:31:20 PM PDT 24
Peak memory 200928 kb
Host smart-238056ec-000e-4adb-98ef-86739ee1d37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014877007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.4014877007
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2134321510
Short name T396
Test name
Test status
Simulation time 16603001144 ps
CPU time 25.22 seconds
Started Aug 15 06:30:48 PM PDT 24
Finished Aug 15 06:31:13 PM PDT 24
Peak memory 200860 kb
Host smart-2b324f13-03cd-4ce5-a641-31d9932b1449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134321510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2134321510
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.3304344212
Short name T1139
Test name
Test status
Simulation time 36775775679 ps
CPU time 16.49 seconds
Started Aug 15 06:30:48 PM PDT 24
Finished Aug 15 06:31:05 PM PDT 24
Peak memory 200752 kb
Host smart-a31d3c5a-d74c-455e-afff-e9e18dec88fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304344212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.3304344212
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.847040314
Short name T922
Test name
Test status
Simulation time 36956693187 ps
CPU time 17.71 seconds
Started Aug 15 06:30:48 PM PDT 24
Finished Aug 15 06:31:05 PM PDT 24
Peak memory 200840 kb
Host smart-c56b23d5-965b-4e7f-9dd5-41c40d8cbbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847040314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.847040314
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1224335943
Short name T210
Test name
Test status
Simulation time 43449528633 ps
CPU time 71.07 seconds
Started Aug 15 06:30:50 PM PDT 24
Finished Aug 15 06:32:01 PM PDT 24
Peak memory 200860 kb
Host smart-c999ca24-3878-499d-a55a-b4a3c0a97810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224335943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1224335943
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.3541873173
Short name T234
Test name
Test status
Simulation time 31845610369 ps
CPU time 26.6 seconds
Started Aug 15 06:30:47 PM PDT 24
Finished Aug 15 06:31:14 PM PDT 24
Peak memory 200964 kb
Host smart-867ba5ef-4d2b-4329-8a68-440812150e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541873173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3541873173
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1933648243
Short name T494
Test name
Test status
Simulation time 71054267006 ps
CPU time 106.88 seconds
Started Aug 15 06:30:57 PM PDT 24
Finished Aug 15 06:32:44 PM PDT 24
Peak memory 200872 kb
Host smart-bc95b5be-324b-4945-b470-dd4e9022b970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933648243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1933648243
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2817274902
Short name T1150
Test name
Test status
Simulation time 173265928459 ps
CPU time 439.26 seconds
Started Aug 15 06:30:56 PM PDT 24
Finished Aug 15 06:38:15 PM PDT 24
Peak memory 200876 kb
Host smart-6e1cfc9f-9479-49fa-88a0-157ee4bc7d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817274902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2817274902
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.757084367
Short name T195
Test name
Test status
Simulation time 194824525290 ps
CPU time 256.89 seconds
Started Aug 15 06:30:56 PM PDT 24
Finished Aug 15 06:35:13 PM PDT 24
Peak memory 200900 kb
Host smart-018be2cf-f92a-4656-aa15-966ad053bbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757084367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.757084367
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.4040434957
Short name T344
Test name
Test status
Simulation time 24115273862 ps
CPU time 29.02 seconds
Started Aug 15 06:30:57 PM PDT 24
Finished Aug 15 06:31:26 PM PDT 24
Peak memory 200948 kb
Host smart-c68c72aa-5a27-45be-acbd-5c6cc99612e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040434957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.4040434957
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1166975946
Short name T446
Test name
Test status
Simulation time 27352253 ps
CPU time 0.59 seconds
Started Aug 15 06:27:28 PM PDT 24
Finished Aug 15 06:27:28 PM PDT 24
Peak memory 196456 kb
Host smart-5e992479-d3d4-4ff9-911c-fbaba6a801e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166975946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1166975946
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.238505141
Short name T259
Test name
Test status
Simulation time 131627288017 ps
CPU time 143.81 seconds
Started Aug 15 06:27:23 PM PDT 24
Finished Aug 15 06:29:47 PM PDT 24
Peak memory 200892 kb
Host smart-7174892e-6868-4a51-ac41-8001e46a6dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238505141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.238505141
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.767854268
Short name T670
Test name
Test status
Simulation time 36780844281 ps
CPU time 38.31 seconds
Started Aug 15 06:27:28 PM PDT 24
Finished Aug 15 06:28:07 PM PDT 24
Peak memory 200832 kb
Host smart-6eacd787-6d35-4d03-a5bc-310074d4459b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767854268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.767854268
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2302719566
Short name T308
Test name
Test status
Simulation time 30020173565 ps
CPU time 14.33 seconds
Started Aug 15 06:27:23 PM PDT 24
Finished Aug 15 06:27:38 PM PDT 24
Peak memory 200904 kb
Host smart-8fadf1c5-b325-41eb-a7e8-099d7c4fbb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302719566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2302719566
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.1081165727
Short name T773
Test name
Test status
Simulation time 33583496047 ps
CPU time 51.64 seconds
Started Aug 15 06:27:29 PM PDT 24
Finished Aug 15 06:28:21 PM PDT 24
Peak memory 200836 kb
Host smart-d2ffa7c2-403d-4781-bf1d-d59ca54c0ec3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081165727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.1081165727
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2072703130
Short name T1074
Test name
Test status
Simulation time 135003740795 ps
CPU time 1127.98 seconds
Started Aug 15 06:27:28 PM PDT 24
Finished Aug 15 06:46:16 PM PDT 24
Peak memory 200924 kb
Host smart-aa64944b-6674-4682-a0a9-eaf4666995f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2072703130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2072703130
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.57823444
Short name T861
Test name
Test status
Simulation time 1446740401 ps
CPU time 0.96 seconds
Started Aug 15 06:27:25 PM PDT 24
Finished Aug 15 06:27:26 PM PDT 24
Peak memory 196816 kb
Host smart-7ef6142b-ba43-4cb6-85f6-a4d85d32344e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57823444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.57823444
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.1006633584
Short name T971
Test name
Test status
Simulation time 123201308629 ps
CPU time 291.05 seconds
Started Aug 15 06:27:28 PM PDT 24
Finished Aug 15 06:32:19 PM PDT 24
Peak memory 200104 kb
Host smart-5a37b23b-9cbe-4702-9ac0-cf398a282301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006633584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1006633584
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3768377074
Short name T478
Test name
Test status
Simulation time 19337304210 ps
CPU time 704.65 seconds
Started Aug 15 06:27:27 PM PDT 24
Finished Aug 15 06:39:12 PM PDT 24
Peak memory 200932 kb
Host smart-f34ec633-bc9d-4f01-8934-5d7154df6d23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3768377074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3768377074
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.235820168
Short name T1006
Test name
Test status
Simulation time 4005841208 ps
CPU time 30.49 seconds
Started Aug 15 06:27:23 PM PDT 24
Finished Aug 15 06:27:54 PM PDT 24
Peak memory 198752 kb
Host smart-9e66a89e-0a42-4ef5-a07b-a133d3c1cc14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=235820168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.235820168
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3620714162
Short name T490
Test name
Test status
Simulation time 47174817500 ps
CPU time 61.2 seconds
Started Aug 15 06:28:02 PM PDT 24
Finished Aug 15 06:29:04 PM PDT 24
Peak memory 200964 kb
Host smart-9aec4dc9-4815-4e72-b535-45428eaa31d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620714162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3620714162
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.2980756289
Short name T1085
Test name
Test status
Simulation time 1839141161 ps
CPU time 3.43 seconds
Started Aug 15 06:27:27 PM PDT 24
Finished Aug 15 06:27:30 PM PDT 24
Peak memory 196628 kb
Host smart-7839a7c2-4e62-479a-b298-ad47cfc0fc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980756289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2980756289
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1567154104
Short name T788
Test name
Test status
Simulation time 1007794769 ps
CPU time 2.06 seconds
Started Aug 15 06:27:23 PM PDT 24
Finished Aug 15 06:27:25 PM PDT 24
Peak memory 199372 kb
Host smart-20b87e47-7063-40f1-84bc-bfe99f4a6725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567154104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1567154104
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.3109695201
Short name T724
Test name
Test status
Simulation time 160619190607 ps
CPU time 69.77 seconds
Started Aug 15 06:27:28 PM PDT 24
Finished Aug 15 06:28:38 PM PDT 24
Peak memory 200864 kb
Host smart-af98aa8c-baac-4254-ab54-e4337d910f72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109695201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3109695201
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.1442944661
Short name T951
Test name
Test status
Simulation time 1176202768 ps
CPU time 4.33 seconds
Started Aug 15 06:27:23 PM PDT 24
Finished Aug 15 06:27:28 PM PDT 24
Peak memory 199212 kb
Host smart-29392342-35e1-481d-a90c-33feafb2eee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442944661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1442944661
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3643839175
Short name T370
Test name
Test status
Simulation time 7807513911 ps
CPU time 13.61 seconds
Started Aug 15 06:27:24 PM PDT 24
Finished Aug 15 06:27:38 PM PDT 24
Peak memory 200956 kb
Host smart-1d07638a-a750-46e0-9fdd-ca37ef5b4081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643839175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3643839175
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1659713744
Short name T693
Test name
Test status
Simulation time 43695099826 ps
CPU time 17.09 seconds
Started Aug 15 06:30:55 PM PDT 24
Finished Aug 15 06:31:12 PM PDT 24
Peak memory 200968 kb
Host smart-a92034f0-3f14-4e7f-9be8-29c81ffcd681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659713744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1659713744
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2860127040
Short name T665
Test name
Test status
Simulation time 19028869273 ps
CPU time 7.76 seconds
Started Aug 15 06:30:56 PM PDT 24
Finished Aug 15 06:31:04 PM PDT 24
Peak memory 199776 kb
Host smart-b54b62b3-4206-44e5-8327-af3224833e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860127040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2860127040
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2886234501
Short name T727
Test name
Test status
Simulation time 23249186229 ps
CPU time 29.53 seconds
Started Aug 15 06:30:55 PM PDT 24
Finished Aug 15 06:31:24 PM PDT 24
Peak memory 200900 kb
Host smart-6e9d49f8-1358-476a-b400-75b2769bccdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886234501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2886234501
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1646149348
Short name T1161
Test name
Test status
Simulation time 363025658883 ps
CPU time 123.11 seconds
Started Aug 15 06:30:55 PM PDT 24
Finished Aug 15 06:32:58 PM PDT 24
Peak memory 200940 kb
Host smart-8af91acc-3324-47e7-81f7-4fb366deaf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646149348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1646149348
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1071580922
Short name T1086
Test name
Test status
Simulation time 134376289131 ps
CPU time 107.8 seconds
Started Aug 15 06:30:56 PM PDT 24
Finished Aug 15 06:32:44 PM PDT 24
Peak memory 200940 kb
Host smart-cacfe589-6bf1-4a90-9b7d-4868f14d292f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071580922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1071580922
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.3326522245
Short name T961
Test name
Test status
Simulation time 45410548898 ps
CPU time 64.62 seconds
Started Aug 15 06:30:57 PM PDT 24
Finished Aug 15 06:32:01 PM PDT 24
Peak memory 200800 kb
Host smart-cd6a13c9-c61a-4837-8b82-88ea2b7aa8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326522245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3326522245
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.3642008485
Short name T940
Test name
Test status
Simulation time 148466460266 ps
CPU time 50.66 seconds
Started Aug 15 06:30:56 PM PDT 24
Finished Aug 15 06:31:47 PM PDT 24
Peak memory 200884 kb
Host smart-eb19f3c0-6ea4-495b-87bd-cb244661902d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642008485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3642008485
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2076254291
Short name T836
Test name
Test status
Simulation time 100314151810 ps
CPU time 81.22 seconds
Started Aug 15 06:30:55 PM PDT 24
Finished Aug 15 06:32:16 PM PDT 24
Peak memory 200916 kb
Host smart-4982632f-ef5b-4cda-9df8-739ac0cac7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076254291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2076254291
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3177063369
Short name T1146
Test name
Test status
Simulation time 71567133972 ps
CPU time 32.42 seconds
Started Aug 15 06:30:55 PM PDT 24
Finished Aug 15 06:31:28 PM PDT 24
Peak memory 200924 kb
Host smart-3dcfeab2-d19a-45fc-b2bf-571ee3551149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177063369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3177063369
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.4082205341
Short name T504
Test name
Test status
Simulation time 111914373259 ps
CPU time 102.48 seconds
Started Aug 15 06:30:55 PM PDT 24
Finished Aug 15 06:32:37 PM PDT 24
Peak memory 200936 kb
Host smart-2154d709-5af9-49cb-a63a-4c6b899f523d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082205341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.4082205341
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1378804633
Short name T1015
Test name
Test status
Simulation time 14881551 ps
CPU time 0.54 seconds
Started Aug 15 06:27:33 PM PDT 24
Finished Aug 15 06:27:33 PM PDT 24
Peak memory 195200 kb
Host smart-d4b82ba1-7f10-4072-940c-57127e45b60e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378804633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1378804633
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.2008292881
Short name T659
Test name
Test status
Simulation time 65720930841 ps
CPU time 27.64 seconds
Started Aug 15 06:27:24 PM PDT 24
Finished Aug 15 06:27:51 PM PDT 24
Peak memory 200880 kb
Host smart-f375d2c3-9aee-478d-9c11-8760eb149ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008292881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.2008292881
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.461814138
Short name T148
Test name
Test status
Simulation time 16671201142 ps
CPU time 8.47 seconds
Started Aug 15 06:27:24 PM PDT 24
Finished Aug 15 06:27:33 PM PDT 24
Peak memory 200700 kb
Host smart-eb4dfb6a-1b07-4f6b-888d-4e51877e2dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461814138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.461814138
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.2940455592
Short name T930
Test name
Test status
Simulation time 108904890817 ps
CPU time 79.31 seconds
Started Aug 15 06:27:22 PM PDT 24
Finished Aug 15 06:28:42 PM PDT 24
Peak memory 200912 kb
Host smart-ec85360d-0c3c-446d-899d-8431f105561d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940455592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2940455592
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.2763383109
Short name T865
Test name
Test status
Simulation time 16571302155 ps
CPU time 12.53 seconds
Started Aug 15 06:27:27 PM PDT 24
Finished Aug 15 06:27:39 PM PDT 24
Peak memory 200680 kb
Host smart-780ed37a-48ea-4909-b8cf-624783f0751c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763383109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2763383109
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.4100306957
Short name T803
Test name
Test status
Simulation time 76024350847 ps
CPU time 136.64 seconds
Started Aug 15 06:27:30 PM PDT 24
Finished Aug 15 06:29:47 PM PDT 24
Peak memory 200864 kb
Host smart-1e795520-9596-4b07-88b4-465301990eed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4100306957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.4100306957
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3324876307
Short name T886
Test name
Test status
Simulation time 5123210345 ps
CPU time 9.45 seconds
Started Aug 15 06:27:30 PM PDT 24
Finished Aug 15 06:27:39 PM PDT 24
Peak memory 199544 kb
Host smart-e0f468ba-2ca2-4631-b096-e72cd1aaa7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324876307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3324876307
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.3771072800
Short name T1166
Test name
Test status
Simulation time 39312238707 ps
CPU time 14.49 seconds
Started Aug 15 06:27:31 PM PDT 24
Finished Aug 15 06:27:45 PM PDT 24
Peak memory 200864 kb
Host smart-a00c2bae-5880-4fe0-a3bc-fe3424bf13f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771072800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3771072800
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.991301621
Short name T901
Test name
Test status
Simulation time 14678394733 ps
CPU time 145.53 seconds
Started Aug 15 06:27:34 PM PDT 24
Finished Aug 15 06:30:00 PM PDT 24
Peak memory 200964 kb
Host smart-6183ed7f-1266-41c0-a4cb-76f8969a8809
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=991301621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.991301621
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.2045835540
Short name T1051
Test name
Test status
Simulation time 2365797897 ps
CPU time 1.94 seconds
Started Aug 15 06:27:23 PM PDT 24
Finished Aug 15 06:27:26 PM PDT 24
Peak memory 199984 kb
Host smart-da971277-80f8-45b2-b6c0-f5b52605c1ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2045835540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2045835540
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.1626542599
Short name T1104
Test name
Test status
Simulation time 53829593657 ps
CPU time 112.53 seconds
Started Aug 15 06:27:32 PM PDT 24
Finished Aug 15 06:29:25 PM PDT 24
Peak memory 200936 kb
Host smart-650df010-3c97-439c-8532-6d76ab1819b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626542599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1626542599
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.3330568193
Short name T669
Test name
Test status
Simulation time 5006863363 ps
CPU time 2.46 seconds
Started Aug 15 06:27:30 PM PDT 24
Finished Aug 15 06:27:33 PM PDT 24
Peak memory 197064 kb
Host smart-61de05f5-e2bb-4487-aff4-0a3a58892775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330568193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3330568193
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.1331309136
Short name T276
Test name
Test status
Simulation time 6075791410 ps
CPU time 21.14 seconds
Started Aug 15 06:27:27 PM PDT 24
Finished Aug 15 06:27:49 PM PDT 24
Peak memory 200424 kb
Host smart-286aad9b-1081-47fd-a02f-e3b594afd320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331309136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1331309136
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.1618855578
Short name T545
Test name
Test status
Simulation time 15094409121 ps
CPU time 59.09 seconds
Started Aug 15 06:27:34 PM PDT 24
Finished Aug 15 06:28:33 PM PDT 24
Peak memory 216836 kb
Host smart-b6bee2a2-2382-4412-97f9-ca8451fe5dca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618855578 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.1618855578
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2179187762
Short name T694
Test name
Test status
Simulation time 6415652143 ps
CPU time 21.93 seconds
Started Aug 15 06:27:30 PM PDT 24
Finished Aug 15 06:27:52 PM PDT 24
Peak memory 200876 kb
Host smart-66c8fd6c-23f4-41ca-b59d-c2ab01d11dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179187762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2179187762
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1128153507
Short name T253
Test name
Test status
Simulation time 123331340895 ps
CPU time 207.68 seconds
Started Aug 15 06:27:22 PM PDT 24
Finished Aug 15 06:30:50 PM PDT 24
Peak memory 200972 kb
Host smart-e168c80b-2812-4dbd-a295-4c05ce577f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128153507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1128153507
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.3916177525
Short name T768
Test name
Test status
Simulation time 125935675271 ps
CPU time 293.61 seconds
Started Aug 15 06:30:56 PM PDT 24
Finished Aug 15 06:35:50 PM PDT 24
Peak memory 200940 kb
Host smart-72a5fb24-9a16-472e-91cf-100760be5ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916177525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3916177525
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1096740512
Short name T772
Test name
Test status
Simulation time 163411762595 ps
CPU time 87.76 seconds
Started Aug 15 06:30:54 PM PDT 24
Finished Aug 15 06:32:21 PM PDT 24
Peak memory 200848 kb
Host smart-761557a2-a45f-4877-a697-fed414936eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096740512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1096740512
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3308991508
Short name T769
Test name
Test status
Simulation time 47909221174 ps
CPU time 85.23 seconds
Started Aug 15 06:30:57 PM PDT 24
Finished Aug 15 06:32:22 PM PDT 24
Peak memory 200944 kb
Host smart-5b65cc6e-4062-401d-86a0-ab84125cf00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308991508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3308991508
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2978057253
Short name T1076
Test name
Test status
Simulation time 13633139311 ps
CPU time 21.8 seconds
Started Aug 15 06:31:03 PM PDT 24
Finished Aug 15 06:31:25 PM PDT 24
Peak memory 200916 kb
Host smart-57149d8f-328e-4bfe-8c32-e09b1aa63513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978057253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2978057253
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2843266124
Short name T1156
Test name
Test status
Simulation time 103172564846 ps
CPU time 41.21 seconds
Started Aug 15 06:31:03 PM PDT 24
Finished Aug 15 06:31:44 PM PDT 24
Peak memory 200884 kb
Host smart-8bd216c0-72a2-4dba-baed-7f969aea8db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843266124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2843266124
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3422652797
Short name T197
Test name
Test status
Simulation time 26334729360 ps
CPU time 41.26 seconds
Started Aug 15 06:31:03 PM PDT 24
Finished Aug 15 06:31:44 PM PDT 24
Peak memory 200948 kb
Host smart-8fe055cd-7e43-4aef-8d42-25aeb40c36d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422652797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3422652797
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.307896736
Short name T196
Test name
Test status
Simulation time 143449004006 ps
CPU time 130.42 seconds
Started Aug 15 06:31:02 PM PDT 24
Finished Aug 15 06:33:13 PM PDT 24
Peak memory 200892 kb
Host smart-1af4d20e-0425-4214-9d34-e0324baf0b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307896736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.307896736
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1813590419
Short name T684
Test name
Test status
Simulation time 228032146655 ps
CPU time 38.99 seconds
Started Aug 15 06:31:07 PM PDT 24
Finished Aug 15 06:31:46 PM PDT 24
Peak memory 200884 kb
Host smart-32d51623-719e-49e9-8778-bf6bac8b301a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813590419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1813590419
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.408915547
Short name T408
Test name
Test status
Simulation time 35890005208 ps
CPU time 10.86 seconds
Started Aug 15 06:31:10 PM PDT 24
Finished Aug 15 06:31:21 PM PDT 24
Peak memory 200896 kb
Host smart-43533c84-7571-4ac1-93ab-e68ef0da968a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408915547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.408915547
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2267813852
Short name T138
Test name
Test status
Simulation time 14870650190 ps
CPU time 26.88 seconds
Started Aug 15 06:31:03 PM PDT 24
Finished Aug 15 06:31:30 PM PDT 24
Peak memory 200964 kb
Host smart-0f8ce921-2dd1-477e-b551-564cec63d5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267813852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2267813852
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3811766299
Short name T414
Test name
Test status
Simulation time 67462927 ps
CPU time 0.54 seconds
Started Aug 15 06:27:53 PM PDT 24
Finished Aug 15 06:27:54 PM PDT 24
Peak memory 196252 kb
Host smart-b0acf485-a24d-48c4-8406-e26b1375b1cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811766299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3811766299
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.1452175214
Short name T548
Test name
Test status
Simulation time 27889585563 ps
CPU time 41.63 seconds
Started Aug 15 06:27:30 PM PDT 24
Finished Aug 15 06:28:11 PM PDT 24
Peak memory 200892 kb
Host smart-2da89421-e563-4625-a603-d1aa1d3182d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452175214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1452175214
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.3966358020
Short name T302
Test name
Test status
Simulation time 66688160522 ps
CPU time 20.49 seconds
Started Aug 15 06:27:32 PM PDT 24
Finished Aug 15 06:27:53 PM PDT 24
Peak memory 200628 kb
Host smart-dde2e089-56bf-4512-a50c-0a52e6a77482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966358020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.3966358020
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_intr.2319322091
Short name T118
Test name
Test status
Simulation time 177066627281 ps
CPU time 129.46 seconds
Started Aug 15 06:27:34 PM PDT 24
Finished Aug 15 06:29:43 PM PDT 24
Peak memory 200916 kb
Host smart-947b981d-5889-417e-bc96-781a4c4b354d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319322091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2319322091
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1390504783
Short name T1134
Test name
Test status
Simulation time 116487781701 ps
CPU time 288.09 seconds
Started Aug 15 06:27:39 PM PDT 24
Finished Aug 15 06:32:27 PM PDT 24
Peak memory 200860 kb
Host smart-44f6bf16-e858-4a6e-a008-85fbc4dbd172
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1390504783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1390504783
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1937952048
Short name T1097
Test name
Test status
Simulation time 4785686450 ps
CPU time 8.65 seconds
Started Aug 15 06:27:40 PM PDT 24
Finished Aug 15 06:27:49 PM PDT 24
Peak memory 199392 kb
Host smart-49b67d0b-018b-4f39-b3c1-103564377451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937952048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1937952048
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.2929071180
Short name T649
Test name
Test status
Simulation time 227517050841 ps
CPU time 56.39 seconds
Started Aug 15 06:27:30 PM PDT 24
Finished Aug 15 06:28:26 PM PDT 24
Peak memory 201136 kb
Host smart-2b109a7c-63cf-425a-8155-d942242744a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929071180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2929071180
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.592948616
Short name T827
Test name
Test status
Simulation time 11495183045 ps
CPU time 343.55 seconds
Started Aug 15 06:27:52 PM PDT 24
Finished Aug 15 06:33:36 PM PDT 24
Peak memory 200976 kb
Host smart-ef38a71d-245c-49ff-b841-a9631caf0d77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=592948616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.592948616
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.3542170462
Short name T17
Test name
Test status
Simulation time 2552449732 ps
CPU time 3.65 seconds
Started Aug 15 06:27:33 PM PDT 24
Finished Aug 15 06:27:37 PM PDT 24
Peak memory 200084 kb
Host smart-48759b56-cf2a-4f60-9932-64c1a3338c2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3542170462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3542170462
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1205553899
Short name T181
Test name
Test status
Simulation time 151606732512 ps
CPU time 55.26 seconds
Started Aug 15 06:27:33 PM PDT 24
Finished Aug 15 06:28:29 PM PDT 24
Peak memory 200752 kb
Host smart-1635e383-30b0-44df-8501-cab34a12b746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205553899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1205553899
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.332329227
Short name T853
Test name
Test status
Simulation time 41372132753 ps
CPU time 60.35 seconds
Started Aug 15 06:27:33 PM PDT 24
Finished Aug 15 06:28:34 PM PDT 24
Peak memory 196972 kb
Host smart-4d7bbcd0-a7d5-4944-9376-67e78e548503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332329227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.332329227
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.93844136
Short name T103
Test name
Test status
Simulation time 5468644613 ps
CPU time 17.32 seconds
Started Aug 15 06:27:34 PM PDT 24
Finished Aug 15 06:27:51 PM PDT 24
Peak memory 200800 kb
Host smart-ddf23fe6-cfd1-46e6-8c46-146a2fcc8721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93844136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.93844136
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.2837043187
Short name T920
Test name
Test status
Simulation time 426388443621 ps
CPU time 270.19 seconds
Started Aug 15 06:27:54 PM PDT 24
Finished Aug 15 06:32:24 PM PDT 24
Peak memory 209404 kb
Host smart-343d633a-fe4f-4dac-a7c0-6f5f83a4e4f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837043187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.2837043187
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.64358863
Short name T645
Test name
Test status
Simulation time 4956430451 ps
CPU time 85.97 seconds
Started Aug 15 06:27:41 PM PDT 24
Finished Aug 15 06:29:07 PM PDT 24
Peak memory 210364 kb
Host smart-6c1db204-8e68-449b-9807-04dc3f795dd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64358863 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.64358863
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.651568953
Short name T531
Test name
Test status
Simulation time 1469313846 ps
CPU time 1.26 seconds
Started Aug 15 06:27:31 PM PDT 24
Finished Aug 15 06:27:32 PM PDT 24
Peak memory 199096 kb
Host smart-309411ad-4d70-4349-83ad-bf645d7521ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651568953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.651568953
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.1763529822
Short name T1010
Test name
Test status
Simulation time 49757937027 ps
CPU time 62.74 seconds
Started Aug 15 06:27:31 PM PDT 24
Finished Aug 15 06:28:34 PM PDT 24
Peak memory 200980 kb
Host smart-83d78d2a-59bd-43ad-9e52-8fb1dd9fc18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763529822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1763529822
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.111349718
Short name T147
Test name
Test status
Simulation time 69922659534 ps
CPU time 32.68 seconds
Started Aug 15 06:31:11 PM PDT 24
Finished Aug 15 06:31:44 PM PDT 24
Peak memory 200944 kb
Host smart-447cb0cc-692c-476f-ae38-99f05c8bd86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111349718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.111349718
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.195956586
Short name T648
Test name
Test status
Simulation time 94874131484 ps
CPU time 59.46 seconds
Started Aug 15 06:31:05 PM PDT 24
Finished Aug 15 06:32:04 PM PDT 24
Peak memory 200952 kb
Host smart-b1039124-1708-41eb-923b-e460afd83f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195956586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.195956586
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3717868252
Short name T109
Test name
Test status
Simulation time 419462175527 ps
CPU time 167.87 seconds
Started Aug 15 06:31:03 PM PDT 24
Finished Aug 15 06:33:51 PM PDT 24
Peak memory 200900 kb
Host smart-d1e23318-d37d-4f5a-8c7f-3e431df3d2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717868252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3717868252
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.2406037333
Short name T990
Test name
Test status
Simulation time 221472752504 ps
CPU time 44.17 seconds
Started Aug 15 06:31:08 PM PDT 24
Finished Aug 15 06:31:52 PM PDT 24
Peak memory 200924 kb
Host smart-535b4d85-1084-4e62-bcc0-bd905d6b074e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406037333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2406037333
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.4266749739
Short name T223
Test name
Test status
Simulation time 190416080647 ps
CPU time 17.45 seconds
Started Aug 15 06:31:09 PM PDT 24
Finished Aug 15 06:31:27 PM PDT 24
Peak memory 200836 kb
Host smart-4423cc1d-e9a0-42d3-b600-216a39a77bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266749739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.4266749739
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.839783339
Short name T389
Test name
Test status
Simulation time 72820074066 ps
CPU time 86.38 seconds
Started Aug 15 06:31:02 PM PDT 24
Finished Aug 15 06:32:29 PM PDT 24
Peak memory 200832 kb
Host smart-aab74671-5f74-4d1d-9ac4-85491cb3efdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839783339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.839783339
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3182707894
Short name T444
Test name
Test status
Simulation time 164631552996 ps
CPU time 43.41 seconds
Started Aug 15 06:31:05 PM PDT 24
Finished Aug 15 06:31:48 PM PDT 24
Peak memory 200948 kb
Host smart-93f728c8-3479-4d89-b8fa-a8e3355c2814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182707894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3182707894
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1108157194
Short name T228
Test name
Test status
Simulation time 71453739974 ps
CPU time 26.81 seconds
Started Aug 15 06:31:02 PM PDT 24
Finished Aug 15 06:31:29 PM PDT 24
Peak memory 200856 kb
Host smart-84874e73-544f-430c-9a29-152788fce98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108157194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1108157194
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.2600163808
Short name T192
Test name
Test status
Simulation time 111663844083 ps
CPU time 144.29 seconds
Started Aug 15 06:31:05 PM PDT 24
Finished Aug 15 06:33:29 PM PDT 24
Peak memory 200936 kb
Host smart-efb31ff2-b18f-4e1a-8133-a70c7894d505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600163808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2600163808
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.385877508
Short name T552
Test name
Test status
Simulation time 21989022 ps
CPU time 0.55 seconds
Started Aug 15 06:27:54 PM PDT 24
Finished Aug 15 06:27:55 PM PDT 24
Peak memory 196268 kb
Host smart-3b92c83e-d351-4e72-8ca3-8c4e8735dd89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385877508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.385877508
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.2471891571
Short name T846
Test name
Test status
Simulation time 25783483262 ps
CPU time 20.91 seconds
Started Aug 15 06:27:54 PM PDT 24
Finished Aug 15 06:28:15 PM PDT 24
Peak memory 200900 kb
Host smart-89d1a8da-9534-4904-9853-27a19b63bde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471891571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2471891571
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.534421493
Short name T637
Test name
Test status
Simulation time 42669651212 ps
CPU time 20.36 seconds
Started Aug 15 06:27:53 PM PDT 24
Finished Aug 15 06:28:14 PM PDT 24
Peak memory 201132 kb
Host smart-5085c244-7fee-4917-91e0-c224842c2edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534421493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.534421493
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.1784220285
Short name T218
Test name
Test status
Simulation time 29572504619 ps
CPU time 24.92 seconds
Started Aug 15 06:27:53 PM PDT 24
Finished Aug 15 06:28:18 PM PDT 24
Peak memory 200956 kb
Host smart-e166e5bc-ae33-458b-a114-0c0988b504a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784220285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.1784220285
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.905512735
Short name T115
Test name
Test status
Simulation time 122762912332 ps
CPU time 42.88 seconds
Started Aug 15 06:27:39 PM PDT 24
Finished Aug 15 06:28:22 PM PDT 24
Peak memory 200880 kb
Host smart-bd3ffd24-dede-490e-b911-5e3a262110b0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905512735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.905512735
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_loopback.413490889
Short name T495
Test name
Test status
Simulation time 6670203008 ps
CPU time 14.4 seconds
Started Aug 15 06:27:39 PM PDT 24
Finished Aug 15 06:27:54 PM PDT 24
Peak memory 200760 kb
Host smart-99cd1a5a-a876-439b-ade6-96ba95a28e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413490889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.413490889
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.708157930
Short name T398
Test name
Test status
Simulation time 68293618361 ps
CPU time 50.32 seconds
Started Aug 15 06:27:39 PM PDT 24
Finished Aug 15 06:28:30 PM PDT 24
Peak memory 199752 kb
Host smart-81744b5a-99ac-4529-b1ae-ca7c0f02d738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708157930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.708157930
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.2162618182
Short name T864
Test name
Test status
Simulation time 16239286039 ps
CPU time 128.92 seconds
Started Aug 15 06:27:54 PM PDT 24
Finished Aug 15 06:30:03 PM PDT 24
Peak memory 200952 kb
Host smart-943ebd18-b3c8-42ad-babe-4c0820b21954
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2162618182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2162618182
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.255410922
Short name T422
Test name
Test status
Simulation time 4135003090 ps
CPU time 7.93 seconds
Started Aug 15 06:27:55 PM PDT 24
Finished Aug 15 06:28:03 PM PDT 24
Peak memory 199404 kb
Host smart-ea5f9215-8ffb-4348-8d6b-8bd57604d483
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=255410922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.255410922
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3464711576
Short name T595
Test name
Test status
Simulation time 69406838800 ps
CPU time 36.62 seconds
Started Aug 15 06:27:51 PM PDT 24
Finished Aug 15 06:28:28 PM PDT 24
Peak memory 200900 kb
Host smart-b580d852-40f3-42c7-a45c-136f1d14f4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464711576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3464711576
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1287417529
Short name T955
Test name
Test status
Simulation time 5160306803 ps
CPU time 1.8 seconds
Started Aug 15 06:27:39 PM PDT 24
Finished Aug 15 06:27:41 PM PDT 24
Peak memory 197008 kb
Host smart-a036b4b3-8ef1-40fc-91f1-9cc31ac30023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287417529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1287417529
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.4155656543
Short name T928
Test name
Test status
Simulation time 663233285 ps
CPU time 1.68 seconds
Started Aug 15 06:27:53 PM PDT 24
Finished Aug 15 06:27:55 PM PDT 24
Peak memory 199784 kb
Host smart-55cbbe22-6e42-4fb4-a7f9-8f3d506f2f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155656543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.4155656543
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.934181903
Short name T517
Test name
Test status
Simulation time 21353372890 ps
CPU time 19.55 seconds
Started Aug 15 06:28:02 PM PDT 24
Finished Aug 15 06:28:22 PM PDT 24
Peak memory 201160 kb
Host smart-052f9d4c-8aa7-43e4-bcf3-75dc959d2db0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934181903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.934181903
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1426493622
Short name T121
Test name
Test status
Simulation time 1560470341 ps
CPU time 42.19 seconds
Started Aug 15 06:27:40 PM PDT 24
Finished Aug 15 06:28:22 PM PDT 24
Peak memory 200968 kb
Host smart-d5eea7fc-ada5-44e5-b825-b212eed97668
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426493622 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1426493622
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1153827978
Short name T907
Test name
Test status
Simulation time 6378239070 ps
CPU time 27.46 seconds
Started Aug 15 06:27:40 PM PDT 24
Finished Aug 15 06:28:08 PM PDT 24
Peak memory 200312 kb
Host smart-6036e01c-9202-4ea8-bf34-d04da26e01f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153827978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1153827978
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.1624015831
Short name T565
Test name
Test status
Simulation time 11310935828 ps
CPU time 11.17 seconds
Started Aug 15 06:27:53 PM PDT 24
Finished Aug 15 06:28:05 PM PDT 24
Peak memory 200888 kb
Host smart-f56dc975-e8de-4336-80c1-ce22d99e10ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624015831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1624015831
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.1551701325
Short name T157
Test name
Test status
Simulation time 127731242354 ps
CPU time 15.39 seconds
Started Aug 15 06:31:11 PM PDT 24
Finished Aug 15 06:31:26 PM PDT 24
Peak memory 200952 kb
Host smart-a9bf0335-105c-442a-a33a-cef0a6c8533b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551701325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1551701325
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.2022999555
Short name T477
Test name
Test status
Simulation time 59389199364 ps
CPU time 7.05 seconds
Started Aug 15 06:31:03 PM PDT 24
Finished Aug 15 06:31:10 PM PDT 24
Peak memory 200984 kb
Host smart-01ec9e93-588c-41e7-bc9a-11ca59d7d368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022999555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2022999555
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2377261057
Short name T137
Test name
Test status
Simulation time 13860215779 ps
CPU time 6.43 seconds
Started Aug 15 06:31:04 PM PDT 24
Finished Aug 15 06:31:11 PM PDT 24
Peak memory 200680 kb
Host smart-9c03b264-d048-4ad9-9d79-f3114773d58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377261057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2377261057
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.4098497020
Short name T830
Test name
Test status
Simulation time 38715512695 ps
CPU time 17.91 seconds
Started Aug 15 06:31:04 PM PDT 24
Finished Aug 15 06:31:22 PM PDT 24
Peak memory 199300 kb
Host smart-02e8b2a1-1c80-451b-9dd9-46e2304ab7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098497020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.4098497020
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.1458370014
Short name T876
Test name
Test status
Simulation time 63487728199 ps
CPU time 98.65 seconds
Started Aug 15 06:31:05 PM PDT 24
Finished Aug 15 06:32:43 PM PDT 24
Peak memory 200924 kb
Host smart-6face8cc-f3f1-495a-8bca-81bf08e1d23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458370014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1458370014
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.1459885233
Short name T1077
Test name
Test status
Simulation time 31169265174 ps
CPU time 52.21 seconds
Started Aug 15 06:31:03 PM PDT 24
Finished Aug 15 06:31:56 PM PDT 24
Peak memory 200888 kb
Host smart-7d3d7602-f7b8-4f95-90dd-cecb17167d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459885233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1459885233
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2495495612
Short name T948
Test name
Test status
Simulation time 63457097987 ps
CPU time 31.69 seconds
Started Aug 15 06:31:07 PM PDT 24
Finished Aug 15 06:31:38 PM PDT 24
Peak memory 200924 kb
Host smart-b854206f-a6cd-4438-8678-a81f602b48d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495495612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2495495612
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.1378004580
Short name T499
Test name
Test status
Simulation time 16956857 ps
CPU time 0.62 seconds
Started Aug 15 06:28:01 PM PDT 24
Finished Aug 15 06:28:02 PM PDT 24
Peak memory 196248 kb
Host smart-c79a4421-976a-48c6-ba3b-066d04e35b4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378004580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1378004580
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2347018096
Short name T131
Test name
Test status
Simulation time 70275921209 ps
CPU time 33.7 seconds
Started Aug 15 06:27:54 PM PDT 24
Finished Aug 15 06:28:28 PM PDT 24
Peak memory 200932 kb
Host smart-ed821c0d-8178-42e2-9b15-1ea018e457a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347018096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2347018096
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3323576017
Short name T995
Test name
Test status
Simulation time 53039366028 ps
CPU time 76.96 seconds
Started Aug 15 06:27:52 PM PDT 24
Finished Aug 15 06:29:09 PM PDT 24
Peak memory 200920 kb
Host smart-f0c7ee66-744a-48d8-b710-4167b28029d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323576017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3323576017
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.4012451143
Short name T974
Test name
Test status
Simulation time 135355045480 ps
CPU time 56.74 seconds
Started Aug 15 06:27:53 PM PDT 24
Finished Aug 15 06:28:50 PM PDT 24
Peak memory 200892 kb
Host smart-5eab0711-1ca8-4636-9d7c-21722d96f8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012451143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.4012451143
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.427529616
Short name T465
Test name
Test status
Simulation time 35250133516 ps
CPU time 18.68 seconds
Started Aug 15 06:27:54 PM PDT 24
Finished Aug 15 06:28:13 PM PDT 24
Peak memory 200908 kb
Host smart-8b1aca5c-6c3d-48e2-81eb-7740087fc289
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427529616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.427529616
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.3531765480
Short name T730
Test name
Test status
Simulation time 72436758237 ps
CPU time 145.27 seconds
Started Aug 15 06:27:52 PM PDT 24
Finished Aug 15 06:30:17 PM PDT 24
Peak memory 200956 kb
Host smart-83a9d57c-c393-4a22-a256-d8bd0f76986d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3531765480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3531765480
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.1554903202
Short name T349
Test name
Test status
Simulation time 3768874807 ps
CPU time 6.23 seconds
Started Aug 15 06:27:52 PM PDT 24
Finished Aug 15 06:27:59 PM PDT 24
Peak memory 197796 kb
Host smart-90989f33-33c8-4e72-8059-df54db7ba0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554903202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1554903202
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.3077632409
Short name T663
Test name
Test status
Simulation time 72678103780 ps
CPU time 39.45 seconds
Started Aug 15 06:28:02 PM PDT 24
Finished Aug 15 06:28:42 PM PDT 24
Peak memory 209328 kb
Host smart-80dd528a-b3ea-43a7-a5c4-d9ba5b51d7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077632409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3077632409
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2662551261
Short name T488
Test name
Test status
Simulation time 11005164006 ps
CPU time 437.97 seconds
Started Aug 15 06:27:51 PM PDT 24
Finished Aug 15 06:35:10 PM PDT 24
Peak memory 200936 kb
Host smart-913cde7b-28c0-4837-8438-8306a97c420f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2662551261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2662551261
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2764354281
Short name T781
Test name
Test status
Simulation time 1396986710 ps
CPU time 1.13 seconds
Started Aug 15 06:27:51 PM PDT 24
Finished Aug 15 06:27:53 PM PDT 24
Peak memory 196488 kb
Host smart-a889a077-c9bd-4681-8cbb-5911449585d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2764354281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2764354281
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.3509256919
Short name T690
Test name
Test status
Simulation time 147306982325 ps
CPU time 23.39 seconds
Started Aug 15 06:27:52 PM PDT 24
Finished Aug 15 06:28:16 PM PDT 24
Peak memory 201000 kb
Host smart-b853e85b-812e-43d9-9174-bb19fa3dfcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509256919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3509256919
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.4110413624
Short name T354
Test name
Test status
Simulation time 4598469489 ps
CPU time 8.01 seconds
Started Aug 15 06:27:53 PM PDT 24
Finished Aug 15 06:28:01 PM PDT 24
Peak memory 197208 kb
Host smart-821fb302-2ea1-4e94-b465-02c239d9fbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110413624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.4110413624
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.407874336
Short name T518
Test name
Test status
Simulation time 6322405379 ps
CPU time 21.01 seconds
Started Aug 15 06:27:53 PM PDT 24
Finished Aug 15 06:28:14 PM PDT 24
Peak memory 200868 kb
Host smart-8c670fa8-fb85-435f-ad13-610a300576d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407874336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.407874336
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.3503608470
Short name T149
Test name
Test status
Simulation time 635460153964 ps
CPU time 975.44 seconds
Started Aug 15 06:27:55 PM PDT 24
Finished Aug 15 06:44:11 PM PDT 24
Peak memory 200940 kb
Host smart-a8ca918b-b696-42ac-859e-65b6a16c64de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503608470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3503608470
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.3419819875
Short name T603
Test name
Test status
Simulation time 1725051645 ps
CPU time 8.01 seconds
Started Aug 15 06:27:54 PM PDT 24
Finished Aug 15 06:28:03 PM PDT 24
Peak memory 216572 kb
Host smart-55a88597-b6d4-4710-bdc7-23b018c58169
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419819875 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.3419819875
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1978320865
Short name T525
Test name
Test status
Simulation time 12590602205 ps
CPU time 5.95 seconds
Started Aug 15 06:27:53 PM PDT 24
Finished Aug 15 06:28:00 PM PDT 24
Peak memory 200676 kb
Host smart-da7a7a30-dd55-4c49-af1c-3b0df7ae800f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978320865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1978320865
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1229733658
Short name T273
Test name
Test status
Simulation time 27394451969 ps
CPU time 5.07 seconds
Started Aug 15 06:27:41 PM PDT 24
Finished Aug 15 06:27:46 PM PDT 24
Peak memory 200896 kb
Host smart-7fed0c14-d1e2-4d72-9e5f-95200b94f732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229733658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1229733658
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.3416291518
Short name T177
Test name
Test status
Simulation time 37189567303 ps
CPU time 33.12 seconds
Started Aug 15 06:31:03 PM PDT 24
Finished Aug 15 06:31:36 PM PDT 24
Peak memory 200828 kb
Host smart-afd606af-1ed9-4b1f-83dc-bab274aa4a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416291518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.3416291518
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.767252581
Short name T205
Test name
Test status
Simulation time 195760748371 ps
CPU time 21.67 seconds
Started Aug 15 06:31:02 PM PDT 24
Finished Aug 15 06:31:23 PM PDT 24
Peak memory 200960 kb
Host smart-67957992-3a5d-4c2b-9de0-0eb6fada4d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767252581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.767252581
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1249075872
Short name T1008
Test name
Test status
Simulation time 24262445830 ps
CPU time 36.3 seconds
Started Aug 15 06:31:09 PM PDT 24
Finished Aug 15 06:31:45 PM PDT 24
Peak memory 200780 kb
Host smart-2f26bf67-446f-4d8e-b812-4b66e082c24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249075872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1249075872
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1888514337
Short name T777
Test name
Test status
Simulation time 31991214267 ps
CPU time 27.85 seconds
Started Aug 15 06:31:03 PM PDT 24
Finished Aug 15 06:31:31 PM PDT 24
Peak memory 200876 kb
Host smart-c7b97b8a-5a78-4df9-83e3-1588b3b0e371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888514337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1888514337
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.1467174228
Short name T954
Test name
Test status
Simulation time 149748054641 ps
CPU time 296.39 seconds
Started Aug 15 06:31:04 PM PDT 24
Finished Aug 15 06:36:01 PM PDT 24
Peak memory 200868 kb
Host smart-f656842d-a7fd-49ff-a6c3-3ca76e27011d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467174228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1467174228
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1630305212
Short name T697
Test name
Test status
Simulation time 175791951426 ps
CPU time 140.12 seconds
Started Aug 15 06:31:11 PM PDT 24
Finished Aug 15 06:33:32 PM PDT 24
Peak memory 200940 kb
Host smart-d2bb5ebd-08e2-4a7d-a82d-abab86419d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630305212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1630305212
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.4102225958
Short name T203
Test name
Test status
Simulation time 34624631551 ps
CPU time 13.7 seconds
Started Aug 15 06:31:11 PM PDT 24
Finished Aug 15 06:31:25 PM PDT 24
Peak memory 200932 kb
Host smart-76f3c6f5-386e-4931-a96b-0ae61af413f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102225958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.4102225958
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3397357518
Short name T456
Test name
Test status
Simulation time 57138880705 ps
CPU time 79.89 seconds
Started Aug 15 06:31:10 PM PDT 24
Finished Aug 15 06:32:31 PM PDT 24
Peak memory 200840 kb
Host smart-752d48b8-d1b6-425e-96d6-190020898499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397357518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3397357518
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.34330772
Short name T1157
Test name
Test status
Simulation time 310833220206 ps
CPU time 85.88 seconds
Started Aug 15 06:31:11 PM PDT 24
Finished Aug 15 06:32:37 PM PDT 24
Peak memory 201140 kb
Host smart-59493355-5cc9-4d3a-b7e7-aa7e40e04f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34330772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.34330772
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.849283821
Short name T151
Test name
Test status
Simulation time 41009684369 ps
CPU time 65.3 seconds
Started Aug 15 06:31:10 PM PDT 24
Finished Aug 15 06:32:15 PM PDT 24
Peak memory 200704 kb
Host smart-cae776d5-0835-49b9-b2a0-1a25dda5788b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849283821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.849283821
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2676486633
Short name T680
Test name
Test status
Simulation time 14803416 ps
CPU time 0.56 seconds
Started Aug 15 06:25:10 PM PDT 24
Finished Aug 15 06:25:11 PM PDT 24
Peak memory 196532 kb
Host smart-dbacf6d0-77f7-4daa-862e-6ee15ac5bce0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676486633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2676486633
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.4246562924
Short name T321
Test name
Test status
Simulation time 56969644929 ps
CPU time 22.7 seconds
Started Aug 15 06:25:03 PM PDT 24
Finished Aug 15 06:25:26 PM PDT 24
Peak memory 200884 kb
Host smart-15c4f11e-6a68-4d5f-926c-dfb81db87c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246562924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.4246562924
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.656439717
Short name T981
Test name
Test status
Simulation time 63340358638 ps
CPU time 66.65 seconds
Started Aug 15 06:25:10 PM PDT 24
Finished Aug 15 06:26:17 PM PDT 24
Peak memory 200940 kb
Host smart-f02c33b6-e332-4524-9fd0-3e94bc1b3490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656439717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.656439717
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1629389173
Short name T810
Test name
Test status
Simulation time 89970326145 ps
CPU time 20.89 seconds
Started Aug 15 06:25:10 PM PDT 24
Finished Aug 15 06:25:31 PM PDT 24
Peak memory 200956 kb
Host smart-b1f606c2-9251-446a-9574-8f083ca3dc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629389173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1629389173
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.2969737274
Short name T384
Test name
Test status
Simulation time 39539324412 ps
CPU time 6.79 seconds
Started Aug 15 06:25:12 PM PDT 24
Finished Aug 15 06:25:19 PM PDT 24
Peak memory 200952 kb
Host smart-df564845-00ff-46f3-9a4f-2c2caa90b544
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969737274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2969737274
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3684018072
Short name T373
Test name
Test status
Simulation time 121768828938 ps
CPU time 565.07 seconds
Started Aug 15 06:25:11 PM PDT 24
Finished Aug 15 06:34:36 PM PDT 24
Peak memory 200884 kb
Host smart-e8832031-97c8-401d-b418-d7c3d6b00352
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3684018072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3684018072
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1084320674
Short name T534
Test name
Test status
Simulation time 665275965 ps
CPU time 1.46 seconds
Started Aug 15 06:25:10 PM PDT 24
Finished Aug 15 06:25:12 PM PDT 24
Peak memory 196560 kb
Host smart-dbdf1325-c05c-450e-a894-10a6e4604f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084320674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1084320674
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.481182136
Short name T335
Test name
Test status
Simulation time 113561911873 ps
CPU time 15.67 seconds
Started Aug 15 06:25:12 PM PDT 24
Finished Aug 15 06:25:28 PM PDT 24
Peak memory 199972 kb
Host smart-504bf2f0-0208-4e70-b6c0-fdfec7c9c01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481182136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.481182136
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.3059813878
Short name T1174
Test name
Test status
Simulation time 14005728177 ps
CPU time 310.24 seconds
Started Aug 15 06:25:10 PM PDT 24
Finished Aug 15 06:30:21 PM PDT 24
Peak memory 200896 kb
Host smart-fbde2af4-7bc7-4f30-9724-76f711fcb40c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3059813878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3059813878
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3327371421
Short name T568
Test name
Test status
Simulation time 6113239987 ps
CPU time 31.89 seconds
Started Aug 15 06:25:10 PM PDT 24
Finished Aug 15 06:25:42 PM PDT 24
Peak memory 199772 kb
Host smart-f353560a-012e-4a54-b598-60c3268a5138
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3327371421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3327371421
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.106787042
Short name T625
Test name
Test status
Simulation time 12950145874 ps
CPU time 23.08 seconds
Started Aug 15 06:25:10 PM PDT 24
Finished Aug 15 06:25:33 PM PDT 24
Peak memory 200992 kb
Host smart-76c0fc04-9d58-4493-9c47-3c81b13c1af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106787042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.106787042
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.1773188252
Short name T1007
Test name
Test status
Simulation time 4733850584 ps
CPU time 8.03 seconds
Started Aug 15 06:25:10 PM PDT 24
Finished Aug 15 06:25:19 PM PDT 24
Peak memory 197416 kb
Host smart-db6816a0-4d40-4f74-83a8-987c6950abc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773188252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1773188252
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.849727792
Short name T85
Test name
Test status
Simulation time 140138932 ps
CPU time 0.77 seconds
Started Aug 15 06:25:11 PM PDT 24
Finished Aug 15 06:25:12 PM PDT 24
Peak memory 219004 kb
Host smart-29c1cda7-1cf7-4b5d-8127-106f0b39de3b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849727792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.849727792
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.3352400706
Short name T1034
Test name
Test status
Simulation time 851044365 ps
CPU time 3.63 seconds
Started Aug 15 06:25:02 PM PDT 24
Finished Aug 15 06:25:06 PM PDT 24
Peak memory 199896 kb
Host smart-8d5fc78f-092b-412f-a2d9-bd81ec1653d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352400706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3352400706
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2435407826
Short name T124
Test name
Test status
Simulation time 9530954544 ps
CPU time 32 seconds
Started Aug 15 06:25:11 PM PDT 24
Finished Aug 15 06:25:43 PM PDT 24
Peak memory 209412 kb
Host smart-773fe6cd-23da-4ccb-9fef-3ea4d8a2c22b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435407826 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2435407826
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1594160102
Short name T328
Test name
Test status
Simulation time 1030026500 ps
CPU time 1.69 seconds
Started Aug 15 06:25:09 PM PDT 24
Finished Aug 15 06:25:11 PM PDT 24
Peak memory 199044 kb
Host smart-53b1f0e3-f9a9-426b-9bd1-3e946171fdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594160102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1594160102
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2024787687
Short name T520
Test name
Test status
Simulation time 30295575838 ps
CPU time 50.12 seconds
Started Aug 15 06:25:03 PM PDT 24
Finished Aug 15 06:25:54 PM PDT 24
Peak memory 200948 kb
Host smart-afdc22d8-f4b0-48ca-953a-8196fa6300fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024787687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2024787687
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3837343318
Short name T28
Test name
Test status
Simulation time 24430289 ps
CPU time 0.56 seconds
Started Aug 15 06:27:54 PM PDT 24
Finished Aug 15 06:27:55 PM PDT 24
Peak memory 196244 kb
Host smart-55f87c37-82d6-4fd7-9bed-3f8a4bdcfc38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837343318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3837343318
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.699584274
Short name T1123
Test name
Test status
Simulation time 67917215555 ps
CPU time 96.31 seconds
Started Aug 15 06:27:55 PM PDT 24
Finished Aug 15 06:29:31 PM PDT 24
Peak memory 200924 kb
Host smart-5c9b19dc-6d68-49bf-8fe6-7ec593bbb9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699584274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.699584274
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1036794247
Short name T493
Test name
Test status
Simulation time 58600640733 ps
CPU time 27.15 seconds
Started Aug 15 06:27:52 PM PDT 24
Finished Aug 15 06:28:20 PM PDT 24
Peak memory 200980 kb
Host smart-832242e8-1363-440b-8840-c22c4df6baa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036794247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1036794247
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3492565297
Short name T144
Test name
Test status
Simulation time 83246201866 ps
CPU time 138.39 seconds
Started Aug 15 06:27:51 PM PDT 24
Finished Aug 15 06:30:10 PM PDT 24
Peak memory 200728 kb
Host smart-c1b20ad9-cf2b-4753-93cf-babf1915def3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492565297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3492565297
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.695328681
Short name T868
Test name
Test status
Simulation time 79572444666 ps
CPU time 46 seconds
Started Aug 15 06:27:53 PM PDT 24
Finished Aug 15 06:28:40 PM PDT 24
Peak memory 200964 kb
Host smart-5730f937-5748-4935-8ce9-173c61ccde0f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695328681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.695328681
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1059591904
Short name T639
Test name
Test status
Simulation time 109397270650 ps
CPU time 638.52 seconds
Started Aug 15 06:28:01 PM PDT 24
Finished Aug 15 06:38:39 PM PDT 24
Peak memory 200876 kb
Host smart-e355fd76-a218-4a94-ab56-7aad425962d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1059591904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1059591904
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3531983885
Short name T627
Test name
Test status
Simulation time 1497786389 ps
CPU time 1.52 seconds
Started Aug 15 06:28:01 PM PDT 24
Finished Aug 15 06:28:03 PM PDT 24
Peak memory 198300 kb
Host smart-7c2bca06-4e45-4d1f-80f2-28c717e887f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531983885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3531983885
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.4219219843
Short name T264
Test name
Test status
Simulation time 6817002161 ps
CPU time 10.46 seconds
Started Aug 15 06:27:52 PM PDT 24
Finished Aug 15 06:28:03 PM PDT 24
Peak memory 198272 kb
Host smart-6ecd6079-681d-4cf1-a3d0-7cbe69db975a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219219843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.4219219843
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.1943102523
Short name T704
Test name
Test status
Simulation time 14290474367 ps
CPU time 701.49 seconds
Started Aug 15 06:27:56 PM PDT 24
Finished Aug 15 06:39:38 PM PDT 24
Peak memory 200968 kb
Host smart-9ea181a2-1dd8-4ce4-a9a4-5a7f0b4f6aad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1943102523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1943102523
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.3314113734
Short name T546
Test name
Test status
Simulation time 2736306127 ps
CPU time 1.69 seconds
Started Aug 15 06:27:52 PM PDT 24
Finished Aug 15 06:27:53 PM PDT 24
Peak memory 198912 kb
Host smart-1dc91ced-2ab4-47d2-b5a5-e033be9143b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3314113734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3314113734
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.116406906
Short name T1037
Test name
Test status
Simulation time 73287011040 ps
CPU time 99.71 seconds
Started Aug 15 06:27:55 PM PDT 24
Finished Aug 15 06:29:35 PM PDT 24
Peak memory 200952 kb
Host smart-23e42a3a-8577-4357-a057-44428d1976c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116406906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.116406906
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.3987973848
Short name T642
Test name
Test status
Simulation time 4040475460 ps
CPU time 3.49 seconds
Started Aug 15 06:27:51 PM PDT 24
Finished Aug 15 06:27:55 PM PDT 24
Peak memory 197188 kb
Host smart-46d364b2-f764-4aab-bbfc-5d98be83618b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987973848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3987973848
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.1213988298
Short name T275
Test name
Test status
Simulation time 118309306 ps
CPU time 0.85 seconds
Started Aug 15 06:27:52 PM PDT 24
Finished Aug 15 06:27:54 PM PDT 24
Peak memory 198748 kb
Host smart-d055e225-8f6a-4a22-905f-39cb45996078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213988298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1213988298
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.914587752
Short name T26
Test name
Test status
Simulation time 3063575576 ps
CPU time 35.57 seconds
Started Aug 15 06:27:55 PM PDT 24
Finished Aug 15 06:28:31 PM PDT 24
Peak memory 200968 kb
Host smart-a34074a8-d8c4-468f-ac1d-72ebdd2b3a60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914587752 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.914587752
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.365329744
Short name T877
Test name
Test status
Simulation time 1276934930 ps
CPU time 3.89 seconds
Started Aug 15 06:27:55 PM PDT 24
Finished Aug 15 06:27:59 PM PDT 24
Peak memory 200516 kb
Host smart-cebe71e1-933a-4840-82d8-2514de479015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365329744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.365329744
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.53224930
Short name T658
Test name
Test status
Simulation time 37970748613 ps
CPU time 30.29 seconds
Started Aug 15 06:27:54 PM PDT 24
Finished Aug 15 06:28:25 PM PDT 24
Peak memory 200888 kb
Host smart-4834b644-1a85-41d2-aef7-02b459bddea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53224930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.53224930
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3615437422
Short name T27
Test name
Test status
Simulation time 39398159 ps
CPU time 0.59 seconds
Started Aug 15 06:28:01 PM PDT 24
Finished Aug 15 06:28:02 PM PDT 24
Peak memory 196532 kb
Host smart-ba4fe224-26b8-4a82-9002-ace37c818279
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615437422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3615437422
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1091546623
Short name T582
Test name
Test status
Simulation time 93173416598 ps
CPU time 129.66 seconds
Started Aug 15 06:27:55 PM PDT 24
Finished Aug 15 06:30:05 PM PDT 24
Peak memory 200936 kb
Host smart-720d1e85-6c3e-41b2-9066-37ac607b9382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091546623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1091546623
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3479600389
Short name T93
Test name
Test status
Simulation time 205422526955 ps
CPU time 167.44 seconds
Started Aug 15 06:27:57 PM PDT 24
Finished Aug 15 06:30:45 PM PDT 24
Peak memory 200888 kb
Host smart-4b25232c-deb4-47cf-9693-bcc04f231fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479600389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3479600389
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3259974659
Short name T849
Test name
Test status
Simulation time 40658988033 ps
CPU time 70.43 seconds
Started Aug 15 06:28:04 PM PDT 24
Finished Aug 15 06:29:14 PM PDT 24
Peak memory 200948 kb
Host smart-1059da5f-2208-4639-a70f-ed040c2815a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259974659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3259974659
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.368532302
Short name T462
Test name
Test status
Simulation time 5318280613 ps
CPU time 7.74 seconds
Started Aug 15 06:28:04 PM PDT 24
Finished Aug 15 06:28:12 PM PDT 24
Peak memory 197760 kb
Host smart-9504ba37-2c47-44d6-ac3f-f11f7d728a4d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368532302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.368532302
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1462582646
Short name T88
Test name
Test status
Simulation time 132588926058 ps
CPU time 335.59 seconds
Started Aug 15 06:27:58 PM PDT 24
Finished Aug 15 06:33:34 PM PDT 24
Peak memory 200920 kb
Host smart-72b26037-89cb-4703-90a2-62698fd4e2db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1462582646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1462582646
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.156594755
Short name T429
Test name
Test status
Simulation time 10905327751 ps
CPU time 9.33 seconds
Started Aug 15 06:28:01 PM PDT 24
Finished Aug 15 06:28:10 PM PDT 24
Peak memory 200876 kb
Host smart-19156eee-2200-4b5c-8f0b-abda788bf29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156594755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.156594755
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.1333207101
Short name T937
Test name
Test status
Simulation time 52655311830 ps
CPU time 89.16 seconds
Started Aug 15 06:28:04 PM PDT 24
Finished Aug 15 06:29:33 PM PDT 24
Peak memory 199912 kb
Host smart-f5f845c6-3a82-4483-9f69-928421386814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333207101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.1333207101
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.4287680328
Short name T711
Test name
Test status
Simulation time 15042052244 ps
CPU time 162.99 seconds
Started Aug 15 06:27:57 PM PDT 24
Finished Aug 15 06:30:40 PM PDT 24
Peak memory 200952 kb
Host smart-c709b00e-9b74-46dd-9403-74c62995aa94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4287680328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.4287680328
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.93858018
Short name T417
Test name
Test status
Simulation time 2756683928 ps
CPU time 5.22 seconds
Started Aug 15 06:27:58 PM PDT 24
Finished Aug 15 06:28:03 PM PDT 24
Peak memory 199864 kb
Host smart-ca5499b6-c6c8-4658-ae19-af1a9903b197
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=93858018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.93858018
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.4020427034
Short name T375
Test name
Test status
Simulation time 21981223843 ps
CPU time 21.4 seconds
Started Aug 15 06:27:58 PM PDT 24
Finished Aug 15 06:28:20 PM PDT 24
Peak memory 200908 kb
Host smart-58e08fd0-a74b-4348-8125-b9fca1dc3739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020427034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.4020427034
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2931594104
Short name T569
Test name
Test status
Simulation time 2550546835 ps
CPU time 4.44 seconds
Started Aug 15 06:28:01 PM PDT 24
Finished Aug 15 06:28:05 PM PDT 24
Peak memory 197356 kb
Host smart-8395e5f7-16b5-4af7-8869-02108e601418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931594104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2931594104
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1051510374
Short name T980
Test name
Test status
Simulation time 504746512 ps
CPU time 1.55 seconds
Started Aug 15 06:27:56 PM PDT 24
Finished Aug 15 06:27:58 PM PDT 24
Peak memory 199068 kb
Host smart-f567a9d1-bc18-4617-b5bb-62ca39c64f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051510374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1051510374
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.1916057113
Short name T610
Test name
Test status
Simulation time 4345771533 ps
CPU time 16.71 seconds
Started Aug 15 06:27:55 PM PDT 24
Finished Aug 15 06:28:12 PM PDT 24
Peak memory 217364 kb
Host smart-147725f6-6439-4df3-afc4-c992dcf951cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916057113 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1916057113
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3496743247
Short name T1135
Test name
Test status
Simulation time 662605903 ps
CPU time 3.06 seconds
Started Aug 15 06:27:57 PM PDT 24
Finished Aug 15 06:28:00 PM PDT 24
Peak memory 200232 kb
Host smart-3fa27ffe-2b84-41e8-9a35-621f8cd3ef58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496743247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3496743247
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.2805281707
Short name T1126
Test name
Test status
Simulation time 6920013982 ps
CPU time 11.75 seconds
Started Aug 15 06:27:56 PM PDT 24
Finished Aug 15 06:28:08 PM PDT 24
Peak memory 200904 kb
Host smart-24a9d25c-cdf0-4103-b9b4-af263d427eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805281707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2805281707
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2452023609
Short name T976
Test name
Test status
Simulation time 35590531 ps
CPU time 0.6 seconds
Started Aug 15 06:28:05 PM PDT 24
Finished Aug 15 06:28:05 PM PDT 24
Peak memory 196544 kb
Host smart-de5af613-8ca4-49c2-be8c-f77420042b06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452023609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2452023609
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.4180570111
Short name T786
Test name
Test status
Simulation time 31254939635 ps
CPU time 22.51 seconds
Started Aug 15 06:27:57 PM PDT 24
Finished Aug 15 06:28:19 PM PDT 24
Peak memory 200952 kb
Host smart-dce3a489-f7bf-4895-b16a-e83a240275dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180570111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.4180570111
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.441065097
Short name T507
Test name
Test status
Simulation time 119715315012 ps
CPU time 51.91 seconds
Started Aug 15 06:28:00 PM PDT 24
Finished Aug 15 06:28:53 PM PDT 24
Peak memory 200892 kb
Host smart-2da43a08-4e22-4e4d-9e12-ed360053c521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441065097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.441065097
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_intr.1997499788
Short name T411
Test name
Test status
Simulation time 112257501849 ps
CPU time 189.75 seconds
Started Aug 15 06:28:03 PM PDT 24
Finished Aug 15 06:31:13 PM PDT 24
Peak memory 200948 kb
Host smart-e64aaec8-aaef-47bb-b747-9731a59cce07
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997499788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1997499788
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_loopback.3026970315
Short name T623
Test name
Test status
Simulation time 2035884950 ps
CPU time 2.48 seconds
Started Aug 15 06:28:07 PM PDT 24
Finished Aug 15 06:28:09 PM PDT 24
Peak memory 199332 kb
Host smart-f57633ec-341a-4779-a703-8753e5537977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026970315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3026970315
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.929271101
Short name T281
Test name
Test status
Simulation time 186421755011 ps
CPU time 264.28 seconds
Started Aug 15 06:28:04 PM PDT 24
Finished Aug 15 06:32:28 PM PDT 24
Peak memory 200964 kb
Host smart-16db0b1c-297a-4975-bc12-b0c104bb7cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929271101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.929271101
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.779744424
Short name T575
Test name
Test status
Simulation time 33835850599 ps
CPU time 482.36 seconds
Started Aug 15 06:28:04 PM PDT 24
Finished Aug 15 06:36:07 PM PDT 24
Peak memory 200900 kb
Host smart-44dc9ebf-f2f0-4f21-815b-5b4bf503ab8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=779744424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.779744424
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.2332633934
Short name T1107
Test name
Test status
Simulation time 1279971168 ps
CPU time 3.06 seconds
Started Aug 15 06:28:03 PM PDT 24
Finished Aug 15 06:28:06 PM PDT 24
Peak memory 198840 kb
Host smart-b24300b4-cf42-43f7-9aff-7c204bbec74d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2332633934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2332633934
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.4237137540
Short name T572
Test name
Test status
Simulation time 50559855398 ps
CPU time 20.9 seconds
Started Aug 15 06:28:02 PM PDT 24
Finished Aug 15 06:28:23 PM PDT 24
Peak memory 197392 kb
Host smart-f4fab0c1-a53c-4665-a49f-98fac76caeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237137540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.4237137540
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3655647531
Short name T447
Test name
Test status
Simulation time 291372505 ps
CPU time 1.09 seconds
Started Aug 15 06:28:03 PM PDT 24
Finished Aug 15 06:28:05 PM PDT 24
Peak memory 199268 kb
Host smart-57801313-af4f-4587-aa56-c763dca410a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655647531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3655647531
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.2158419155
Short name T620
Test name
Test status
Simulation time 217232293566 ps
CPU time 101.97 seconds
Started Aug 15 06:28:04 PM PDT 24
Finished Aug 15 06:29:46 PM PDT 24
Peak memory 200884 kb
Host smart-742e7013-74f7-4c19-8b5d-e115148757b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158419155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2158419155
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1521478694
Short name T553
Test name
Test status
Simulation time 4211153398 ps
CPU time 27.27 seconds
Started Aug 15 06:28:05 PM PDT 24
Finished Aug 15 06:28:32 PM PDT 24
Peak memory 209416 kb
Host smart-c2a1965c-2676-4230-82e7-1fb04c188a89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521478694 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1521478694
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.872079143
Short name T20
Test name
Test status
Simulation time 1621280880 ps
CPU time 2.61 seconds
Started Aug 15 06:28:10 PM PDT 24
Finished Aug 15 06:28:13 PM PDT 24
Peak memory 199464 kb
Host smart-7d1dd8c5-4973-4db1-82ba-326489140b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872079143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.872079143
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3692514379
Short name T613
Test name
Test status
Simulation time 118151568762 ps
CPU time 58.98 seconds
Started Aug 15 06:27:57 PM PDT 24
Finished Aug 15 06:28:56 PM PDT 24
Peak memory 200872 kb
Host smart-895f4bf3-a0d4-4b53-b57f-27c90b04e429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692514379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3692514379
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.269312529
Short name T367
Test name
Test status
Simulation time 12190593 ps
CPU time 0.57 seconds
Started Aug 15 06:28:12 PM PDT 24
Finished Aug 15 06:28:12 PM PDT 24
Peak memory 196540 kb
Host smart-a463be0b-d8c1-42ff-9691-ca2f470a72f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269312529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.269312529
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.74725286
Short name T420
Test name
Test status
Simulation time 123471337703 ps
CPU time 107.52 seconds
Started Aug 15 06:28:10 PM PDT 24
Finished Aug 15 06:29:58 PM PDT 24
Peak memory 200880 kb
Host smart-c1fa31ac-e568-46c7-8c1b-d28ea142b37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74725286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.74725286
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.2665642085
Short name T1080
Test name
Test status
Simulation time 16720936014 ps
CPU time 25.8 seconds
Started Aug 15 06:28:04 PM PDT 24
Finished Aug 15 06:28:30 PM PDT 24
Peak memory 200376 kb
Host smart-13f4025f-8150-4523-b5b9-70a150707fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665642085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2665642085
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2151924229
Short name T1040
Test name
Test status
Simulation time 79500711166 ps
CPU time 10.7 seconds
Started Aug 15 06:28:04 PM PDT 24
Finished Aug 15 06:28:15 PM PDT 24
Peak memory 200916 kb
Host smart-c6e87af5-349c-4d9d-b445-21d8cae4f430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151924229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2151924229
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.1471030426
Short name T731
Test name
Test status
Simulation time 24482818210 ps
CPU time 44.68 seconds
Started Aug 15 06:28:10 PM PDT 24
Finished Aug 15 06:28:54 PM PDT 24
Peak memory 200848 kb
Host smart-303cc253-5031-4c1f-b47b-b178513223b2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471030426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1471030426
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.950809766
Short name T979
Test name
Test status
Simulation time 149352875914 ps
CPU time 165.1 seconds
Started Aug 15 06:28:13 PM PDT 24
Finished Aug 15 06:30:59 PM PDT 24
Peak memory 201140 kb
Host smart-355e4c87-8c9e-4377-9fac-52c955780307
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=950809766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.950809766
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.1156667976
Short name T347
Test name
Test status
Simulation time 9023519879 ps
CPU time 16.67 seconds
Started Aug 15 06:28:04 PM PDT 24
Finished Aug 15 06:28:21 PM PDT 24
Peak memory 200736 kb
Host smart-f14877f6-700a-4cce-94f4-4697e128d312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156667976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1156667976
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.2726201189
Short name T303
Test name
Test status
Simulation time 12923659056 ps
CPU time 18.01 seconds
Started Aug 15 06:28:04 PM PDT 24
Finished Aug 15 06:28:22 PM PDT 24
Peak memory 199288 kb
Host smart-69687ce4-7b3a-4590-843b-ff68602e1f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726201189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2726201189
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.1900237937
Short name T258
Test name
Test status
Simulation time 9767658658 ps
CPU time 114.66 seconds
Started Aug 15 06:28:14 PM PDT 24
Finished Aug 15 06:30:09 PM PDT 24
Peak memory 200964 kb
Host smart-d8ecc151-032f-4d89-9c0d-875ec74d2a59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1900237937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1900237937
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2683813930
Short name T720
Test name
Test status
Simulation time 3860257702 ps
CPU time 5.1 seconds
Started Aug 15 06:28:06 PM PDT 24
Finished Aug 15 06:28:12 PM PDT 24
Peak memory 200252 kb
Host smart-d8d86bc2-d696-4c6b-bdfa-064558300613
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2683813930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2683813930
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2085338120
Short name T1072
Test name
Test status
Simulation time 126905730301 ps
CPU time 64.03 seconds
Started Aug 15 06:28:07 PM PDT 24
Finished Aug 15 06:29:11 PM PDT 24
Peak memory 200892 kb
Host smart-fbaebe10-62f9-4972-bb68-4dbcce80396b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085338120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2085338120
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1262644126
Short name T824
Test name
Test status
Simulation time 40335828585 ps
CPU time 16.18 seconds
Started Aug 15 06:28:10 PM PDT 24
Finished Aug 15 06:28:27 PM PDT 24
Peak memory 196708 kb
Host smart-f376d26e-0a40-466e-89a9-9b39f444266e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262644126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1262644126
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.4151638388
Short name T1176
Test name
Test status
Simulation time 879180728 ps
CPU time 4.95 seconds
Started Aug 15 06:28:04 PM PDT 24
Finished Aug 15 06:28:09 PM PDT 24
Peak memory 199252 kb
Host smart-0c3031ff-5072-4bfb-8ad8-2f6f59e62299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151638388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.4151638388
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.745783746
Short name T643
Test name
Test status
Simulation time 210339646506 ps
CPU time 178.49 seconds
Started Aug 15 06:28:12 PM PDT 24
Finished Aug 15 06:31:11 PM PDT 24
Peak memory 200896 kb
Host smart-851f251e-f78c-4f81-ab05-b7b0ab0833c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745783746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.745783746
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.1238566015
Short name T686
Test name
Test status
Simulation time 5247500934 ps
CPU time 13 seconds
Started Aug 15 06:28:13 PM PDT 24
Finished Aug 15 06:28:26 PM PDT 24
Peak memory 217392 kb
Host smart-e5dd250d-86cd-4fb4-9501-e85d05bdcd27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238566015 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1238566015
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.1730944487
Short name T19
Test name
Test status
Simulation time 1264149856 ps
CPU time 3.81 seconds
Started Aug 15 06:28:04 PM PDT 24
Finished Aug 15 06:28:08 PM PDT 24
Peak memory 199552 kb
Host smart-f2887878-feff-469a-a746-61bbc4ca6342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730944487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1730944487
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2422133173
Short name T1175
Test name
Test status
Simulation time 96216213757 ps
CPU time 17.53 seconds
Started Aug 15 06:28:04 PM PDT 24
Finished Aug 15 06:28:21 PM PDT 24
Peak memory 200892 kb
Host smart-8960ae15-9099-4036-ba2d-3602a6d4dc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422133173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2422133173
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2824501535
Short name T847
Test name
Test status
Simulation time 16653610 ps
CPU time 0.54 seconds
Started Aug 15 06:28:16 PM PDT 24
Finished Aug 15 06:28:16 PM PDT 24
Peak memory 195676 kb
Host smart-217214bd-ff6a-4e33-a7f0-b55936e2ead7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824501535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2824501535
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.2835893083
Short name T449
Test name
Test status
Simulation time 59305716978 ps
CPU time 103.06 seconds
Started Aug 15 06:28:11 PM PDT 24
Finished Aug 15 06:29:54 PM PDT 24
Peak memory 200896 kb
Host smart-3dac0d71-eeaa-4e68-b6c5-3bec187a76ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835893083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2835893083
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.741483150
Short name T165
Test name
Test status
Simulation time 11487963647 ps
CPU time 5.49 seconds
Started Aug 15 06:28:14 PM PDT 24
Finished Aug 15 06:28:20 PM PDT 24
Peak memory 200896 kb
Host smart-27dfefff-2725-4c3e-8eed-1e8c70d736fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741483150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.741483150
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.1973841249
Short name T1064
Test name
Test status
Simulation time 151650172197 ps
CPU time 25.85 seconds
Started Aug 15 06:28:13 PM PDT 24
Finished Aug 15 06:28:39 PM PDT 24
Peak memory 200892 kb
Host smart-83303f2a-3f53-4ec4-98d4-17ae43ade8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973841249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1973841249
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.434224637
Short name T700
Test name
Test status
Simulation time 47134321001 ps
CPU time 58.4 seconds
Started Aug 15 06:28:13 PM PDT 24
Finished Aug 15 06:29:11 PM PDT 24
Peak memory 200972 kb
Host smart-40eddcf6-b027-4725-bba0-2b18e846d767
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434224637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.434224637
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.447283611
Short name T296
Test name
Test status
Simulation time 74619794031 ps
CPU time 138.11 seconds
Started Aug 15 06:28:11 PM PDT 24
Finished Aug 15 06:30:29 PM PDT 24
Peak memory 200864 kb
Host smart-d8b6f399-6c31-42ac-9d52-100b7dce509e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=447283611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.447283611
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.4196205636
Short name T754
Test name
Test status
Simulation time 2233391049 ps
CPU time 1.66 seconds
Started Aug 15 06:28:14 PM PDT 24
Finished Aug 15 06:28:16 PM PDT 24
Peak memory 198320 kb
Host smart-3d9e07b4-e796-46e6-ac80-a9e1246cce47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196205636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.4196205636
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.2424668259
Short name T1162
Test name
Test status
Simulation time 65380228741 ps
CPU time 127.82 seconds
Started Aug 15 06:28:11 PM PDT 24
Finished Aug 15 06:30:19 PM PDT 24
Peak memory 201148 kb
Host smart-41e02e02-9e3f-457e-be70-fe61b8767f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424668259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2424668259
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.832026917
Short name T946
Test name
Test status
Simulation time 14848045389 ps
CPU time 649.55 seconds
Started Aug 15 06:28:12 PM PDT 24
Finished Aug 15 06:39:02 PM PDT 24
Peak memory 200956 kb
Host smart-ae6a2b16-f239-41a1-999d-8b7c70e99dd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=832026917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.832026917
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.3994410262
Short name T1036
Test name
Test status
Simulation time 7136844510 ps
CPU time 16.45 seconds
Started Aug 15 06:28:12 PM PDT 24
Finished Aug 15 06:28:29 PM PDT 24
Peak memory 199288 kb
Host smart-e692be24-59a9-47eb-a59b-5dfdb532f7c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3994410262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3994410262
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.170856367
Short name T140
Test name
Test status
Simulation time 99005203230 ps
CPU time 80.29 seconds
Started Aug 15 06:28:12 PM PDT 24
Finished Aug 15 06:29:32 PM PDT 24
Peak memory 200924 kb
Host smart-6346b83c-293b-4659-b862-1913889edbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170856367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.170856367
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.278856665
Short name T1160
Test name
Test status
Simulation time 31004181442 ps
CPU time 6.1 seconds
Started Aug 15 06:28:12 PM PDT 24
Finished Aug 15 06:28:18 PM PDT 24
Peak memory 197228 kb
Host smart-a9c342e5-7dd1-4057-8cd5-4f3bd3c6be77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278856665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.278856665
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3768799922
Short name T397
Test name
Test status
Simulation time 451433963 ps
CPU time 2.15 seconds
Started Aug 15 06:28:18 PM PDT 24
Finished Aug 15 06:28:20 PM PDT 24
Peak memory 199216 kb
Host smart-30c1ef1d-8fb4-4fc4-ad65-ebc3f29fa0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768799922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3768799922
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1951427258
Short name T36
Test name
Test status
Simulation time 9180809852 ps
CPU time 33.93 seconds
Started Aug 15 06:28:13 PM PDT 24
Finished Aug 15 06:28:47 PM PDT 24
Peak memory 209356 kb
Host smart-74e3c2e2-016e-4999-a484-9cb873e9337e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951427258 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1951427258
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1801483470
Short name T508
Test name
Test status
Simulation time 746591124 ps
CPU time 1.85 seconds
Started Aug 15 06:28:13 PM PDT 24
Finished Aug 15 06:28:15 PM PDT 24
Peak memory 199388 kb
Host smart-7cbf23eb-0cd7-4180-bfb2-feb54175eb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801483470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1801483470
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1293384459
Short name T489
Test name
Test status
Simulation time 41698831529 ps
CPU time 24.23 seconds
Started Aug 15 06:28:18 PM PDT 24
Finished Aug 15 06:28:42 PM PDT 24
Peak memory 200884 kb
Host smart-651f981a-55ee-4cfc-870b-1db75f4d1d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293384459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1293384459
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.267090613
Short name T399
Test name
Test status
Simulation time 47446726 ps
CPU time 0.6 seconds
Started Aug 15 06:28:20 PM PDT 24
Finished Aug 15 06:28:21 PM PDT 24
Peak memory 196280 kb
Host smart-ec94869c-afb9-4e1a-9753-0e365aba3ad3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267090613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.267090613
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.88091632
Short name T632
Test name
Test status
Simulation time 46964823830 ps
CPU time 34.3 seconds
Started Aug 15 06:28:11 PM PDT 24
Finished Aug 15 06:28:45 PM PDT 24
Peak memory 200896 kb
Host smart-492ec516-f523-4e1a-b9c8-0608672d60b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88091632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.88091632
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1703463575
Short name T1047
Test name
Test status
Simulation time 28866671649 ps
CPU time 50.07 seconds
Started Aug 15 06:28:13 PM PDT 24
Finished Aug 15 06:29:04 PM PDT 24
Peak memory 201000 kb
Host smart-4217ad19-e45c-4b25-bd0b-0072601a7497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703463575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1703463575
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.618266292
Short name T1035
Test name
Test status
Simulation time 31740360423 ps
CPU time 11.94 seconds
Started Aug 15 06:28:13 PM PDT 24
Finished Aug 15 06:28:25 PM PDT 24
Peak memory 200384 kb
Host smart-417a6505-eb9e-45d6-8268-9ca58cc0b495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618266292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.618266292
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.4151365699
Short name T883
Test name
Test status
Simulation time 38778896822 ps
CPU time 62.83 seconds
Started Aug 15 06:28:12 PM PDT 24
Finished Aug 15 06:29:15 PM PDT 24
Peak memory 200888 kb
Host smart-877b2891-c2a3-493c-8944-944cf300443f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151365699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.4151365699
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3841313047
Short name T540
Test name
Test status
Simulation time 40738429000 ps
CPU time 69.6 seconds
Started Aug 15 06:28:22 PM PDT 24
Finished Aug 15 06:29:32 PM PDT 24
Peak memory 200980 kb
Host smart-f82f6935-d755-4afe-8b9e-de91f7e2193f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3841313047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3841313047
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1041413508
Short name T543
Test name
Test status
Simulation time 4226064281 ps
CPU time 7.91 seconds
Started Aug 15 06:28:19 PM PDT 24
Finished Aug 15 06:28:27 PM PDT 24
Peak memory 200180 kb
Host smart-266fc887-6980-4a12-8ea0-249d60724c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041413508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1041413508
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.761712117
Short name T1183
Test name
Test status
Simulation time 77151681610 ps
CPU time 151.75 seconds
Started Aug 15 06:28:20 PM PDT 24
Finished Aug 15 06:30:52 PM PDT 24
Peak memory 201124 kb
Host smart-effcd307-cc4e-4a05-805b-08b3f944946e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761712117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.761712117
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2179433899
Short name T1106
Test name
Test status
Simulation time 21447696753 ps
CPU time 617.08 seconds
Started Aug 15 06:28:20 PM PDT 24
Finished Aug 15 06:38:37 PM PDT 24
Peak memory 200952 kb
Host smart-27f0a34c-687b-4cbf-8e96-607f1874dbf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2179433899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2179433899
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3143300629
Short name T1173
Test name
Test status
Simulation time 7335755874 ps
CPU time 33.92 seconds
Started Aug 15 06:28:14 PM PDT 24
Finished Aug 15 06:28:49 PM PDT 24
Peak memory 200200 kb
Host smart-c11ff1d4-224d-458a-89b6-ac4c66ef24bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3143300629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3143300629
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.3942365695
Short name T1131
Test name
Test status
Simulation time 108676734470 ps
CPU time 45.76 seconds
Started Aug 15 06:28:20 PM PDT 24
Finished Aug 15 06:29:06 PM PDT 24
Peak memory 200856 kb
Host smart-ef1a556c-99c1-4529-bf08-0766b1ff7ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942365695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3942365695
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3130244887
Short name T991
Test name
Test status
Simulation time 3332226022 ps
CPU time 1.33 seconds
Started Aug 15 06:28:19 PM PDT 24
Finished Aug 15 06:28:21 PM PDT 24
Peak memory 197372 kb
Host smart-b5af5cc8-2175-4376-ba67-b4e1c5330ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130244887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3130244887
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2308982758
Short name T715
Test name
Test status
Simulation time 5906794800 ps
CPU time 17.86 seconds
Started Aug 15 06:28:15 PM PDT 24
Finished Aug 15 06:28:33 PM PDT 24
Peak memory 200844 kb
Host smart-0a98020e-2677-411a-9ee0-970ffb9e31fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308982758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2308982758
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.101643392
Short name T155
Test name
Test status
Simulation time 389020415421 ps
CPU time 196.7 seconds
Started Aug 15 06:28:19 PM PDT 24
Finished Aug 15 06:31:36 PM PDT 24
Peak memory 200836 kb
Host smart-b76e9eea-9cfa-48ef-a78c-833bb134e769
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101643392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.101643392
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3892577978
Short name T1079
Test name
Test status
Simulation time 17458981231 ps
CPU time 91.42 seconds
Started Aug 15 06:28:19 PM PDT 24
Finished Aug 15 06:29:50 PM PDT 24
Peak memory 217604 kb
Host smart-60bfaa01-7789-4153-94ec-3e8c42586ebd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892577978 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3892577978
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.237001020
Short name T814
Test name
Test status
Simulation time 3295538059 ps
CPU time 1.37 seconds
Started Aug 15 06:28:21 PM PDT 24
Finished Aug 15 06:28:22 PM PDT 24
Peak memory 199924 kb
Host smart-f72fc1c2-a71d-461b-8a36-ae406f60439e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237001020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.237001020
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1671118432
Short name T935
Test name
Test status
Simulation time 157356116559 ps
CPU time 88.87 seconds
Started Aug 15 06:28:12 PM PDT 24
Finished Aug 15 06:29:41 PM PDT 24
Peak memory 200968 kb
Host smart-da0126c1-e3c9-4726-bb01-5ca7f6086c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671118432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1671118432
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3635035315
Short name T924
Test name
Test status
Simulation time 22552535 ps
CPU time 0.57 seconds
Started Aug 15 06:28:27 PM PDT 24
Finished Aug 15 06:28:28 PM PDT 24
Peak memory 196540 kb
Host smart-c86060f5-3ed7-43bc-b07c-15b0b74e92b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635035315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3635035315
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2758654397
Short name T993
Test name
Test status
Simulation time 329525183171 ps
CPU time 136.78 seconds
Started Aug 15 06:28:17 PM PDT 24
Finished Aug 15 06:30:34 PM PDT 24
Peak memory 200908 kb
Host smart-8addeb0d-91ac-400a-974c-d463c4655df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758654397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2758654397
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.331828187
Short name T1149
Test name
Test status
Simulation time 69115713737 ps
CPU time 33.69 seconds
Started Aug 15 06:28:24 PM PDT 24
Finished Aug 15 06:28:57 PM PDT 24
Peak memory 200952 kb
Host smart-f3ca6eb4-c9e0-4029-b835-76683e5c6432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331828187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.331828187
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.4118012743
Short name T338
Test name
Test status
Simulation time 37114633805 ps
CPU time 82.85 seconds
Started Aug 15 06:28:17 PM PDT 24
Finished Aug 15 06:29:40 PM PDT 24
Peak memory 200828 kb
Host smart-ea3e59a7-bd58-4e72-804c-d7c4eb2b2bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118012743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.4118012743
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.2235717993
Short name T683
Test name
Test status
Simulation time 56289120486 ps
CPU time 94.54 seconds
Started Aug 15 06:28:20 PM PDT 24
Finished Aug 15 06:29:54 PM PDT 24
Peak memory 200904 kb
Host smart-5ededfef-4329-458a-adda-0fadb4ef87ed
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235717993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2235717993
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.455107797
Short name T497
Test name
Test status
Simulation time 134130564070 ps
CPU time 622.48 seconds
Started Aug 15 06:28:28 PM PDT 24
Finished Aug 15 06:38:51 PM PDT 24
Peak memory 200916 kb
Host smart-86987dd2-e255-4e53-bfaa-6df34ae35101
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=455107797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.455107797
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.722447197
Short name T345
Test name
Test status
Simulation time 6843049946 ps
CPU time 20.8 seconds
Started Aug 15 06:28:28 PM PDT 24
Finished Aug 15 06:28:49 PM PDT 24
Peak memory 200864 kb
Host smart-7b0d48b6-196d-4e43-873f-375302eb5436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722447197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.722447197
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.760248709
Short name T593
Test name
Test status
Simulation time 43192228818 ps
CPU time 73.38 seconds
Started Aug 15 06:28:21 PM PDT 24
Finished Aug 15 06:29:35 PM PDT 24
Peak memory 200744 kb
Host smart-2e567fa7-5520-4678-ad72-a164b6725ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760248709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.760248709
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.300619728
Short name T529
Test name
Test status
Simulation time 28924859232 ps
CPU time 303.59 seconds
Started Aug 15 06:28:26 PM PDT 24
Finished Aug 15 06:33:30 PM PDT 24
Peak memory 200972 kb
Host smart-a672ba65-cff1-401e-bcd9-c8da6426c2cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=300619728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.300619728
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.2871498462
Short name T366
Test name
Test status
Simulation time 1171362530 ps
CPU time 1.47 seconds
Started Aug 15 06:28:23 PM PDT 24
Finished Aug 15 06:28:24 PM PDT 24
Peak memory 197672 kb
Host smart-6de3a51d-207b-4277-9cd0-d84fd9d91559
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2871498462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.2871498462
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2655604121
Short name T573
Test name
Test status
Simulation time 128380763282 ps
CPU time 129.83 seconds
Started Aug 15 06:28:26 PM PDT 24
Finished Aug 15 06:30:36 PM PDT 24
Peak memory 200964 kb
Host smart-67ee9d03-dde8-4468-b1ca-b5f44aeb6908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655604121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2655604121
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.2094895360
Short name T521
Test name
Test status
Simulation time 4011617525 ps
CPU time 6.77 seconds
Started Aug 15 06:28:25 PM PDT 24
Finished Aug 15 06:28:32 PM PDT 24
Peak memory 197076 kb
Host smart-95d7759c-86e5-4788-9a9a-90e363be0d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094895360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2094895360
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1997372768
Short name T675
Test name
Test status
Simulation time 10546093846 ps
CPU time 16.45 seconds
Started Aug 15 06:28:18 PM PDT 24
Finished Aug 15 06:28:35 PM PDT 24
Peak memory 200872 kb
Host smart-bfa14585-3f09-4bb2-9fdc-131ed372557d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997372768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1997372768
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.4070479337
Short name T641
Test name
Test status
Simulation time 2505808652 ps
CPU time 8.34 seconds
Started Aug 15 06:28:29 PM PDT 24
Finished Aug 15 06:28:37 PM PDT 24
Peak memory 199720 kb
Host smart-90727cba-f388-4508-a868-1d3acaf4ea7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070479337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.4070479337
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1701307479
Short name T96
Test name
Test status
Simulation time 2376617216 ps
CPU time 23.7 seconds
Started Aug 15 06:28:27 PM PDT 24
Finished Aug 15 06:28:51 PM PDT 24
Peak memory 209400 kb
Host smart-2ebe1f78-5541-4b70-89e7-53d27fd368da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701307479 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1701307479
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2603815366
Short name T298
Test name
Test status
Simulation time 6504336759 ps
CPU time 29.95 seconds
Started Aug 15 06:28:26 PM PDT 24
Finished Aug 15 06:28:56 PM PDT 24
Peak memory 200344 kb
Host smart-d6818516-9137-4ad9-a3dc-efd1bb9541f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603815366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2603815366
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.285689046
Short name T751
Test name
Test status
Simulation time 66437715189 ps
CPU time 73.06 seconds
Started Aug 15 06:28:21 PM PDT 24
Finished Aug 15 06:29:34 PM PDT 24
Peak memory 200896 kb
Host smart-abb24ad9-cee2-44f5-bb0a-a914d9404fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285689046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.285689046
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.3231848902
Short name T505
Test name
Test status
Simulation time 13471278 ps
CPU time 0.57 seconds
Started Aug 15 06:28:41 PM PDT 24
Finished Aug 15 06:28:42 PM PDT 24
Peak memory 196212 kb
Host smart-df64af2e-3afe-480c-a9e9-a81ac0db28d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231848902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3231848902
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3183034297
Short name T1055
Test name
Test status
Simulation time 108269661614 ps
CPU time 185.17 seconds
Started Aug 15 06:28:27 PM PDT 24
Finished Aug 15 06:31:32 PM PDT 24
Peak memory 200884 kb
Host smart-32e9cd7e-4e01-43a5-ae56-104eb3d7cb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183034297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3183034297
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.1569908515
Short name T176
Test name
Test status
Simulation time 195498647911 ps
CPU time 29.92 seconds
Started Aug 15 06:28:35 PM PDT 24
Finished Aug 15 06:29:05 PM PDT 24
Peak memory 200976 kb
Host smart-2e4e9d54-845c-48ab-bf72-ff02df076033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569908515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1569908515
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.2218991060
Short name T405
Test name
Test status
Simulation time 58251340931 ps
CPU time 38.76 seconds
Started Aug 15 06:28:36 PM PDT 24
Finished Aug 15 06:29:15 PM PDT 24
Peak memory 200952 kb
Host smart-08e76102-6b90-43a6-8516-8d5ff67cc50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218991060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2218991060
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2642094608
Short name T409
Test name
Test status
Simulation time 21487215641 ps
CPU time 5.47 seconds
Started Aug 15 06:28:35 PM PDT 24
Finished Aug 15 06:28:41 PM PDT 24
Peak memory 200804 kb
Host smart-45ddfc10-8a3b-497e-83bc-b9076536d805
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642094608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2642094608
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.688468723
Short name T909
Test name
Test status
Simulation time 119654186902 ps
CPU time 725.3 seconds
Started Aug 15 06:28:34 PM PDT 24
Finished Aug 15 06:40:39 PM PDT 24
Peak memory 200944 kb
Host smart-50fad9e2-59f6-409c-8f5d-53cadeaf86fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=688468723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.688468723
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.1244293376
Short name T22
Test name
Test status
Simulation time 1274378115 ps
CPU time 1.27 seconds
Started Aug 15 06:28:35 PM PDT 24
Finished Aug 15 06:28:36 PM PDT 24
Peak memory 197080 kb
Host smart-b7c42ce0-86a1-4041-a6fa-08c5ff47a906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244293376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1244293376
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.4216044449
Short name T1084
Test name
Test status
Simulation time 17656702495 ps
CPU time 25.69 seconds
Started Aug 15 06:28:36 PM PDT 24
Finished Aug 15 06:29:01 PM PDT 24
Peak memory 201008 kb
Host smart-41520ff3-6161-4203-8321-b62f46cd1ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216044449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.4216044449
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.1324652513
Short name T587
Test name
Test status
Simulation time 11968795610 ps
CPU time 693.72 seconds
Started Aug 15 06:28:37 PM PDT 24
Finished Aug 15 06:40:11 PM PDT 24
Peak memory 200824 kb
Host smart-f2b1a7b6-755e-4513-aecf-49fb6aa57a6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1324652513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1324652513
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.1236451601
Short name T360
Test name
Test status
Simulation time 2319414369 ps
CPU time 13.24 seconds
Started Aug 15 06:28:36 PM PDT 24
Finished Aug 15 06:28:50 PM PDT 24
Peak memory 199352 kb
Host smart-03708bac-9a2c-4f83-a7ff-09b135cf5118
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1236451601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.1236451601
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.2951350908
Short name T474
Test name
Test status
Simulation time 33324956173 ps
CPU time 7.24 seconds
Started Aug 15 06:28:34 PM PDT 24
Finished Aug 15 06:28:41 PM PDT 24
Peak memory 200924 kb
Host smart-a6fda6cd-1055-4127-9e4b-04f238578e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951350908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2951350908
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.2469316045
Short name T1184
Test name
Test status
Simulation time 3723704052 ps
CPU time 3.25 seconds
Started Aug 15 06:28:35 PM PDT 24
Finished Aug 15 06:28:39 PM PDT 24
Peak memory 197264 kb
Host smart-6dde00ee-54bf-4e82-916a-1da77b8e893f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469316045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2469316045
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3754671015
Short name T550
Test name
Test status
Simulation time 436798925 ps
CPU time 1.41 seconds
Started Aug 15 06:28:26 PM PDT 24
Finished Aug 15 06:28:27 PM PDT 24
Peak memory 199292 kb
Host smart-27d04b16-d169-4029-bd5d-29da07243177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754671015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3754671015
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1224620280
Short name T893
Test name
Test status
Simulation time 3505181376 ps
CPU time 40.87 seconds
Started Aug 15 06:28:35 PM PDT 24
Finished Aug 15 06:29:16 PM PDT 24
Peak memory 209416 kb
Host smart-c974a0a0-e6f2-4286-a977-0eddb0abc32c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224620280 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1224620280
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.225917171
Short name T1154
Test name
Test status
Simulation time 706916278 ps
CPU time 3.02 seconds
Started Aug 15 06:28:40 PM PDT 24
Finished Aug 15 06:28:43 PM PDT 24
Peak memory 199636 kb
Host smart-0c4b5229-3477-47e4-9eda-20b4aad23d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225917171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.225917171
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.3258904053
Short name T732
Test name
Test status
Simulation time 41710331853 ps
CPU time 137.52 seconds
Started Aug 15 06:28:27 PM PDT 24
Finished Aug 15 06:30:45 PM PDT 24
Peak memory 200924 kb
Host smart-b1ec71cf-d5f6-4589-8ea2-d5ed2d985d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258904053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3258904053
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2122138002
Short name T1110
Test name
Test status
Simulation time 14776418 ps
CPU time 0.55 seconds
Started Aug 15 06:28:41 PM PDT 24
Finished Aug 15 06:28:42 PM PDT 24
Peak memory 196540 kb
Host smart-45f9a03c-3291-4292-95f7-923cd27c7598
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122138002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2122138002
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.673747844
Short name T668
Test name
Test status
Simulation time 64555930769 ps
CPU time 20.11 seconds
Started Aug 15 06:28:34 PM PDT 24
Finished Aug 15 06:28:55 PM PDT 24
Peak memory 200952 kb
Host smart-495860c2-29db-4e17-a9ba-3e9555ba62ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673747844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.673747844
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3087046300
Short name T915
Test name
Test status
Simulation time 73681952583 ps
CPU time 146.16 seconds
Started Aug 15 06:28:34 PM PDT 24
Finished Aug 15 06:31:01 PM PDT 24
Peak memory 200928 kb
Host smart-62175fce-bb93-4693-addb-cfcb8e50f612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087046300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3087046300
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.1173059764
Short name T193
Test name
Test status
Simulation time 27480006749 ps
CPU time 38.05 seconds
Started Aug 15 06:28:40 PM PDT 24
Finished Aug 15 06:29:18 PM PDT 24
Peak memory 200908 kb
Host smart-c6d0a2cc-8b46-4d6e-80ce-362dbb12cebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173059764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1173059764
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3496815880
Short name T527
Test name
Test status
Simulation time 48386852208 ps
CPU time 35.63 seconds
Started Aug 15 06:28:41 PM PDT 24
Finished Aug 15 06:29:17 PM PDT 24
Peak memory 200972 kb
Host smart-17f0605f-bb9b-47d4-82ef-e50ec9ab8359
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496815880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3496815880
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.4184637882
Short name T843
Test name
Test status
Simulation time 294960968149 ps
CPU time 150.25 seconds
Started Aug 15 06:28:36 PM PDT 24
Finished Aug 15 06:31:07 PM PDT 24
Peak memory 200872 kb
Host smart-f93c673e-2e6f-4752-ac32-65cb74d53e21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4184637882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.4184637882
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.2916356329
Short name T794
Test name
Test status
Simulation time 5309375103 ps
CPU time 10.08 seconds
Started Aug 15 06:28:34 PM PDT 24
Finished Aug 15 06:28:44 PM PDT 24
Peak memory 199992 kb
Host smart-ae275606-abcd-43b8-8967-c1c6450dc934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916356329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2916356329
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.2694967841
Short name T262
Test name
Test status
Simulation time 74069917325 ps
CPU time 29.11 seconds
Started Aug 15 06:28:35 PM PDT 24
Finished Aug 15 06:29:04 PM PDT 24
Peak memory 201024 kb
Host smart-3a2ab663-1c69-4d63-860f-92ca742544c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694967841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.2694967841
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.559971515
Short name T1032
Test name
Test status
Simulation time 27233911741 ps
CPU time 1522.04 seconds
Started Aug 15 06:28:32 PM PDT 24
Finished Aug 15 06:53:55 PM PDT 24
Peak memory 200924 kb
Host smart-b1d63e14-61c1-495c-a75d-7df29dd783a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=559971515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.559971515
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.3406119837
Short name T1014
Test name
Test status
Simulation time 3610405005 ps
CPU time 24.42 seconds
Started Aug 15 06:28:36 PM PDT 24
Finished Aug 15 06:29:01 PM PDT 24
Peak memory 199992 kb
Host smart-f29cbee7-c252-4d81-81d0-a20c895527a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3406119837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.3406119837
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.3556348494
Short name T541
Test name
Test status
Simulation time 199340804139 ps
CPU time 109.37 seconds
Started Aug 15 06:28:33 PM PDT 24
Finished Aug 15 06:30:22 PM PDT 24
Peak memory 200968 kb
Host smart-856f1c19-c4a9-461a-b495-59fe6059d651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556348494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3556348494
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1063671309
Short name T311
Test name
Test status
Simulation time 5713362211 ps
CPU time 6.43 seconds
Started Aug 15 06:28:41 PM PDT 24
Finished Aug 15 06:28:48 PM PDT 24
Peak memory 197100 kb
Host smart-85f049a8-997e-4ec7-831e-0a2b64e8c8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063671309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1063671309
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3484082475
Short name T889
Test name
Test status
Simulation time 711970885 ps
CPU time 2.58 seconds
Started Aug 15 06:28:34 PM PDT 24
Finished Aug 15 06:28:36 PM PDT 24
Peak memory 200408 kb
Host smart-1b868f80-0fa8-4119-95b6-f735bdc99db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484082475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3484082475
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.1741410301
Short name T640
Test name
Test status
Simulation time 280962267062 ps
CPU time 488.14 seconds
Started Aug 15 06:28:42 PM PDT 24
Finished Aug 15 06:36:50 PM PDT 24
Peak memory 209332 kb
Host smart-55b5a69a-62dd-4136-97a0-5de09e5f0726
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741410301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1741410301
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1960418354
Short name T1108
Test name
Test status
Simulation time 18111380969 ps
CPU time 80.05 seconds
Started Aug 15 06:28:43 PM PDT 24
Finished Aug 15 06:30:03 PM PDT 24
Peak memory 216600 kb
Host smart-51627723-4f53-4a74-805b-a542b5cff163
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960418354 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1960418354
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2595427390
Short name T430
Test name
Test status
Simulation time 1265354018 ps
CPU time 2.46 seconds
Started Aug 15 06:28:37 PM PDT 24
Finished Aug 15 06:28:39 PM PDT 24
Peak memory 199732 kb
Host smart-eb9883b5-6e8f-493b-ad8e-c010e5f2c3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595427390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2595427390
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.3910522436
Short name T737
Test name
Test status
Simulation time 96664008452 ps
CPU time 41.57 seconds
Started Aug 15 06:28:34 PM PDT 24
Finished Aug 15 06:29:15 PM PDT 24
Peak memory 200924 kb
Host smart-0274d8b8-ede2-43a5-bea9-d48c3c23e534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910522436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3910522436
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2700708152
Short name T879
Test name
Test status
Simulation time 37980750 ps
CPU time 0.57 seconds
Started Aug 15 06:28:43 PM PDT 24
Finished Aug 15 06:28:43 PM PDT 24
Peak memory 196248 kb
Host smart-eae0a433-2848-412a-9af5-6f962ebaa4ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700708152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2700708152
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.838604066
Short name T291
Test name
Test status
Simulation time 27396554126 ps
CPU time 49.61 seconds
Started Aug 15 06:28:42 PM PDT 24
Finished Aug 15 06:29:32 PM PDT 24
Peak memory 200896 kb
Host smart-5bfdd432-ccb7-411b-b732-6cb818a785de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838604066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.838604066
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.1883387262
Short name T628
Test name
Test status
Simulation time 40825592587 ps
CPU time 19.37 seconds
Started Aug 15 06:28:47 PM PDT 24
Finished Aug 15 06:29:06 PM PDT 24
Peak memory 200872 kb
Host smart-74a16db7-ac43-4416-8f43-1bff28f0f4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883387262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1883387262
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.3747872349
Short name T614
Test name
Test status
Simulation time 87871586074 ps
CPU time 115.37 seconds
Started Aug 15 06:28:44 PM PDT 24
Finished Aug 15 06:30:39 PM PDT 24
Peak memory 200876 kb
Host smart-9b4f90e6-c34d-4933-9ac9-47e90162724d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747872349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3747872349
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.3613220366
Short name T320
Test name
Test status
Simulation time 8997577355 ps
CPU time 3.96 seconds
Started Aug 15 06:28:42 PM PDT 24
Finished Aug 15 06:28:46 PM PDT 24
Peak memory 198460 kb
Host smart-4467f7dc-a001-4893-9cb7-f7b25c3e6446
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613220366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3613220366
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.216909195
Short name T881
Test name
Test status
Simulation time 95131392971 ps
CPU time 244.7 seconds
Started Aug 15 06:28:44 PM PDT 24
Finished Aug 15 06:32:48 PM PDT 24
Peak memory 200812 kb
Host smart-efd636bc-ce4d-41e4-ace8-b1577403b77b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=216909195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.216909195
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.314549337
Short name T372
Test name
Test status
Simulation time 10650311745 ps
CPU time 19.42 seconds
Started Aug 15 06:28:46 PM PDT 24
Finished Aug 15 06:29:05 PM PDT 24
Peak memory 200440 kb
Host smart-80eb397f-14fe-4646-bd86-5eb12b900c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314549337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.314549337
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.2318107502
Short name T959
Test name
Test status
Simulation time 200213624432 ps
CPU time 117.58 seconds
Started Aug 15 06:28:41 PM PDT 24
Finished Aug 15 06:30:38 PM PDT 24
Peak memory 200988 kb
Host smart-e9b2049a-2f79-428f-a0d6-94462cc0bcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318107502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2318107502
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.2383148273
Short name T1066
Test name
Test status
Simulation time 9145120792 ps
CPU time 415.51 seconds
Started Aug 15 06:28:45 PM PDT 24
Finished Aug 15 06:35:40 PM PDT 24
Peak memory 200912 kb
Host smart-f8cae859-d908-438b-b675-1bae59cb56ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2383148273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2383148273
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.280625198
Short name T917
Test name
Test status
Simulation time 6311076712 ps
CPU time 27.66 seconds
Started Aug 15 06:28:42 PM PDT 24
Finished Aug 15 06:29:10 PM PDT 24
Peak memory 199112 kb
Host smart-0abadb75-430c-460b-8bca-439826479bbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=280625198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.280625198
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1759000694
Short name T453
Test name
Test status
Simulation time 35967805892 ps
CPU time 15.73 seconds
Started Aug 15 06:28:42 PM PDT 24
Finished Aug 15 06:28:57 PM PDT 24
Peak memory 200908 kb
Host smart-f416c2cb-42fc-4aa3-bb8a-36f58321cda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759000694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1759000694
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.474433103
Short name T578
Test name
Test status
Simulation time 50587244933 ps
CPU time 68.06 seconds
Started Aug 15 06:28:44 PM PDT 24
Finished Aug 15 06:29:52 PM PDT 24
Peak memory 196824 kb
Host smart-c5cfb725-7a06-4fda-9562-f6e9cc6a52b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474433103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.474433103
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1370272049
Short name T295
Test name
Test status
Simulation time 6204466051 ps
CPU time 10.62 seconds
Started Aug 15 06:28:43 PM PDT 24
Finished Aug 15 06:28:53 PM PDT 24
Peak memory 200676 kb
Host smart-0f154dc0-43d9-487f-b0bd-ce9e683c2187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370272049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1370272049
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2618676181
Short name T647
Test name
Test status
Simulation time 239617124552 ps
CPU time 2297.03 seconds
Started Aug 15 06:28:41 PM PDT 24
Finished Aug 15 07:06:58 PM PDT 24
Peak memory 209260 kb
Host smart-08e18bdc-38be-4ba0-aca1-ebeff30f4c14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618676181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2618676181
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.931490005
Short name T1041
Test name
Test status
Simulation time 4726618830 ps
CPU time 53.61 seconds
Started Aug 15 06:28:45 PM PDT 24
Finished Aug 15 06:29:39 PM PDT 24
Peak memory 217400 kb
Host smart-2ba037c5-9950-466f-998c-1e7af99774ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931490005 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.931490005
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3054676164
Short name T459
Test name
Test status
Simulation time 988252470 ps
CPU time 1.64 seconds
Started Aug 15 06:28:41 PM PDT 24
Finished Aug 15 06:28:43 PM PDT 24
Peak memory 199888 kb
Host smart-c220e995-9ea4-4d35-bf12-7ab047585fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054676164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3054676164
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2287194348
Short name T1144
Test name
Test status
Simulation time 73302315388 ps
CPU time 22.58 seconds
Started Aug 15 06:28:41 PM PDT 24
Finished Aug 15 06:29:04 PM PDT 24
Peak memory 200904 kb
Host smart-c366ce19-11c5-4c38-869f-038d0745e38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287194348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2287194348
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.4125360550
Short name T923
Test name
Test status
Simulation time 13721653 ps
CPU time 0.55 seconds
Started Aug 15 06:25:18 PM PDT 24
Finished Aug 15 06:25:19 PM PDT 24
Peak memory 196492 kb
Host smart-3498a263-ae98-44aa-ad74-a29d7c851bc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125360550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.4125360550
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.93094969
Short name T838
Test name
Test status
Simulation time 38765451105 ps
CPU time 68.24 seconds
Started Aug 15 06:25:20 PM PDT 24
Finished Aug 15 06:26:28 PM PDT 24
Peak memory 200936 kb
Host smart-6aef5d8c-2434-4b92-8b33-c151fc2fb4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93094969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.93094969
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.2257436988
Short name T280
Test name
Test status
Simulation time 335606374355 ps
CPU time 160.9 seconds
Started Aug 15 06:25:21 PM PDT 24
Finished Aug 15 06:28:02 PM PDT 24
Peak memory 200896 kb
Host smart-e8913027-3385-498f-9da3-c6d8c397fbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257436988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.2257436988
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.679270408
Short name T204
Test name
Test status
Simulation time 95421034077 ps
CPU time 67.62 seconds
Started Aug 15 06:25:18 PM PDT 24
Finished Aug 15 06:26:26 PM PDT 24
Peak memory 200912 kb
Host smart-d0ebc24b-5b9e-499b-86fe-92ace0f1ebbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679270408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.679270408
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.1735489645
Short name T498
Test name
Test status
Simulation time 36317049264 ps
CPU time 5.78 seconds
Started Aug 15 06:25:17 PM PDT 24
Finished Aug 15 06:25:23 PM PDT 24
Peak memory 200972 kb
Host smart-475e2b47-25cb-4e2b-b2ed-fb634b6b13ff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735489645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1735489645
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3097010315
Short name T431
Test name
Test status
Simulation time 171112994784 ps
CPU time 469.76 seconds
Started Aug 15 06:25:19 PM PDT 24
Finished Aug 15 06:33:09 PM PDT 24
Peak memory 200928 kb
Host smart-e4ce4d02-5204-4ef8-a0ac-5cd06107aa4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3097010315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3097010315
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.1680790724
Short name T616
Test name
Test status
Simulation time 4375848071 ps
CPU time 2.89 seconds
Started Aug 15 06:25:19 PM PDT 24
Finished Aug 15 06:25:22 PM PDT 24
Peak memory 200844 kb
Host smart-e7bbc49d-7b88-4bc4-be69-bd0481b25d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680790724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1680790724
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.357178047
Short name T581
Test name
Test status
Simulation time 11496501546 ps
CPU time 5.88 seconds
Started Aug 15 06:25:18 PM PDT 24
Finished Aug 15 06:25:24 PM PDT 24
Peak memory 199144 kb
Host smart-1cadabec-69c1-4e86-abab-0c027e1e4c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357178047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.357178047
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.2820819962
Short name T728
Test name
Test status
Simulation time 12983169200 ps
CPU time 598.54 seconds
Started Aug 15 06:25:18 PM PDT 24
Finished Aug 15 06:35:17 PM PDT 24
Peak memory 200876 kb
Host smart-4bbec9df-4d99-4e94-a30c-e6198d2c47fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2820819962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2820819962
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2553775269
Short name T718
Test name
Test status
Simulation time 2238704207 ps
CPU time 1.33 seconds
Started Aug 15 06:25:19 PM PDT 24
Finished Aug 15 06:25:20 PM PDT 24
Peak memory 199076 kb
Host smart-6823a223-684c-48c4-9096-e379a99e6948
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2553775269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2553775269
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.959406626
Short name T183
Test name
Test status
Simulation time 117580216721 ps
CPU time 173.58 seconds
Started Aug 15 06:25:19 PM PDT 24
Finished Aug 15 06:28:13 PM PDT 24
Peak memory 200956 kb
Host smart-c144a22e-88b2-41dd-bf88-a97472a8df7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959406626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.959406626
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2434430584
Short name T265
Test name
Test status
Simulation time 34188240345 ps
CPU time 49.29 seconds
Started Aug 15 06:25:20 PM PDT 24
Finished Aug 15 06:26:10 PM PDT 24
Peak memory 196752 kb
Host smart-929421d4-49d4-45c5-9681-be494ddc6a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434430584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2434430584
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.571129756
Short name T30
Test name
Test status
Simulation time 412680887 ps
CPU time 0.89 seconds
Started Aug 15 06:25:19 PM PDT 24
Finished Aug 15 06:25:20 PM PDT 24
Peak memory 218960 kb
Host smart-bc424e79-7882-4f19-b86f-df1ed03cd7e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571129756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.571129756
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.888720359
Short name T42
Test name
Test status
Simulation time 682280382 ps
CPU time 1.7 seconds
Started Aug 15 06:25:09 PM PDT 24
Finished Aug 15 06:25:11 PM PDT 24
Peak memory 200820 kb
Host smart-871bea39-f6d1-49a1-adbb-b5f220555653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888720359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.888720359
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.4282084064
Short name T450
Test name
Test status
Simulation time 226190735844 ps
CPU time 233.02 seconds
Started Aug 15 06:25:18 PM PDT 24
Finished Aug 15 06:29:11 PM PDT 24
Peak memory 201116 kb
Host smart-045645f4-3ce1-4153-b497-4d95f54e7b60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282084064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.4282084064
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.1503874770
Short name T656
Test name
Test status
Simulation time 2070156586 ps
CPU time 13.43 seconds
Started Aug 15 06:25:18 PM PDT 24
Finished Aug 15 06:25:32 PM PDT 24
Peak memory 200928 kb
Host smart-407b3fbe-42a9-41d9-9de1-817e61107840
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503874770 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1503874770
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.389242173
Short name T965
Test name
Test status
Simulation time 539857381 ps
CPU time 1.73 seconds
Started Aug 15 06:25:21 PM PDT 24
Finished Aug 15 06:25:23 PM PDT 24
Peak memory 199696 kb
Host smart-51e0c6b8-aa55-4f69-b7a2-d0e3a814273f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389242173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.389242173
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3843905453
Short name T696
Test name
Test status
Simulation time 82545992091 ps
CPU time 26.13 seconds
Started Aug 15 06:25:17 PM PDT 24
Finished Aug 15 06:25:44 PM PDT 24
Peak memory 200876 kb
Host smart-69928403-4abb-41b0-929b-a2faa1ac156c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843905453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3843905453
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.3338166388
Short name T812
Test name
Test status
Simulation time 38560586 ps
CPU time 0.59 seconds
Started Aug 15 06:28:49 PM PDT 24
Finished Aug 15 06:28:50 PM PDT 24
Peak memory 196276 kb
Host smart-063902db-cb60-4735-88b3-69a9a56d0667
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338166388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3338166388
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3581444438
Short name T1021
Test name
Test status
Simulation time 228543895395 ps
CPU time 167 seconds
Started Aug 15 06:28:43 PM PDT 24
Finished Aug 15 06:31:31 PM PDT 24
Peak memory 200900 kb
Host smart-a8f2e2ac-de95-41ea-9289-31e0265bd1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581444438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3581444438
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.3438523718
Short name T719
Test name
Test status
Simulation time 73963604873 ps
CPU time 121.15 seconds
Started Aug 15 06:28:51 PM PDT 24
Finished Aug 15 06:30:52 PM PDT 24
Peak memory 200880 kb
Host smart-2129866c-264e-4a8c-ba40-f687a8b14b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438523718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3438523718
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.1353786087
Short name T566
Test name
Test status
Simulation time 68660083077 ps
CPU time 86.61 seconds
Started Aug 15 06:28:48 PM PDT 24
Finished Aug 15 06:30:15 PM PDT 24
Peak memory 200948 kb
Host smart-9ac47c3b-cf11-4ece-84f4-4fc944529b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353786087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1353786087
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.2147611338
Short name T866
Test name
Test status
Simulation time 273868595130 ps
CPU time 397.17 seconds
Started Aug 15 06:28:49 PM PDT 24
Finished Aug 15 06:35:27 PM PDT 24
Peak memory 197952 kb
Host smart-85eed5c3-09cd-4869-b0af-44c238cec0b7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147611338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2147611338
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.504084632
Short name T470
Test name
Test status
Simulation time 71638819048 ps
CPU time 484.67 seconds
Started Aug 15 06:28:51 PM PDT 24
Finished Aug 15 06:36:56 PM PDT 24
Peak memory 200956 kb
Host smart-299a8c96-1d56-41c4-b299-faf1c5a53849
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=504084632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.504084632
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.212757967
Short name T435
Test name
Test status
Simulation time 7901388763 ps
CPU time 15.1 seconds
Started Aug 15 06:28:54 PM PDT 24
Finished Aug 15 06:29:09 PM PDT 24
Peak memory 199824 kb
Host smart-3e97558d-edab-4f63-8f40-1912c14e2ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212757967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.212757967
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.734631960
Short name T313
Test name
Test status
Simulation time 210627269507 ps
CPU time 52.43 seconds
Started Aug 15 06:28:48 PM PDT 24
Finished Aug 15 06:29:40 PM PDT 24
Peak memory 209280 kb
Host smart-a50012cc-50f6-4a8e-8378-2f84c92724e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734631960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.734631960
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.3201011606
Short name T811
Test name
Test status
Simulation time 5101581033 ps
CPU time 82.97 seconds
Started Aug 15 06:28:47 PM PDT 24
Finished Aug 15 06:30:10 PM PDT 24
Peak memory 200688 kb
Host smart-10f18e73-39b7-4fb7-b2ac-12c610c4b670
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3201011606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3201011606
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.2763157009
Short name T1046
Test name
Test status
Simulation time 5871939109 ps
CPU time 23.31 seconds
Started Aug 15 06:28:48 PM PDT 24
Finished Aug 15 06:29:11 PM PDT 24
Peak memory 200828 kb
Host smart-47785a24-aef5-4360-a61c-3ecd5a6ef4d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2763157009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2763157009
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3447629100
Short name T688
Test name
Test status
Simulation time 14240381841 ps
CPU time 11.4 seconds
Started Aug 15 06:28:49 PM PDT 24
Finished Aug 15 06:29:01 PM PDT 24
Peak memory 200688 kb
Host smart-c6be6c57-5d8a-4f39-9fd3-4c411935afb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447629100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3447629100
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2626804474
Short name T289
Test name
Test status
Simulation time 6643378627 ps
CPU time 5.3 seconds
Started Aug 15 06:28:50 PM PDT 24
Finished Aug 15 06:28:55 PM PDT 24
Peak memory 197264 kb
Host smart-3fb0ba78-4e31-4de2-8ac2-4cce9e1b2ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626804474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2626804474
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.642914210
Short name T426
Test name
Test status
Simulation time 316031962 ps
CPU time 1.44 seconds
Started Aug 15 06:28:46 PM PDT 24
Finished Aug 15 06:28:48 PM PDT 24
Peak memory 200852 kb
Host smart-1146a0d4-8e3f-426f-93b0-6fb06fd604df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642914210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.642914210
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.3631118290
Short name T1073
Test name
Test status
Simulation time 90677687069 ps
CPU time 657.09 seconds
Started Aug 15 06:28:51 PM PDT 24
Finished Aug 15 06:39:48 PM PDT 24
Peak memory 200880 kb
Host smart-084bb9fd-4516-4c8d-9256-701bddeddd0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631118290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3631118290
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.1819602661
Short name T756
Test name
Test status
Simulation time 10101488060 ps
CPU time 60 seconds
Started Aug 15 06:28:49 PM PDT 24
Finished Aug 15 06:29:49 PM PDT 24
Peak memory 217392 kb
Host smart-d704cebc-4987-4806-966b-9204ed832777
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819602661 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.1819602661
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.4101159007
Short name T962
Test name
Test status
Simulation time 807055855 ps
CPU time 2.67 seconds
Started Aug 15 06:28:48 PM PDT 24
Finished Aug 15 06:28:51 PM PDT 24
Peak memory 200536 kb
Host smart-4d0bf84a-ebe7-43b9-b417-8cc067cbfd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101159007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.4101159007
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.338267532
Short name T760
Test name
Test status
Simulation time 40748255397 ps
CPU time 40.44 seconds
Started Aug 15 06:28:45 PM PDT 24
Finished Aug 15 06:29:25 PM PDT 24
Peak memory 200880 kb
Host smart-9f32d81d-dd56-4719-a8fd-4174b818c0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338267532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.338267532
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1512437039
Short name T410
Test name
Test status
Simulation time 23983949 ps
CPU time 0.55 seconds
Started Aug 15 06:28:55 PM PDT 24
Finished Aug 15 06:28:56 PM PDT 24
Peak memory 196232 kb
Host smart-22a17ba4-f696-4541-b89a-0ded6b5295ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512437039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1512437039
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2116352252
Short name T1179
Test name
Test status
Simulation time 50186662537 ps
CPU time 70.99 seconds
Started Aug 15 06:28:49 PM PDT 24
Finished Aug 15 06:30:00 PM PDT 24
Peak memory 200908 kb
Host smart-25f1a84c-6789-4bf9-a0e0-519e65366811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116352252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2116352252
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.1968243115
Short name T134
Test name
Test status
Simulation time 15956384640 ps
CPU time 25.97 seconds
Started Aug 15 06:28:51 PM PDT 24
Finished Aug 15 06:29:17 PM PDT 24
Peak memory 200904 kb
Host smart-7acda657-69ed-418b-993e-fb9e5da2a90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968243115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1968243115
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2860136909
Short name T406
Test name
Test status
Simulation time 52141949404 ps
CPU time 12.83 seconds
Started Aug 15 06:28:48 PM PDT 24
Finished Aug 15 06:29:01 PM PDT 24
Peak memory 197304 kb
Host smart-7a2eb3d7-f456-434e-8d95-6f2f97541ee1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860136909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2860136909
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.4146831262
Short name T630
Test name
Test status
Simulation time 137640918350 ps
CPU time 191.76 seconds
Started Aug 15 06:28:55 PM PDT 24
Finished Aug 15 06:32:07 PM PDT 24
Peak memory 201080 kb
Host smart-0ec69c2a-57ce-4bba-b946-4f1896df33ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4146831262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.4146831262
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1188247469
Short name T574
Test name
Test status
Simulation time 8502715428 ps
CPU time 5.6 seconds
Started Aug 15 06:28:53 PM PDT 24
Finished Aug 15 06:28:59 PM PDT 24
Peak memory 199492 kb
Host smart-0b7d03b5-6001-45e3-8c81-f22d4eb78678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188247469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1188247469
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.2969151382
Short name T851
Test name
Test status
Simulation time 42053633504 ps
CPU time 73.1 seconds
Started Aug 15 06:28:53 PM PDT 24
Finished Aug 15 06:30:07 PM PDT 24
Peak memory 201228 kb
Host smart-9a85715c-6f39-451e-9cf5-b9cccd6aea67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969151382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2969151382
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.2905243135
Short name T304
Test name
Test status
Simulation time 8738303613 ps
CPU time 487.31 seconds
Started Aug 15 06:28:51 PM PDT 24
Finished Aug 15 06:36:59 PM PDT 24
Peak memory 200852 kb
Host smart-cb58d600-3e04-4fce-a8aa-1c4cc61a787c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2905243135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2905243135
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.1587753228
Short name T379
Test name
Test status
Simulation time 2195926350 ps
CPU time 11.56 seconds
Started Aug 15 06:28:49 PM PDT 24
Finished Aug 15 06:29:00 PM PDT 24
Peak memory 199340 kb
Host smart-290e2f17-d3f2-4ca4-82d6-afa30fd77e32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1587753228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1587753228
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.1724975884
Short name T992
Test name
Test status
Simulation time 103575900323 ps
CPU time 864.83 seconds
Started Aug 15 06:28:47 PM PDT 24
Finished Aug 15 06:43:13 PM PDT 24
Peak memory 200728 kb
Host smart-67626f98-2f14-4a2d-afea-e576d784e71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724975884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1724975884
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.1135657705
Short name T269
Test name
Test status
Simulation time 30245848220 ps
CPU time 7.09 seconds
Started Aug 15 06:28:54 PM PDT 24
Finished Aug 15 06:29:01 PM PDT 24
Peak memory 197020 kb
Host smart-6dda513a-b093-4d01-a700-356cf5fb547a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135657705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1135657705
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.1117165419
Short name T4
Test name
Test status
Simulation time 950553625 ps
CPU time 2.55 seconds
Started Aug 15 06:28:49 PM PDT 24
Finished Aug 15 06:28:51 PM PDT 24
Peak memory 200584 kb
Host smart-5643af1f-291b-4251-99aa-b59788b33cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117165419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1117165419
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.2772077351
Short name T655
Test name
Test status
Simulation time 17858796192 ps
CPU time 524.61 seconds
Started Aug 15 06:28:56 PM PDT 24
Finished Aug 15 06:37:41 PM PDT 24
Peak memory 200908 kb
Host smart-83d57441-829c-4922-9669-701eaaeadef2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772077351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2772077351
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.1464469211
Short name T887
Test name
Test status
Simulation time 1681773227 ps
CPU time 17.46 seconds
Started Aug 15 06:28:54 PM PDT 24
Finished Aug 15 06:29:11 PM PDT 24
Peak memory 200884 kb
Host smart-6126b384-7c6c-4c6b-a85b-afed7b660465
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464469211 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.1464469211
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3581521048
Short name T1168
Test name
Test status
Simulation time 6944358063 ps
CPU time 18.64 seconds
Started Aug 15 06:28:54 PM PDT 24
Finished Aug 15 06:29:13 PM PDT 24
Peak memory 200332 kb
Host smart-d5308184-6329-4a33-aaab-905b671a5695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581521048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3581521048
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2403919150
Short name T1043
Test name
Test status
Simulation time 115647961043 ps
CPU time 49.87 seconds
Started Aug 15 06:28:48 PM PDT 24
Finished Aug 15 06:29:38 PM PDT 24
Peak memory 200956 kb
Host smart-7c4377e5-44b7-4098-982c-6fa1145300a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403919150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2403919150
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1359768647
Short name T661
Test name
Test status
Simulation time 178634140 ps
CPU time 0.53 seconds
Started Aug 15 06:28:59 PM PDT 24
Finished Aug 15 06:29:00 PM PDT 24
Peak memory 196260 kb
Host smart-ec1f8cd7-d8cc-4e9c-8e2a-d512877adf20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359768647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1359768647
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.1263171336
Short name T359
Test name
Test status
Simulation time 30709919584 ps
CPU time 48.86 seconds
Started Aug 15 06:28:55 PM PDT 24
Finished Aug 15 06:29:44 PM PDT 24
Peak memory 200868 kb
Host smart-4d9beabb-6b9e-49de-acff-20fede34a697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263171336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1263171336
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3880782702
Short name T1095
Test name
Test status
Simulation time 24336854339 ps
CPU time 35.23 seconds
Started Aug 15 06:28:54 PM PDT 24
Finished Aug 15 06:29:29 PM PDT 24
Peak memory 200444 kb
Host smart-5b3d5d52-1e9a-4a04-8e4c-608c9e3f329d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880782702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3880782702
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3243578024
Short name T549
Test name
Test status
Simulation time 39522213969 ps
CPU time 18.53 seconds
Started Aug 15 06:28:54 PM PDT 24
Finished Aug 15 06:29:13 PM PDT 24
Peak memory 200972 kb
Host smart-0cc246a5-461f-45a4-9994-9df453ded6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243578024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3243578024
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.1888851060
Short name T925
Test name
Test status
Simulation time 36666391743 ps
CPU time 26.68 seconds
Started Aug 15 06:28:55 PM PDT 24
Finished Aug 15 06:29:22 PM PDT 24
Peak memory 200952 kb
Host smart-4cbf2916-2552-406c-93c3-863d85608887
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888851060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1888851060
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.4164207960
Short name T840
Test name
Test status
Simulation time 95954304533 ps
CPU time 646.24 seconds
Started Aug 15 06:28:54 PM PDT 24
Finished Aug 15 06:39:41 PM PDT 24
Peak memory 200864 kb
Host smart-e9fa5539-f74e-4fa1-9134-47d7224928fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4164207960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.4164207960
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.4235542345
Short name T791
Test name
Test status
Simulation time 2594594046 ps
CPU time 3.33 seconds
Started Aug 15 06:28:54 PM PDT 24
Finished Aug 15 06:28:57 PM PDT 24
Peak memory 199960 kb
Host smart-e811e218-c2e3-4494-8073-47036b811aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235542345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.4235542345
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3206779060
Short name T1002
Test name
Test status
Simulation time 72975026578 ps
CPU time 30.58 seconds
Started Aug 15 06:28:55 PM PDT 24
Finished Aug 15 06:29:26 PM PDT 24
Peak memory 201092 kb
Host smart-59d9f5db-b77f-4f14-93e1-4c8d40fa7225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206779060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3206779060
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.808679603
Short name T567
Test name
Test status
Simulation time 18147675974 ps
CPU time 1096.22 seconds
Started Aug 15 06:28:58 PM PDT 24
Finished Aug 15 06:47:14 PM PDT 24
Peak memory 200896 kb
Host smart-72869ff1-b310-4bd3-a204-a16598a7db27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=808679603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.808679603
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.1404644710
Short name T597
Test name
Test status
Simulation time 7273861262 ps
CPU time 63.63 seconds
Started Aug 15 06:28:54 PM PDT 24
Finished Aug 15 06:29:58 PM PDT 24
Peak memory 199904 kb
Host smart-198108b6-13ed-458f-a0b1-39ba04aef4ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1404644710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.1404644710
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3616520899
Short name T293
Test name
Test status
Simulation time 30273075852 ps
CPU time 55.76 seconds
Started Aug 15 06:28:53 PM PDT 24
Finished Aug 15 06:29:49 PM PDT 24
Peak memory 200836 kb
Host smart-5e4776f0-8aa2-43ec-998a-017bcc520a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616520899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3616520899
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1408526491
Short name T681
Test name
Test status
Simulation time 1902128868 ps
CPU time 3.57 seconds
Started Aug 15 06:28:55 PM PDT 24
Finished Aug 15 06:28:59 PM PDT 24
Peak memory 196440 kb
Host smart-d68ee9c8-3efc-4eee-947f-9aa6daddf9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408526491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1408526491
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2239260957
Short name T532
Test name
Test status
Simulation time 263638559 ps
CPU time 1.61 seconds
Started Aug 15 06:28:53 PM PDT 24
Finished Aug 15 06:28:55 PM PDT 24
Peak memory 199516 kb
Host smart-1f1a04f5-391e-49f9-a0e4-1eae4b533d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239260957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2239260957
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.110981537
Short name T35
Test name
Test status
Simulation time 7596094290 ps
CPU time 81.57 seconds
Started Aug 15 06:28:57 PM PDT 24
Finished Aug 15 06:30:19 PM PDT 24
Peak memory 217576 kb
Host smart-15101769-2c12-47de-b318-4eb59f9294de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110981537 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.110981537
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3093927949
Short name T388
Test name
Test status
Simulation time 7771820111 ps
CPU time 10.83 seconds
Started Aug 15 06:28:55 PM PDT 24
Finished Aug 15 06:29:06 PM PDT 24
Peak memory 200796 kb
Host smart-916a8235-88d5-4f52-81b9-d0d7735d69da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093927949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3093927949
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.3479517192
Short name T695
Test name
Test status
Simulation time 8252861685 ps
CPU time 11.63 seconds
Started Aug 15 06:28:54 PM PDT 24
Finished Aug 15 06:29:06 PM PDT 24
Peak memory 198588 kb
Host smart-8ab6328f-954b-47a9-8bd8-5120622c32d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479517192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3479517192
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3590055753
Short name T753
Test name
Test status
Simulation time 30695655 ps
CPU time 0.56 seconds
Started Aug 15 06:29:02 PM PDT 24
Finished Aug 15 06:29:03 PM PDT 24
Peak memory 196196 kb
Host smart-f17fa861-8f1b-4755-abec-7102e9473365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590055753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3590055753
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1950181878
Short name T158
Test name
Test status
Simulation time 30327897627 ps
CPU time 26.67 seconds
Started Aug 15 06:29:01 PM PDT 24
Finished Aug 15 06:29:28 PM PDT 24
Peak memory 200892 kb
Host smart-46ca53d2-0d10-4828-918b-4ed209eadbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950181878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1950181878
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1918928292
Short name T161
Test name
Test status
Simulation time 20085949540 ps
CPU time 35.37 seconds
Started Aug 15 06:29:03 PM PDT 24
Finished Aug 15 06:29:39 PM PDT 24
Peak memory 200920 kb
Host smart-63e608a3-c5b4-448d-906f-2b67931f304b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918928292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1918928292
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2703625076
Short name T858
Test name
Test status
Simulation time 10732286530 ps
CPU time 15.53 seconds
Started Aug 15 06:29:02 PM PDT 24
Finished Aug 15 06:29:18 PM PDT 24
Peak memory 200960 kb
Host smart-d8992a5e-e099-4e34-9b27-33fbc98bb4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703625076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2703625076
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3828978217
Short name T15
Test name
Test status
Simulation time 19880233622 ps
CPU time 34.61 seconds
Started Aug 15 06:29:03 PM PDT 24
Finished Aug 15 06:29:38 PM PDT 24
Peak memory 200820 kb
Host smart-f42aa4e7-a168-43ab-8016-305be2461d2c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828978217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3828978217
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.917136241
Short name T880
Test name
Test status
Simulation time 168114014466 ps
CPU time 1297.76 seconds
Started Aug 15 06:29:03 PM PDT 24
Finished Aug 15 06:50:41 PM PDT 24
Peak memory 200956 kb
Host smart-b3741651-389b-4e55-b1d9-35320fca6830
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=917136241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.917136241
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1646622297
Short name T536
Test name
Test status
Simulation time 2174007229 ps
CPU time 5.97 seconds
Started Aug 15 06:29:03 PM PDT 24
Finished Aug 15 06:29:09 PM PDT 24
Peak memory 199548 kb
Host smart-5a891c07-69d5-463b-80f7-42cfceaac9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646622297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1646622297
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.1828107723
Short name T752
Test name
Test status
Simulation time 59076729420 ps
CPU time 38.36 seconds
Started Aug 15 06:29:02 PM PDT 24
Finished Aug 15 06:29:40 PM PDT 24
Peak memory 200976 kb
Host smart-f81b7b55-3c07-4870-bca6-72b11ded1c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828107723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1828107723
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.3322268240
Short name T1172
Test name
Test status
Simulation time 20290859863 ps
CPU time 284.86 seconds
Started Aug 15 06:29:04 PM PDT 24
Finished Aug 15 06:33:49 PM PDT 24
Peak memory 200820 kb
Host smart-f09e3572-2ff2-43cf-9567-d2343134460e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3322268240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.3322268240
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.4094555383
Short name T329
Test name
Test status
Simulation time 4256132448 ps
CPU time 16.61 seconds
Started Aug 15 06:29:04 PM PDT 24
Finished Aug 15 06:29:20 PM PDT 24
Peak memory 199260 kb
Host smart-de7a142a-cc55-4305-aacc-ec9d78166dd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4094555383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.4094555383
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3743082489
Short name T519
Test name
Test status
Simulation time 31464704153 ps
CPU time 51.42 seconds
Started Aug 15 06:29:02 PM PDT 24
Finished Aug 15 06:29:54 PM PDT 24
Peak memory 200756 kb
Host smart-dada5ab1-2f7b-4965-9687-d3e8910f247e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743082489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3743082489
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.1328183688
Short name T294
Test name
Test status
Simulation time 4207955681 ps
CPU time 6.51 seconds
Started Aug 15 06:29:04 PM PDT 24
Finished Aug 15 06:29:10 PM PDT 24
Peak memory 197080 kb
Host smart-f1685ec5-cf8a-4ec4-a3d5-2405ce2f1633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328183688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1328183688
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1568652841
Short name T556
Test name
Test status
Simulation time 320140123 ps
CPU time 1 seconds
Started Aug 15 06:29:03 PM PDT 24
Finished Aug 15 06:29:04 PM PDT 24
Peak memory 200836 kb
Host smart-46cd20b4-91a6-41bd-adc6-fbf0c82f843b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568652841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1568652841
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2310832213
Short name T1060
Test name
Test status
Simulation time 105632770328 ps
CPU time 66.9 seconds
Started Aug 15 06:29:01 PM PDT 24
Finished Aug 15 06:30:08 PM PDT 24
Peak memory 200872 kb
Host smart-06ef5182-bf79-48bd-81d6-15cd13daf801
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310832213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2310832213
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.1465641361
Short name T835
Test name
Test status
Simulation time 3766020140 ps
CPU time 32.57 seconds
Started Aug 15 06:29:03 PM PDT 24
Finished Aug 15 06:29:36 PM PDT 24
Peak memory 216512 kb
Host smart-49ded72a-9cfc-46d1-94fb-587a0b009777
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465641361 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.1465641361
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.1679412550
Short name T400
Test name
Test status
Simulation time 1635043281 ps
CPU time 1.81 seconds
Started Aug 15 06:29:01 PM PDT 24
Finished Aug 15 06:29:03 PM PDT 24
Peak memory 199404 kb
Host smart-cf11dd99-73d7-4b91-8ac7-d1920ea3f6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679412550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1679412550
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.2164509657
Short name T317
Test name
Test status
Simulation time 58385282077 ps
CPU time 35.8 seconds
Started Aug 15 06:29:01 PM PDT 24
Finished Aug 15 06:29:37 PM PDT 24
Peak memory 200948 kb
Host smart-56694c69-9211-41d5-82be-1338da28748a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164509657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2164509657
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2182377279
Short name T385
Test name
Test status
Simulation time 25745908 ps
CPU time 0.58 seconds
Started Aug 15 06:29:10 PM PDT 24
Finished Aug 15 06:29:11 PM PDT 24
Peak memory 196536 kb
Host smart-834b7017-64f7-4a32-94ad-8d567fe58204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182377279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2182377279
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.924737838
Short name T807
Test name
Test status
Simulation time 37312902713 ps
CPU time 15.6 seconds
Started Aug 15 06:29:04 PM PDT 24
Finished Aug 15 06:29:20 PM PDT 24
Peak memory 200908 kb
Host smart-43233e82-f1aa-4ffa-be83-12bc5a67401a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924737838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.924737838
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.878799142
Short name T110
Test name
Test status
Simulation time 15879470061 ps
CPU time 24.26 seconds
Started Aug 15 06:29:03 PM PDT 24
Finished Aug 15 06:29:27 PM PDT 24
Peak memory 200912 kb
Host smart-21cdaa62-8ea5-4b04-a98c-e1df75b6e146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878799142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.878799142
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2799880192
Short name T903
Test name
Test status
Simulation time 127263782382 ps
CPU time 173.98 seconds
Started Aug 15 06:29:04 PM PDT 24
Finished Aug 15 06:31:58 PM PDT 24
Peak memory 200848 kb
Host smart-8b6a6880-c0f8-47a3-a8ff-3346d6378e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799880192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2799880192
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.3231350408
Short name T476
Test name
Test status
Simulation time 20984890412 ps
CPU time 3.57 seconds
Started Aug 15 06:29:02 PM PDT 24
Finished Aug 15 06:29:06 PM PDT 24
Peak memory 199112 kb
Host smart-37a30997-8fef-45a9-8d7c-b22eb0e4596a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231350408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3231350408
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.3984915400
Short name T467
Test name
Test status
Simulation time 105533739705 ps
CPU time 297.11 seconds
Started Aug 15 06:29:11 PM PDT 24
Finished Aug 15 06:34:08 PM PDT 24
Peak memory 200948 kb
Host smart-14c370bf-6cb3-46cd-95d0-0ab84bc88593
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3984915400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3984915400
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.2592044143
Short name T1143
Test name
Test status
Simulation time 9395111573 ps
CPU time 16.99 seconds
Started Aug 15 06:29:04 PM PDT 24
Finished Aug 15 06:29:21 PM PDT 24
Peak memory 200912 kb
Host smart-c10f6008-2e20-4503-9a01-a38bef7b70a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592044143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2592044143
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.2984133061
Short name T1065
Test name
Test status
Simulation time 122840052828 ps
CPU time 73.15 seconds
Started Aug 15 06:29:02 PM PDT 24
Finished Aug 15 06:30:16 PM PDT 24
Peak memory 209012 kb
Host smart-75d0212d-7983-48f1-9c35-f1d77564a082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984133061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2984133061
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.1553283264
Short name T576
Test name
Test status
Simulation time 18940401658 ps
CPU time 741.28 seconds
Started Aug 15 06:29:02 PM PDT 24
Finished Aug 15 06:41:23 PM PDT 24
Peak memory 200924 kb
Host smart-40315491-b0cd-47b8-8825-37f1f2de7a2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1553283264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1553283264
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.509851836
Short name T1000
Test name
Test status
Simulation time 6995201747 ps
CPU time 64.84 seconds
Started Aug 15 06:29:02 PM PDT 24
Finished Aug 15 06:30:07 PM PDT 24
Peak memory 200108 kb
Host smart-9477b8fa-307d-4aef-9a83-f47e3d2958b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=509851836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.509851836
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3675747721
Short name T322
Test name
Test status
Simulation time 172855616875 ps
CPU time 68.27 seconds
Started Aug 15 06:29:02 PM PDT 24
Finished Aug 15 06:30:10 PM PDT 24
Peak memory 200924 kb
Host smart-75a21c64-a2fe-4a11-af1a-1c0c58c8151b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675747721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3675747721
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2111410425
Short name T387
Test name
Test status
Simulation time 2024847538 ps
CPU time 1.51 seconds
Started Aug 15 06:29:04 PM PDT 24
Finished Aug 15 06:29:06 PM PDT 24
Peak memory 196368 kb
Host smart-f96daa76-58fb-4335-812d-8aeadddcde65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111410425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2111410425
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3291845161
Short name T793
Test name
Test status
Simulation time 613776536 ps
CPU time 1.91 seconds
Started Aug 15 06:29:04 PM PDT 24
Finished Aug 15 06:29:06 PM PDT 24
Peak memory 200408 kb
Host smart-cc6e6499-1ef1-4c8f-9d2e-25b4a3afe54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291845161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3291845161
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.4259360682
Short name T424
Test name
Test status
Simulation time 135257084743 ps
CPU time 1007.52 seconds
Started Aug 15 06:29:11 PM PDT 24
Finished Aug 15 06:45:58 PM PDT 24
Peak memory 200916 kb
Host smart-63fa1a64-6282-4c3e-b8af-fda2c0df4039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259360682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.4259360682
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.464030574
Short name T611
Test name
Test status
Simulation time 2978622740 ps
CPU time 38.27 seconds
Started Aug 15 06:29:10 PM PDT 24
Finished Aug 15 06:29:49 PM PDT 24
Peak memory 200960 kb
Host smart-c19e6c6b-5244-4753-98bf-2be67ece9be8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464030574 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.464030574
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1089644249
Short name T735
Test name
Test status
Simulation time 2532108506 ps
CPU time 1.9 seconds
Started Aug 15 06:29:02 PM PDT 24
Finished Aug 15 06:29:04 PM PDT 24
Peak memory 199316 kb
Host smart-a8277e25-c17d-425c-b56f-e2acf182ed5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089644249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1089644249
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3577031005
Short name T432
Test name
Test status
Simulation time 66215807813 ps
CPU time 45.37 seconds
Started Aug 15 06:29:04 PM PDT 24
Finished Aug 15 06:29:49 PM PDT 24
Peak memory 200884 kb
Host smart-c4b10157-7c6e-4915-9e37-62f5ce83d392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577031005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3577031005
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3157559595
Short name T423
Test name
Test status
Simulation time 11134214 ps
CPU time 0.52 seconds
Started Aug 15 06:29:10 PM PDT 24
Finished Aug 15 06:29:11 PM PDT 24
Peak memory 195480 kb
Host smart-3fda372a-605e-418a-b326-e754fbe27ad9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157559595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3157559595
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.306021250
Short name T691
Test name
Test status
Simulation time 27675442951 ps
CPU time 53.25 seconds
Started Aug 15 06:29:10 PM PDT 24
Finished Aug 15 06:30:03 PM PDT 24
Peak memory 200880 kb
Host smart-78d62645-4e6c-4a99-91f7-3dfc4f6639b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306021250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.306021250
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.1944632794
Short name T560
Test name
Test status
Simulation time 27256087314 ps
CPU time 41.65 seconds
Started Aug 15 06:29:11 PM PDT 24
Finished Aug 15 06:29:53 PM PDT 24
Peak memory 200668 kb
Host smart-72669a35-74eb-4fc9-9a9e-e6baebfdaff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944632794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.1944632794
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.1711889502
Short name T957
Test name
Test status
Simulation time 23936909526 ps
CPU time 38.78 seconds
Started Aug 15 06:29:11 PM PDT 24
Finished Aug 15 06:29:49 PM PDT 24
Peak memory 200744 kb
Host smart-8717fbc1-f526-4380-97ec-79ff87788564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711889502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.1711889502
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.1336925285
Short name T897
Test name
Test status
Simulation time 17132627352 ps
CPU time 14.77 seconds
Started Aug 15 06:29:09 PM PDT 24
Finished Aug 15 06:29:24 PM PDT 24
Peak memory 200888 kb
Host smart-e8e09426-9204-49be-8049-6d87c1dbff3d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336925285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1336925285
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.2513628969
Short name T701
Test name
Test status
Simulation time 135260850757 ps
CPU time 985.17 seconds
Started Aug 15 06:29:09 PM PDT 24
Finished Aug 15 06:45:34 PM PDT 24
Peak memory 200964 kb
Host smart-4d0cbfb1-bb04-47c0-849b-415e15fa9635
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2513628969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2513628969
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.772614386
Short name T950
Test name
Test status
Simulation time 7003730962 ps
CPU time 4.55 seconds
Started Aug 15 06:29:10 PM PDT 24
Finished Aug 15 06:29:14 PM PDT 24
Peak memory 200440 kb
Host smart-a05d9243-2fd1-4133-b191-18e3b8d9f586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772614386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.772614386
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.2425943086
Short name T895
Test name
Test status
Simulation time 2449410152 ps
CPU time 4.08 seconds
Started Aug 15 06:29:09 PM PDT 24
Finished Aug 15 06:29:13 PM PDT 24
Peak memory 200912 kb
Host smart-404beff0-c62b-4c3f-aff7-104465ba3aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425943086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2425943086
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.2644587964
Short name T283
Test name
Test status
Simulation time 25990484214 ps
CPU time 184.1 seconds
Started Aug 15 06:29:10 PM PDT 24
Finished Aug 15 06:32:14 PM PDT 24
Peak memory 200944 kb
Host smart-01d109d7-07f9-4fcd-ac16-00278bf296f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2644587964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2644587964
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3949660913
Short name T8
Test name
Test status
Simulation time 4715950154 ps
CPU time 9.11 seconds
Started Aug 15 06:29:09 PM PDT 24
Finished Aug 15 06:29:18 PM PDT 24
Peak memory 199004 kb
Host smart-2fdfc1a6-c433-46cd-930b-91dede623b9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3949660913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3949660913
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.1331492577
Short name T941
Test name
Test status
Simulation time 37211112137 ps
CPU time 60.68 seconds
Started Aug 15 06:29:09 PM PDT 24
Finished Aug 15 06:30:10 PM PDT 24
Peak memory 200848 kb
Host smart-6a9c5d34-2d81-47ef-8a50-c5fc24a62137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331492577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.1331492577
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.1357652014
Short name T898
Test name
Test status
Simulation time 3328540753 ps
CPU time 2.99 seconds
Started Aug 15 06:29:09 PM PDT 24
Finished Aug 15 06:29:12 PM PDT 24
Peak memory 196844 kb
Host smart-409c256a-8ee3-4e00-bbcf-fcb533038109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357652014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.1357652014
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.4043476460
Short name T564
Test name
Test status
Simulation time 690861476 ps
CPU time 2.64 seconds
Started Aug 15 06:29:08 PM PDT 24
Finished Aug 15 06:29:11 PM PDT 24
Peak memory 200660 kb
Host smart-00d8e2f5-40ca-4cba-90bb-3f5eb3ba00b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043476460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.4043476460
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.4022149600
Short name T710
Test name
Test status
Simulation time 7647038838 ps
CPU time 26.52 seconds
Started Aug 15 06:29:11 PM PDT 24
Finished Aug 15 06:29:38 PM PDT 24
Peak memory 216592 kb
Host smart-316d20f3-e961-40e7-9a36-ac8ba2363b56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022149600 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.4022149600
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.1023340095
Short name T733
Test name
Test status
Simulation time 1649307291 ps
CPU time 4.82 seconds
Started Aug 15 06:29:09 PM PDT 24
Finished Aug 15 06:29:14 PM PDT 24
Peak memory 199228 kb
Host smart-04aa0ddf-f8a5-410f-ae58-139758be61f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023340095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1023340095
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3344609958
Short name T392
Test name
Test status
Simulation time 51983620041 ps
CPU time 29.92 seconds
Started Aug 15 06:29:11 PM PDT 24
Finished Aug 15 06:29:41 PM PDT 24
Peak memory 200920 kb
Host smart-67824f8b-b329-4e01-b7df-171c7d87acd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344609958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3344609958
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.4228094391
Short name T535
Test name
Test status
Simulation time 12574498 ps
CPU time 0.55 seconds
Started Aug 15 06:29:18 PM PDT 24
Finished Aug 15 06:29:19 PM PDT 24
Peak memory 195548 kb
Host smart-f2eaa781-b870-46f3-8611-2926dcf60fc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228094391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.4228094391
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1568393048
Short name T953
Test name
Test status
Simulation time 12339409890 ps
CPU time 16.94 seconds
Started Aug 15 06:29:11 PM PDT 24
Finished Aug 15 06:29:28 PM PDT 24
Peak memory 200948 kb
Host smart-177e61b2-78e0-48d3-8c97-0f7b43d5f1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568393048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1568393048
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1150030656
Short name T709
Test name
Test status
Simulation time 118011828896 ps
CPU time 270.98 seconds
Started Aug 15 06:29:11 PM PDT 24
Finished Aug 15 06:33:42 PM PDT 24
Peak memory 200892 kb
Host smart-907994db-17ea-4dac-a875-e68bbeea3849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150030656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1150030656
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_intr.1287206344
Short name T966
Test name
Test status
Simulation time 98599983892 ps
CPU time 31.1 seconds
Started Aug 15 06:29:10 PM PDT 24
Finished Aug 15 06:29:41 PM PDT 24
Peak memory 197120 kb
Host smart-830df55f-b5f6-4b5b-a2be-ec888dddfba3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287206344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1287206344
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.2281867790
Short name T1012
Test name
Test status
Simulation time 282735202849 ps
CPU time 82.28 seconds
Started Aug 15 06:29:16 PM PDT 24
Finished Aug 15 06:30:38 PM PDT 24
Peak memory 200908 kb
Host smart-588a857e-fcb3-4ff6-b972-8e8b55331069
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2281867790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2281867790
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.3069870326
Short name T356
Test name
Test status
Simulation time 8441046399 ps
CPU time 6.34 seconds
Started Aug 15 06:29:15 PM PDT 24
Finished Aug 15 06:29:22 PM PDT 24
Peak memory 199956 kb
Host smart-42239feb-f009-46d1-ba1b-409e18b017f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069870326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3069870326
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.2674678269
Short name T1163
Test name
Test status
Simulation time 38734678252 ps
CPU time 10.52 seconds
Started Aug 15 06:29:09 PM PDT 24
Finished Aug 15 06:29:20 PM PDT 24
Peak memory 198132 kb
Host smart-c4ccf48a-44fd-4d6e-b6bb-6e3a900e8a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674678269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2674678269
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1541328484
Short name T292
Test name
Test status
Simulation time 5718230700 ps
CPU time 78.78 seconds
Started Aug 15 06:29:15 PM PDT 24
Finished Aug 15 06:30:34 PM PDT 24
Peak memory 200928 kb
Host smart-708a17e3-95a2-480f-bbfa-81bb59484931
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1541328484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1541328484
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.1175790732
Short name T416
Test name
Test status
Simulation time 7144555038 ps
CPU time 32.92 seconds
Started Aug 15 06:29:09 PM PDT 24
Finished Aug 15 06:29:42 PM PDT 24
Peak memory 199080 kb
Host smart-7f192a09-c3b0-42f0-a828-d67d9288b494
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1175790732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1175790732
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2213965510
Short name T248
Test name
Test status
Simulation time 101255086048 ps
CPU time 148.35 seconds
Started Aug 15 06:29:15 PM PDT 24
Finished Aug 15 06:31:44 PM PDT 24
Peak memory 200916 kb
Host smart-a70a4e19-9ea8-4d73-9721-8b72a672cf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213965510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2213965510
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3417065037
Short name T982
Test name
Test status
Simulation time 2196580703 ps
CPU time 2.37 seconds
Started Aug 15 06:29:09 PM PDT 24
Finished Aug 15 06:29:12 PM PDT 24
Peak memory 196500 kb
Host smart-1d89da54-9ad1-4f70-8283-02b42f4d65e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417065037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3417065037
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.1368096753
Short name T1148
Test name
Test status
Simulation time 734545414 ps
CPU time 1.69 seconds
Started Aug 15 06:29:09 PM PDT 24
Finished Aug 15 06:29:11 PM PDT 24
Peak memory 200752 kb
Host smart-8f44e7e1-d292-456f-9781-22906586488e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368096753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1368096753
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.2513390300
Short name T1142
Test name
Test status
Simulation time 165067799830 ps
CPU time 631.59 seconds
Started Aug 15 06:29:15 PM PDT 24
Finished Aug 15 06:39:46 PM PDT 24
Peak memory 200880 kb
Host smart-270aee6b-135e-4b89-ab86-3ea4c5a588c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513390300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.2513390300
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.3135317828
Short name T712
Test name
Test status
Simulation time 1459772682 ps
CPU time 18.99 seconds
Started Aug 15 06:29:18 PM PDT 24
Finished Aug 15 06:29:37 PM PDT 24
Peak memory 209280 kb
Host smart-71623a15-563c-4671-a9a9-89b70ef06150
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135317828 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.3135317828
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.1672882855
Short name T666
Test name
Test status
Simulation time 7751844975 ps
CPU time 5.96 seconds
Started Aug 15 06:29:17 PM PDT 24
Finished Aug 15 06:29:23 PM PDT 24
Peak memory 200836 kb
Host smart-d4c935f9-abff-45e0-a88e-4003140b3bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672882855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1672882855
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1307204351
Short name T1057
Test name
Test status
Simulation time 142942788550 ps
CPU time 122.49 seconds
Started Aug 15 06:29:10 PM PDT 24
Finished Aug 15 06:31:12 PM PDT 24
Peak memory 200956 kb
Host smart-bc581bec-b761-4e60-863c-560f5d55af88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307204351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1307204351
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1845566113
Short name T357
Test name
Test status
Simulation time 42362821 ps
CPU time 0.58 seconds
Started Aug 15 06:29:23 PM PDT 24
Finished Aug 15 06:29:23 PM PDT 24
Peak memory 195520 kb
Host smart-c5aa881d-286a-4deb-878d-5c4de1c33a9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845566113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1845566113
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3259376627
Short name T2
Test name
Test status
Simulation time 23970419729 ps
CPU time 19.17 seconds
Started Aug 15 06:29:18 PM PDT 24
Finished Aug 15 06:29:37 PM PDT 24
Peak memory 200948 kb
Host smart-1360bebe-5a16-43c2-8ddb-736af35fcfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259376627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3259376627
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.954136860
Short name T622
Test name
Test status
Simulation time 61615894485 ps
CPU time 25.04 seconds
Started Aug 15 06:29:18 PM PDT 24
Finished Aug 15 06:29:43 PM PDT 24
Peak memory 199664 kb
Host smart-82a675fa-4abb-42b3-856e-b20057da11f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954136860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.954136860
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3968897242
Short name T789
Test name
Test status
Simulation time 134988532929 ps
CPU time 58.93 seconds
Started Aug 15 06:29:15 PM PDT 24
Finished Aug 15 06:30:14 PM PDT 24
Peak memory 200864 kb
Host smart-cfb0b5ac-126d-4b93-805f-984f61389ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968897242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3968897242
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.1147017443
Short name T94
Test name
Test status
Simulation time 3785859310 ps
CPU time 3.15 seconds
Started Aug 15 06:29:14 PM PDT 24
Finished Aug 15 06:29:17 PM PDT 24
Peak memory 197840 kb
Host smart-29d3d204-074d-4059-a0ba-9a72ee18c9ad
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147017443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1147017443
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2457863023
Short name T934
Test name
Test status
Simulation time 121397135575 ps
CPU time 206.78 seconds
Started Aug 15 06:29:23 PM PDT 24
Finished Aug 15 06:32:50 PM PDT 24
Peak memory 200944 kb
Host smart-e22b261d-f5ab-45a1-9446-eccb49057eee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2457863023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2457863023
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.119608927
Short name T599
Test name
Test status
Simulation time 11086328638 ps
CPU time 13.28 seconds
Started Aug 15 06:29:33 PM PDT 24
Finished Aug 15 06:29:46 PM PDT 24
Peak memory 200808 kb
Host smart-aca2cf84-c1b6-4723-a8c2-eaa544e41de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119608927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.119608927
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.1611245324
Short name T744
Test name
Test status
Simulation time 244245950472 ps
CPU time 137.54 seconds
Started Aug 15 06:29:15 PM PDT 24
Finished Aug 15 06:31:33 PM PDT 24
Peak memory 209368 kb
Host smart-923a9324-0eac-4a21-8e0c-735e5bc1d1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611245324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.1611245324
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.4061905384
Short name T538
Test name
Test status
Simulation time 19496124848 ps
CPU time 199.8 seconds
Started Aug 15 06:29:24 PM PDT 24
Finished Aug 15 06:32:44 PM PDT 24
Peak memory 200952 kb
Host smart-2d9a3d67-aded-4c5e-b3f4-da1f0b1686be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4061905384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.4061905384
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.485736066
Short name T939
Test name
Test status
Simulation time 6672310557 ps
CPU time 53.96 seconds
Started Aug 15 06:29:15 PM PDT 24
Finished Aug 15 06:30:09 PM PDT 24
Peak memory 199276 kb
Host smart-362e5967-b2f0-4e81-b53c-f185a9623b38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=485736066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.485736066
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3586691683
Short name T533
Test name
Test status
Simulation time 113811113380 ps
CPU time 24.23 seconds
Started Aug 15 06:29:24 PM PDT 24
Finished Aug 15 06:29:48 PM PDT 24
Peak memory 200720 kb
Host smart-2f6a437c-9a78-43bc-b2d8-ac999d1528d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586691683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3586691683
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.2293904502
Short name T1177
Test name
Test status
Simulation time 2226443059 ps
CPU time 3.71 seconds
Started Aug 15 06:29:16 PM PDT 24
Finished Aug 15 06:29:20 PM PDT 24
Peak memory 196500 kb
Host smart-ff72f860-cc28-45c4-a8ca-748a7d00f1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293904502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2293904502
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3862624094
Short name T454
Test name
Test status
Simulation time 6206594231 ps
CPU time 7.75 seconds
Started Aug 15 06:29:15 PM PDT 24
Finished Aug 15 06:29:23 PM PDT 24
Peak memory 200672 kb
Host smart-826796ef-717b-45f1-9f42-db3a24fe3e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862624094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3862624094
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.2380789779
Short name T884
Test name
Test status
Simulation time 88227473103 ps
CPU time 157.9 seconds
Started Aug 15 06:29:24 PM PDT 24
Finished Aug 15 06:32:02 PM PDT 24
Peak memory 200888 kb
Host smart-be8a23be-8b6b-43d9-8b85-93763ff8628f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380789779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2380789779
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.975202503
Short name T217
Test name
Test status
Simulation time 4600278611 ps
CPU time 32.26 seconds
Started Aug 15 06:29:25 PM PDT 24
Finished Aug 15 06:29:58 PM PDT 24
Peak memory 209604 kb
Host smart-8dc2909a-30e0-4957-8444-11c1e60b2a9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975202503 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.975202503
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.47850572
Short name T503
Test name
Test status
Simulation time 1184028743 ps
CPU time 3.51 seconds
Started Aug 15 06:29:25 PM PDT 24
Finished Aug 15 06:29:29 PM PDT 24
Peak memory 199352 kb
Host smart-b8c40af2-5973-470b-a5b3-8c3137d01769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47850572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.47850572
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.3441512570
Short name T46
Test name
Test status
Simulation time 41626187050 ps
CPU time 67.23 seconds
Started Aug 15 06:29:16 PM PDT 24
Finished Aug 15 06:30:24 PM PDT 24
Peak memory 200872 kb
Host smart-964c7897-cd3b-4f41-b7d2-dc43d37da3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441512570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.3441512570
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.36754661
Short name T1094
Test name
Test status
Simulation time 13300097 ps
CPU time 0.55 seconds
Started Aug 15 06:29:31 PM PDT 24
Finished Aug 15 06:29:32 PM PDT 24
Peak memory 196260 kb
Host smart-24433619-db33-442e-b8cb-717395f28472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36754661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.36754661
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1258551491
Short name T1030
Test name
Test status
Simulation time 150242549610 ps
CPU time 59.27 seconds
Started Aug 15 06:29:25 PM PDT 24
Finished Aug 15 06:30:24 PM PDT 24
Peak memory 200944 kb
Host smart-47a60ee8-c0b8-46ef-a9d1-6a775b8f8e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258551491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1258551491
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.781098308
Short name T986
Test name
Test status
Simulation time 46582597660 ps
CPU time 11.45 seconds
Started Aug 15 06:29:23 PM PDT 24
Finished Aug 15 06:29:35 PM PDT 24
Peak memory 200948 kb
Host smart-2c642405-f33d-4f28-be70-5dafa73dd744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781098308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.781098308
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.3025240283
Short name T119
Test name
Test status
Simulation time 198475162883 ps
CPU time 132.66 seconds
Started Aug 15 06:29:24 PM PDT 24
Finished Aug 15 06:31:37 PM PDT 24
Peak memory 200880 kb
Host smart-b96c940f-6fbd-440a-9001-b3778e13ac10
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025240283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3025240283
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2344259085
Short name T1096
Test name
Test status
Simulation time 36490199075 ps
CPU time 61.32 seconds
Started Aug 15 06:29:33 PM PDT 24
Finished Aug 15 06:30:35 PM PDT 24
Peak memory 200900 kb
Host smart-13f98163-2d54-4f45-9da3-dbe711a2a877
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2344259085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2344259085
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.3995267481
Short name T368
Test name
Test status
Simulation time 3492497289 ps
CPU time 4.17 seconds
Started Aug 15 06:29:24 PM PDT 24
Finished Aug 15 06:29:28 PM PDT 24
Peak memory 198912 kb
Host smart-34f18667-ff57-4400-9e42-525678d55f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995267481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.3995267481
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.1980499995
Short name T247
Test name
Test status
Simulation time 179561582715 ps
CPU time 84.45 seconds
Started Aug 15 06:29:23 PM PDT 24
Finished Aug 15 06:30:48 PM PDT 24
Peak memory 209176 kb
Host smart-bc373ef7-beed-4a03-9994-0b4249160ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980499995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1980499995
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.1984941586
Short name T378
Test name
Test status
Simulation time 13757608196 ps
CPU time 48.38 seconds
Started Aug 15 06:29:35 PM PDT 24
Finished Aug 15 06:30:24 PM PDT 24
Peak memory 200896 kb
Host smart-0dffd94c-c65a-425c-9b41-300b1f76e6c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1984941586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.1984941586
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2464897647
Short name T1050
Test name
Test status
Simulation time 2923828277 ps
CPU time 1.38 seconds
Started Aug 15 06:29:23 PM PDT 24
Finished Aug 15 06:29:25 PM PDT 24
Peak memory 199772 kb
Host smart-2e5480a8-f3a1-4645-8f16-1ef3b319e200
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2464897647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2464897647
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2381018388
Short name T825
Test name
Test status
Simulation time 105752688472 ps
CPU time 160.69 seconds
Started Aug 15 06:29:24 PM PDT 24
Finished Aug 15 06:32:04 PM PDT 24
Peak memory 200952 kb
Host smart-77f2eec8-0810-45cb-a0a2-92cac12d556c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381018388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2381018388
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1036079827
Short name T1158
Test name
Test status
Simulation time 677027406 ps
CPU time 1.25 seconds
Started Aug 15 06:29:23 PM PDT 24
Finished Aug 15 06:29:25 PM PDT 24
Peak memory 196432 kb
Host smart-a067a2e4-6c46-4592-af59-0cb31984e35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036079827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1036079827
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.965391418
Short name T689
Test name
Test status
Simulation time 891574229 ps
CPU time 3.19 seconds
Started Aug 15 06:29:24 PM PDT 24
Finished Aug 15 06:29:28 PM PDT 24
Peak memory 199296 kb
Host smart-86733b95-1f6f-4abb-9ec4-e1aa2f8c0f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965391418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.965391418
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.2743728522
Short name T601
Test name
Test status
Simulation time 176369242124 ps
CPU time 279.52 seconds
Started Aug 15 06:29:32 PM PDT 24
Finished Aug 15 06:34:11 PM PDT 24
Peak memory 200928 kb
Host smart-e7f25afb-4132-4390-a8f7-dd0400ba14ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743728522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2743728522
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.488262322
Short name T332
Test name
Test status
Simulation time 5489963252 ps
CPU time 14.2 seconds
Started Aug 15 06:29:32 PM PDT 24
Finished Aug 15 06:29:46 PM PDT 24
Peak memory 209236 kb
Host smart-029d8b0a-ab97-4b2a-bcd6-7f21eaff8432
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488262322 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.488262322
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3484062839
Short name T413
Test name
Test status
Simulation time 1476130525 ps
CPU time 1.82 seconds
Started Aug 15 06:29:24 PM PDT 24
Finished Aug 15 06:29:26 PM PDT 24
Peak memory 199596 kb
Host smart-ab9bafac-38ea-43f4-a876-7c20073bf5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484062839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3484062839
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.82783510
Short name T629
Test name
Test status
Simulation time 82002122839 ps
CPU time 34.55 seconds
Started Aug 15 06:29:23 PM PDT 24
Finished Aug 15 06:29:57 PM PDT 24
Peak memory 200840 kb
Host smart-bfbfd0eb-d361-41c1-9acb-adafcf180834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82783510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.82783510
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1079696319
Short name T401
Test name
Test status
Simulation time 27453805 ps
CPU time 0.51 seconds
Started Aug 15 06:29:38 PM PDT 24
Finished Aug 15 06:29:39 PM PDT 24
Peak memory 195596 kb
Host smart-9585b5fe-ca3f-444a-b093-c4e888bcd4f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079696319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1079696319
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.769571794
Short name T1054
Test name
Test status
Simulation time 66726596255 ps
CPU time 58.53 seconds
Started Aug 15 06:29:31 PM PDT 24
Finished Aug 15 06:30:30 PM PDT 24
Peak memory 200904 kb
Host smart-9eb96f9b-fb64-45a5-b086-d5f7b18c191b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769571794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.769571794
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.1611975461
Short name T605
Test name
Test status
Simulation time 87919650642 ps
CPU time 74.09 seconds
Started Aug 15 06:29:35 PM PDT 24
Finished Aug 15 06:30:50 PM PDT 24
Peak memory 200872 kb
Host smart-5a9ac6ed-754a-4666-8799-6f64a6aa650a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611975461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1611975461
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.1733043629
Short name T371
Test name
Test status
Simulation time 86010510078 ps
CPU time 32.79 seconds
Started Aug 15 06:29:32 PM PDT 24
Finished Aug 15 06:30:05 PM PDT 24
Peak memory 200844 kb
Host smart-3ac033e6-574c-4ab0-b552-3d1f7f41554a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733043629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1733043629
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.1475410335
Short name T361
Test name
Test status
Simulation time 6698944727 ps
CPU time 8.62 seconds
Started Aug 15 06:29:32 PM PDT 24
Finished Aug 15 06:29:41 PM PDT 24
Peak memory 197648 kb
Host smart-bc158399-4b13-41f5-8314-6f4eda1e0a2d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475410335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1475410335
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.2533156747
Short name T299
Test name
Test status
Simulation time 187818850263 ps
CPU time 469.33 seconds
Started Aug 15 06:29:39 PM PDT 24
Finished Aug 15 06:37:29 PM PDT 24
Peak memory 200960 kb
Host smart-45b49211-9e02-4124-bd93-48d22d8ad8ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2533156747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2533156747
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1320339166
Short name T854
Test name
Test status
Simulation time 12372228971 ps
CPU time 9.29 seconds
Started Aug 15 06:29:33 PM PDT 24
Finished Aug 15 06:29:42 PM PDT 24
Peak memory 200928 kb
Host smart-e7b3c57d-48ef-4adb-a489-100c73730fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320339166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1320339166
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.3500741319
Short name T742
Test name
Test status
Simulation time 139015929033 ps
CPU time 49.84 seconds
Started Aug 15 06:29:30 PM PDT 24
Finished Aug 15 06:30:20 PM PDT 24
Peak memory 200048 kb
Host smart-b4c4d512-cfcf-4acb-823c-8759f84c7dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500741319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3500741319
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.631173520
Short name T412
Test name
Test status
Simulation time 18872100972 ps
CPU time 532.6 seconds
Started Aug 15 06:29:33 PM PDT 24
Finished Aug 15 06:38:25 PM PDT 24
Peak memory 200908 kb
Host smart-485ca9f7-c84d-4cba-ac72-0e6615328dc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=631173520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.631173520
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.2098467791
Short name T1001
Test name
Test status
Simulation time 1782369641 ps
CPU time 1.17 seconds
Started Aug 15 06:29:35 PM PDT 24
Finished Aug 15 06:29:37 PM PDT 24
Peak memory 199140 kb
Host smart-2220aa68-cd70-493e-927b-d033ee1fe61b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2098467791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.2098467791
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2338484621
Short name T828
Test name
Test status
Simulation time 219658424126 ps
CPU time 155.38 seconds
Started Aug 15 06:29:31 PM PDT 24
Finished Aug 15 06:32:07 PM PDT 24
Peak memory 200924 kb
Host smart-ec8c8628-63cf-45cb-91f9-7f16ea226348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338484621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2338484621
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.2259937997
Short name T654
Test name
Test status
Simulation time 4142578808 ps
CPU time 2.03 seconds
Started Aug 15 06:29:32 PM PDT 24
Finished Aug 15 06:29:35 PM PDT 24
Peak memory 197072 kb
Host smart-91b0c5e1-b5cb-4537-9f00-471a8dea3651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259937997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2259937997
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.3064435621
Short name T104
Test name
Test status
Simulation time 271386041 ps
CPU time 1.88 seconds
Started Aug 15 06:29:36 PM PDT 24
Finished Aug 15 06:29:38 PM PDT 24
Peak memory 199348 kb
Host smart-633c3ae9-5a37-489c-8efc-8d4383a21d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064435621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3064435621
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2337095723
Short name T577
Test name
Test status
Simulation time 222752535857 ps
CPU time 234.35 seconds
Started Aug 15 06:29:40 PM PDT 24
Finished Aug 15 06:33:34 PM PDT 24
Peak memory 200896 kb
Host smart-32aa79a4-a48b-459e-8cec-22258318ac94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337095723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2337095723
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.862317427
Short name T602
Test name
Test status
Simulation time 6403145958 ps
CPU time 47.95 seconds
Started Aug 15 06:29:38 PM PDT 24
Finished Aug 15 06:30:26 PM PDT 24
Peak memory 209208 kb
Host smart-4d1682a7-c0b7-48ec-9fb7-5b741218c0b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862317427 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.862317427
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2864057662
Short name T252
Test name
Test status
Simulation time 12323250417 ps
CPU time 32.71 seconds
Started Aug 15 06:29:32 PM PDT 24
Finished Aug 15 06:30:05 PM PDT 24
Peak memory 200888 kb
Host smart-55cfbcee-6e68-464f-8b90-e52ee16c162f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864057662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2864057662
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2979743719
Short name T341
Test name
Test status
Simulation time 30559046581 ps
CPU time 51.87 seconds
Started Aug 15 06:29:33 PM PDT 24
Finished Aug 15 06:30:25 PM PDT 24
Peak memory 200912 kb
Host smart-b1fb9758-93b6-4b55-8fed-7483ce398cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979743719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2979743719
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.1138233538
Short name T822
Test name
Test status
Simulation time 20288306 ps
CPU time 0.52 seconds
Started Aug 15 06:25:35 PM PDT 24
Finished Aug 15 06:25:35 PM PDT 24
Peak memory 196280 kb
Host smart-ad909b39-be1c-4b1e-9734-c99f6a16fdf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138233538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.1138233538
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1865763552
Short name T154
Test name
Test status
Simulation time 216402296043 ps
CPU time 24.21 seconds
Started Aug 15 06:25:25 PM PDT 24
Finished Aug 15 06:25:49 PM PDT 24
Peak memory 200900 kb
Host smart-2e840b2c-21c4-4dc9-9879-82de21ed73b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865763552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1865763552
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.2366304255
Short name T472
Test name
Test status
Simulation time 18800154374 ps
CPU time 26.24 seconds
Started Aug 15 06:25:27 PM PDT 24
Finished Aug 15 06:25:53 PM PDT 24
Peak memory 200884 kb
Host smart-452d4b9d-7ceb-41c0-8703-24516df0d292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366304255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2366304255
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.1914937465
Short name T1019
Test name
Test status
Simulation time 64714055296 ps
CPU time 102.63 seconds
Started Aug 15 06:25:26 PM PDT 24
Finished Aug 15 06:27:09 PM PDT 24
Peak memory 200960 kb
Host smart-00f34606-521a-4201-8ff5-ef8a7ecd8271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914937465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1914937465
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1465754471
Short name T1124
Test name
Test status
Simulation time 8397008379 ps
CPU time 6.4 seconds
Started Aug 15 06:25:25 PM PDT 24
Finished Aug 15 06:25:32 PM PDT 24
Peak memory 197644 kb
Host smart-a079005c-f7a7-4fe9-a762-cac87c1358f9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465754471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1465754471
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.4066408529
Short name T783
Test name
Test status
Simulation time 103206986244 ps
CPU time 332.04 seconds
Started Aug 15 06:25:25 PM PDT 24
Finished Aug 15 06:30:57 PM PDT 24
Peak memory 200956 kb
Host smart-58e2e597-11d7-4720-a64f-3d461b6f921e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4066408529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.4066408529
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3488291476
Short name T977
Test name
Test status
Simulation time 6737456945 ps
CPU time 7.31 seconds
Started Aug 15 06:25:27 PM PDT 24
Finished Aug 15 06:25:34 PM PDT 24
Peak memory 200812 kb
Host smart-d0e04653-b752-40fd-857b-d0c9d2d0f0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488291476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3488291476
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.15320450
Short name T892
Test name
Test status
Simulation time 24507680631 ps
CPU time 41.54 seconds
Started Aug 15 06:25:26 PM PDT 24
Finished Aug 15 06:26:08 PM PDT 24
Peak memory 200788 kb
Host smart-8ab0db2c-3296-42ad-9358-a6620ab1883a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15320450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.15320450
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.1738718218
Short name T1181
Test name
Test status
Simulation time 12927407787 ps
CPU time 755.02 seconds
Started Aug 15 06:25:25 PM PDT 24
Finished Aug 15 06:38:00 PM PDT 24
Peak memory 200880 kb
Host smart-953db200-d099-47ca-b2bc-a0047c69af83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1738718218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.1738718218
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1997765954
Short name T1052
Test name
Test status
Simulation time 8197860667 ps
CPU time 20.3 seconds
Started Aug 15 06:25:27 PM PDT 24
Finished Aug 15 06:25:47 PM PDT 24
Peak memory 199456 kb
Host smart-ec5d183b-ca49-4b05-b574-b53e7551c05f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1997765954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1997765954
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3135773882
Short name T1105
Test name
Test status
Simulation time 33390098428 ps
CPU time 22.71 seconds
Started Aug 15 06:25:25 PM PDT 24
Finished Aug 15 06:25:48 PM PDT 24
Peak memory 200692 kb
Host smart-05133243-888c-4162-aa83-f60d00605d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135773882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3135773882
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.2839284023
Short name T698
Test name
Test status
Simulation time 3287739830 ps
CPU time 1.49 seconds
Started Aug 15 06:25:26 PM PDT 24
Finished Aug 15 06:25:27 PM PDT 24
Peak memory 197260 kb
Host smart-33aefb65-007f-45c1-a909-d970f91b3d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839284023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2839284023
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2265511896
Short name T808
Test name
Test status
Simulation time 141377210 ps
CPU time 0.85 seconds
Started Aug 15 06:25:22 PM PDT 24
Finished Aug 15 06:25:23 PM PDT 24
Peak memory 199256 kb
Host smart-eec8403a-73a8-49cb-bfdf-206d151fb555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265511896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2265511896
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3831601108
Short name T736
Test name
Test status
Simulation time 322321858121 ps
CPU time 351.08 seconds
Started Aug 15 06:25:25 PM PDT 24
Finished Aug 15 06:31:16 PM PDT 24
Peak memory 200888 kb
Host smart-8bf026dc-c385-464a-bc5b-4bff24e66f3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831601108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3831601108
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.929761431
Short name T770
Test name
Test status
Simulation time 4322299856 ps
CPU time 99.27 seconds
Started Aug 15 06:25:25 PM PDT 24
Finished Aug 15 06:27:05 PM PDT 24
Peak memory 217384 kb
Host smart-ab2501a5-36bb-46cb-a481-ba28f9c30930
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929761431 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.929761431
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1268106068
Short name T699
Test name
Test status
Simulation time 1018836013 ps
CPU time 1.65 seconds
Started Aug 15 06:25:26 PM PDT 24
Finished Aug 15 06:25:27 PM PDT 24
Peak memory 199612 kb
Host smart-31161968-48a8-4c5b-b210-242a4f0f99e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268106068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1268106068
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.454790566
Short name T261
Test name
Test status
Simulation time 35938407590 ps
CPU time 17.57 seconds
Started Aug 15 06:25:24 PM PDT 24
Finished Aug 15 06:25:41 PM PDT 24
Peak memory 200836 kb
Host smart-9f33d0cb-8797-4709-a13c-218b2a79c915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454790566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.454790566
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.3590670182
Short name T243
Test name
Test status
Simulation time 20129082276 ps
CPU time 16.16 seconds
Started Aug 15 06:29:38 PM PDT 24
Finished Aug 15 06:29:54 PM PDT 24
Peak memory 200456 kb
Host smart-fbd7f369-5b3d-401f-a691-1917963a9467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590670182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.3590670182
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2455232017
Short name T1138
Test name
Test status
Simulation time 14697865807 ps
CPU time 12.62 seconds
Started Aug 15 06:29:38 PM PDT 24
Finished Aug 15 06:29:51 PM PDT 24
Peak memory 200824 kb
Host smart-27cac23e-29d2-479c-912c-d1c77ffca379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455232017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2455232017
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.3859280742
Short name T101
Test name
Test status
Simulation time 6558248689 ps
CPU time 19.29 seconds
Started Aug 15 06:29:43 PM PDT 24
Finished Aug 15 06:30:03 PM PDT 24
Peak memory 209180 kb
Host smart-cc753434-d58b-495f-94bf-ee00c1279585
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859280742 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.3859280742
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.1874101426
Short name T1133
Test name
Test status
Simulation time 32170505042 ps
CPU time 44.2 seconds
Started Aug 15 06:29:44 PM PDT 24
Finished Aug 15 06:30:29 PM PDT 24
Peak memory 200896 kb
Host smart-35e8eb96-83a8-45a0-bf40-ef2228bb56b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874101426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1874101426
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.3011197459
Short name T1093
Test name
Test status
Simulation time 1576859888 ps
CPU time 20.31 seconds
Started Aug 15 06:29:41 PM PDT 24
Finished Aug 15 06:30:01 PM PDT 24
Peak memory 217304 kb
Host smart-61f8b7ae-8f0e-409e-835f-82f48aca35e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011197459 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.3011197459
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.479720131
Short name T721
Test name
Test status
Simulation time 16098699475 ps
CPU time 10.54 seconds
Started Aug 15 06:29:38 PM PDT 24
Finished Aug 15 06:29:49 PM PDT 24
Peak memory 200800 kb
Host smart-8d240260-ea94-49ca-a8d6-0513a6e4f3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479720131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.479720131
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.2529986496
Short name T970
Test name
Test status
Simulation time 2270378532 ps
CPU time 30.79 seconds
Started Aug 15 06:29:40 PM PDT 24
Finished Aug 15 06:30:11 PM PDT 24
Peak memory 201080 kb
Host smart-134dd018-6355-42a9-ada5-831133a0b2fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529986496 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2529986496
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1103375118
Short name T1114
Test name
Test status
Simulation time 33313598048 ps
CPU time 6.6 seconds
Started Aug 15 06:29:41 PM PDT 24
Finished Aug 15 06:29:48 PM PDT 24
Peak memory 199804 kb
Host smart-dc3a4807-cc82-403a-b192-1aade68bbca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103375118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1103375118
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.369762253
Short name T526
Test name
Test status
Simulation time 1583881029 ps
CPU time 10.7 seconds
Started Aug 15 06:29:39 PM PDT 24
Finished Aug 15 06:29:50 PM PDT 24
Peak memory 200888 kb
Host smart-a05bb147-fc99-4186-953d-59b5a38e29b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369762253 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.369762253
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.2925533719
Short name T579
Test name
Test status
Simulation time 59909117048 ps
CPU time 30.28 seconds
Started Aug 15 06:29:39 PM PDT 24
Finished Aug 15 06:30:10 PM PDT 24
Peak memory 200944 kb
Host smart-78efc6f6-fb26-4bcf-a6e8-82d6019e76a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925533719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2925533719
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.488704873
Short name T722
Test name
Test status
Simulation time 4120367867 ps
CPU time 57.05 seconds
Started Aug 15 06:29:41 PM PDT 24
Finished Aug 15 06:30:39 PM PDT 24
Peak memory 216888 kb
Host smart-a67fa503-cd01-4cfd-b1b7-40f5541dce05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488704873 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.488704873
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3195053467
Short name T805
Test name
Test status
Simulation time 1215470101 ps
CPU time 23.06 seconds
Started Aug 15 06:29:39 PM PDT 24
Finished Aug 15 06:30:02 PM PDT 24
Peak memory 217484 kb
Host smart-2dcd8769-d968-4bc0-861c-65b099974151
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195053467 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3195053467
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.649845753
Short name T635
Test name
Test status
Simulation time 6935136546 ps
CPU time 17.9 seconds
Started Aug 15 06:29:37 PM PDT 24
Finished Aug 15 06:29:55 PM PDT 24
Peak memory 209340 kb
Host smart-f0b5a51c-75d1-436e-8a2b-a9cc11b00c2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649845753 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.649845753
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.2385578039
Short name T1017
Test name
Test status
Simulation time 69481570760 ps
CPU time 28.55 seconds
Started Aug 15 06:29:38 PM PDT 24
Finished Aug 15 06:30:07 PM PDT 24
Peak memory 200804 kb
Host smart-fb0352d0-4831-4a64-aefe-e39958f7f25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385578039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2385578039
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.1170956383
Short name T785
Test name
Test status
Simulation time 3909544206 ps
CPU time 50.84 seconds
Started Aug 15 06:29:39 PM PDT 24
Finished Aug 15 06:30:30 PM PDT 24
Peak memory 217588 kb
Host smart-528f6a81-5086-4193-8b9d-cf9c36d3ad9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170956383 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.1170956383
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3087623058
Short name T466
Test name
Test status
Simulation time 10462532608 ps
CPU time 8.52 seconds
Started Aug 15 06:29:37 PM PDT 24
Finished Aug 15 06:29:46 PM PDT 24
Peak memory 200364 kb
Host smart-55147f6a-d815-4cb2-a9a1-37fc7a35dfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087623058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3087623058
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1543010549
Short name T894
Test name
Test status
Simulation time 1517637502 ps
CPU time 10.82 seconds
Started Aug 15 06:29:38 PM PDT 24
Finished Aug 15 06:29:49 PM PDT 24
Peak memory 200908 kb
Host smart-84267006-e49e-47cf-920c-a88da7b206c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543010549 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1543010549
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.4166011108
Short name T1053
Test name
Test status
Simulation time 21651253 ps
CPU time 0.53 seconds
Started Aug 15 06:25:34 PM PDT 24
Finished Aug 15 06:25:34 PM PDT 24
Peak memory 195648 kb
Host smart-ba0f2a6f-9a6c-4a34-b433-bd7caa387904
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166011108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.4166011108
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.211000049
Short name T705
Test name
Test status
Simulation time 203475395554 ps
CPU time 289.01 seconds
Started Aug 15 06:25:37 PM PDT 24
Finished Aug 15 06:30:26 PM PDT 24
Peak memory 200872 kb
Host smart-aec6ca48-fbce-4c28-b8b3-a935fc5b1c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211000049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.211000049
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2313404582
Short name T1068
Test name
Test status
Simulation time 32482470012 ps
CPU time 24 seconds
Started Aug 15 06:25:34 PM PDT 24
Finished Aug 15 06:25:58 PM PDT 24
Peak memory 200924 kb
Host smart-c0a46188-584b-4d60-ba0f-c8abcb1c9518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313404582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2313404582
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.2650049652
Short name T875
Test name
Test status
Simulation time 136470356635 ps
CPU time 31.69 seconds
Started Aug 15 06:25:38 PM PDT 24
Finished Aug 15 06:26:09 PM PDT 24
Peak memory 200904 kb
Host smart-537991e2-77ab-44bb-93ad-ae8ddfb58ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650049652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2650049652
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.3946041622
Short name T500
Test name
Test status
Simulation time 7365372766 ps
CPU time 3.22 seconds
Started Aug 15 06:25:35 PM PDT 24
Finished Aug 15 06:25:39 PM PDT 24
Peak memory 197192 kb
Host smart-9050bf04-76db-429b-97d6-5a6b2cab0091
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946041622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3946041622
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1005350363
Short name T796
Test name
Test status
Simulation time 125987387005 ps
CPU time 301.77 seconds
Started Aug 15 06:25:33 PM PDT 24
Finished Aug 15 06:30:35 PM PDT 24
Peak memory 200884 kb
Host smart-17e7b534-0abe-4036-a946-d70a9a541c8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1005350363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1005350363
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1605000884
Short name T856
Test name
Test status
Simulation time 594954153 ps
CPU time 1.48 seconds
Started Aug 15 06:25:36 PM PDT 24
Finished Aug 15 06:25:38 PM PDT 24
Peak memory 196564 kb
Host smart-af1d153f-3ad2-46ac-81d1-84f4ac3b31c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605000884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1605000884
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.3609695508
Short name T249
Test name
Test status
Simulation time 45058381481 ps
CPU time 48.79 seconds
Started Aug 15 06:25:34 PM PDT 24
Finished Aug 15 06:26:23 PM PDT 24
Peak memory 209288 kb
Host smart-a30eb461-19b8-4a54-a34c-f7b27c35ed99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609695508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3609695508
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.4016594235
Short name T1130
Test name
Test status
Simulation time 32825258814 ps
CPU time 414.76 seconds
Started Aug 15 06:25:37 PM PDT 24
Finished Aug 15 06:32:32 PM PDT 24
Peak memory 200956 kb
Host smart-73c79626-0967-40bc-9045-761a824395ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4016594235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.4016594235
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3639479383
Short name T834
Test name
Test status
Simulation time 3390045857 ps
CPU time 14.17 seconds
Started Aug 15 06:25:44 PM PDT 24
Finished Aug 15 06:25:58 PM PDT 24
Peak memory 198884 kb
Host smart-9d49492d-76ac-4531-9056-0ea784b2327c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3639479383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3639479383
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1533917146
Short name T179
Test name
Test status
Simulation time 151546091416 ps
CPU time 67.77 seconds
Started Aug 15 06:25:35 PM PDT 24
Finished Aug 15 06:26:43 PM PDT 24
Peak memory 200920 kb
Host smart-f6f00dc9-b4aa-4e3b-85bd-61534d30ceb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533917146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1533917146
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1696402644
Short name T441
Test name
Test status
Simulation time 2127758799 ps
CPU time 2.13 seconds
Started Aug 15 06:25:35 PM PDT 24
Finished Aug 15 06:25:37 PM PDT 24
Peak memory 196600 kb
Host smart-ab2bb326-b966-4cbc-a64d-3dab917fad53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696402644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1696402644
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.855872208
Short name T692
Test name
Test status
Simulation time 409366929 ps
CPU time 1.78 seconds
Started Aug 15 06:25:35 PM PDT 24
Finished Aug 15 06:25:37 PM PDT 24
Peak memory 200612 kb
Host smart-1c8aeb09-a00f-4a40-a52e-8deb1dfded8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855872208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.855872208
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2194024556
Short name T905
Test name
Test status
Simulation time 647092205866 ps
CPU time 418.09 seconds
Started Aug 15 06:25:33 PM PDT 24
Finished Aug 15 06:32:31 PM PDT 24
Peak memory 200976 kb
Host smart-9f6e8a16-aef1-4369-8253-b8409a9fa34c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194024556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2194024556
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3795889936
Short name T25
Test name
Test status
Simulation time 2133067948 ps
CPU time 14.38 seconds
Started Aug 15 06:25:36 PM PDT 24
Finished Aug 15 06:25:51 PM PDT 24
Peak memory 207780 kb
Host smart-99a19d06-08a3-4537-9945-37e9f8a3f4ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795889936 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3795889936
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.3146729122
Short name T987
Test name
Test status
Simulation time 2632208126 ps
CPU time 2.34 seconds
Started Aug 15 06:25:34 PM PDT 24
Finished Aug 15 06:25:36 PM PDT 24
Peak memory 199924 kb
Host smart-e3756438-ae5e-4b7e-aaef-fea9f3de339b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146729122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3146729122
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2150826067
Short name T891
Test name
Test status
Simulation time 63060282946 ps
CPU time 51.63 seconds
Started Aug 15 06:25:35 PM PDT 24
Finished Aug 15 06:26:26 PM PDT 24
Peak memory 200848 kb
Host smart-71cb6475-1066-4875-b864-b0ec8ba02c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150826067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2150826067
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1265498127
Short name T156
Test name
Test status
Simulation time 204372979123 ps
CPU time 133.22 seconds
Started Aug 15 06:29:48 PM PDT 24
Finished Aug 15 06:32:02 PM PDT 24
Peak memory 200928 kb
Host smart-0bc965b7-1fdd-40e8-bf0c-d4126a55cdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265498127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1265498127
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.2776821734
Short name T600
Test name
Test status
Simulation time 14571078195 ps
CPU time 33.67 seconds
Started Aug 15 06:29:51 PM PDT 24
Finished Aug 15 06:30:25 PM PDT 24
Peak memory 217544 kb
Host smart-b95a6c48-5c4f-4faf-a33b-575d5cdde9f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776821734 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.2776821734
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1584106368
Short name T209
Test name
Test status
Simulation time 20258556961 ps
CPU time 13.86 seconds
Started Aug 15 06:29:49 PM PDT 24
Finished Aug 15 06:30:03 PM PDT 24
Peak memory 200896 kb
Host smart-b8730e54-4fe5-4e89-a933-33e397b50b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584106368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1584106368
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.3327705324
Short name T100
Test name
Test status
Simulation time 5007924503 ps
CPU time 73.89 seconds
Started Aug 15 06:29:47 PM PDT 24
Finished Aug 15 06:31:01 PM PDT 24
Peak memory 210460 kb
Host smart-e81a06af-c23c-4d28-ab47-e94d3cd4c99d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327705324 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.3327705324
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.1217533726
Short name T1118
Test name
Test status
Simulation time 42730122888 ps
CPU time 17.24 seconds
Started Aug 15 06:29:50 PM PDT 24
Finished Aug 15 06:30:08 PM PDT 24
Peak memory 200944 kb
Host smart-4d42c9df-6b11-480c-b953-b467bfd73af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217533726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1217533726
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3705944677
Short name T39
Test name
Test status
Simulation time 2789631435 ps
CPU time 28.05 seconds
Started Aug 15 06:29:49 PM PDT 24
Finished Aug 15 06:30:17 PM PDT 24
Peak memory 201024 kb
Host smart-5f09fe7e-1a38-45d2-a43b-0f606d5743fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705944677 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3705944677
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2253652610
Short name T460
Test name
Test status
Simulation time 142003107752 ps
CPU time 146.48 seconds
Started Aug 15 06:29:49 PM PDT 24
Finished Aug 15 06:32:16 PM PDT 24
Peak memory 200860 kb
Host smart-f4599990-08e0-4961-9db7-c597b4290a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253652610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2253652610
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.1428965182
Short name T113
Test name
Test status
Simulation time 42765177253 ps
CPU time 97.73 seconds
Started Aug 15 06:29:51 PM PDT 24
Finished Aug 15 06:31:29 PM PDT 24
Peak memory 200848 kb
Host smart-c2665b1c-a760-407f-b6ed-6272c95ad871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428965182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.1428965182
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.3971461440
Short name T860
Test name
Test status
Simulation time 4442137340 ps
CPU time 48.68 seconds
Started Aug 15 06:29:48 PM PDT 24
Finished Aug 15 06:30:37 PM PDT 24
Peak memory 209428 kb
Host smart-c21ed5f7-0477-4109-8f95-22dd0fbaa375
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971461440 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.3971461440
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.436971583
Short name T776
Test name
Test status
Simulation time 53168216161 ps
CPU time 17 seconds
Started Aug 15 06:29:49 PM PDT 24
Finished Aug 15 06:30:06 PM PDT 24
Peak memory 200904 kb
Host smart-f906d450-696e-4440-98f0-7e2292e1e460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436971583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.436971583
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.88369005
Short name T944
Test name
Test status
Simulation time 2925183796 ps
CPU time 31.89 seconds
Started Aug 15 06:29:48 PM PDT 24
Finished Aug 15 06:30:20 PM PDT 24
Peak memory 209424 kb
Host smart-42be1142-fe84-4b24-bfad-3e9ede7165a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88369005 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.88369005
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.2469440986
Short name T301
Test name
Test status
Simulation time 194282406681 ps
CPU time 119.57 seconds
Started Aug 15 06:29:47 PM PDT 24
Finished Aug 15 06:31:47 PM PDT 24
Peak memory 200956 kb
Host smart-e01b90cd-84cc-4f63-9815-35ac1c35922c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469440986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2469440986
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.1310234269
Short name T815
Test name
Test status
Simulation time 5501770039 ps
CPU time 42.37 seconds
Started Aug 15 06:29:49 PM PDT 24
Finished Aug 15 06:30:32 PM PDT 24
Peak memory 217600 kb
Host smart-1021d647-82e8-447f-97c3-aa8d2cf1d674
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310234269 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.1310234269
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.3649654138
Short name T913
Test name
Test status
Simulation time 17226652015 ps
CPU time 6.94 seconds
Started Aug 15 06:29:49 PM PDT 24
Finished Aug 15 06:29:56 PM PDT 24
Peak memory 199940 kb
Host smart-38037857-d11d-4121-b282-f1ebd799e672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649654138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3649654138
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1281212866
Short name T1153
Test name
Test status
Simulation time 14525714201 ps
CPU time 62.18 seconds
Started Aug 15 06:29:48 PM PDT 24
Finished Aug 15 06:30:51 PM PDT 24
Peak memory 217532 kb
Host smart-ff6388a3-f872-4b42-853c-ab478c5b3751
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281212866 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1281212866
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.3096096063
Short name T745
Test name
Test status
Simulation time 17840468175 ps
CPU time 25.5 seconds
Started Aug 15 06:29:48 PM PDT 24
Finished Aug 15 06:30:13 PM PDT 24
Peak memory 200972 kb
Host smart-b2387f49-e284-4d18-881a-9c0db254d471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096096063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3096096063
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.799915249
Short name T510
Test name
Test status
Simulation time 2745733089 ps
CPU time 29.6 seconds
Started Aug 15 06:29:51 PM PDT 24
Finished Aug 15 06:30:21 PM PDT 24
Peak memory 217400 kb
Host smart-2725c5a9-aa60-41db-8cc4-1faafefd5226
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799915249 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.799915249
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.2978703769
Short name T619
Test name
Test status
Simulation time 35581273283 ps
CPU time 28.9 seconds
Started Aug 15 06:29:51 PM PDT 24
Finished Aug 15 06:30:20 PM PDT 24
Peak memory 200916 kb
Host smart-1eec872e-302e-4e92-b9ac-9ebdaaaedd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978703769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2978703769
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.3717077796
Short name T544
Test name
Test status
Simulation time 5519902113 ps
CPU time 36.78 seconds
Started Aug 15 06:29:51 PM PDT 24
Finished Aug 15 06:30:28 PM PDT 24
Peak memory 217352 kb
Host smart-5bb77a35-8728-46d8-a943-0cf0ba41b82b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717077796 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.3717077796
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.4073813640
Short name T415
Test name
Test status
Simulation time 12025513 ps
CPU time 0.56 seconds
Started Aug 15 06:25:46 PM PDT 24
Finished Aug 15 06:25:47 PM PDT 24
Peak memory 196256 kb
Host smart-bc049226-9e11-42f9-a941-90faeae5d31c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073813640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.4073813640
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2563575143
Short name T594
Test name
Test status
Simulation time 57604146458 ps
CPU time 43.85 seconds
Started Aug 15 06:25:33 PM PDT 24
Finished Aug 15 06:26:17 PM PDT 24
Peak memory 200828 kb
Host smart-a7de6ff4-5f5b-494e-a78d-a91990b3ac88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563575143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2563575143
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.210715362
Short name T170
Test name
Test status
Simulation time 113462575611 ps
CPU time 111.56 seconds
Started Aug 15 06:25:34 PM PDT 24
Finished Aug 15 06:27:26 PM PDT 24
Peak memory 200916 kb
Host smart-c86791d1-289e-45b5-93d7-c32ea5c0b62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210715362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.210715362
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.626466428
Short name T942
Test name
Test status
Simulation time 60330175884 ps
CPU time 38.89 seconds
Started Aug 15 06:25:40 PM PDT 24
Finished Aug 15 06:26:19 PM PDT 24
Peak memory 200956 kb
Host smart-e14dec78-9c5e-4aac-b84d-5217342a3653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626466428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.626466428
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.2674927737
Short name T963
Test name
Test status
Simulation time 158537678868 ps
CPU time 70.22 seconds
Started Aug 15 06:25:41 PM PDT 24
Finished Aug 15 06:26:51 PM PDT 24
Peak memory 200848 kb
Host smart-82337f66-55b4-4f81-8cf7-c8e2402197e8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674927737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2674927737
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.351014062
Short name T885
Test name
Test status
Simulation time 130057220346 ps
CPU time 513.67 seconds
Started Aug 15 06:25:47 PM PDT 24
Finished Aug 15 06:34:20 PM PDT 24
Peak memory 200904 kb
Host smart-b3f06ff1-c537-4435-a353-5506b2e8f560
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=351014062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.351014062
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1412104535
Short name T391
Test name
Test status
Simulation time 8463906411 ps
CPU time 16.56 seconds
Started Aug 15 06:25:42 PM PDT 24
Finished Aug 15 06:25:59 PM PDT 24
Peak memory 200380 kb
Host smart-4540195f-4112-44f1-8c0f-1cffb428a08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412104535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1412104535
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.2331179790
Short name T557
Test name
Test status
Simulation time 33375610620 ps
CPU time 16.51 seconds
Started Aug 15 06:25:40 PM PDT 24
Finished Aug 15 06:25:57 PM PDT 24
Peak memory 209328 kb
Host smart-36fcafeb-c2b2-4e5e-bd68-4fc873bad027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331179790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2331179790
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.3759954475
Short name T726
Test name
Test status
Simulation time 7392852501 ps
CPU time 109.08 seconds
Started Aug 15 06:25:41 PM PDT 24
Finished Aug 15 06:27:30 PM PDT 24
Peak memory 200972 kb
Host smart-ec772f56-7a13-4d29-b795-63fbd40af830
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3759954475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3759954475
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.992289788
Short name T723
Test name
Test status
Simulation time 3249468269 ps
CPU time 4.31 seconds
Started Aug 15 06:25:44 PM PDT 24
Finished Aug 15 06:25:49 PM PDT 24
Peak memory 199148 kb
Host smart-afc5235f-13c8-48ab-892d-79ee447b9f69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=992289788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.992289788
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.4288251742
Short name T590
Test name
Test status
Simulation time 127997196776 ps
CPU time 61.61 seconds
Started Aug 15 06:25:40 PM PDT 24
Finished Aug 15 06:26:42 PM PDT 24
Peak memory 200900 kb
Host smart-9448eb1b-8124-4e03-af37-6aa895c4423b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288251742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.4288251742
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.2991170374
Short name T952
Test name
Test status
Simulation time 4882852960 ps
CPU time 8.3 seconds
Started Aug 15 06:25:46 PM PDT 24
Finished Aug 15 06:25:54 PM PDT 24
Peak memory 197020 kb
Host smart-f0fa3aef-02ee-4140-ba8e-fe7525fc305f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991170374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2991170374
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.202861058
Short name T418
Test name
Test status
Simulation time 952651009 ps
CPU time 2.3 seconds
Started Aug 15 06:25:36 PM PDT 24
Finished Aug 15 06:25:38 PM PDT 24
Peak memory 199740 kb
Host smart-3ff32b7a-8842-41e0-b103-ab1fcd8042c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202861058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.202861058
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.2950400128
Short name T122
Test name
Test status
Simulation time 178290360382 ps
CPU time 59.13 seconds
Started Aug 15 06:25:48 PM PDT 24
Finished Aug 15 06:26:47 PM PDT 24
Peak memory 201076 kb
Host smart-beca8179-7226-4d67-8986-98d74f68fc3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950400128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2950400128
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.347374495
Short name T841
Test name
Test status
Simulation time 7815566319 ps
CPU time 7.34 seconds
Started Aug 15 06:25:45 PM PDT 24
Finished Aug 15 06:25:53 PM PDT 24
Peak memory 200588 kb
Host smart-fb66dc1c-d584-4ca6-9b57-1c4c88991328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347374495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.347374495
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1410329076
Short name T604
Test name
Test status
Simulation time 74443455470 ps
CPU time 31.06 seconds
Started Aug 15 06:25:35 PM PDT 24
Finished Aug 15 06:26:06 PM PDT 24
Peak memory 200948 kb
Host smart-d3c9f0f6-cd4b-499c-beef-6c3d580fe30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410329076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1410329076
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.940852387
Short name T1140
Test name
Test status
Simulation time 10213401133 ps
CPU time 38.47 seconds
Started Aug 15 06:29:51 PM PDT 24
Finished Aug 15 06:30:29 PM PDT 24
Peak memory 210400 kb
Host smart-7d69d5b9-d23f-4102-829f-e36473918569
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940852387 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.940852387
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.553924332
Short name T225
Test name
Test status
Simulation time 11712273918 ps
CPU time 14.48 seconds
Started Aug 15 06:29:51 PM PDT 24
Finished Aug 15 06:30:06 PM PDT 24
Peak memory 200624 kb
Host smart-d7b4cd57-c448-40cd-a74b-0d73e33e8ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553924332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.553924332
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.10948359
Short name T1071
Test name
Test status
Simulation time 3077084336 ps
CPU time 37.75 seconds
Started Aug 15 06:29:53 PM PDT 24
Finished Aug 15 06:30:31 PM PDT 24
Peak memory 216500 kb
Host smart-bf978d14-f4ce-40a8-99d6-c21106fb4f2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10948359 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.10948359
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.2695928262
Short name T784
Test name
Test status
Simulation time 23871933213 ps
CPU time 151.03 seconds
Started Aug 15 06:29:49 PM PDT 24
Finished Aug 15 06:32:20 PM PDT 24
Peak memory 216820 kb
Host smart-87d55572-c8bd-4d7a-a792-601a039758b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695928262 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.2695928262
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3229491707
Short name T211
Test name
Test status
Simulation time 18969342017 ps
CPU time 29.51 seconds
Started Aug 15 06:29:59 PM PDT 24
Finished Aug 15 06:30:29 PM PDT 24
Peak memory 200896 kb
Host smart-ff363990-1fbb-4c70-866e-2761c824d550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229491707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3229491707
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3264196678
Short name T657
Test name
Test status
Simulation time 1747745610 ps
CPU time 69.42 seconds
Started Aug 15 06:29:56 PM PDT 24
Finished Aug 15 06:31:06 PM PDT 24
Peak memory 209312 kb
Host smart-e9f768ae-2d4e-4d6a-bfae-29bc0063d14f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264196678 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3264196678
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1954477476
Short name T178
Test name
Test status
Simulation time 31225457406 ps
CPU time 35.88 seconds
Started Aug 15 06:29:57 PM PDT 24
Finished Aug 15 06:30:33 PM PDT 24
Peak memory 200908 kb
Host smart-761aaf52-afa6-4e6b-8d5c-4aae7d952ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954477476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1954477476
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3418547341
Short name T16
Test name
Test status
Simulation time 6096229598 ps
CPU time 171.9 seconds
Started Aug 15 06:29:58 PM PDT 24
Finished Aug 15 06:32:50 PM PDT 24
Peak memory 216884 kb
Host smart-e01035a3-d782-4b24-a8fe-bb3b1c9bf3dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418547341 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3418547341
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3063266637
Short name T207
Test name
Test status
Simulation time 196408684728 ps
CPU time 36.02 seconds
Started Aug 15 06:30:01 PM PDT 24
Finished Aug 15 06:30:37 PM PDT 24
Peak memory 200888 kb
Host smart-c7340b99-8a63-42ea-8234-94928132ae49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063266637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3063266637
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1169304718
Short name T1103
Test name
Test status
Simulation time 38176563596 ps
CPU time 43.26 seconds
Started Aug 15 06:30:00 PM PDT 24
Finished Aug 15 06:30:44 PM PDT 24
Peak memory 217544 kb
Host smart-09bc865c-ec31-49cd-befa-174eaf96f298
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169304718 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1169304718
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.2413638595
Short name T284
Test name
Test status
Simulation time 10180850085 ps
CPU time 32.16 seconds
Started Aug 15 06:29:55 PM PDT 24
Finished Aug 15 06:30:28 PM PDT 24
Peak memory 209396 kb
Host smart-7ce3c555-d327-474b-aebc-be2cd146099a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413638595 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2413638595
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.4222359688
Short name T888
Test name
Test status
Simulation time 117821220340 ps
CPU time 177.6 seconds
Started Aug 15 06:30:00 PM PDT 24
Finished Aug 15 06:32:58 PM PDT 24
Peak memory 200944 kb
Host smart-6747ae20-c487-4881-b18f-91f6ecfd8231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222359688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.4222359688
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.3341723043
Short name T933
Test name
Test status
Simulation time 9412568574 ps
CPU time 28.19 seconds
Started Aug 15 06:30:05 PM PDT 24
Finished Aug 15 06:30:33 PM PDT 24
Peak memory 209956 kb
Host smart-9a5562b3-e51c-4287-808a-5c8775389830
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341723043 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.3341723043
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.646521382
Short name T145
Test name
Test status
Simulation time 93097238399 ps
CPU time 146.56 seconds
Started Aug 15 06:29:58 PM PDT 24
Finished Aug 15 06:32:25 PM PDT 24
Peak memory 200948 kb
Host smart-8262f70c-b692-4620-b19f-f2dfaa07d2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646521382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.646521382
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.992574359
Short name T402
Test name
Test status
Simulation time 18835915058 ps
CPU time 32.11 seconds
Started Aug 15 06:29:58 PM PDT 24
Finished Aug 15 06:30:30 PM PDT 24
Peak memory 200820 kb
Host smart-43eb2994-0ed4-4d42-ab3d-f59202637c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992574359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.992574359
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2365332088
Short name T606
Test name
Test status
Simulation time 10078199180 ps
CPU time 12.25 seconds
Started Aug 15 06:29:57 PM PDT 24
Finished Aug 15 06:30:09 PM PDT 24
Peak memory 217376 kb
Host smart-2e72a62b-4610-4536-bc0a-ae5ecac5fbd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365332088 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2365332088
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2508677927
Short name T382
Test name
Test status
Simulation time 32836702 ps
CPU time 0.55 seconds
Started Aug 15 06:25:47 PM PDT 24
Finished Aug 15 06:25:48 PM PDT 24
Peak memory 196260 kb
Host smart-d691fd86-be8e-49cd-80e6-c5bb7997ade9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508677927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2508677927
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3444786626
Short name T362
Test name
Test status
Simulation time 92211929702 ps
CPU time 17.25 seconds
Started Aug 15 06:25:48 PM PDT 24
Finished Aug 15 06:26:05 PM PDT 24
Peak memory 200936 kb
Host smart-d7fc4fbc-eeb7-44b1-9e77-c7d85c40bc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444786626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3444786626
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.2609049987
Short name T1089
Test name
Test status
Simulation time 20720195418 ps
CPU time 32.46 seconds
Started Aug 15 06:25:49 PM PDT 24
Finished Aug 15 06:26:22 PM PDT 24
Peak memory 200716 kb
Host smart-fe40c1b3-99d2-4e8d-b87a-23dc512bfc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609049987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2609049987
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.1973812297
Short name T559
Test name
Test status
Simulation time 18143124288 ps
CPU time 14.63 seconds
Started Aug 15 06:25:49 PM PDT 24
Finished Aug 15 06:26:03 PM PDT 24
Peak memory 200840 kb
Host smart-10a0cdf8-556f-43e9-9b5d-6374f7d423e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973812297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1973812297
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.1453268758
Short name T931
Test name
Test status
Simulation time 11358838635 ps
CPU time 10.34 seconds
Started Aug 15 06:25:46 PM PDT 24
Finished Aug 15 06:25:57 PM PDT 24
Peak memory 200904 kb
Host smart-67ecf0cd-7719-48a1-86c1-847920c5228a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453268758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.1453268758
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.71172057
Short name T809
Test name
Test status
Simulation time 67298971701 ps
CPU time 153.51 seconds
Started Aug 15 06:25:48 PM PDT 24
Finished Aug 15 06:28:22 PM PDT 24
Peak memory 200860 kb
Host smart-85980dce-a16b-415f-8cd7-f2ee86620cb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=71172057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.71172057
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.2739120810
Short name T618
Test name
Test status
Simulation time 529334649 ps
CPU time 0.79 seconds
Started Aug 15 06:25:52 PM PDT 24
Finished Aug 15 06:25:53 PM PDT 24
Peak memory 196324 kb
Host smart-fff25efc-c192-4f19-8e4a-5516b518ebf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739120810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2739120810
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.3092541451
Short name T1088
Test name
Test status
Simulation time 225648092366 ps
CPU time 69.1 seconds
Started Aug 15 06:25:47 PM PDT 24
Finished Aug 15 06:26:56 PM PDT 24
Peak memory 201108 kb
Host smart-32bc2b7e-80cc-49ec-af4e-4afa5bf5c404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092541451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3092541451
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3034120091
Short name T1186
Test name
Test status
Simulation time 16433849481 ps
CPU time 233.93 seconds
Started Aug 15 06:25:47 PM PDT 24
Finished Aug 15 06:29:41 PM PDT 24
Peak memory 200868 kb
Host smart-c93db8e5-0594-4c4c-9d5d-f92cdd0110cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3034120091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3034120091
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3605286380
Short name T1027
Test name
Test status
Simulation time 7490364481 ps
CPU time 54.52 seconds
Started Aug 15 06:25:47 PM PDT 24
Finished Aug 15 06:26:42 PM PDT 24
Peak memory 200240 kb
Host smart-ac13d293-cb37-4533-863a-3815770e2c54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3605286380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3605286380
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.1626799676
Short name T1185
Test name
Test status
Simulation time 135338029319 ps
CPU time 163.77 seconds
Started Aug 15 06:25:46 PM PDT 24
Finished Aug 15 06:28:30 PM PDT 24
Peak memory 200892 kb
Host smart-1660e1ce-ddfa-4f2b-9334-34df37e49824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626799676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1626799676
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3165963662
Short name T1022
Test name
Test status
Simulation time 4265239313 ps
CPU time 1.53 seconds
Started Aug 15 06:25:49 PM PDT 24
Finished Aug 15 06:25:51 PM PDT 24
Peak memory 197020 kb
Host smart-1e642917-8105-4b5d-bd47-a9a67029f0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165963662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3165963662
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.2299874653
Short name T353
Test name
Test status
Simulation time 848356179 ps
CPU time 2.76 seconds
Started Aug 15 06:25:49 PM PDT 24
Finished Aug 15 06:25:52 PM PDT 24
Peak memory 199892 kb
Host smart-6fd94cd8-017e-40af-acae-eaebdc5d98bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299874653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2299874653
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.4132111163
Short name T958
Test name
Test status
Simulation time 5511941274 ps
CPU time 30.53 seconds
Started Aug 15 06:25:49 PM PDT 24
Finished Aug 15 06:26:19 PM PDT 24
Peak memory 217516 kb
Host smart-9db91ce4-7270-4842-a4bd-0b7bd7f6628a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132111163 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.4132111163
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.253632382
Short name T1178
Test name
Test status
Simulation time 1130050845 ps
CPU time 2.23 seconds
Started Aug 15 06:25:49 PM PDT 24
Finished Aug 15 06:25:51 PM PDT 24
Peak memory 200876 kb
Host smart-4e87e1f2-40de-4f85-9e68-78c26b6f37da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253632382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.253632382
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.1448183757
Short name T570
Test name
Test status
Simulation time 79105551152 ps
CPU time 14.76 seconds
Started Aug 15 06:25:47 PM PDT 24
Finished Aug 15 06:26:02 PM PDT 24
Peak memory 200872 kb
Host smart-21a2b1c9-98b7-4865-8173-655dad2337ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448183757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1448183757
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2566912046
Short name T111
Test name
Test status
Simulation time 25425552362 ps
CPU time 42.17 seconds
Started Aug 15 06:30:00 PM PDT 24
Finished Aug 15 06:30:43 PM PDT 24
Peak memory 200912 kb
Host smart-7bb91c78-6f55-4ae6-ab8b-20838b027f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566912046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2566912046
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3732612055
Short name T326
Test name
Test status
Simulation time 7125964345 ps
CPU time 49.58 seconds
Started Aug 15 06:29:57 PM PDT 24
Finished Aug 15 06:30:47 PM PDT 24
Peak memory 216464 kb
Host smart-57184621-c4cd-4b41-a9b7-9df1748ec98d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732612055 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3732612055
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.77186594
Short name T999
Test name
Test status
Simulation time 243636150761 ps
CPU time 84.1 seconds
Started Aug 15 06:29:59 PM PDT 24
Finished Aug 15 06:31:23 PM PDT 24
Peak memory 200888 kb
Host smart-3914ba6b-86d7-49c1-a4c6-73cbc305fd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77186594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.77186594
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2007687072
Short name T739
Test name
Test status
Simulation time 28534635523 ps
CPU time 59.7 seconds
Started Aug 15 06:29:59 PM PDT 24
Finished Aug 15 06:30:59 PM PDT 24
Peak memory 213048 kb
Host smart-fc0b7aff-7b89-4414-992c-b343188ddedc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007687072 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2007687072
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.1418587750
Short name T1116
Test name
Test status
Simulation time 39980865392 ps
CPU time 22.32 seconds
Started Aug 15 06:29:58 PM PDT 24
Finished Aug 15 06:30:21 PM PDT 24
Peak memory 200916 kb
Host smart-f96420c3-1146-4104-aaa9-8f554633c5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418587750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1418587750
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.490068546
Short name T1164
Test name
Test status
Simulation time 8975701892 ps
CPU time 29.32 seconds
Started Aug 15 06:29:58 PM PDT 24
Finished Aug 15 06:30:28 PM PDT 24
Peak memory 201028 kb
Host smart-9ba5a459-c856-4606-a5b9-960cf9966e71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490068546 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.490068546
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.672739851
Short name T130
Test name
Test status
Simulation time 98389116272 ps
CPU time 128.89 seconds
Started Aug 15 06:29:56 PM PDT 24
Finished Aug 15 06:32:05 PM PDT 24
Peak memory 200916 kb
Host smart-eeb2c460-f37e-49d5-a698-b9c50e6b4bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672739851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.672739851
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2130847350
Short name T95
Test name
Test status
Simulation time 10460723513 ps
CPU time 24.19 seconds
Started Aug 15 06:29:56 PM PDT 24
Finished Aug 15 06:30:21 PM PDT 24
Peak memory 217512 kb
Host smart-7505bd9d-b3b1-44c3-bfc8-0176c19fbf77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130847350 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2130847350
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.686048356
Short name T1165
Test name
Test status
Simulation time 93715561380 ps
CPU time 138.63 seconds
Started Aug 15 06:29:59 PM PDT 24
Finished Aug 15 06:32:18 PM PDT 24
Peak memory 200760 kb
Host smart-78583c11-9fde-4cc3-bcd4-06442f5f10a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686048356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.686048356
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.653925867
Short name T92
Test name
Test status
Simulation time 3415409773 ps
CPU time 44.39 seconds
Started Aug 15 06:30:00 PM PDT 24
Finished Aug 15 06:30:44 PM PDT 24
Peak memory 217184 kb
Host smart-646edb3f-8f75-4092-90f2-eede3e48bd26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653925867 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.653925867
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3748558885
Short name T340
Test name
Test status
Simulation time 19833424629 ps
CPU time 28.66 seconds
Started Aug 15 06:29:57 PM PDT 24
Finished Aug 15 06:30:25 PM PDT 24
Peak memory 200900 kb
Host smart-9183f5e3-49f5-4f87-99bb-c1369a498929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748558885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3748558885
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.3085278578
Short name T1128
Test name
Test status
Simulation time 5716225420 ps
CPU time 49.18 seconds
Started Aug 15 06:29:58 PM PDT 24
Finished Aug 15 06:30:47 PM PDT 24
Peak memory 209152 kb
Host smart-f4842311-bb3f-43eb-9b3a-c190b8e9fd2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085278578 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.3085278578
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3185806028
Short name T458
Test name
Test status
Simulation time 82865657032 ps
CPU time 35.37 seconds
Started Aug 15 06:29:59 PM PDT 24
Finished Aug 15 06:30:35 PM PDT 24
Peak memory 200904 kb
Host smart-6e57d38b-c6bb-4474-ae86-52beeef64789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185806028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3185806028
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.110255444
Short name T481
Test name
Test status
Simulation time 2139672603 ps
CPU time 20.32 seconds
Started Aug 15 06:29:57 PM PDT 24
Finished Aug 15 06:30:18 PM PDT 24
Peak memory 216588 kb
Host smart-f0f2096c-ad66-4f16-8340-f379b1a9bd8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110255444 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.110255444
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3659482751
Short name T859
Test name
Test status
Simulation time 15556580046 ps
CPU time 25.93 seconds
Started Aug 15 06:29:57 PM PDT 24
Finished Aug 15 06:30:23 PM PDT 24
Peak memory 200848 kb
Host smart-99955bec-82f6-43a0-a04e-9cd374f006fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659482751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3659482751
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.434200346
Short name T636
Test name
Test status
Simulation time 35937642126 ps
CPU time 60.12 seconds
Started Aug 15 06:29:59 PM PDT 24
Finished Aug 15 06:31:00 PM PDT 24
Peak memory 200920 kb
Host smart-f2218d7d-2958-4116-a752-73cf5c689410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434200346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.434200346
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3897714135
Short name T1137
Test name
Test status
Simulation time 8879260205 ps
CPU time 29.61 seconds
Started Aug 15 06:29:59 PM PDT 24
Finished Aug 15 06:30:29 PM PDT 24
Peak memory 201208 kb
Host smart-24f5f060-1222-4bcf-a02b-ee3cfaa0ca4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897714135 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3897714135
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.2494694691
Short name T1069
Test name
Test status
Simulation time 25266565256 ps
CPU time 25.89 seconds
Started Aug 15 06:29:59 PM PDT 24
Finished Aug 15 06:30:25 PM PDT 24
Peak memory 200916 kb
Host smart-2618258c-028d-48a0-b666-b2a59396b400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494694691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2494694691
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.4219609535
Short name T1117
Test name
Test status
Simulation time 3384441271 ps
CPU time 33.04 seconds
Started Aug 15 06:29:58 PM PDT 24
Finished Aug 15 06:30:31 PM PDT 24
Peak memory 210608 kb
Host smart-1a4aa52b-ec93-420c-a052-72d9e10a1ece
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219609535 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.4219609535
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.181431889
Short name T882
Test name
Test status
Simulation time 14355481 ps
CPU time 0.54 seconds
Started Aug 15 06:25:55 PM PDT 24
Finished Aug 15 06:25:56 PM PDT 24
Peak memory 196548 kb
Host smart-50e96994-4bac-4b71-8d03-d54201bc2a8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181431889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.181431889
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.2338016318
Short name T558
Test name
Test status
Simulation time 69163177403 ps
CPU time 30.79 seconds
Started Aug 15 06:25:46 PM PDT 24
Finished Aug 15 06:26:17 PM PDT 24
Peak memory 200908 kb
Host smart-fecc8a31-912e-407d-9c2a-8c66fe318cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338016318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2338016318
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2271614808
Short name T169
Test name
Test status
Simulation time 142649866830 ps
CPU time 52.15 seconds
Started Aug 15 06:25:47 PM PDT 24
Finished Aug 15 06:26:39 PM PDT 24
Peak memory 201000 kb
Host smart-60b2ce7b-d632-4677-a2bb-e00b6689bf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271614808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2271614808
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1737203498
Short name T646
Test name
Test status
Simulation time 6924289003 ps
CPU time 12.14 seconds
Started Aug 15 06:25:47 PM PDT 24
Finished Aug 15 06:25:59 PM PDT 24
Peak memory 200288 kb
Host smart-f56391cd-64c3-496b-b35e-83cf1d97fa3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737203498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1737203498
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.3171220561
Short name T117
Test name
Test status
Simulation time 40375811085 ps
CPU time 75.48 seconds
Started Aug 15 06:25:47 PM PDT 24
Finished Aug 15 06:27:02 PM PDT 24
Peak memory 200844 kb
Host smart-e1ccb9ce-dff6-4843-8887-a3a823082b5d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171220561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3171220561
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1787121624
Short name T254
Test name
Test status
Simulation time 73161487883 ps
CPU time 455.03 seconds
Started Aug 15 06:25:58 PM PDT 24
Finished Aug 15 06:33:33 PM PDT 24
Peak memory 200904 kb
Host smart-2827101d-491c-49c8-a00b-87c5a15276c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1787121624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1787121624
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1469011016
Short name T918
Test name
Test status
Simulation time 7669488381 ps
CPU time 13.02 seconds
Started Aug 15 06:25:57 PM PDT 24
Finished Aug 15 06:26:10 PM PDT 24
Peak memory 199828 kb
Host smart-f0c8798b-c0fc-46e4-a39e-f2bc29af974d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469011016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1469011016
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.923809516
Short name T473
Test name
Test status
Simulation time 118524772243 ps
CPU time 60.3 seconds
Started Aug 15 06:25:49 PM PDT 24
Finished Aug 15 06:26:50 PM PDT 24
Peak memory 201072 kb
Host smart-5d3e9497-0458-4ad3-bea4-cbd519f2f33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923809516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.923809516
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.3312331919
Short name T337
Test name
Test status
Simulation time 17899953645 ps
CPU time 466.01 seconds
Started Aug 15 06:25:55 PM PDT 24
Finished Aug 15 06:33:41 PM PDT 24
Peak memory 200960 kb
Host smart-2c5d0751-27c7-4fb7-8db9-485281081d93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3312331919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3312331919
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.228636729
Short name T664
Test name
Test status
Simulation time 3787440991 ps
CPU time 8.71 seconds
Started Aug 15 06:25:47 PM PDT 24
Finished Aug 15 06:25:56 PM PDT 24
Peak memory 199508 kb
Host smart-baee7f40-c42a-47b8-aed1-853513f01067
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=228636729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.228636729
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.1054651382
Short name T502
Test name
Test status
Simulation time 38180461642 ps
CPU time 15.1 seconds
Started Aug 15 06:25:57 PM PDT 24
Finished Aug 15 06:26:13 PM PDT 24
Peak memory 200864 kb
Host smart-cdb6855e-5be9-418f-aeb1-6a4e3dc0247d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054651382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1054651382
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.884766450
Short name T740
Test name
Test status
Simulation time 1754452360 ps
CPU time 1.32 seconds
Started Aug 15 06:25:49 PM PDT 24
Finished Aug 15 06:25:50 PM PDT 24
Peak memory 196420 kb
Host smart-c1eb4299-0d9f-48ca-b110-2c3990027c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884766450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.884766450
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1446572257
Short name T896
Test name
Test status
Simulation time 491690236 ps
CPU time 2.39 seconds
Started Aug 15 06:25:51 PM PDT 24
Finished Aug 15 06:25:53 PM PDT 24
Peak memory 200844 kb
Host smart-39d2d45a-2624-408a-acac-81066c136b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446572257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1446572257
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.1701553430
Short name T741
Test name
Test status
Simulation time 172359949174 ps
CPU time 399.21 seconds
Started Aug 15 06:25:56 PM PDT 24
Finished Aug 15 06:32:35 PM PDT 24
Peak memory 200968 kb
Host smart-982933c2-f1fb-4caa-81a8-980455447499
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701553430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1701553430
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.438946112
Short name T126
Test name
Test status
Simulation time 8818811015 ps
CPU time 92.62 seconds
Started Aug 15 06:25:57 PM PDT 24
Finished Aug 15 06:27:29 PM PDT 24
Peak memory 209244 kb
Host smart-d4ef033a-e9df-4b00-a304-ef93863ba059
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438946112 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.438946112
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1627546130
Short name T486
Test name
Test status
Simulation time 876697086 ps
CPU time 2.86 seconds
Started Aug 15 06:25:55 PM PDT 24
Finished Aug 15 06:25:58 PM PDT 24
Peak memory 199728 kb
Host smart-0f51e272-160d-4e65-bccf-0964691000ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627546130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1627546130
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.238706915
Short name T857
Test name
Test status
Simulation time 14036128982 ps
CPU time 25.5 seconds
Started Aug 15 06:25:46 PM PDT 24
Finished Aug 15 06:26:12 PM PDT 24
Peak memory 200956 kb
Host smart-36776037-a42b-4133-a152-81a6b2699ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238706915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.238706915
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2654643819
Short name T1067
Test name
Test status
Simulation time 191878433061 ps
CPU time 49.98 seconds
Started Aug 15 06:30:00 PM PDT 24
Finished Aug 15 06:30:50 PM PDT 24
Peak memory 200964 kb
Host smart-1df72cc9-7967-4645-b3f5-696b6a5b72d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654643819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2654643819
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1049335032
Short name T1049
Test name
Test status
Simulation time 4663084388 ps
CPU time 57.94 seconds
Started Aug 15 06:30:02 PM PDT 24
Finished Aug 15 06:31:00 PM PDT 24
Peak memory 200948 kb
Host smart-7d2fb642-5089-4415-83d9-c2bc7ba67504
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049335032 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1049335032
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2772551964
Short name T912
Test name
Test status
Simulation time 19115073915 ps
CPU time 29.02 seconds
Started Aug 15 06:29:59 PM PDT 24
Finished Aug 15 06:30:28 PM PDT 24
Peak memory 200760 kb
Host smart-a9a7ecfb-1e1c-442d-ac12-6e0f09dd6e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772551964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2772551964
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.208319033
Short name T97
Test name
Test status
Simulation time 20956015018 ps
CPU time 60.15 seconds
Started Aug 15 06:29:56 PM PDT 24
Finished Aug 15 06:30:57 PM PDT 24
Peak memory 217304 kb
Host smart-ca41f542-59a0-4cf8-960d-1b7dbf943b60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208319033 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.208319033
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.2558842703
Short name T766
Test name
Test status
Simulation time 16435272449 ps
CPU time 11.9 seconds
Started Aug 15 06:29:58 PM PDT 24
Finished Aug 15 06:30:10 PM PDT 24
Peak memory 200848 kb
Host smart-31822c09-cfa1-4cda-92a7-5a133f162d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558842703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2558842703
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.196650841
Short name T685
Test name
Test status
Simulation time 4450542165 ps
CPU time 65.76 seconds
Started Aug 15 06:29:59 PM PDT 24
Finished Aug 15 06:31:05 PM PDT 24
Peak memory 209408 kb
Host smart-46d4b92d-86ec-463d-b0cb-a7e1afbc90ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196650841 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.196650841
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.867260317
Short name T596
Test name
Test status
Simulation time 2700448245 ps
CPU time 25.53 seconds
Started Aug 15 06:30:05 PM PDT 24
Finished Aug 15 06:30:30 PM PDT 24
Peak memory 217360 kb
Host smart-b564d68f-f955-4cfc-b08e-49286c9c986e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867260317 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.867260317
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3250102354
Short name T239
Test name
Test status
Simulation time 57062194880 ps
CPU time 56.5 seconds
Started Aug 15 06:30:04 PM PDT 24
Finished Aug 15 06:31:01 PM PDT 24
Peak memory 200900 kb
Host smart-522e82ef-3dd2-468c-a0b4-3d8b3a180493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250102354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3250102354
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1340351132
Short name T586
Test name
Test status
Simulation time 2491013034 ps
CPU time 29.99 seconds
Started Aug 15 06:30:05 PM PDT 24
Finished Aug 15 06:30:35 PM PDT 24
Peak memory 216588 kb
Host smart-5e40878f-d1af-48be-9288-0cda1797cd5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340351132 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1340351132
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.4260213011
Short name T829
Test name
Test status
Simulation time 63131321263 ps
CPU time 25.74 seconds
Started Aug 15 06:30:10 PM PDT 24
Finished Aug 15 06:30:36 PM PDT 24
Peak memory 200904 kb
Host smart-36432039-b1af-4951-92b9-6d0270912036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260213011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.4260213011
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.2196154877
Short name T324
Test name
Test status
Simulation time 20220376955 ps
CPU time 48.61 seconds
Started Aug 15 06:30:05 PM PDT 24
Finished Aug 15 06:30:54 PM PDT 24
Peak memory 216520 kb
Host smart-ca4ab072-a860-452f-80a2-3e6e0b47dbdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196154877 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2196154877
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.2181116582
Short name T513
Test name
Test status
Simulation time 60120032865 ps
CPU time 68.82 seconds
Started Aug 15 06:30:05 PM PDT 24
Finished Aug 15 06:31:14 PM PDT 24
Peak memory 200936 kb
Host smart-34e6ce54-3024-46f2-be34-213f9407ecd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181116582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2181116582
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.2898825162
Short name T817
Test name
Test status
Simulation time 5171384421 ps
CPU time 60.73 seconds
Started Aug 15 06:30:03 PM PDT 24
Finished Aug 15 06:31:04 PM PDT 24
Peak memory 210440 kb
Host smart-220f981e-3b58-4a18-b13c-4deae251e6b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898825162 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2898825162
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2987133370
Short name T972
Test name
Test status
Simulation time 117212665934 ps
CPU time 93.38 seconds
Started Aug 15 06:30:05 PM PDT 24
Finished Aug 15 06:31:39 PM PDT 24
Peak memory 200948 kb
Host smart-ce94a8f1-0a48-44d5-b39d-08592eed3679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987133370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2987133370
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1551187040
Short name T716
Test name
Test status
Simulation time 6105534136 ps
CPU time 86.38 seconds
Started Aug 15 06:30:05 PM PDT 24
Finished Aug 15 06:31:32 PM PDT 24
Peak memory 217352 kb
Host smart-83e930ba-e78d-4e15-8ab0-f3903e6308a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551187040 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1551187040
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.2855622482
Short name T802
Test name
Test status
Simulation time 49481379747 ps
CPU time 100.96 seconds
Started Aug 15 06:30:03 PM PDT 24
Finished Aug 15 06:31:44 PM PDT 24
Peak memory 200912 kb
Host smart-258cca38-3200-4ea5-9915-be3321b93491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855622482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2855622482
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1821123776
Short name T38
Test name
Test status
Simulation time 3232312024 ps
CPU time 20.35 seconds
Started Aug 15 06:30:04 PM PDT 24
Finished Aug 15 06:30:25 PM PDT 24
Peak memory 217380 kb
Host smart-55ee98e6-feef-493e-a5df-90abaae358c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821123776 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1821123776
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.3718891233
Short name T1132
Test name
Test status
Simulation time 61747872322 ps
CPU time 106.31 seconds
Started Aug 15 06:30:04 PM PDT 24
Finished Aug 15 06:31:50 PM PDT 24
Peak memory 200968 kb
Host smart-f716d03d-1048-406f-b322-c1285eb703f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718891233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.3718891233
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.3345926296
Short name T37
Test name
Test status
Simulation time 2834168008 ps
CPU time 14.58 seconds
Started Aug 15 06:30:11 PM PDT 24
Finished Aug 15 06:30:26 PM PDT 24
Peak memory 201028 kb
Host smart-5cad6004-94ed-4e4c-816d-a58a50b4b677
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345926296 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3345926296
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%