Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	91918	1			T1	19		T2	33		T3	9
all_values[1]	91918	1			T1	19		T2	33		T3	9
all_values[2]	91918	1			T1	19		T2	33		T3	9
all_values[3]	91918	1			T1	19		T2	33		T3	9
all_values[4]	91918	1			T1	19		T2	33		T3	9
all_values[5]	91918	1			T1	19		T2	33		T3	9
all_values[6]	91918	1			T1	19		T2	33		T3	9
all_values[7]	91918	1			T1	19		T2	33		T3	9
all_values[8]	91918	1			T1	19		T2	33		T3	9

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

425307

1

T1

80

T2

182

T3

37

auto[1]

401955

1

T1

91

T2

115

T3

44

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

751106

1

T1

156

T2

283

T3

64

auto[1]

76156

1

T1

15

T2

14

T3

17

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	27959	1			T2	13		T4	17		T6	6
all_values[0]	auto[0]	auto[1]	18209	1			T3	2		T4	3		T5	2
all_values[0]	auto[1]	auto[0]	26486	1			T1	18		T2	14		T3	2
all_values[0]	auto[1]	auto[1]	19264	1			T1	1		T2	6		T3	5
all_values[1]	auto[0]	auto[0]	47082	1			T2	27		T3	6		T4	17
all_values[1]	auto[0]	auto[1]	1328	1			T1	5		T9	2		T93	5
all_values[1]	auto[1]	auto[0]	42091	1			T1	8		T2	6		T3	3
all_values[1]	auto[1]	auto[1]	1417	1			T1	6		T9	2		T14	6
all_values[2]	auto[0]	auto[0]	45728	1			T1	3		T2	3		T3	3
all_values[2]	auto[0]	auto[1]	2237	1			T1	2		T3	1		T5	1
all_values[2]	auto[1]	auto[0]	41724	1			T1	14		T2	26		T3	3
all_values[2]	auto[1]	auto[1]	2229	1			T2	4		T3	2		T4	9
all_values[3]	auto[0]	auto[0]	47640	1			T1	14		T2	18		T4	20
all_values[3]	auto[0]	auto[1]	258	1			T9	2		T15	1		T94	2
all_values[3]	auto[1]	auto[0]	43764	1			T1	5		T2	14		T3	9
all_values[3]	auto[1]	auto[1]	256	1			T2	1		T9	1		T14	1
all_values[4]	auto[0]	auto[0]	44127	1			T1	14		T2	30		T3	9
all_values[4]	auto[0]	auto[1]	391	1			T18	4		T19	4		T20	1
all_values[4]	auto[1]	auto[0]	47114	1			T1	5		T2	3		T4	19
all_values[4]	auto[1]	auto[1]	286	1			T18	3		T19	2		T20	3
all_values[5]	auto[0]	auto[0]	47517	1			T1	14		T2	15		T3	5
all_values[5]	auto[0]	auto[1]	177	1			T18	1		T20	1		T37	1
all_values[5]	auto[1]	auto[0]	44054	1			T1	5		T2	18		T3	4
all_values[5]	auto[1]	auto[1]	170	1			T18	3		T19	2		T20	2
all_values[6]	auto[0]	auto[0]	45636	1			T1	10		T2	28		T3	1
all_values[6]	auto[0]	auto[1]	175	1			T18	1		T19	4		T20	5
all_values[6]	auto[1]	auto[0]	45943	1			T1	9		T2	5		T3	8
all_values[6]	auto[1]	auto[1]	164	1			T18	3		T19	1		T20	1
all_values[7]	auto[0]	auto[0]	50031	1			T1	9		T2	33		T3	2
all_values[7]	auto[0]	auto[1]	240	1			T93	5		T106	1		T18	1
all_values[7]	auto[1]	auto[0]	41343	1			T1	10		T3	7		T4	3
all_values[7]	auto[1]	auto[1]	304	1			T93	2		T106	1		T18	3
all_values[8]	auto[0]	auto[0]	32981	1			T1	8		T2	15		T3	2
all_values[8]	auto[0]	auto[1]	13591	1			T1	1		T3	6		T4	3
all_values[8]	auto[1]	auto[0]	29886	1			T1	10		T2	15		T8	7
all_values[8]	auto[1]	auto[1]	15460	1			T2	3		T3	1		T4	3