Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1924	1			T1	1		T2	1		T3	1
auto[BaudRate115200]	1553	1			T3	2		T4	2		T6	1
auto[BaudRate230400]	1573	1			T1	1		T2	2		T7	1
auto[BaudRate128Kbps]	1502	1			T2	1		T3	1		T4	1
auto[BaudRate256Kbps]	1735	1			T1	1		T2	3		T3	2
auto[BaudRate1Mbps]	1411	1			T1	2		T3	1		T4	1
auto[BaudRate1p5Mbps]	949	1			T2	1		T3	1		T4	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1331	1			T331	1		T45	8		T37	21
freqs[25]	895	1			T12	12		T14	7		T94	9
freqs[48]	380	1			T7	2		T16	16		T327	2
freqs[50]	314	1			T5	2		T11	3		T21	8
freqs[100]	1025	1			T29	2		T17	18		T18	7

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	231	1			T45	3		T37	6		T277	2
auto[BaudRate9600]	freqs[25]	156	1			T12	3		T14	1		T94	1
auto[BaudRate9600]	freqs[48]	68	1			T16	16		T91	2		T267	1
auto[BaudRate9600]	freqs[50]	73	1			T21	8		T171	1		T50	1
auto[BaudRate9600]	freqs[100]	204	1			T17	18		T18	3		T111	2
auto[BaudRate115200]	freqs[24]	180	1			T45	1		T37	1		T24	2
auto[BaudRate115200]	freqs[25]	131	1			T12	1		T94	1		T38	1
auto[BaudRate115200]	freqs[48]	51	1			T91	2		T267	1		T268	1
auto[BaudRate115200]	freqs[50]	39	1			T106	3		T269	2		T183	2
auto[BaudRate115200]	freqs[100]	119	1			T111	2		T35	2		T46	1
auto[BaudRate230400]	freqs[24]	190	1			T331	1		T37	4		T121	1
auto[BaudRate230400]	freqs[25]	146	1			T12	3		T14	2		T94	2
auto[BaudRate230400]	freqs[48]	72	1			T7	1		T355	2		T91	5
auto[BaudRate230400]	freqs[50]	33	1			T11	2		T171	1		T50	3
auto[BaudRate230400]	freqs[100]	111	1			T18	2		T111	1		T35	2
auto[BaudRate128Kbps]	freqs[24]	178	1			T45	1		T37	2		T24	2
auto[BaudRate128Kbps]	freqs[25]	136	1			T12	2		T94	2		T38	2
auto[BaudRate128Kbps]	freqs[48]	37	1			T91	1		T268	1		T280	6
auto[BaudRate128Kbps]	freqs[50]	40	1			T5	1		T11	1		T106	1
auto[BaudRate128Kbps]	freqs[100]	134	1			T29	2		T46	1		T333	1
auto[BaudRate256Kbps]	freqs[24]	227	1			T45	1		T37	4		T256	1
auto[BaudRate256Kbps]	freqs[25]	137	1			T12	1		T14	1		T38	1
auto[BaudRate256Kbps]	freqs[48]	63	1			T327	1		T91	6		T320	1
auto[BaudRate256Kbps]	freqs[50]	52	1			T106	1		T254	5		T171	1
auto[BaudRate256Kbps]	freqs[100]	134	1			T111	1		T265	1		T46	1
auto[BaudRate1Mbps]	freqs[24]	201	1			T45	1		T37	3		T256	1
auto[BaudRate1Mbps]	freqs[25]	131	1			T12	2		T14	3		T94	1
auto[BaudRate1Mbps]	freqs[48]	41	1			T91	3		T267	1		T268	1
auto[BaudRate1Mbps]	freqs[50]	47	1			T5	1		T106	1		T254	3
auto[BaudRate1Mbps]	freqs[100]	169	1			T18	2		T111	1		T35	1
auto[BaudRate1p5Mbps]	freqs[25]	58	1			T94	2		T248	1		T255	1
auto[BaudRate1p5Mbps]	freqs[48]	48	1			T7	1		T327	1		T91	10
auto[BaudRate1p5Mbps]	freqs[50]	30	1			T106	2		T254	2		T50	1
auto[BaudRate1p5Mbps]	freqs[100]	154	1			T111	1		T265	1		T46	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded