Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	9	121	93.08

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	9	121	93.08	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	29189930	1			T1	43		T2	85		T3	28
all_levels[1]	155056	1			T2	1		T3	3		T4	11
all_levels[2]	2169	1			T3	1		T4	1		T14	2
all_levels[3]	1005	1			T3	2		T9	2		T14	7
all_levels[4]	658	1			T12	1		T14	4		T42	2
all_levels[5]	527	1			T3	1		T14	3		T42	1
all_levels[6]	371	1			T12	1		T93	2		T106	2
all_levels[7]	272	1			T42	1		T94	2		T93	1
all_levels[8]	260	1			T42	1		T44	1		T97	1
all_levels[9]	208	1			T42	2		T44	2		T93	1
all_levels[10]	167	1			T106	1		T48	3		T107	1
all_levels[11]	186	1			T1	1		T42	1		T44	1
all_levels[12]	149	1			T94	2		T46	1		T47	2
all_levels[13]	117	1			T44	1		T106	1		T46	1
all_levels[14]	119	1			T12	1		T42	1		T93	1
all_levels[15]	105	1			T12	1		T93	1		T108	1
all_levels[16]	103	1			T42	1		T93	1		T109	1
all_levels[17]	66	1			T3	1		T42	1		T93	1
all_levels[18]	60	1			T42	1		T47	1		T110	1
all_levels[19]	62	1			T111	1		T112	1		T113	1
all_levels[20]	79	1			T93	1		T106	1		T113	1
all_levels[21]	61	1			T1	1		T111	1		T48	2
all_levels[22]	51	1			T42	1		T111	2		T109	1
all_levels[23]	62	1			T113	1		T114	2		T115	1
all_levels[24]	51	1			T44	1		T111	1		T46	1
all_levels[25]	43	1			T111	4		T116	1		T109	1
all_levels[26]	44	1			T106	1		T111	2		T37	1
all_levels[27]	29	1			T47	1		T113	3		T117	1
all_levels[28]	32	1			T118	2		T119	1		T120	2
all_levels[29]	48	1			T111	1		T112	1		T110	1
all_levels[30]	29	1			T106	1		T119	1		T121	1
all_levels[31]	30	1			T92	2		T109	1		T122	1
all_levels[32]	24	1			T106	1		T123	1		T124	1
all_levels[33]	20	1			T1	1		T48	1		T99	1
all_levels[34]	17	1			T93	1		T125	2		T126	1
all_levels[35]	17	1			T125	1		T127	2		T128	1
all_levels[36]	13	1			T3	1		T46	1		T116	1
all_levels[37]	24	1			T106	1		T46	1		T129	1
all_levels[38]	18	1			T42	1		T125	1		T123	1
all_levels[39]	20	1			T106	1		T118	1		T119	2
all_levels[40]	11	1			T130	1		T131	1		T132	1
all_levels[41]	15	1			T119	1		T133	1		T134	1
all_levels[42]	18	1			T135	1		T136	1		T137	1
all_levels[43]	13	1			T94	1		T46	1		T121	2
all_levels[44]	24	1			T14	3		T138	2		T139	1
all_levels[45]	12	1			T93	1		T140	1		T141	1
all_levels[46]	10	1			T140	1		T142	1		T133	1
all_levels[47]	10	1			T143	1		T144	3		T145	1
all_levels[48]	9	1			T98	1		T146	2		T147	1
all_levels[49]	10	1			T97	1		T125	1		T148	1
all_levels[50]	10	1			T149	1		T150	1		T151	2
all_levels[51]	5	1			T152	1		T153	1		T154	1
all_levels[52]	6	1			T99	1		T133	1		T155	1
all_levels[53]	11	1			T116	4		T156	1		T134	1
all_levels[54]	11	1			T157	1		T98	2		T158	1
all_levels[55]	7	1			T159	1		T160	1		T134	1
all_levels[56]	11	1			T158	1		T137	1		T161	1
all_levels[57]	6	1			T162	1		T163	1		T155	1
all_levels[58]	8	1			T139	1		T164	1		T165	1
all_levels[59]	2	1			T141	2		-	-		-	-
all_levels[60]	13	1			T135	3		T162	1		T150	1
all_levels[61]	11	1			T157	1		T158	1		T156	4
all_levels[62]	6	1			T166	1		T167	1		T152	1
all_levels[63]	3	1			T168	1		T169	1		T170	1
all_levels[64]	98	1			T2	1		T15	2		T44	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29348710

1

T1

46

T2

83

T3

29

auto[1]

3932

1

T2

4

T3

8

T4

3

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	9	121	93.08	9

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[22]]	[auto[1]]	0	1	1
[all_levels[41]]	[auto[1]]	0	1	1
[all_levels[46]]	[auto[1]]	0	1	1
[all_levels[50] , all_levels[51] , all_levels[52]]	[auto[1]]	--	--	3
[all_levels[55]]	[auto[1]]	0	1	1
[all_levels[57]]	[auto[1]]	0	1	1
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	29186454	1			T1	43		T2	81		T3	20
all_levels[0]	auto[1]	3476	1			T2	4		T3	8		T4	3
all_levels[1]	auto[0]	154979	1			T2	1		T3	3		T4	11
all_levels[1]	auto[1]	77	1			T42	1		T47	1		T107	4
all_levels[2]	auto[0]	2141	1			T3	1		T4	1		T14	2
all_levels[2]	auto[1]	28	1			T94	1		T113	1		T166	1
all_levels[3]	auto[0]	980	1			T3	2		T9	2		T14	5
all_levels[3]	auto[1]	25	1			T14	2		T45	2		T171	1
all_levels[4]	auto[0]	639	1			T12	1		T14	4		T42	2
all_levels[4]	auto[1]	19	1			T120	1		T172	2		T157	1
all_levels[5]	auto[0]	502	1			T3	1		T14	3		T42	1
all_levels[5]	auto[1]	25	1			T173	1		T174	2		T175	1
all_levels[6]	auto[0]	364	1			T12	1		T93	2		T106	2
all_levels[6]	auto[1]	7	1			T176	1		T177	1		T178	1
all_levels[7]	auto[0]	264	1			T42	1		T94	1		T93	1
all_levels[7]	auto[1]	8	1			T94	1		T179	1		T130	1
all_levels[8]	auto[0]	236	1			T42	1		T44	1		T97	1
all_levels[8]	auto[1]	24	1			T116	2		T180	1		T181	1
all_levels[9]	auto[0]	200	1			T42	2		T44	2		T93	1
all_levels[9]	auto[1]	8	1			T113	4		T114	1		T182	1
all_levels[10]	auto[0]	159	1			T106	1		T48	3		T107	1
all_levels[10]	auto[1]	8	1			T183	1		T184	1		T185	1
all_levels[11]	auto[0]	178	1			T1	1		T42	1		T44	1
all_levels[11]	auto[1]	8	1			T98	2		T186	2		T187	1
all_levels[12]	auto[0]	131	1			T94	2		T46	1		T47	1
all_levels[12]	auto[1]	18	1			T47	1		T173	1		T183	2
all_levels[13]	auto[0]	101	1			T44	1		T106	1		T46	1
all_levels[13]	auto[1]	16	1			T188	1		T129	3		T189	1
all_levels[14]	auto[0]	109	1			T12	1		T42	1		T93	1
all_levels[14]	auto[1]	10	1			T190	2		T191	1		T192	1
all_levels[15]	auto[0]	96	1			T12	1		T93	1		T108	1
all_levels[15]	auto[1]	9	1			T110	1		T120	1		T193	1
all_levels[16]	auto[0]	87	1			T42	1		T93	1		T109	1
all_levels[16]	auto[1]	16	1			T107	1		T188	1		T194	1
all_levels[17]	auto[0]	64	1			T3	1		T42	1		T93	1
all_levels[17]	auto[1]	2	1			T195	1		T196	1		-	-
all_levels[18]	auto[0]	57	1			T42	1		T47	1		T110	1
all_levels[18]	auto[1]	3	1			T197	1		T198	1		T199	1
all_levels[19]	auto[0]	53	1			T111	1		T112	1		T113	1
all_levels[19]	auto[1]	9	1			T200	2		T201	1		T202	4
all_levels[20]	auto[0]	71	1			T93	1		T106	1		T113	1
all_levels[20]	auto[1]	8	1			T203	2		T204	1		T205	1
all_levels[21]	auto[0]	49	1			T1	1		T111	1		T48	2
all_levels[21]	auto[1]	12	1			T206	1		T159	2		T207	1
all_levels[22]	auto[0]	51	1			T42	1		T111	2		T109	1
all_levels[23]	auto[0]	58	1			T113	1		T114	1		T115	1
all_levels[23]	auto[1]	4	1			T114	1		T208	2		T153	1
all_levels[24]	auto[0]	39	1			T44	1		T111	1		T46	1
all_levels[24]	auto[1]	12	1			T209	2		T210	4		T143	1
all_levels[25]	auto[0]	35	1			T111	4		T116	1		T109	1
all_levels[25]	auto[1]	8	1			T211	3		T212	1		T213	1
all_levels[26]	auto[0]	40	1			T106	1		T111	2		T37	1
all_levels[26]	auto[1]	4	1			T214	1		T215	2		T216	1
all_levels[27]	auto[0]	27	1			T47	1		T113	3		T117	1
all_levels[27]	auto[1]	2	1			T186	1		T217	1		-	-
all_levels[28]	auto[0]	29	1			T118	2		T119	1		T120	2
all_levels[28]	auto[1]	3	1			T218	1		T219	1		T220	1
all_levels[29]	auto[0]	41	1			T111	1		T112	1		T110	1
all_levels[29]	auto[1]	7	1			T221	1		T182	1		T222	1
all_levels[30]	auto[0]	26	1			T106	1		T119	1		T121	1
all_levels[30]	auto[1]	3	1			T122	1		T223	1		T224	1
all_levels[31]	auto[0]	28	1			T92	1		T109	1		T122	1
all_levels[31]	auto[1]	2	1			T92	1		T225	1		-	-
all_levels[32]	auto[0]	23	1			T106	1		T123	1		T124	1
all_levels[32]	auto[1]	1	1			T226	1		-	-		-	-
all_levels[33]	auto[0]	19	1			T1	1		T48	1		T99	1
all_levels[33]	auto[1]	1	1			T216	1		-	-		-	-
all_levels[34]	auto[0]	14	1			T93	1		T125	2		T126	1
all_levels[34]	auto[1]	3	1			T227	3		-	-		-	-
all_levels[35]	auto[0]	14	1			T125	1		T127	1		T128	1
all_levels[35]	auto[1]	3	1			T127	1		T228	1		T229	1
all_levels[36]	auto[0]	12	1			T3	1		T46	1		T116	1
all_levels[36]	auto[1]	1	1			T230	1		-	-		-	-
all_levels[37]	auto[0]	18	1			T106	1		T46	1		T129	1
all_levels[37]	auto[1]	6	1			T231	1		T232	2		T233	2
all_levels[38]	auto[0]	17	1			T42	1		T125	1		T123	1
all_levels[38]	auto[1]	1	1			T234	1		-	-		-	-
all_levels[39]	auto[0]	16	1			T106	1		T118	1		T119	1
all_levels[39]	auto[1]	4	1			T119	1		T235	3		-	-
all_levels[40]	auto[0]	7	1			T130	1		T131	1		T132	1
all_levels[40]	auto[1]	4	1			T229	2		T236	2		-	-
all_levels[41]	auto[0]	15	1			T119	1		T133	1		T134	1
all_levels[42]	auto[0]	13	1			T135	1		T136	1		T137	1
all_levels[42]	auto[1]	5	1			T237	4		T238	1		-	-
all_levels[43]	auto[0]	12	1			T94	1		T46	1		T121	2
all_levels[43]	auto[1]	1	1			T239	1		-	-		-	-
all_levels[44]	auto[0]	19	1			T14	1		T138	2		T139	1
all_levels[44]	auto[1]	5	1			T14	2		T135	1		T98	1
all_levels[45]	auto[0]	11	1			T93	1		T140	1		T141	1
all_levels[45]	auto[1]	1	1			T229	1		-	-		-	-
all_levels[46]	auto[0]	10	1			T140	1		T142	1		T133	1
all_levels[47]	auto[0]	7	1			T143	1		T144	1		T145	1
all_levels[47]	auto[1]	3	1			T144	2		T240	1		-	-
all_levels[48]	auto[0]	7	1			T98	1		T146	1		T147	1
all_levels[48]	auto[1]	2	1			T146	1		T213	1		-	-
all_levels[49]	auto[0]	9	1			T97	1		T125	1		T148	1
all_levels[49]	auto[1]	1	1			T241	1		-	-		-	-
all_levels[50]	auto[0]	10	1			T149	1		T150	1		T151	2
all_levels[51]	auto[0]	5	1			T152	1		T153	1		T154	1
all_levels[52]	auto[0]	6	1			T99	1		T133	1		T155	1
all_levels[53]	auto[0]	7	1			T116	1		T156	1		T134	1
all_levels[53]	auto[1]	4	1			T116	3		T242	1		-	-
all_levels[54]	auto[0]	10	1			T157	1		T98	1		T158	1
all_levels[54]	auto[1]	1	1			T98	1		-	-		-	-
all_levels[55]	auto[0]	7	1			T159	1		T160	1		T134	1
all_levels[56]	auto[0]	8	1			T158	1		T137	1		T161	1
all_levels[56]	auto[1]	3	1			T243	3		-	-		-	-
all_levels[57]	auto[0]	6	1			T162	1		T163	1		T155	1
all_levels[58]	auto[0]	7	1			T139	1		T164	1		T165	1
all_levels[58]	auto[1]	1	1			T187	1		-	-		-	-
all_levels[59]	auto[0]	1	1			T141	1		-	-		-	-
all_levels[59]	auto[1]	1	1			T141	1		-	-		-	-
all_levels[60]	auto[0]	7	1			T135	1		T162	1		T150	1
all_levels[60]	auto[1]	6	1			T135	2		T170	1		T244	3
all_levels[61]	auto[0]	8	1			T157	1		T158	1		T156	1
all_levels[61]	auto[1]	3	1			T156	3		-	-		-	-
all_levels[62]	auto[0]	5	1			T166	1		T167	1		T152	1
all_levels[62]	auto[1]	1	1			T245	1		-	-		-	-
all_levels[63]	auto[0]	3	1			T168	1		T169	1		T170	1
all_levels[64]	auto[0]	89	1			T2	1		T15	2		T44	1
all_levels[64]	auto[1]	9	1			T246	1		T122	1		T136	1