Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
8 |
1 |
7 |
87.50 |
Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_watermark_lvl |
8 |
1 |
7 |
87.50 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_watermark_lvl
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
1 |
7 |
87.50 |
User Defined Bins for cp_watermark_lvl
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
all_levels[7] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_levels[0] |
1226 |
1 |
|
|
T9 |
3 |
|
T92 |
1 |
|
T93 |
17 |
all_levels[1] |
563 |
1 |
|
|
T1 |
6 |
|
T14 |
6 |
|
T94 |
2 |
all_levels[2] |
280 |
1 |
|
|
T45 |
3 |
|
T91 |
1 |
|
T95 |
2 |
all_levels[3] |
318 |
1 |
|
|
T1 |
5 |
|
T46 |
7 |
|
T22 |
6 |
all_levels[4] |
192 |
1 |
|
|
T22 |
10 |
|
T48 |
8 |
|
T96 |
6 |
all_levels[5] |
108 |
1 |
|
|
T97 |
2 |
|
T98 |
2 |
|
T99 |
6 |
all_levels[6] |
45 |
1 |
|
|
T100 |
8 |
|
T101 |
6 |
|
T102 |
4 |
0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |