Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	91918	1			T1	19		T2	33		T3	9
all_pins[1]	91918	1			T1	19		T2	33		T3	9
all_pins[2]	91918	1			T1	19		T2	33		T3	9
all_pins[3]	91918	1			T1	19		T2	33		T3	9
all_pins[4]	91918	1			T1	19		T2	33		T3	9
all_pins[5]	91918	1			T1	19		T2	33		T3	9
all_pins[6]	91918	1			T1	19		T2	33		T3	9
all_pins[7]	91918	1			T1	19		T2	33		T3	9
all_pins[8]	91918	1			T1	19		T2	33		T3	9

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	786897	1			T1	164		T2	282		T3	71
values[0x1]	40365	1			T1	7		T2	15		T3	10
transitions[0x0=>0x1]	30377	1			T1	7		T2	12		T3	10
transitions[0x1=>0x0]	30160	1			T1	6		T2	12		T3	9

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	72590	1			T1	18		T2	27		T3	4
all_pins[0]	values[0x1]	19328	1			T1	1		T2	6		T3	5
all_pins[0]	transitions[0x0=>0x1]	18754	1			T1	1		T2	6		T3	5
all_pins[0]	transitions[0x1=>0x0]	839	1			T1	6		T14	6		T94	2
all_pins[1]	values[0x0]	90505	1			T1	13		T2	33		T3	9
all_pins[1]	values[0x1]	1413	1			T1	6		T9	1		T14	6
all_pins[1]	transitions[0x0=>0x1]	1307	1			T1	6		T9	1		T14	6
all_pins[1]	transitions[0x1=>0x0]	2155	1			T2	4		T3	2		T4	9
all_pins[2]	values[0x0]	89657	1			T1	19		T2	29		T3	7
all_pins[2]	values[0x1]	2261	1			T2	4		T3	2		T4	9
all_pins[2]	transitions[0x0=>0x1]	2201	1			T2	3		T3	2		T4	9
all_pins[2]	transitions[0x1=>0x0]	196	1			T9	1		T14	1		T18	2
all_pins[3]	values[0x0]	91662	1			T1	19		T2	32		T3	9
all_pins[3]	values[0x1]	256	1			T2	1		T9	1		T14	1
all_pins[3]	transitions[0x0=>0x1]	219	1			T2	1		T9	1		T14	1
all_pins[3]	transitions[0x1=>0x0]	249	1			T18	3		T19	2		T20	3
all_pins[4]	values[0x0]	91632	1			T1	19		T2	33		T3	9
all_pins[4]	values[0x1]	286	1			T18	3		T19	2		T20	3
all_pins[4]	transitions[0x0=>0x1]	224	1			T18	3		T19	1		T20	2
all_pins[4]	transitions[0x1=>0x0]	158	1			T18	3		T19	1		T20	1
all_pins[5]	values[0x0]	91698	1			T1	19		T2	33		T3	9
all_pins[5]	values[0x1]	220	1			T18	3		T19	2		T20	2
all_pins[5]	transitions[0x0=>0x1]	173	1			T18	3		T19	2		T20	2
all_pins[5]	transitions[0x1=>0x0]	720	1			T2	1		T3	2		T6	1
all_pins[6]	values[0x0]	91151	1			T1	19		T2	32		T3	7
all_pins[6]	values[0x1]	767	1			T2	1		T3	2		T6	1
all_pins[6]	transitions[0x0=>0x1]	709	1			T2	1		T3	2		T6	1
all_pins[6]	transitions[0x1=>0x0]	246	1			T93	2		T18	3		T19	1
all_pins[7]	values[0x0]	91614	1			T1	19		T2	33		T3	9
all_pins[7]	values[0x1]	304	1			T93	2		T106	1		T18	3
all_pins[7]	transitions[0x0=>0x1]	128	1			T93	2		T106	1		T18	2
all_pins[7]	transitions[0x1=>0x0]	15354	1			T2	3		T3	1		T4	3
all_pins[8]	values[0x0]	76388	1			T1	19		T2	30		T3	8
all_pins[8]	values[0x1]	15530	1			T2	3		T3	1		T4	3
all_pins[8]	transitions[0x0=>0x1]	6662	1			T2	1		T3	1		T4	3
all_pins[8]	transitions[0x1=>0x0]	10243	1			T2	4		T3	4		T4	4