Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6928640	1			T1	1		T2	9		T3	29
all_levels[1]	1644906	1			T2	3		T4	15		T9	2
all_levels[2]	298825	1			T1	1		T9	1		T12	227
all_levels[3]	236778	1			T2	1		T4	1		T42	3
all_levels[4]	199574	1			T6	3		T8	2		T12	1
all_levels[5]	460060	1			T12	1		T14	4		T43	1002
all_levels[6]	323287	1			T42	2		T43	997		T92	3
all_levels[7]	300087	1			T11	3		T43	1002		T94	5
all_levels[8]	250613	1			T3	1		T11	556		T12	1
all_levels[9]	181942	1			T42	1		T43	1002		T97	4
all_levels[10]	356485	1			T42	2		T43	1000		T97	4
all_levels[11]	498347	1			T42	3		T43	1000		T93	3
all_levels[12]	313079	1			T1	2		T8	2		T12	1
all_levels[13]	173111	1			T12	1		T40	11		T43	996
all_levels[14]	612000	1			T43	1001		T20	75		T273	1
all_levels[15]	187012	1			T4	3		T8	1		T9	1
all_levels[16]	246871	1			T9	2		T40	3		T43	1
all_levels[17]	752441	1			T43	1		T20	63		T247	7656
all_levels[18]	162683	1			T8	1		T40	1		T42	1
all_levels[19]	162682	1			T40	6		T42	1		T43	13248
all_levels[20]	152213	1			T4	4		T8	1		T9	1
all_levels[21]	239272	1			T4	2		T9	1		T40	8
all_levels[22]	154226	1			T4	4		T6	5		T12	5
all_levels[23]	230576	1			T4	4		T12	1		T15	2
all_levels[24]	148860	1			T4	3		T6	2		T8	2
all_levels[25]	137362	1			T4	5		T8	1		T20	38
all_levels[26]	135382	1			T3	3		T4	6		T42	2
all_levels[27]	146359	1			T4	4		T6	2		T270	1
all_levels[28]	427491	1			T4	5		T92	4		T93	2
all_levels[29]	342353	1			T8	1		T20	40		T247	7107
all_levels[30]	292072	1			T4	2		T6	2		T9	1
all_levels[31]	442887	1			T4	7		T6	2		T8	2
all_levels[32]	12213946	1			T1	43		T2	77		T3	5

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29348710

1

T1

46

T2

83

T3

29

auto[1]

3712

1

T1

1

T2

7

T3

9

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6926481	1			T1	1		T2	6		T3	23
all_levels[0]	auto[1]	2159	1			T2	3		T3	6		T4	3
all_levels[1]	auto[0]	1644672	1			T2	3		T4	14		T9	2
all_levels[1]	auto[1]	234	1			T4	1		T42	2		T47	1
all_levels[2]	auto[0]	298783	1			T1	1		T9	1		T12	227
all_levels[2]	auto[1]	42	1			T94	2		T278	1		T188	1
all_levels[3]	auto[0]	236707	1			T2	1		T4	1		T42	3
all_levels[3]	auto[1]	71	1			T108	1		T48	1		T183	1
all_levels[4]	auto[0]	199548	1			T6	1		T8	2		T12	1
all_levels[4]	auto[1]	26	1			T6	2		T107	1		T221	3
all_levels[5]	auto[0]	460023	1			T12	1		T14	2		T43	1002
all_levels[5]	auto[1]	37	1			T14	2		T183	1		T362	1
all_levels[6]	auto[0]	323256	1			T42	2		T43	997		T92	2
all_levels[6]	auto[1]	31	1			T92	1		T246	1		T122	2
all_levels[7]	auto[0]	300013	1			T11	1		T43	1002		T94	4
all_levels[7]	auto[1]	74	1			T11	2		T94	1		T304	2
all_levels[8]	auto[0]	250583	1			T3	1		T11	556		T12	1
all_levels[8]	auto[1]	30	1			T116	3		T253	1		T127	1
all_levels[9]	auto[0]	181925	1			T42	1		T43	1002		T97	4
all_levels[9]	auto[1]	17	1			T47	1		T271	1		T246	1
all_levels[10]	auto[0]	356464	1			T42	2		T43	1000		T97	4
all_levels[10]	auto[1]	21	1			T143	1		T363	1		T364	1
all_levels[11]	auto[0]	498322	1			T42	2		T43	1000		T93	3
all_levels[11]	auto[1]	25	1			T42	1		T246	2		T114	1
all_levels[12]	auto[0]	313056	1			T1	2		T8	2		T12	1
all_levels[12]	auto[1]	23	1			T42	1		T183	1		T336	2
all_levels[13]	auto[0]	173090	1			T12	1		T40	11		T43	996
all_levels[13]	auto[1]	21	1			T273	2		T304	1		T280	1
all_levels[14]	auto[0]	611980	1			T43	1001		T20	75		T273	1
all_levels[14]	auto[1]	20	1			T122	1		T365	1		T136	2
all_levels[15]	auto[0]	186895	1			T4	2		T8	1		T9	1
all_levels[15]	auto[1]	117	1			T4	1		T257	1		T321	5
all_levels[16]	auto[0]	246860	1			T9	2		T40	3		T43	1
all_levels[16]	auto[1]	11	1			T50	2		T114	1		T316	1
all_levels[17]	auto[0]	752419	1			T43	1		T20	63		T247	7656
all_levels[17]	auto[1]	22	1			T180	3		T188	1		T366	1
all_levels[18]	auto[0]	162661	1			T8	1		T40	1		T42	1
all_levels[18]	auto[1]	22	1			T175	2		T367	3		T364	2
all_levels[19]	auto[0]	162664	1			T40	5		T42	1		T43	13247
all_levels[19]	auto[1]	18	1			T40	1		T43	1		T119	1
all_levels[20]	auto[0]	152191	1			T4	3		T8	1		T9	1
all_levels[20]	auto[1]	22	1			T4	1		T129	2		T157	1
all_levels[21]	auto[0]	239255	1			T4	2		T9	1		T40	8
all_levels[21]	auto[1]	17	1			T368	1		T369	1		T370	1
all_levels[22]	auto[0]	154211	1			T4	4		T6	1		T12	5
all_levels[22]	auto[1]	15	1			T6	4		T138	1		T207	1
all_levels[23]	auto[0]	230559	1			T4	4		T12	1		T15	2
all_levels[23]	auto[1]	17	1			T333	1		T120	1		T207	2
all_levels[24]	auto[0]	148836	1			T4	3		T6	2		T8	2
all_levels[24]	auto[1]	24	1			T107	1		T117	2		T223	3
all_levels[25]	auto[0]	137340	1			T4	5		T8	1		T20	38
all_levels[25]	auto[1]	22	1			T117	5		T246	1		T120	1
all_levels[26]	auto[0]	135361	1			T3	1		T4	6		T42	2
all_levels[26]	auto[1]	21	1			T3	2		T92	1		T188	2
all_levels[27]	auto[0]	146349	1			T4	4		T6	2		T270	1
all_levels[27]	auto[1]	10	1			T117	1		T180	1		T188	1
all_levels[28]	auto[0]	427476	1			T4	5		T92	1		T93	2
all_levels[28]	auto[1]	15	1			T92	3		T107	2		T287	1
all_levels[29]	auto[0]	342332	1			T8	1		T20	40		T247	7107
all_levels[29]	auto[1]	21	1			T107	1		T319	1		T135	2
all_levels[30]	auto[0]	292053	1			T4	2		T6	2		T9	1
all_levels[30]	auto[1]	19	1			T15	3		T326	2		T371	1
all_levels[31]	auto[0]	442865	1			T4	7		T6	2		T8	2
all_levels[31]	auto[1]	22	1			T171	1		T110	1		T285	1
all_levels[32]	auto[0]	12213480	1			T1	42		T2	73		T3	4
all_levels[32]	auto[1]	466	1			T1	1		T2	4		T3	1